drivers/net/ethernet/mellanox/mlx5/core/en_clock.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/clocksource.h>
  34 #include "en.h"
  35
  36 enum {
  37         MLX5E_CYCLES_SHIFT      = 23
  38 };
  39
  40 enum {
  41         MLX5E_PIN_MODE_IN               = 0x0,
  42         MLX5E_PIN_MODE_OUT              = 0x1,
  43 };
  44
  45 enum {
  46         MLX5E_OUT_PATTERN_PULSE         = 0x0,
  47         MLX5E_OUT_PATTERN_PERIODIC      = 0x1,
  48 };
  49
  50 enum {
  51         MLX5E_EVENT_MODE_DISABLE        = 0x0,
  52         MLX5E_EVENT_MODE_REPETETIVE     = 0x1,
  53         MLX5E_EVENT_MODE_ONCE_TILL_ARM  = 0x2,
  54 };
  55
  56 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *tstamp, u64 timestamp,
  57                         struct skb_shared_hwtstamps *hwts)
  58 {
  59         u64 nsec;
  60
  61         read_lock(&tstamp->lock);
  62         nsec = timecounter_cyc2time(&tstamp->clock, timestamp);
  63         read_unlock(&tstamp->lock);
  64
  65         hwts->hwtstamp = ns_to_ktime(nsec);
  66 }
  67
  68 static u64 mlx5e_read_internal_timer(const struct cyclecounter *cc)
  69 {
  70         struct mlx5e_tstamp *tstamp = container_of(cc, struct mlx5e_tstamp,
  71                                                    cycles);
  72
  73         return mlx5_read_internal_timer(tstamp->mdev) & cc->mask;
  74 }
  75
  76 static void mlx5e_timestamp_overflow(struct work_struct *work)
  77 {
  78         struct delayed_work *dwork = to_delayed_work(work);
  79         struct mlx5e_tstamp *tstamp = container_of(dwork, struct mlx5e_tstamp,
  80                                                    overflow_work);
  81         unsigned long flags;
  82
  83         write_lock_irqsave(&tstamp->lock, flags);
  84         timecounter_read(&tstamp->clock);
  85         write_unlock_irqrestore(&tstamp->lock, flags);
  86         schedule_delayed_work(&tstamp->overflow_work, tstamp->overflow_period);
  87 }
  88
  89 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
  90 {
  91         struct mlx5e_priv *priv = netdev_priv(dev);
  92         struct hwtstamp_config config;
  93         int err;
  94
  95         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
  96                 return -EOPNOTSUPP;
  97
  98         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  99                 return -EFAULT;
 100
 101         /* TX HW timestamp */
 102         switch (config.tx_type) {
 103         case HWTSTAMP_TX_OFF:
 104         case HWTSTAMP_TX_ON:
 105                 break;
 106         default:
 107                 return -ERANGE;
 108         }
 109
 110         mutex_lock(&priv->state_lock);
 111         /* RX HW timestamp */
 112         switch (config.rx_filter) {
 113         case HWTSTAMP_FILTER_NONE:
 114                 /* Reset CQE compression to Admin default */
 115                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
 116                 break;
 117         case HWTSTAMP_FILTER_ALL:
 118         case HWTSTAMP_FILTER_SOME:
 119         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 120         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 121         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 122         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 123         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 124         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 125         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 126         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 127         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 128         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 129         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 130         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 131                 /* Disable CQE compression */
 132                 netdev_warn(dev, "Disabling cqe compression");
 133                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
 134                 if (err) {
 135                         netdev_err(dev, "Failed disabling cqe compression err=%d\n", err);
 136                         mutex_unlock(&priv->state_lock);
 137                         return err;
 138                 }
 139                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 140                 break;
 141         default:
 142                 mutex_unlock(&priv->state_lock);
 143                 return -ERANGE;
 144         }
 145
 146         memcpy(&priv->tstamp.hwtstamp_config, &config, sizeof(config));
 147         mutex_unlock(&priv->state_lock);
 148
 149         return copy_to_user(ifr->ifr_data, &config,
 150                             sizeof(config)) ? -EFAULT : 0;
 151 }
 152
 153 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr)
 154 {
 155         struct mlx5e_priv *priv = netdev_priv(dev);
 156         struct hwtstamp_config *cfg = &priv->tstamp.hwtstamp_config;
 157
 158         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
 159                 return -EOPNOTSUPP;
 160
 161         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
 162 }
 163
 164 static int mlx5e_ptp_settime(struct ptp_clock_info *ptp,
 165                              const struct timespec64 *ts)
 166 {
 167         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 168                                                    ptp_info);
 169         u64 ns = timespec64_to_ns(ts);
 170         unsigned long flags;
 171
 172         write_lock_irqsave(&tstamp->lock, flags);
 173         timecounter_init(&tstamp->clock, &tstamp->cycles, ns);
 174         write_unlock_irqrestore(&tstamp->lock, flags);
 175
 176         return 0;
 177 }
 178
 179 static int mlx5e_ptp_gettime(struct ptp_clock_info *ptp,
 180                              struct timespec64 *ts)
 181 {
 182         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 183                                                    ptp_info);
 184         u64 ns;
 185         unsigned long flags;
 186
 187         write_lock_irqsave(&tstamp->lock, flags);
 188         ns = timecounter_read(&tstamp->clock);
 189         write_unlock_irqrestore(&tstamp->lock, flags);
 190
 191         *ts = ns_to_timespec64(ns);
 192
 193         return 0;
 194 }
 195
 196 static int mlx5e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 197 {
 198         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 199                                                    ptp_info);
 200         unsigned long flags;
 201
 202         write_lock_irqsave(&tstamp->lock, flags);
 203         timecounter_adjtime(&tstamp->clock, delta);
 204         write_unlock_irqrestore(&tstamp->lock, flags);
 205
 206         return 0;
 207 }
 208
 209 static int mlx5e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
 210 {
 211         u64 adj;
 212         u32 diff;
 213         unsigned long flags;
 214         int neg_adj = 0;
 215         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 216                                                   ptp_info);
 217         struct mlx5e_priv *priv =
 218                 container_of(tstamp, struct mlx5e_priv, tstamp);
 219
 220         if (MLX5_CAP_GEN(priv->mdev, pps_modify)) {
 221                 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
 222
 223                 /* For future use need to add a loop for finding all 1PPS out pins */
 224                 MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_OUT);
 225                 MLX5_SET(mtpps_reg, in, out_periodic_adjustment, delta & 0xFFFF);
 226
 227                 mlx5_set_mtpps(priv->mdev, in, sizeof(in));
 228         }
 229
 230         if (delta < 0) {
 231                 neg_adj = 1;
 232                 delta = -delta;
 233         }
 234
 235         adj = tstamp->nominal_c_mult;
 236         adj *= delta;
 237         diff = div_u64(adj, 1000000000ULL);
 238
 239         write_lock_irqsave(&tstamp->lock, flags);
 240         timecounter_read(&tstamp->clock);
 241         tstamp->cycles.mult = neg_adj ? tstamp->nominal_c_mult - diff :
 242                                         tstamp->nominal_c_mult + diff;
 243         write_unlock_irqrestore(&tstamp->lock, flags);
 244
 245         return 0;
 246 }
 247
 248 static int mlx5e_extts_configure(struct ptp_clock_info *ptp,
 249                                  struct ptp_clock_request *rq,
 250                                  int on)
 251 {
 252         struct mlx5e_tstamp *tstamp =
 253                 container_of(ptp, struct mlx5e_tstamp, ptp_info);
 254         struct mlx5e_priv *priv =
 255                 container_of(tstamp, struct mlx5e_priv, tstamp);
 256         u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
 257         u8 pattern = 0;
 258         int pin = -1;
 259         int err = 0;
 260
 261         if (!MLX5_CAP_GEN(priv->mdev, pps) ||
 262             !MLX5_CAP_GEN(priv->mdev, pps_modify))
 263                 return -EOPNOTSUPP;
 264
 265         if (rq->extts.index >= tstamp->ptp_info.n_pins)
 266                 return -EINVAL;
 267
 268         if (on) {
 269                 pin = ptp_find_pin(tstamp->ptp, PTP_PF_EXTTS, rq->extts.index);
 270                 if (pin < 0)
 271                         return -EBUSY;
 272         }
 273
 274         if (rq->extts.flags & PTP_FALLING_EDGE)
 275                 pattern = 1;
 276
 277         MLX5_SET(mtpps_reg, in, pin, pin);
 278         MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_IN);
 279         MLX5_SET(mtpps_reg, in, pattern, pattern);
 280         MLX5_SET(mtpps_reg, in, enable, on);
 281
 282         err = mlx5_set_mtpps(priv->mdev, in, sizeof(in));
 283         if (err)
 284                 return err;
 285
 286         return mlx5_set_mtppse(priv->mdev, pin, 0,
 287                                MLX5E_EVENT_MODE_REPETETIVE & on);
 288 }
 289
 290 static int mlx5e_perout_configure(struct ptp_clock_info *ptp,
 291                                   struct ptp_clock_request *rq,
 292                                   int on)
 293 {
 294         struct mlx5e_tstamp *tstamp =
 295                 container_of(ptp, struct mlx5e_tstamp, ptp_info);
 296         struct mlx5e_priv *priv =
 297                 container_of(tstamp, struct mlx5e_priv, tstamp);
 298         u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
 299         u64 nsec_now, nsec_delta, time_stamp;
 300         u64 cycles_now, cycles_delta;
 301         struct timespec64 ts;
 302         unsigned long flags;
 303         int pin = -1;
 304         s64 ns;
 305
 306         if (!MLX5_CAP_GEN(priv->mdev, pps_modify))
 307                 return -EOPNOTSUPP;
 308
 309         if (rq->perout.index >= tstamp->ptp_info.n_pins)
 310                 return -EINVAL;
 311
 312         if (on) {
 313                 pin = ptp_find_pin(tstamp->ptp, PTP_PF_PEROUT,
 314                                    rq->perout.index);
 315                 if (pin < 0)
 316                         return -EBUSY;
 317         }
 318
 319         ts.tv_sec = rq->perout.period.sec;
 320         ts.tv_nsec = rq->perout.period.nsec;
 321         ns = timespec64_to_ns(&ts);
 322         if (on)
 323                 if ((ns >> 1) != 500000000LL)
 324                         return -EINVAL;
 325         ts.tv_sec = rq->perout.start.sec;
 326         ts.tv_nsec = rq->perout.start.nsec;
 327         ns = timespec64_to_ns(&ts);
 328         cycles_now = mlx5_read_internal_timer(tstamp->mdev);
 329         write_lock_irqsave(&tstamp->lock, flags);
 330         nsec_now = timecounter_cyc2time(&tstamp->clock, cycles_now);
 331         nsec_delta = ns - nsec_now;
 332         cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift,
 333                                  tstamp->cycles.mult);
 334         write_unlock_irqrestore(&tstamp->lock, flags);
 335         time_stamp = cycles_now + cycles_delta;
 336         MLX5_SET(mtpps_reg, in, pin, pin);
 337         MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_OUT);
 338         MLX5_SET(mtpps_reg, in, pattern, MLX5E_OUT_PATTERN_PERIODIC);
 339         MLX5_SET(mtpps_reg, in, enable, on);
 340         MLX5_SET64(mtpps_reg, in, time_stamp, time_stamp);
 341
 342         return mlx5_set_mtpps(priv->mdev, in, sizeof(in));
 343 }
 344
 345 static int mlx5e_ptp_enable(struct ptp_clock_info *ptp,
 346                             struct ptp_clock_request *rq,
 347                             int on)
 348 {
 349         switch (rq->type) {
 350         case PTP_CLK_REQ_EXTTS:
 351                 return mlx5e_extts_configure(ptp, rq, on);
 352         case PTP_CLK_REQ_PEROUT:
 353                 return mlx5e_perout_configure(ptp, rq, on);
 354         default:
 355                 return -EOPNOTSUPP;
 356         }
 357         return 0;
 358 }
 359
 360 static int mlx5e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
 361                             enum ptp_pin_function func, unsigned int chan)
 362 {
 363         return (func == PTP_PF_PHYSYNC) ? -EOPNOTSUPP : 0;
 364 }
 365
 366 static const struct ptp_clock_info mlx5e_ptp_clock_info = {
 367         .owner          = THIS_MODULE,
 368         .max_adj        = 100000000,
 369         .n_alarm        = 0,
 370         .n_ext_ts       = 0,
 371         .n_per_out      = 0,
 372         .n_pins         = 0,
 373         .pps            = 0,
 374         .adjfreq        = mlx5e_ptp_adjfreq,
 375         .adjtime        = mlx5e_ptp_adjtime,
 376         .gettime64      = mlx5e_ptp_gettime,
 377         .settime64      = mlx5e_ptp_settime,
 378         .enable         = NULL,
 379         .verify         = NULL,
 380 };
 381
 382 static void mlx5e_timestamp_init_config(struct mlx5e_tstamp *tstamp)
 383 {
 384         tstamp->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
 385         tstamp->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
 386 }
 387
 388 static int mlx5e_init_pin_config(struct mlx5e_tstamp *tstamp)
 389 {
 390         int i;
 391
 392         tstamp->ptp_info.pin_config =
 393                 kzalloc(sizeof(*tstamp->ptp_info.pin_config) *
 394                                tstamp->ptp_info.n_pins, GFP_KERNEL);
 395         if (!tstamp->ptp_info.pin_config)
 396                 return -ENOMEM;
 397         tstamp->ptp_info.enable = mlx5e_ptp_enable;
 398         tstamp->ptp_info.verify = mlx5e_ptp_verify;
 399
 400         for (i = 0; i < tstamp->ptp_info.n_pins; i++) {
 401                 snprintf(tstamp->ptp_info.pin_config[i].name,
 402                          sizeof(tstamp->ptp_info.pin_config[i].name),
 403                          "mlx5_pps%d", i);
 404                 tstamp->ptp_info.pin_config[i].index = i;
 405                 tstamp->ptp_info.pin_config[i].func = PTP_PF_NONE;
 406                 tstamp->ptp_info.pin_config[i].chan = i;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static void mlx5e_get_pps_caps(struct mlx5e_priv *priv,
 413                                struct mlx5e_tstamp *tstamp)
 414 {
 415         u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
 416
 417         mlx5_query_mtpps(priv->mdev, out, sizeof(out));
 418
 419         tstamp->ptp_info.n_pins = MLX5_GET(mtpps_reg, out,
 420                                            cap_number_of_pps_pins);
 421         tstamp->ptp_info.n_ext_ts = MLX5_GET(mtpps_reg, out,
 422                                              cap_max_num_of_pps_in_pins);
 423         tstamp->ptp_info.n_per_out = MLX5_GET(mtpps_reg, out,
 424                                               cap_max_num_of_pps_out_pins);
 425
 426         tstamp->pps_pin_caps[0] = MLX5_GET(mtpps_reg, out, cap_pin_0_mode);
 427         tstamp->pps_pin_caps[1] = MLX5_GET(mtpps_reg, out, cap_pin_1_mode);
 428         tstamp->pps_pin_caps[2] = MLX5_GET(mtpps_reg, out, cap_pin_2_mode);
 429         tstamp->pps_pin_caps[3] = MLX5_GET(mtpps_reg, out, cap_pin_3_mode);
 430         tstamp->pps_pin_caps[4] = MLX5_GET(mtpps_reg, out, cap_pin_4_mode);
 431         tstamp->pps_pin_caps[5] = MLX5_GET(mtpps_reg, out, cap_pin_5_mode);
 432         tstamp->pps_pin_caps[6] = MLX5_GET(mtpps_reg, out, cap_pin_6_mode);
 433         tstamp->pps_pin_caps[7] = MLX5_GET(mtpps_reg, out, cap_pin_7_mode);
 434 }
 435
 436 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
 437                              struct ptp_clock_event *event)
 438 {
 439         struct mlx5e_tstamp *tstamp = &priv->tstamp;
 440
 441         ptp_clock_event(tstamp->ptp, event);
 442 }
 443
 444 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
 445 {
 446         struct mlx5e_tstamp *tstamp = &priv->tstamp;
 447         u64 ns;
 448         u64 frac = 0;
 449         u32 dev_freq;
 450
 451         mlx5e_timestamp_init_config(tstamp);
 452         dev_freq = MLX5_CAP_GEN(priv->mdev, device_frequency_khz);
 453         if (!dev_freq) {
 454                 mlx5_core_warn(priv->mdev, "invalid device_frequency_khz, aborting HW clock init\n");
 455                 return;
 456         }
 457         rwlock_init(&tstamp->lock);
 458         tstamp->cycles.read = mlx5e_read_internal_timer;
 459         tstamp->cycles.shift = MLX5E_CYCLES_SHIFT;
 460         tstamp->cycles.mult = clocksource_khz2mult(dev_freq,
 461                                                    tstamp->cycles.shift);
 462         tstamp->nominal_c_mult = tstamp->cycles.mult;
 463         tstamp->cycles.mask = CLOCKSOURCE_MASK(41);
 464         tstamp->mdev = priv->mdev;
 465
 466         timecounter_init(&tstamp->clock, &tstamp->cycles,
 467                          ktime_to_ns(ktime_get_real()));
 468
 469         /* Calculate period in seconds to call the overflow watchdog - to make
 470          * sure counter is checked at least once every wrap around.
 471          */
 472         ns = cyclecounter_cyc2ns(&tstamp->cycles, tstamp->cycles.mask,
 473                                  frac, &frac);
 474         do_div(ns, NSEC_PER_SEC / 2 / HZ);
 475         tstamp->overflow_period = ns;
 476
 477         INIT_DELAYED_WORK(&tstamp->overflow_work, mlx5e_timestamp_overflow);
 478         if (tstamp->overflow_period)
 479                 schedule_delayed_work(&tstamp->overflow_work, 0);
 480         else
 481                 mlx5_core_warn(priv->mdev, "invalid overflow period, overflow_work is not scheduled\n");
 482
 483         /* Configure the PHC */
 484         tstamp->ptp_info = mlx5e_ptp_clock_info;
 485         snprintf(tstamp->ptp_info.name, 16, "mlx5 ptp");
 486
 487         /* Initialize 1PPS data structures */
 488 #define MAX_PIN_NUM     8
 489         tstamp->pps_pin_caps = kzalloc(sizeof(u8) * MAX_PIN_NUM, GFP_KERNEL);
 490         if (tstamp->pps_pin_caps) {
 491                 if (MLX5_CAP_GEN(priv->mdev, pps))
 492                         mlx5e_get_pps_caps(priv, tstamp);
 493                 if (tstamp->ptp_info.n_pins)
 494                         mlx5e_init_pin_config(tstamp);
 495         } else {
 496                 mlx5_core_warn(priv->mdev, "1PPS initialization failed\n");
 497         }
 498
 499         tstamp->ptp = ptp_clock_register(&tstamp->ptp_info,
 500                                          &priv->mdev->pdev->dev);
 501         if (IS_ERR(tstamp->ptp)) {
 502                 mlx5_core_warn(priv->mdev, "ptp_clock_register failed %ld\n",
 503                                PTR_ERR(tstamp->ptp));
 504                 tstamp->ptp = NULL;
 505         }
 506 }
 507
 508 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv)
 509 {
 510         struct mlx5e_tstamp *tstamp = &priv->tstamp;
 511
 512         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
 513                 return;
 514
 515         if (priv->tstamp.ptp) {
 516                 ptp_clock_unregister(priv->tstamp.ptp);
 517                 priv->tstamp.ptp = NULL;
 518         }
 519
 520         kfree(tstamp->pps_pin_caps);
 521         kfree(tstamp->ptp_info.pin_config);
 522
 523         cancel_delayed_work_sync(&tstamp->overflow_work);
 524 }