2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
48 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
49 sizeof(drvinfo->bus_info));
52 struct ptys2ethtool_config {
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
54 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
58 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
60 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
62 struct ptys2ethtool_config *cfg; \
63 const unsigned int modes[] = { __VA_ARGS__ }; \
65 cfg = &ptys2ethtool_table[reg_]; \
66 cfg->speed = speed_; \
67 bitmap_zero(cfg->supported, \
68 __ETHTOOL_LINK_MODE_MASK_NBITS); \
69 bitmap_zero(cfg->advertised, \
70 __ETHTOOL_LINK_MODE_MASK_NBITS); \
71 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
72 __set_bit(modes[i], cfg->supported); \
73 __set_bit(modes[i], cfg->advertised); \
77 void mlx5e_build_ptys2ethtool_map(void)
79 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
80 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
81 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
82 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
83 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
84 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
85 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
86 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
87 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
88 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
89 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
90 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
91 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
92 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
94 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
96 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
98 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
100 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
102 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
104 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
106 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
108 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
110 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
112 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
114 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
116 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
118 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
120 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
122 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
124 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
126 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
128 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
131 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
133 struct mlx5_core_dev *mdev = priv->mdev;
138 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
140 return err ? 0 : pfc_en_tx | pfc_en_rx;
143 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
145 struct mlx5_core_dev *mdev = priv->mdev;
150 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
152 return err ? false : rx_pause | tx_pause;
155 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
156 #define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
157 #define MLX5E_NUM_SQ_STATS(priv) \
158 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
159 #define MLX5E_NUM_PFC_COUNTERS(priv) \
160 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
161 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
163 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
165 struct mlx5e_priv *priv = netdev_priv(dev);
169 return NUM_SW_COUNTERS +
170 MLX5E_NUM_Q_CNTRS(priv) +
171 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
172 NUM_PCIE_COUNTERS(priv) +
173 MLX5E_NUM_RQ_STATS(priv) +
174 MLX5E_NUM_SQ_STATS(priv) +
175 MLX5E_NUM_PFC_COUNTERS(priv) +
176 ARRAY_SIZE(mlx5e_pme_status_desc) +
177 ARRAY_SIZE(mlx5e_pme_error_desc);
179 case ETH_SS_PRIV_FLAGS:
180 return ARRAY_SIZE(mlx5e_priv_flags);
182 return mlx5e_self_test_num(priv);
189 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
191 int i, j, tc, prio, idx = 0;
192 unsigned long pfc_combined;
195 for (i = 0; i < NUM_SW_COUNTERS; i++)
196 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
199 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
200 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
203 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
204 strcpy(data + (idx++) * ETH_GSTRING_LEN,
205 vport_stats_desc[i].format);
208 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
209 strcpy(data + (idx++) * ETH_GSTRING_LEN,
210 pport_802_3_stats_desc[i].format);
212 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
214 pport_2863_stats_desc[i].format);
216 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
217 strcpy(data + (idx++) * ETH_GSTRING_LEN,
218 pport_2819_stats_desc[i].format);
220 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
221 strcpy(data + (idx++) * ETH_GSTRING_LEN,
222 pport_phy_statistical_stats_desc[i].format);
224 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
225 strcpy(data + (idx++) * ETH_GSTRING_LEN,
226 pcie_perf_stats_desc[i].format);
228 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
229 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
230 sprintf(data + (idx++) * ETH_GSTRING_LEN,
231 pport_per_prio_traffic_stats_desc[i].format, prio);
234 pfc_combined = mlx5e_query_pfc_combined(priv);
235 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
236 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
237 char pfc_string[ETH_GSTRING_LEN];
239 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
240 sprintf(data + (idx++) * ETH_GSTRING_LEN,
241 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
245 if (mlx5e_query_global_pause_combined(priv)) {
246 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
247 sprintf(data + (idx++) * ETH_GSTRING_LEN,
248 pport_per_prio_pfc_stats_desc[i].format, "global");
252 /* port module event counters */
253 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
254 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
256 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
257 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
259 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
262 /* per channel counters */
263 for (i = 0; i < priv->channels.num; i++)
264 for (j = 0; j < NUM_RQ_STATS; j++)
265 sprintf(data + (idx++) * ETH_GSTRING_LEN,
266 rq_stats_desc[j].format, i);
268 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
269 for (i = 0; i < priv->channels.num; i++)
270 for (j = 0; j < NUM_SQ_STATS; j++)
271 sprintf(data + (idx++) * ETH_GSTRING_LEN,
272 sq_stats_desc[j].format,
273 priv->channel_tc2txq[i][tc]);
276 static void mlx5e_get_strings(struct net_device *dev,
277 uint32_t stringset, uint8_t *data)
279 struct mlx5e_priv *priv = netdev_priv(dev);
283 case ETH_SS_PRIV_FLAGS:
284 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
285 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
289 for (i = 0; i < mlx5e_self_test_num(priv); i++)
290 strcpy(data + i * ETH_GSTRING_LEN,
291 mlx5e_self_tests[i]);
295 mlx5e_fill_stats_strings(priv, data);
300 static void mlx5e_get_ethtool_stats(struct net_device *dev,
301 struct ethtool_stats *stats, u64 *data)
303 struct mlx5e_priv *priv = netdev_priv(dev);
304 struct mlx5e_channels *channels;
305 struct mlx5_priv *mlx5_priv;
306 int i, j, tc, prio, idx = 0;
307 unsigned long pfc_combined;
312 mutex_lock(&priv->state_lock);
313 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
314 mlx5e_update_stats(priv);
315 channels = &priv->channels;
316 mutex_unlock(&priv->state_lock);
318 for (i = 0; i < NUM_SW_COUNTERS; i++)
319 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
322 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
323 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
326 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
327 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
328 vport_stats_desc, i);
330 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
331 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
332 pport_802_3_stats_desc, i);
334 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
335 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
336 pport_2863_stats_desc, i);
338 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
339 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
340 pport_2819_stats_desc, i);
342 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
343 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
344 pport_phy_statistical_stats_desc, i);
346 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
347 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
348 pcie_perf_stats_desc, i);
350 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
351 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
352 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
353 pport_per_prio_traffic_stats_desc, i);
356 pfc_combined = mlx5e_query_pfc_combined(priv);
357 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
358 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
359 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
360 pport_per_prio_pfc_stats_desc, i);
364 if (mlx5e_query_global_pause_combined(priv)) {
365 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
366 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
367 pport_per_prio_pfc_stats_desc, i);
371 /* port module event counters */
372 mlx5_priv = &priv->mdev->priv;
373 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
374 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
375 mlx5e_pme_status_desc, i);
377 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
378 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
379 mlx5e_pme_error_desc, i);
381 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
384 /* per channel counters */
385 for (i = 0; i < channels->num; i++)
386 for (j = 0; j < NUM_RQ_STATS; j++)
388 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
391 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
392 for (i = 0; i < channels->num; i++)
393 for (j = 0; j < NUM_SQ_STATS; j++)
394 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
398 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
406 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
409 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
410 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
411 wqe_size = stride_size * num_strides;
413 packets_per_wqe = wqe_size /
414 ALIGN(ETH_DATA_LEN, stride_size);
415 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
418 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
427 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
430 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
431 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
432 wqe_size = stride_size * num_strides;
434 num_packets = (1 << order_base_2(num_packets));
436 packets_per_wqe = wqe_size /
437 ALIGN(ETH_DATA_LEN, stride_size);
438 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
439 return 1 << (order_base_2(num_wqes));
442 static void mlx5e_get_ringparam(struct net_device *dev,
443 struct ethtool_ringparam *param)
445 struct mlx5e_priv *priv = netdev_priv(dev);
446 int rq_wq_type = priv->channels.params.rq_wq_type;
448 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
449 1 << mlx5_max_log_rq_size(rq_wq_type));
450 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
451 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
452 1 << priv->channels.params.log_rq_size);
453 param->tx_pending = 1 << priv->channels.params.log_sq_size;
456 static int mlx5e_set_ringparam(struct net_device *dev,
457 struct ethtool_ringparam *param)
459 struct mlx5e_priv *priv = netdev_priv(dev);
460 int rq_wq_type = priv->channels.params.rq_wq_type;
461 struct mlx5e_channels new_channels = {};
470 if (param->rx_jumbo_pending) {
471 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
475 if (param->rx_mini_pending) {
476 netdev_info(dev, "%s: rx_mini_pending not supported\n",
481 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
482 1 << mlx5_min_log_rq_size(rq_wq_type));
483 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
484 1 << mlx5_max_log_rq_size(rq_wq_type));
485 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
488 if (param->rx_pending < min_rq_size) {
489 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
490 __func__, param->rx_pending,
494 if (param->rx_pending > max_rq_size) {
495 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
496 __func__, param->rx_pending,
501 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
502 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
503 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
504 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
505 __func__, param->rx_pending);
509 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
510 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
511 __func__, param->tx_pending,
512 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
515 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
516 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
517 __func__, param->tx_pending,
518 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
522 log_rq_size = order_base_2(rx_pending_wqes);
523 log_sq_size = order_base_2(param->tx_pending);
525 if (log_rq_size == priv->channels.params.log_rq_size &&
526 log_sq_size == priv->channels.params.log_sq_size)
529 mutex_lock(&priv->state_lock);
531 new_channels.params = priv->channels.params;
532 new_channels.params.log_rq_size = log_rq_size;
533 new_channels.params.log_sq_size = log_sq_size;
535 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
536 priv->channels.params = new_channels.params;
540 err = mlx5e_open_channels(priv, &new_channels);
544 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
547 mutex_unlock(&priv->state_lock);
552 static void mlx5e_get_channels(struct net_device *dev,
553 struct ethtool_channels *ch)
555 struct mlx5e_priv *priv = netdev_priv(dev);
557 ch->max_combined = priv->profile->max_nch(priv->mdev);
558 ch->combined_count = priv->channels.params.num_channels;
561 static int mlx5e_set_channels(struct net_device *dev,
562 struct ethtool_channels *ch)
564 struct mlx5e_priv *priv = netdev_priv(dev);
565 unsigned int count = ch->combined_count;
566 struct mlx5e_channels new_channels = {};
571 netdev_info(dev, "%s: combined_count=0 not supported\n",
576 if (priv->channels.params.num_channels == count)
579 mutex_lock(&priv->state_lock);
581 new_channels.params = priv->channels.params;
582 new_channels.params.num_channels = count;
583 mlx5e_build_default_indir_rqt(priv->mdev, new_channels.params.indirection_rqt,
584 MLX5E_INDIR_RQT_SIZE, count);
586 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
587 priv->channels.params = new_channels.params;
591 /* Create fresh channels with new parameters */
592 err = mlx5e_open_channels(priv, &new_channels);
596 arfs_enabled = dev->features & NETIF_F_NTUPLE;
598 mlx5e_arfs_disable(priv);
600 /* Switch to new channels, set new parameters and close old ones */
601 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
604 err = mlx5e_arfs_enable(priv);
606 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
611 mutex_unlock(&priv->state_lock);
616 static int mlx5e_get_coalesce(struct net_device *netdev,
617 struct ethtool_coalesce *coal)
619 struct mlx5e_priv *priv = netdev_priv(netdev);
621 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
624 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
625 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
626 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
627 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
628 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
634 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
636 struct mlx5_core_dev *mdev = priv->mdev;
640 for (i = 0; i < priv->channels.num; ++i) {
641 struct mlx5e_channel *c = priv->channels.c[i];
643 for (tc = 0; tc < c->num_tc; tc++) {
644 mlx5_core_modify_cq_moderation(mdev,
646 coal->tx_coalesce_usecs,
647 coal->tx_max_coalesced_frames);
650 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
651 coal->rx_coalesce_usecs,
652 coal->rx_max_coalesced_frames);
656 static int mlx5e_set_coalesce(struct net_device *netdev,
657 struct ethtool_coalesce *coal)
659 struct mlx5e_priv *priv = netdev_priv(netdev);
660 struct mlx5_core_dev *mdev = priv->mdev;
661 struct mlx5e_channels new_channels = {};
665 if (!MLX5_CAP_GEN(mdev, cq_moderation))
668 mutex_lock(&priv->state_lock);
669 new_channels.params = priv->channels.params;
671 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
672 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
673 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
674 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
675 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
677 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
678 priv->channels.params = new_channels.params;
683 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
685 mlx5e_set_priv_channels_coalesce(priv, coal);
686 priv->channels.params = new_channels.params;
690 /* open fresh channels with new coal parameters */
691 err = mlx5e_open_channels(priv, &new_channels);
695 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
698 mutex_unlock(&priv->state_lock);
702 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
705 unsigned long proto_cap = eth_proto_cap;
708 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
709 bitmap_or(supported_modes, supported_modes,
710 ptys2ethtool_table[proto].supported,
711 __ETHTOOL_LINK_MODE_MASK_NBITS);
714 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
717 unsigned long proto_cap = eth_proto_cap;
720 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
721 bitmap_or(advertising_modes, advertising_modes,
722 ptys2ethtool_table[proto].advertised,
723 __ETHTOOL_LINK_MODE_MASK_NBITS);
726 static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
729 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
730 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
731 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
732 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
733 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
734 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
735 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
738 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
739 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
740 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
741 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
742 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
743 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
747 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
754 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
758 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
759 if (proto_cap & MLX5E_PROT_MASK(i))
760 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
766 static void get_speed_duplex(struct net_device *netdev,
768 struct ethtool_link_ksettings *link_ksettings)
771 u32 speed = SPEED_UNKNOWN;
772 u8 duplex = DUPLEX_UNKNOWN;
774 if (!netif_carrier_ok(netdev))
777 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
778 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
779 speed = ptys2ethtool_table[i].speed;
780 duplex = DUPLEX_FULL;
785 link_ksettings->base.speed = speed;
786 link_ksettings->base.duplex = duplex;
789 static void get_supported(u32 eth_proto_cap,
790 struct ethtool_link_ksettings *link_ksettings)
792 unsigned long *supported = link_ksettings->link_modes.supported;
794 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
795 ptys2ethtool_supported_link(supported, eth_proto_cap);
796 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
799 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
801 struct ethtool_link_ksettings *link_ksettings)
803 unsigned long *advertising = link_ksettings->link_modes.advertising;
805 ptys2ethtool_adver_link(advertising, eth_proto_cap);
807 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
808 if (tx_pause ^ rx_pause)
809 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
812 static u8 get_connector_port(u32 eth_proto)
814 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
815 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
816 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
817 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
821 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
822 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
823 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
827 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
828 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
829 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
830 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
837 static void get_lp_advertising(u32 eth_proto_lp,
838 struct ethtool_link_ksettings *link_ksettings)
840 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
842 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
845 static int mlx5e_get_link_ksettings(struct net_device *netdev,
846 struct ethtool_link_ksettings *link_ksettings)
848 struct mlx5e_priv *priv = netdev_priv(netdev);
849 struct mlx5_core_dev *mdev = priv->mdev;
850 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
861 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
863 netdev_err(netdev, "%s: query port ptys failed: %d\n",
868 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
869 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
870 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
871 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
872 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
873 an_status = MLX5_GET(ptys_reg, out, an_status);
875 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
877 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
878 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
880 get_supported(eth_proto_cap, link_ksettings);
881 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
882 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
884 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
886 link_ksettings->base.port = get_connector_port(eth_proto_oper);
887 get_lp_advertising(eth_proto_lp, link_ksettings);
889 if (an_status == MLX5_AN_COMPLETE)
890 ethtool_link_ksettings_add_link_mode(link_ksettings,
891 lp_advertising, Autoneg);
893 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
895 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
897 if (!an_disable_admin)
898 ethtool_link_ksettings_add_link_mode(link_ksettings,
899 advertising, Autoneg);
905 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
907 u32 i, ptys_modes = 0;
909 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
910 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
912 __ETHTOOL_LINK_MODE_MASK_NBITS))
913 ptys_modes |= MLX5E_PROT_MASK(i);
919 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
921 u32 i, speed_links = 0;
923 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
924 if (ptys2ethtool_table[i].speed == speed)
925 speed_links |= MLX5E_PROT_MASK(i);
931 static int mlx5e_set_link_ksettings(struct net_device *netdev,
932 const struct ethtool_link_ksettings *link_ksettings)
934 struct mlx5e_priv *priv = netdev_priv(netdev);
935 struct mlx5_core_dev *mdev = priv->mdev;
936 u32 eth_proto_cap, eth_proto_admin;
937 bool an_changes = false;
946 speed = link_ksettings->base.speed;
948 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
949 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
950 mlx5e_ethtool2ptys_speed_link(speed);
952 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
954 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
959 link_modes = link_modes & eth_proto_cap;
961 netdev_err(netdev, "%s: Not supported link mode(s) requested",
967 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
969 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
974 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
975 &an_disable_cap, &an_disable_admin);
977 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
978 an_changes = ((!an_disable && an_disable_admin) ||
979 (an_disable && !an_disable_admin));
981 if (!an_changes && link_modes == eth_proto_admin)
984 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
985 mlx5_toggle_port_link(mdev);
991 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
993 struct mlx5e_priv *priv = netdev_priv(netdev);
995 return sizeof(priv->channels.params.toeplitz_hash_key);
998 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1000 return MLX5E_INDIR_RQT_SIZE;
1003 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1006 struct mlx5e_priv *priv = netdev_priv(netdev);
1009 memcpy(indir, priv->channels.params.indirection_rqt,
1010 sizeof(priv->channels.params.indirection_rqt));
1013 memcpy(key, priv->channels.params.toeplitz_hash_key,
1014 sizeof(priv->channels.params.toeplitz_hash_key));
1017 *hfunc = priv->channels.params.rss_hfunc;
1022 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1024 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1025 struct mlx5_core_dev *mdev = priv->mdev;
1026 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
1029 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
1031 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1032 memset(tirc, 0, ctxlen);
1033 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
1034 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1038 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1039 const u8 *key, const u8 hfunc)
1041 struct mlx5e_priv *priv = netdev_priv(dev);
1042 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1043 bool hash_changed = false;
1046 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1047 (hfunc != ETH_RSS_HASH_XOR) &&
1048 (hfunc != ETH_RSS_HASH_TOP))
1051 in = mlx5_vzalloc(inlen);
1055 mutex_lock(&priv->state_lock);
1057 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
1058 hfunc != priv->channels.params.rss_hfunc) {
1059 priv->channels.params.rss_hfunc = hfunc;
1060 hash_changed = true;
1064 memcpy(priv->channels.params.indirection_rqt, indir,
1065 sizeof(priv->channels.params.indirection_rqt));
1067 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1068 u32 rqtn = priv->indir_rqt.rqtn;
1069 struct mlx5e_redirect_rqt_param rrp = {
1073 .hfunc = priv->channels.params.rss_hfunc,
1074 .channels = &priv->channels,
1079 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1084 memcpy(priv->channels.params.toeplitz_hash_key, key,
1085 sizeof(priv->channels.params.toeplitz_hash_key));
1086 hash_changed = hash_changed ||
1087 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1091 mlx5e_modify_tirs_hash(priv, in, inlen);
1093 mutex_unlock(&priv->state_lock);
1100 static int mlx5e_get_rxnfc(struct net_device *netdev,
1101 struct ethtool_rxnfc *info, u32 *rule_locs)
1103 struct mlx5e_priv *priv = netdev_priv(netdev);
1106 switch (info->cmd) {
1107 case ETHTOOL_GRXRINGS:
1108 info->data = priv->channels.params.num_channels;
1110 case ETHTOOL_GRXCLSRLCNT:
1111 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1113 case ETHTOOL_GRXCLSRULE:
1114 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1116 case ETHTOOL_GRXCLSRLALL:
1117 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1127 static int mlx5e_get_tunable(struct net_device *dev,
1128 const struct ethtool_tunable *tuna,
1131 const struct mlx5e_priv *priv = netdev_priv(dev);
1135 case ETHTOOL_TX_COPYBREAK:
1136 *(u32 *)data = priv->channels.params.tx_max_inline;
1146 static int mlx5e_set_tunable(struct net_device *dev,
1147 const struct ethtool_tunable *tuna,
1150 struct mlx5e_priv *priv = netdev_priv(dev);
1151 struct mlx5_core_dev *mdev = priv->mdev;
1152 struct mlx5e_channels new_channels = {};
1156 mutex_lock(&priv->state_lock);
1159 case ETHTOOL_TX_COPYBREAK:
1161 if (val > mlx5e_get_max_inline_cap(mdev)) {
1166 new_channels.params = priv->channels.params;
1167 new_channels.params.tx_max_inline = val;
1169 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1170 priv->channels.params = new_channels.params;
1174 err = mlx5e_open_channels(priv, &new_channels);
1177 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1185 mutex_unlock(&priv->state_lock);
1189 static void mlx5e_get_pauseparam(struct net_device *netdev,
1190 struct ethtool_pauseparam *pauseparam)
1192 struct mlx5e_priv *priv = netdev_priv(netdev);
1193 struct mlx5_core_dev *mdev = priv->mdev;
1196 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1197 &pauseparam->tx_pause);
1199 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1204 static int mlx5e_set_pauseparam(struct net_device *netdev,
1205 struct ethtool_pauseparam *pauseparam)
1207 struct mlx5e_priv *priv = netdev_priv(netdev);
1208 struct mlx5_core_dev *mdev = priv->mdev;
1211 if (pauseparam->autoneg)
1214 err = mlx5_set_port_pause(mdev,
1215 pauseparam->rx_pause ? 1 : 0,
1216 pauseparam->tx_pause ? 1 : 0);
1218 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1225 static int mlx5e_get_ts_info(struct net_device *dev,
1226 struct ethtool_ts_info *info)
1228 struct mlx5e_priv *priv = netdev_priv(dev);
1231 ret = ethtool_op_get_ts_info(dev, info);
1235 info->phc_index = priv->tstamp.ptp ?
1236 ptp_clock_index(priv->tstamp.ptp) : -1;
1238 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1241 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1242 SOF_TIMESTAMPING_RX_HARDWARE |
1243 SOF_TIMESTAMPING_RAW_HARDWARE;
1245 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1246 (BIT(1) << HWTSTAMP_TX_ON);
1248 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1249 (BIT(1) << HWTSTAMP_FILTER_ALL);
1254 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1258 if (MLX5_CAP_GEN(mdev, wol_g))
1261 if (MLX5_CAP_GEN(mdev, wol_s))
1262 ret |= WAKE_MAGICSECURE;
1264 if (MLX5_CAP_GEN(mdev, wol_a))
1267 if (MLX5_CAP_GEN(mdev, wol_b))
1270 if (MLX5_CAP_GEN(mdev, wol_m))
1273 if (MLX5_CAP_GEN(mdev, wol_u))
1276 if (MLX5_CAP_GEN(mdev, wol_p))
1282 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1286 if (mode & MLX5_WOL_MAGIC)
1289 if (mode & MLX5_WOL_SECURED_MAGIC)
1290 ret |= WAKE_MAGICSECURE;
1292 if (mode & MLX5_WOL_ARP)
1295 if (mode & MLX5_WOL_BROADCAST)
1298 if (mode & MLX5_WOL_MULTICAST)
1301 if (mode & MLX5_WOL_UNICAST)
1304 if (mode & MLX5_WOL_PHY_ACTIVITY)
1310 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1314 if (mode & WAKE_MAGIC)
1315 ret |= MLX5_WOL_MAGIC;
1317 if (mode & WAKE_MAGICSECURE)
1318 ret |= MLX5_WOL_SECURED_MAGIC;
1320 if (mode & WAKE_ARP)
1321 ret |= MLX5_WOL_ARP;
1323 if (mode & WAKE_BCAST)
1324 ret |= MLX5_WOL_BROADCAST;
1326 if (mode & WAKE_MCAST)
1327 ret |= MLX5_WOL_MULTICAST;
1329 if (mode & WAKE_UCAST)
1330 ret |= MLX5_WOL_UNICAST;
1332 if (mode & WAKE_PHY)
1333 ret |= MLX5_WOL_PHY_ACTIVITY;
1338 static void mlx5e_get_wol(struct net_device *netdev,
1339 struct ethtool_wolinfo *wol)
1341 struct mlx5e_priv *priv = netdev_priv(netdev);
1342 struct mlx5_core_dev *mdev = priv->mdev;
1346 memset(wol, 0, sizeof(*wol));
1348 wol->supported = mlx5e_get_wol_supported(mdev);
1349 if (!wol->supported)
1352 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1356 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1359 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1361 struct mlx5e_priv *priv = netdev_priv(netdev);
1362 struct mlx5_core_dev *mdev = priv->mdev;
1363 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1369 if (wol->wolopts & ~wol_supported)
1372 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1374 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1377 static int mlx5e_set_phys_id(struct net_device *dev,
1378 enum ethtool_phys_id_state state)
1380 struct mlx5e_priv *priv = netdev_priv(dev);
1381 struct mlx5_core_dev *mdev = priv->mdev;
1382 u16 beacon_duration;
1384 if (!MLX5_CAP_GEN(mdev, beacon_led))
1388 case ETHTOOL_ID_ACTIVE:
1389 beacon_duration = MLX5_BEACON_DURATION_INF;
1391 case ETHTOOL_ID_INACTIVE:
1392 beacon_duration = MLX5_BEACON_DURATION_OFF;
1398 return mlx5_set_port_beacon(mdev, beacon_duration);
1401 static int mlx5e_get_module_info(struct net_device *netdev,
1402 struct ethtool_modinfo *modinfo)
1404 struct mlx5e_priv *priv = netdev_priv(netdev);
1405 struct mlx5_core_dev *dev = priv->mdev;
1409 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1413 /* data[0] = identifier byte */
1415 case MLX5_MODULE_ID_QSFP:
1416 modinfo->type = ETH_MODULE_SFF_8436;
1417 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1419 case MLX5_MODULE_ID_QSFP_PLUS:
1420 case MLX5_MODULE_ID_QSFP28:
1421 /* data[1] = revision id */
1422 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1423 modinfo->type = ETH_MODULE_SFF_8636;
1424 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1426 modinfo->type = ETH_MODULE_SFF_8436;
1427 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1430 case MLX5_MODULE_ID_SFP:
1431 modinfo->type = ETH_MODULE_SFF_8472;
1432 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1435 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1443 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1444 struct ethtool_eeprom *ee,
1447 struct mlx5e_priv *priv = netdev_priv(netdev);
1448 struct mlx5_core_dev *mdev = priv->mdev;
1449 int offset = ee->offset;
1456 memset(data, 0, ee->len);
1458 while (i < ee->len) {
1459 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1466 if (size_read < 0) {
1467 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1468 __func__, size_read);
1473 offset += size_read;
1479 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1481 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1483 struct mlx5e_priv *priv = netdev_priv(netdev);
1484 struct mlx5_core_dev *mdev = priv->mdev;
1485 struct mlx5e_channels new_channels = {};
1486 bool rx_mode_changed;
1487 u8 rx_cq_period_mode;
1490 rx_cq_period_mode = enable ?
1491 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1492 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1493 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
1495 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1496 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1499 if (!rx_mode_changed)
1502 new_channels.params = priv->channels.params;
1503 mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
1505 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1506 priv->channels.params = new_channels.params;
1510 err = mlx5e_open_channels(priv, &new_channels);
1514 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1518 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1520 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1521 struct mlx5e_channels new_channels = {};
1524 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1525 return new_val ? -EOPNOTSUPP : 0;
1527 if (curr_val == new_val)
1530 new_channels.params = priv->channels.params;
1531 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1533 mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,
1534 new_channels.params.rq_wq_type);
1536 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1537 priv->channels.params = new_channels.params;
1541 err = mlx5e_open_channels(priv, &new_channels);
1545 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1549 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1552 struct mlx5e_priv *priv = netdev_priv(netdev);
1553 struct mlx5_core_dev *mdev = priv->mdev;
1555 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1558 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1559 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1563 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1564 priv->channels.params.rx_cqe_compress_def = enable;
1569 static int mlx5e_handle_pflag(struct net_device *netdev,
1571 enum mlx5e_priv_flag flag,
1572 mlx5e_pflag_handler pflag_handler)
1574 struct mlx5e_priv *priv = netdev_priv(netdev);
1575 bool enable = !!(wanted_flags & flag);
1576 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1579 if (!(changes & flag))
1582 err = pflag_handler(netdev, enable);
1584 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1585 enable ? "Enable" : "Disable", flag, err);
1589 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1593 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1595 struct mlx5e_priv *priv = netdev_priv(netdev);
1598 mutex_lock(&priv->state_lock);
1599 err = mlx5e_handle_pflag(netdev, pflags,
1600 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1601 set_pflag_rx_cqe_based_moder);
1605 err = mlx5e_handle_pflag(netdev, pflags,
1606 MLX5E_PFLAG_RX_CQE_COMPRESS,
1607 set_pflag_rx_cqe_compress);
1610 mutex_unlock(&priv->state_lock);
1614 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1616 struct mlx5e_priv *priv = netdev_priv(netdev);
1618 return priv->channels.params.pflags;
1621 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1624 struct mlx5e_priv *priv = netdev_priv(dev);
1627 case ETHTOOL_SRXCLSRLINS:
1628 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1630 case ETHTOOL_SRXCLSRLDEL:
1631 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1641 const struct ethtool_ops mlx5e_ethtool_ops = {
1642 .get_drvinfo = mlx5e_get_drvinfo,
1643 .get_link = ethtool_op_get_link,
1644 .get_strings = mlx5e_get_strings,
1645 .get_sset_count = mlx5e_get_sset_count,
1646 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1647 .get_ringparam = mlx5e_get_ringparam,
1648 .set_ringparam = mlx5e_set_ringparam,
1649 .get_channels = mlx5e_get_channels,
1650 .set_channels = mlx5e_set_channels,
1651 .get_coalesce = mlx5e_get_coalesce,
1652 .set_coalesce = mlx5e_set_coalesce,
1653 .get_link_ksettings = mlx5e_get_link_ksettings,
1654 .set_link_ksettings = mlx5e_set_link_ksettings,
1655 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1656 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1657 .get_rxfh = mlx5e_get_rxfh,
1658 .set_rxfh = mlx5e_set_rxfh,
1659 .get_rxnfc = mlx5e_get_rxnfc,
1660 .set_rxnfc = mlx5e_set_rxnfc,
1661 .get_tunable = mlx5e_get_tunable,
1662 .set_tunable = mlx5e_set_tunable,
1663 .get_pauseparam = mlx5e_get_pauseparam,
1664 .set_pauseparam = mlx5e_set_pauseparam,
1665 .get_ts_info = mlx5e_get_ts_info,
1666 .set_phys_id = mlx5e_set_phys_id,
1667 .get_wol = mlx5e_get_wol,
1668 .set_wol = mlx5e_set_wol,
1669 .get_module_info = mlx5e_get_module_info,
1670 .get_module_eeprom = mlx5e_get_module_eeprom,
1671 .get_priv_flags = mlx5e_get_priv_flags,
1672 .set_priv_flags = mlx5e_set_priv_flags,
1673 .self_test = mlx5e_self_test,