drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41 #include "vxlan.h"
  42
  43 struct mlx5e_rq_param {
  44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  45         struct mlx5_wq_param    wq;
  46         bool                    am_enabled;
  47 };
  48
  49 struct mlx5e_sq_param {
  50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  51         struct mlx5_wq_param       wq;
  52         u16                        max_inline;
  53         u8                         min_inline_mode;
  54         enum mlx5e_sq_type         type;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         return MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79 }
  80
  81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  82 {
  83         priv->params.rq_wq_type = rq_type;
  84         switch (priv->params.rq_wq_type) {
  85         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  86                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  87                 priv->params.mpwqe_log_stride_sz =
  88                         MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
  89                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
  90                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
  91                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  92                         priv->params.mpwqe_log_stride_sz;
  93                 break;
  94         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  95                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  96         }
  97         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
  98                                                BIT(priv->params.log_rq_size));
  99
 100         mlx5_core_info(priv->mdev,
 101                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 102                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 103                        BIT(priv->params.log_rq_size),
 104                        BIT(priv->params.mpwqe_log_stride_sz),
 105                        MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
 106 }
 107
 108 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 109 {
 110         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 111                     !priv->xdp_prog ?
 112                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 113                     MLX5_WQ_TYPE_LINKED_LIST;
 114         mlx5e_set_rq_type_params(priv, rq_type);
 115 }
 116
 117 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 118 {
 119         struct mlx5_core_dev *mdev = priv->mdev;
 120         u8 port_state;
 121
 122         port_state = mlx5_query_vport_state(mdev,
 123                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 124
 125         if (port_state == VPORT_STATE_UP) {
 126                 netdev_info(priv->netdev, "Link up\n");
 127                 netif_carrier_on(priv->netdev);
 128         } else {
 129                 netdev_info(priv->netdev, "Link down\n");
 130                 netif_carrier_off(priv->netdev);
 131         }
 132 }
 133
 134 static void mlx5e_update_carrier_work(struct work_struct *work)
 135 {
 136         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 137                                                update_carrier_work);
 138
 139         mutex_lock(&priv->state_lock);
 140         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 141                 mlx5e_update_carrier(priv);
 142         mutex_unlock(&priv->state_lock);
 143 }
 144
 145 static void mlx5e_tx_timeout_work(struct work_struct *work)
 146 {
 147         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 148                                                tx_timeout_work);
 149         int err;
 150
 151         rtnl_lock();
 152         mutex_lock(&priv->state_lock);
 153         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 154                 goto unlock;
 155         mlx5e_close_locked(priv->netdev);
 156         err = mlx5e_open_locked(priv->netdev);
 157         if (err)
 158                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 159                            err);
 160 unlock:
 161         mutex_unlock(&priv->state_lock);
 162         rtnl_unlock();
 163 }
 164
 165 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 166 {
 167         struct mlx5e_sw_stats *s = &priv->stats.sw;
 168         struct mlx5e_rq_stats *rq_stats;
 169         struct mlx5e_sq_stats *sq_stats;
 170         u64 tx_offload_none = 0;
 171         int i, j;
 172
 173         memset(s, 0, sizeof(*s));
 174         for (i = 0; i < priv->params.num_channels; i++) {
 175                 rq_stats = &priv->channel[i]->rq.stats;
 176
 177                 s->rx_packets   += rq_stats->packets;
 178                 s->rx_bytes     += rq_stats->bytes;
 179                 s->rx_lro_packets += rq_stats->lro_packets;
 180                 s->rx_lro_bytes += rq_stats->lro_bytes;
 181                 s->rx_csum_none += rq_stats->csum_none;
 182                 s->rx_csum_complete += rq_stats->csum_complete;
 183                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 184                 s->rx_xdp_drop += rq_stats->xdp_drop;
 185                 s->rx_xdp_tx += rq_stats->xdp_tx;
 186                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 187                 s->rx_wqe_err   += rq_stats->wqe_err;
 188                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 189                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 190                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 191                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 192                 s->rx_cache_reuse += rq_stats->cache_reuse;
 193                 s->rx_cache_full  += rq_stats->cache_full;
 194                 s->rx_cache_empty += rq_stats->cache_empty;
 195                 s->rx_cache_busy  += rq_stats->cache_busy;
 196
 197                 for (j = 0; j < priv->params.num_tc; j++) {
 198                         sq_stats = &priv->channel[i]->sq[j].stats;
 199
 200                         s->tx_packets           += sq_stats->packets;
 201                         s->tx_bytes             += sq_stats->bytes;
 202                         s->tx_tso_packets       += sq_stats->tso_packets;
 203                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 204                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 205                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 206                         s->tx_queue_stopped     += sq_stats->stopped;
 207                         s->tx_queue_wake        += sq_stats->wake;
 208                         s->tx_queue_dropped     += sq_stats->dropped;
 209                         s->tx_xmit_more         += sq_stats->xmit_more;
 210                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 211                         tx_offload_none         += sq_stats->csum_none;
 212                 }
 213         }
 214
 215         /* Update calculated offload counters */
 216         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 217         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 218
 219         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 220                                 priv->stats.pport.phy_counters,
 221                                 counter_set.phys_layer_cntrs.link_down_events);
 222 }
 223
 224 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 225 {
 226         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 227         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 228         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 229         struct mlx5_core_dev *mdev = priv->mdev;
 230
 231         MLX5_SET(query_vport_counter_in, in, opcode,
 232                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 233         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 234         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 235
 236         memset(out, 0, outlen);
 237         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 238 }
 239
 240 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 241 {
 242         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 243         struct mlx5_core_dev *mdev = priv->mdev;
 244         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 245         int prio;
 246         void *out;
 247         u32 *in;
 248
 249         in = mlx5_vzalloc(sz);
 250         if (!in)
 251                 goto free_out;
 252
 253         MLX5_SET(ppcnt_reg, in, local_port, 1);
 254
 255         out = pstats->IEEE_802_3_counters;
 256         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 257         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 258
 259         out = pstats->RFC_2863_counters;
 260         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 261         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 262
 263         out = pstats->RFC_2819_counters;
 264         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 265         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 266
 267         out = pstats->phy_counters;
 268         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 269         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 270
 271         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 272         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 273                 out = pstats->per_prio_counters[prio];
 274                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 275                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 276                                      MLX5_REG_PPCNT, 0, 0);
 277         }
 278
 279 free_out:
 280         kvfree(in);
 281 }
 282
 283 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 284 {
 285         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 286
 287         if (!priv->q_counter)
 288                 return;
 289
 290         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 291                                       &qcnt->rx_out_of_buffer);
 292 }
 293
 294 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 295 {
 296         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
 297         struct mlx5_core_dev *mdev = priv->mdev;
 298         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 299         void *out;
 300         u32 *in;
 301
 302         in = mlx5_vzalloc(sz);
 303         if (!in)
 304                 return;
 305
 306         out = pcie_stats->pcie_perf_counters;
 307         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 308         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 309
 310         out = pcie_stats->pcie_tas_counters;
 311         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 312         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 313
 314         kvfree(in);
 315 }
 316
 317 void mlx5e_update_stats(struct mlx5e_priv *priv)
 318 {
 319         mlx5e_update_q_counter(priv);
 320         mlx5e_update_vport_counters(priv);
 321         mlx5e_update_pport_counters(priv);
 322         mlx5e_update_sw_counters(priv);
 323         mlx5e_update_pcie_counters(priv);
 324 }
 325
 326 void mlx5e_update_stats_work(struct work_struct *work)
 327 {
 328         struct delayed_work *dwork = to_delayed_work(work);
 329         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 330                                                update_stats_work);
 331         mutex_lock(&priv->state_lock);
 332         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 333                 priv->profile->update_stats(priv);
 334                 queue_delayed_work(priv->wq, dwork,
 335                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 336         }
 337         mutex_unlock(&priv->state_lock);
 338 }
 339
 340 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 341                               enum mlx5_dev_event event, unsigned long param)
 342 {
 343         struct mlx5e_priv *priv = vpriv;
 344
 345         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 346                 return;
 347
 348         switch (event) {
 349         case MLX5_DEV_EVENT_PORT_UP:
 350         case MLX5_DEV_EVENT_PORT_DOWN:
 351                 queue_work(priv->wq, &priv->update_carrier_work);
 352                 break;
 353
 354         default:
 355                 break;
 356         }
 357 }
 358
 359 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 360 {
 361         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 362 }
 363
 364 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 365 {
 366         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 367         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 368 }
 369
 370 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 371 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 372
 373 static inline int mlx5e_get_wqe_mtt_sz(void)
 374 {
 375         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 376          * To avoid copying garbage after the mtt array, we allocate
 377          * a little more.
 378          */
 379         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 380                      MLX5_UMR_MTT_ALIGNMENT);
 381 }
 382
 383 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 384                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 385 {
 386         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 387         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 388         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 389         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 390         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 391         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 392
 393         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 394                                       ds_cnt);
 395         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 396         cseg->imm       = rq->mkey_be;
 397
 398         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 399         ucseg->klm_octowords =
 400                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 401         ucseg->bsf_octowords =
 402                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 403         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 404
 405         dseg->lkey = sq->mkey_be;
 406         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 407 }
 408
 409 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 410                                      struct mlx5e_channel *c)
 411 {
 412         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 413         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 414         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 415         int i;
 416
 417         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 418                                       GFP_KERNEL, cpu_to_node(c->cpu));
 419         if (!rq->mpwqe.info)
 420                 goto err_out;
 421
 422         /* We allocate more than mtt_sz as we will align the pointer */
 423         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 424                                         cpu_to_node(c->cpu));
 425         if (unlikely(!rq->mpwqe.mtt_no_align))
 426                 goto err_free_wqe_info;
 427
 428         for (i = 0; i < wq_sz; i++) {
 429                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 430
 431                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 432                                         MLX5_UMR_ALIGN);
 433                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 434                                                   PCI_DMA_TODEVICE);
 435                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 436                         goto err_unmap_mtts;
 437
 438                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 439         }
 440
 441         return 0;
 442
 443 err_unmap_mtts:
 444         while (--i >= 0) {
 445                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 446
 447                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 448                                  PCI_DMA_TODEVICE);
 449         }
 450         kfree(rq->mpwqe.mtt_no_align);
 451 err_free_wqe_info:
 452         kfree(rq->mpwqe.info);
 453
 454 err_out:
 455         return -ENOMEM;
 456 }
 457
 458 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 459 {
 460         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 461         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 462         int i;
 463
 464         for (i = 0; i < wq_sz; i++) {
 465                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 466
 467                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 468                                  PCI_DMA_TODEVICE);
 469         }
 470         kfree(rq->mpwqe.mtt_no_align);
 471         kfree(rq->mpwqe.info);
 472 }
 473
 474 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
 475                                  u64 npages, u8 page_shift,
 476                                  struct mlx5_core_mkey *umr_mkey)
 477 {
 478         struct mlx5_core_dev *mdev = priv->mdev;
 479         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 480         void *mkc;
 481         u32 *in;
 482         int err;
 483
 484         if (!MLX5E_VALID_NUM_MTTS(npages))
 485                 return -EINVAL;
 486
 487         in = mlx5_vzalloc(inlen);
 488         if (!in)
 489                 return -ENOMEM;
 490
 491         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 492
 493         MLX5_SET(mkc, mkc, free, 1);
 494         MLX5_SET(mkc, mkc, umr_en, 1);
 495         MLX5_SET(mkc, mkc, lw, 1);
 496         MLX5_SET(mkc, mkc, lr, 1);
 497         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 498
 499         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 500         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 501         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 502         MLX5_SET(mkc, mkc, translations_octword_size,
 503                  MLX5_MTT_OCTW(npages));
 504         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 505
 506         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 507
 508         kvfree(in);
 509         return err;
 510 }
 511
 512 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
 513 {
 514         struct mlx5e_priv *priv = rq->priv;
 515         u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
 516
 517         return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 518 }
 519
 520 static int mlx5e_create_rq(struct mlx5e_channel *c,
 521                            struct mlx5e_rq_param *param,
 522                            struct mlx5e_rq *rq)
 523 {
 524         struct mlx5e_priv *priv = c->priv;
 525         struct mlx5_core_dev *mdev = priv->mdev;
 526         void *rqc = param->rqc;
 527         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 528         u32 byte_count;
 529         u32 frag_sz;
 530         int npages;
 531         int wq_sz;
 532         int err;
 533         int i;
 534
 535         param->wq.db_numa_node = cpu_to_node(c->cpu);
 536
 537         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 538                                 &rq->wq_ctrl);
 539         if (err)
 540                 return err;
 541
 542         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 543
 544         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 545
 546         rq->wq_type = priv->params.rq_wq_type;
 547         rq->pdev    = c->pdev;
 548         rq->netdev  = c->netdev;
 549         rq->tstamp  = &priv->tstamp;
 550         rq->channel = c;
 551         rq->ix      = c->ix;
 552         rq->priv    = c->priv;
 553
 554         rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
 555         if (IS_ERR(rq->xdp_prog)) {
 556                 err = PTR_ERR(rq->xdp_prog);
 557                 rq->xdp_prog = NULL;
 558                 goto err_rq_wq_destroy;
 559         }
 560
 561         rq->buff.map_dir = DMA_FROM_DEVICE;
 562         if (rq->xdp_prog)
 563                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 564
 565         switch (priv->params.rq_wq_type) {
 566         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 567                 if (mlx5e_is_vf_vport_rep(priv)) {
 568                         err = -EINVAL;
 569                         goto err_rq_wq_destroy;
 570                 }
 571
 572                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 573                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 574                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 575
 576                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 577                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 578
 579                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 580                 byte_count = rq->buff.wqe_sz;
 581
 582                 err = mlx5e_create_rq_umr_mkey(rq);
 583                 if (err)
 584                         goto err_rq_wq_destroy;
 585                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 586
 587                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 588                 if (err)
 589                         goto err_destroy_umr_mkey;
 590                 break;
 591         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 592                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 593                                             GFP_KERNEL, cpu_to_node(c->cpu));
 594                 if (!rq->dma_info) {
 595                         err = -ENOMEM;
 596                         goto err_rq_wq_destroy;
 597                 }
 598
 599                 if (mlx5e_is_vf_vport_rep(priv))
 600                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 601                 else
 602                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 603
 604                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 605                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 606
 607                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 608                                 priv->params.lro_wqe_sz :
 609                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 610                 byte_count = rq->buff.wqe_sz;
 611
 612                 /* calc the required page order */
 613                 frag_sz = MLX5_RX_HEADROOM +
 614                           byte_count /* packet data */ +
 615                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 616                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 617
 618                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 619                 rq->buff.page_order = order_base_2(npages);
 620
 621                 byte_count |= MLX5_HW_START_PADDING;
 622                 rq->mkey_be = c->mkey_be;
 623         }
 624
 625         for (i = 0; i < wq_sz; i++) {
 626                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 627
 628                 wqe->data.byte_count = cpu_to_be32(byte_count);
 629                 wqe->data.lkey = rq->mkey_be;
 630         }
 631
 632         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 633         rq->am.mode = priv->params.rx_cq_period_mode;
 634
 635         rq->page_cache.head = 0;
 636         rq->page_cache.tail = 0;
 637
 638         return 0;
 639
 640 err_destroy_umr_mkey:
 641         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 642
 643 err_rq_wq_destroy:
 644         if (rq->xdp_prog)
 645                 bpf_prog_put(rq->xdp_prog);
 646         mlx5_wq_destroy(&rq->wq_ctrl);
 647
 648         return err;
 649 }
 650
 651 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 652 {
 653         int i;
 654
 655         if (rq->xdp_prog)
 656                 bpf_prog_put(rq->xdp_prog);
 657
 658         switch (rq->wq_type) {
 659         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 660                 mlx5e_rq_free_mpwqe_info(rq);
 661                 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
 662                 break;
 663         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 664                 kfree(rq->dma_info);
 665         }
 666
 667         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 668              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 669                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 670
 671                 mlx5e_page_release(rq, dma_info, false);
 672         }
 673         mlx5_wq_destroy(&rq->wq_ctrl);
 674 }
 675
 676 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 677 {
 678         struct mlx5e_priv *priv = rq->priv;
 679         struct mlx5_core_dev *mdev = priv->mdev;
 680
 681         void *in;
 682         void *rqc;
 683         void *wq;
 684         int inlen;
 685         int err;
 686
 687         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 688                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 689         in = mlx5_vzalloc(inlen);
 690         if (!in)
 691                 return -ENOMEM;
 692
 693         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 694         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 695
 696         memcpy(rqc, param->rqc, sizeof(param->rqc));
 697
 698         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 699         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 700         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 701         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 702                                                 MLX5_ADAPTER_PAGE_SHIFT);
 703         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 704
 705         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 706                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 707
 708         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 709
 710         kvfree(in);
 711
 712         return err;
 713 }
 714
 715 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 716                                  int next_state)
 717 {
 718         struct mlx5e_channel *c = rq->channel;
 719         struct mlx5e_priv *priv = c->priv;
 720         struct mlx5_core_dev *mdev = priv->mdev;
 721
 722         void *in;
 723         void *rqc;
 724         int inlen;
 725         int err;
 726
 727         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 728         in = mlx5_vzalloc(inlen);
 729         if (!in)
 730                 return -ENOMEM;
 731
 732         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 733
 734         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 735         MLX5_SET(rqc, rqc, state, next_state);
 736
 737         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 738
 739         kvfree(in);
 740
 741         return err;
 742 }
 743
 744 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 745 {
 746         struct mlx5e_channel *c = rq->channel;
 747         struct mlx5e_priv *priv = c->priv;
 748         struct mlx5_core_dev *mdev = priv->mdev;
 749
 750         void *in;
 751         void *rqc;
 752         int inlen;
 753         int err;
 754
 755         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 756         in = mlx5_vzalloc(inlen);
 757         if (!in)
 758                 return -ENOMEM;
 759
 760         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 761
 762         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 763         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 764                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 765         MLX5_SET(rqc, rqc, vsd, vsd);
 766         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 767
 768         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 769
 770         kvfree(in);
 771
 772         return err;
 773 }
 774
 775 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 776 {
 777         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 778 }
 779
 780 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 781 {
 782         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 783         struct mlx5e_channel *c = rq->channel;
 784         struct mlx5e_priv *priv = c->priv;
 785         struct mlx5_wq_ll *wq = &rq->wq;
 786
 787         while (time_before(jiffies, exp_time)) {
 788                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 789                         return 0;
 790
 791                 msleep(20);
 792         }
 793
 794         return -ETIMEDOUT;
 795 }
 796
 797 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 798 {
 799         struct mlx5_wq_ll *wq = &rq->wq;
 800         struct mlx5e_rx_wqe *wqe;
 801         __be16 wqe_ix_be;
 802         u16 wqe_ix;
 803
 804         /* UMR WQE (if in progress) is always at wq->head */
 805         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 806                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 807
 808         while (!mlx5_wq_ll_is_empty(wq)) {
 809                 wqe_ix_be = *wq->tail_next;
 810                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 811                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 812                 rq->dealloc_wqe(rq, wqe_ix);
 813                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 814                                &wqe->next.next_wqe_index);
 815         }
 816 }
 817
 818 static int mlx5e_open_rq(struct mlx5e_channel *c,
 819                          struct mlx5e_rq_param *param,
 820                          struct mlx5e_rq *rq)
 821 {
 822         struct mlx5e_sq *sq = &c->icosq;
 823         u16 pi = sq->pc & sq->wq.sz_m1;
 824         int err;
 825
 826         err = mlx5e_create_rq(c, param, rq);
 827         if (err)
 828                 return err;
 829
 830         err = mlx5e_enable_rq(rq, param);
 831         if (err)
 832                 goto err_destroy_rq;
 833
 834         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 835         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 836         if (err)
 837                 goto err_disable_rq;
 838
 839         if (param->am_enabled)
 840                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 841
 842         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 843         sq->db.ico_wqe[pi].num_wqebbs = 1;
 844         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 845
 846         return 0;
 847
 848 err_disable_rq:
 849         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 850         mlx5e_disable_rq(rq);
 851 err_destroy_rq:
 852         mlx5e_destroy_rq(rq);
 853
 854         return err;
 855 }
 856
 857 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 858 {
 859         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 860         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 861         cancel_work_sync(&rq->am.work);
 862
 863         mlx5e_disable_rq(rq);
 864         mlx5e_free_rx_descs(rq);
 865         mlx5e_destroy_rq(rq);
 866 }
 867
 868 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 869 {
 870         kfree(sq->db.xdp.di);
 871         kfree(sq->db.xdp.wqe_info);
 872 }
 873
 874 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 875 {
 876         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 877
 878         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 879                                      GFP_KERNEL, numa);
 880         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 881                                            GFP_KERNEL, numa);
 882         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 883                 mlx5e_free_sq_xdp_db(sq);
 884                 return -ENOMEM;
 885         }
 886
 887         return 0;
 888 }
 889
 890 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 891 {
 892         kfree(sq->db.ico_wqe);
 893 }
 894
 895 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 896 {
 897         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 898
 899         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 900                                       GFP_KERNEL, numa);
 901         if (!sq->db.ico_wqe)
 902                 return -ENOMEM;
 903
 904         return 0;
 905 }
 906
 907 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 908 {
 909         kfree(sq->db.txq.wqe_info);
 910         kfree(sq->db.txq.dma_fifo);
 911         kfree(sq->db.txq.skb);
 912 }
 913
 914 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 915 {
 916         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 917         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 918
 919         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 920                                       GFP_KERNEL, numa);
 921         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 922                                            GFP_KERNEL, numa);
 923         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 924                                            GFP_KERNEL, numa);
 925         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 926                 mlx5e_free_sq_txq_db(sq);
 927                 return -ENOMEM;
 928         }
 929
 930         sq->dma_fifo_mask = df_sz - 1;
 931
 932         return 0;
 933 }
 934
 935 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 936 {
 937         switch (sq->type) {
 938         case MLX5E_SQ_TXQ:
 939                 mlx5e_free_sq_txq_db(sq);
 940                 break;
 941         case MLX5E_SQ_ICO:
 942                 mlx5e_free_sq_ico_db(sq);
 943                 break;
 944         case MLX5E_SQ_XDP:
 945                 mlx5e_free_sq_xdp_db(sq);
 946                 break;
 947         }
 948 }
 949
 950 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 951 {
 952         switch (sq->type) {
 953         case MLX5E_SQ_TXQ:
 954                 return mlx5e_alloc_sq_txq_db(sq, numa);
 955         case MLX5E_SQ_ICO:
 956                 return mlx5e_alloc_sq_ico_db(sq, numa);
 957         case MLX5E_SQ_XDP:
 958                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 959         }
 960
 961         return 0;
 962 }
 963
 964 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 965 {
 966         switch (sq_type) {
 967         case MLX5E_SQ_ICO:
 968                 return MLX5E_ICOSQ_MAX_WQEBBS;
 969         case MLX5E_SQ_XDP:
 970                 return MLX5E_XDP_TX_WQEBBS;
 971         }
 972         return MLX5_SEND_WQE_MAX_WQEBBS;
 973 }
 974
 975 static int mlx5e_create_sq(struct mlx5e_channel *c,
 976                            int tc,
 977                            struct mlx5e_sq_param *param,
 978                            struct mlx5e_sq *sq)
 979 {
 980         struct mlx5e_priv *priv = c->priv;
 981         struct mlx5_core_dev *mdev = priv->mdev;
 982
 983         void *sqc = param->sqc;
 984         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 985         int err;
 986
 987         sq->type      = param->type;
 988         sq->pdev      = c->pdev;
 989         sq->tstamp    = &priv->tstamp;
 990         sq->mkey_be   = c->mkey_be;
 991         sq->channel   = c;
 992         sq->tc        = tc;
 993
 994         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 995         if (err)
 996                 return err;
 997
 998         param->wq.db_numa_node = cpu_to_node(c->cpu);
 999
1000         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1001                                  &sq->wq_ctrl);
1002         if (err)
1003                 goto err_unmap_free_uar;
1004
1005         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
1006         if (sq->uar.bf_map) {
1007                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1008                 sq->uar_map = sq->uar.bf_map;
1009         } else {
1010                 sq->uar_map = sq->uar.map;
1011         }
1012         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1013         sq->max_inline  = param->max_inline;
1014         sq->min_inline_mode =
1015                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
1016                 param->min_inline_mode : 0;
1017
1018         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1019         if (err)
1020                 goto err_sq_wq_destroy;
1021
1022         if (sq->type == MLX5E_SQ_TXQ) {
1023                 int txq_ix;
1024
1025                 txq_ix = c->ix + tc * priv->params.num_channels;
1026                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1027                 priv->txq_to_sq_map[txq_ix] = sq;
1028         }
1029
1030         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1031         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1032
1033         return 0;
1034
1035 err_sq_wq_destroy:
1036         mlx5_wq_destroy(&sq->wq_ctrl);
1037
1038 err_unmap_free_uar:
1039         mlx5_unmap_free_uar(mdev, &sq->uar);
1040
1041         return err;
1042 }
1043
1044 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1045 {
1046         struct mlx5e_channel *c = sq->channel;
1047         struct mlx5e_priv *priv = c->priv;
1048
1049         mlx5e_free_sq_db(sq);
1050         mlx5_wq_destroy(&sq->wq_ctrl);
1051         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1052 }
1053
1054 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1055 {
1056         struct mlx5e_channel *c = sq->channel;
1057         struct mlx5e_priv *priv = c->priv;
1058         struct mlx5_core_dev *mdev = priv->mdev;
1059
1060         void *in;
1061         void *sqc;
1062         void *wq;
1063         int inlen;
1064         int err;
1065
1066         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1067                 sizeof(u64) * sq->wq_ctrl.buf.npages;
1068         in = mlx5_vzalloc(inlen);
1069         if (!in)
1070                 return -ENOMEM;
1071
1072         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1073         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1074
1075         memcpy(sqc, param->sqc, sizeof(param->sqc));
1076
1077         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1078                                        0 : priv->tisn[sq->tc]);
1079         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1080         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1081         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1082         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1083
1084         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1085         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
1086         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1087                                           MLX5_ADAPTER_PAGE_SHIFT);
1088         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1089
1090         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1091                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1092
1093         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1094
1095         kvfree(in);
1096
1097         return err;
1098 }
1099
1100 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1101                            int next_state, bool update_rl, int rl_index)
1102 {
1103         struct mlx5e_channel *c = sq->channel;
1104         struct mlx5e_priv *priv = c->priv;
1105         struct mlx5_core_dev *mdev = priv->mdev;
1106
1107         void *in;
1108         void *sqc;
1109         int inlen;
1110         int err;
1111
1112         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1113         in = mlx5_vzalloc(inlen);
1114         if (!in)
1115                 return -ENOMEM;
1116
1117         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1118
1119         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1120         MLX5_SET(sqc, sqc, state, next_state);
1121         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1122                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1123                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1124         }
1125
1126         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1127
1128         kvfree(in);
1129
1130         return err;
1131 }
1132
1133 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1134 {
1135         struct mlx5e_channel *c = sq->channel;
1136         struct mlx5e_priv *priv = c->priv;
1137         struct mlx5_core_dev *mdev = priv->mdev;
1138
1139         mlx5_core_destroy_sq(mdev, sq->sqn);
1140         if (sq->rate_limit)
1141                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1142 }
1143
1144 static int mlx5e_open_sq(struct mlx5e_channel *c,
1145                          int tc,
1146                          struct mlx5e_sq_param *param,
1147                          struct mlx5e_sq *sq)
1148 {
1149         int err;
1150
1151         err = mlx5e_create_sq(c, tc, param, sq);
1152         if (err)
1153                 return err;
1154
1155         err = mlx5e_enable_sq(sq, param);
1156         if (err)
1157                 goto err_destroy_sq;
1158
1159         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1160         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1161                               false, 0);
1162         if (err)
1163                 goto err_disable_sq;
1164
1165         if (sq->txq) {
1166                 netdev_tx_reset_queue(sq->txq);
1167                 netif_tx_start_queue(sq->txq);
1168         }
1169
1170         return 0;
1171
1172 err_disable_sq:
1173         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1174         mlx5e_disable_sq(sq);
1175 err_destroy_sq:
1176         mlx5e_destroy_sq(sq);
1177
1178         return err;
1179 }
1180
1181 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1182 {
1183         __netif_tx_lock_bh(txq);
1184         netif_tx_stop_queue(txq);
1185         __netif_tx_unlock_bh(txq);
1186 }
1187
1188 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1189 {
1190         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1191         /* prevent netif_tx_wake_queue */
1192         napi_synchronize(&sq->channel->napi);
1193
1194         if (sq->txq) {
1195                 netif_tx_disable_queue(sq->txq);
1196
1197                 /* last doorbell out, godspeed .. */
1198                 if (mlx5e_sq_has_room_for(sq, 1)) {
1199                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1200                         mlx5e_send_nop(sq, true);
1201                 }
1202         }
1203
1204         mlx5e_disable_sq(sq);
1205         mlx5e_free_sq_descs(sq);
1206         mlx5e_destroy_sq(sq);
1207 }
1208
1209 static int mlx5e_create_cq(struct mlx5e_channel *c,
1210                            struct mlx5e_cq_param *param,
1211                            struct mlx5e_cq *cq)
1212 {
1213         struct mlx5e_priv *priv = c->priv;
1214         struct mlx5_core_dev *mdev = priv->mdev;
1215         struct mlx5_core_cq *mcq = &cq->mcq;
1216         int eqn_not_used;
1217         unsigned int irqn;
1218         int err;
1219         u32 i;
1220
1221         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1222         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1223         param->eq_ix   = c->ix;
1224
1225         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1226                                &cq->wq_ctrl);
1227         if (err)
1228                 return err;
1229
1230         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1231
1232         cq->napi        = &c->napi;
1233
1234         mcq->cqe_sz     = 64;
1235         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1236         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1237         *mcq->set_ci_db = 0;
1238         *mcq->arm_db    = 0;
1239         mcq->vector     = param->eq_ix;
1240         mcq->comp       = mlx5e_completion_event;
1241         mcq->event      = mlx5e_cq_error_event;
1242         mcq->irqn       = irqn;
1243         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1244
1245         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1246                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1247
1248                 cqe->op_own = 0xf1;
1249         }
1250
1251         cq->channel = c;
1252         cq->priv = priv;
1253
1254         return 0;
1255 }
1256
1257 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1258 {
1259         mlx5_cqwq_destroy(&cq->wq_ctrl);
1260 }
1261
1262 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1263 {
1264         struct mlx5e_priv *priv = cq->priv;
1265         struct mlx5_core_dev *mdev = priv->mdev;
1266         struct mlx5_core_cq *mcq = &cq->mcq;
1267
1268         void *in;
1269         void *cqc;
1270         int inlen;
1271         unsigned int irqn_not_used;
1272         int eqn;
1273         int err;
1274
1275         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1276                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1277         in = mlx5_vzalloc(inlen);
1278         if (!in)
1279                 return -ENOMEM;
1280
1281         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1282
1283         memcpy(cqc, param->cqc, sizeof(param->cqc));
1284
1285         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1286                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1287
1288         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1289
1290         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1291         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1292         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1293         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1294                                             MLX5_ADAPTER_PAGE_SHIFT);
1295         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1296
1297         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1298
1299         kvfree(in);
1300
1301         if (err)
1302                 return err;
1303
1304         mlx5e_cq_arm(cq);
1305
1306         return 0;
1307 }
1308
1309 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1310 {
1311         struct mlx5e_priv *priv = cq->priv;
1312         struct mlx5_core_dev *mdev = priv->mdev;
1313
1314         mlx5_core_destroy_cq(mdev, &cq->mcq);
1315 }
1316
1317 static int mlx5e_open_cq(struct mlx5e_channel *c,
1318                          struct mlx5e_cq_param *param,
1319                          struct mlx5e_cq *cq,
1320                          struct mlx5e_cq_moder moderation)
1321 {
1322         int err;
1323         struct mlx5e_priv *priv = c->priv;
1324         struct mlx5_core_dev *mdev = priv->mdev;
1325
1326         err = mlx5e_create_cq(c, param, cq);
1327         if (err)
1328                 return err;
1329
1330         err = mlx5e_enable_cq(cq, param);
1331         if (err)
1332                 goto err_destroy_cq;
1333
1334         if (MLX5_CAP_GEN(mdev, cq_moderation))
1335                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1336                                                moderation.usec,
1337                                                moderation.pkts);
1338         return 0;
1339
1340 err_destroy_cq:
1341         mlx5e_destroy_cq(cq);
1342
1343         return err;
1344 }
1345
1346 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1347 {
1348         mlx5e_disable_cq(cq);
1349         mlx5e_destroy_cq(cq);
1350 }
1351
1352 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1353 {
1354         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1355 }
1356
1357 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1358                              struct mlx5e_channel_param *cparam)
1359 {
1360         struct mlx5e_priv *priv = c->priv;
1361         int err;
1362         int tc;
1363
1364         for (tc = 0; tc < c->num_tc; tc++) {
1365                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1366                                     priv->params.tx_cq_moderation);
1367                 if (err)
1368                         goto err_close_tx_cqs;
1369         }
1370
1371         return 0;
1372
1373 err_close_tx_cqs:
1374         for (tc--; tc >= 0; tc--)
1375                 mlx5e_close_cq(&c->sq[tc].cq);
1376
1377         return err;
1378 }
1379
1380 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1381 {
1382         int tc;
1383
1384         for (tc = 0; tc < c->num_tc; tc++)
1385                 mlx5e_close_cq(&c->sq[tc].cq);
1386 }
1387
1388 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1389                           struct mlx5e_channel_param *cparam)
1390 {
1391         int err;
1392         int tc;
1393
1394         for (tc = 0; tc < c->num_tc; tc++) {
1395                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1396                 if (err)
1397                         goto err_close_sqs;
1398         }
1399
1400         return 0;
1401
1402 err_close_sqs:
1403         for (tc--; tc >= 0; tc--)
1404                 mlx5e_close_sq(&c->sq[tc]);
1405
1406         return err;
1407 }
1408
1409 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1410 {
1411         int tc;
1412
1413         for (tc = 0; tc < c->num_tc; tc++)
1414                 mlx5e_close_sq(&c->sq[tc]);
1415 }
1416
1417 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1418 {
1419         int i;
1420
1421         for (i = 0; i < priv->profile->max_tc; i++)
1422                 priv->channeltc_to_txq_map[ix][i] =
1423                         ix + i * priv->params.num_channels;
1424 }
1425
1426 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1427                                 struct mlx5e_sq *sq, u32 rate)
1428 {
1429         struct mlx5e_priv *priv = netdev_priv(dev);
1430         struct mlx5_core_dev *mdev = priv->mdev;
1431         u16 rl_index = 0;
1432         int err;
1433
1434         if (rate == sq->rate_limit)
1435                 /* nothing to do */
1436                 return 0;
1437
1438         if (sq->rate_limit)
1439                 /* remove current rl index to free space to next ones */
1440                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1441
1442         sq->rate_limit = 0;
1443
1444         if (rate) {
1445                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1446                 if (err) {
1447                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1448                                    rate, err);
1449                         return err;
1450                 }
1451         }
1452
1453         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1454                               MLX5_SQC_STATE_RDY, true, rl_index);
1455         if (err) {
1456                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1457                            rate, err);
1458                 /* remove the rate from the table */
1459                 if (rate)
1460                         mlx5_rl_remove_rate(mdev, rate);
1461                 return err;
1462         }
1463
1464         sq->rate_limit = rate;
1465         return 0;
1466 }
1467
1468 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1469 {
1470         struct mlx5e_priv *priv = netdev_priv(dev);
1471         struct mlx5_core_dev *mdev = priv->mdev;
1472         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1473         int err = 0;
1474
1475         if (!mlx5_rl_is_supported(mdev)) {
1476                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1477                 return -EINVAL;
1478         }
1479
1480         /* rate is given in Mb/sec, HW config is in Kb/sec */
1481         rate = rate << 10;
1482
1483         /* Check whether rate in valid range, 0 is always valid */
1484         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1485                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1486                 return -ERANGE;
1487         }
1488
1489         mutex_lock(&priv->state_lock);
1490         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1491                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1492         if (!err)
1493                 priv->tx_rates[index] = rate;
1494         mutex_unlock(&priv->state_lock);
1495
1496         return err;
1497 }
1498
1499 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1500                               struct mlx5e_channel_param *cparam,
1501                               struct mlx5e_channel **cp)
1502 {
1503         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1504         struct net_device *netdev = priv->netdev;
1505         struct mlx5e_cq_moder rx_cq_profile;
1506         int cpu = mlx5e_get_cpu(priv, ix);
1507         struct mlx5e_channel *c;
1508         struct mlx5e_sq *sq;
1509         int err;
1510         int i;
1511
1512         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1513         if (!c)
1514                 return -ENOMEM;
1515
1516         c->priv     = priv;
1517         c->ix       = ix;
1518         c->cpu      = cpu;
1519         c->pdev     = &priv->mdev->pdev->dev;
1520         c->netdev   = priv->netdev;
1521         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1522         c->num_tc   = priv->params.num_tc;
1523         c->xdp      = !!priv->xdp_prog;
1524
1525         if (priv->params.rx_am_enabled)
1526                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1527         else
1528                 rx_cq_profile = priv->params.rx_cq_moderation;
1529
1530         mlx5e_build_channeltc_to_txq_map(priv, ix);
1531
1532         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1533
1534         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1535         if (err)
1536                 goto err_napi_del;
1537
1538         err = mlx5e_open_tx_cqs(c, cparam);
1539         if (err)
1540                 goto err_close_icosq_cq;
1541
1542         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1543                             rx_cq_profile);
1544         if (err)
1545                 goto err_close_tx_cqs;
1546
1547         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1548         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1549                                      priv->params.tx_cq_moderation) : 0;
1550         if (err)
1551                 goto err_close_rx_cq;
1552
1553         napi_enable(&c->napi);
1554
1555         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1556         if (err)
1557                 goto err_disable_napi;
1558
1559         err = mlx5e_open_sqs(c, cparam);
1560         if (err)
1561                 goto err_close_icosq;
1562
1563         for (i = 0; i < priv->params.num_tc; i++) {
1564                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1565
1566                 if (priv->tx_rates[txq_ix]) {
1567                         sq = priv->txq_to_sq_map[txq_ix];
1568                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1569                                              priv->tx_rates[txq_ix]);
1570                 }
1571         }
1572
1573         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1574         if (err)
1575                 goto err_close_sqs;
1576
1577         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1578         if (err)
1579                 goto err_close_xdp_sq;
1580
1581         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1582         *cp = c;
1583
1584         return 0;
1585 err_close_xdp_sq:
1586         if (c->xdp)
1587                 mlx5e_close_sq(&c->xdp_sq);
1588
1589 err_close_sqs:
1590         mlx5e_close_sqs(c);
1591
1592 err_close_icosq:
1593         mlx5e_close_sq(&c->icosq);
1594
1595 err_disable_napi:
1596         napi_disable(&c->napi);
1597         if (c->xdp)
1598                 mlx5e_close_cq(&c->xdp_sq.cq);
1599
1600 err_close_rx_cq:
1601         mlx5e_close_cq(&c->rq.cq);
1602
1603 err_close_tx_cqs:
1604         mlx5e_close_tx_cqs(c);
1605
1606 err_close_icosq_cq:
1607         mlx5e_close_cq(&c->icosq.cq);
1608
1609 err_napi_del:
1610         netif_napi_del(&c->napi);
1611         kfree(c);
1612
1613         return err;
1614 }
1615
1616 static void mlx5e_close_channel(struct mlx5e_channel *c)
1617 {
1618         mlx5e_close_rq(&c->rq);
1619         if (c->xdp)
1620                 mlx5e_close_sq(&c->xdp_sq);
1621         mlx5e_close_sqs(c);
1622         mlx5e_close_sq(&c->icosq);
1623         napi_disable(&c->napi);
1624         if (c->xdp)
1625                 mlx5e_close_cq(&c->xdp_sq.cq);
1626         mlx5e_close_cq(&c->rq.cq);
1627         mlx5e_close_tx_cqs(c);
1628         mlx5e_close_cq(&c->icosq.cq);
1629         netif_napi_del(&c->napi);
1630
1631         kfree(c);
1632 }
1633
1634 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1635                                  struct mlx5e_rq_param *param)
1636 {
1637         void *rqc = param->rqc;
1638         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1639
1640         switch (priv->params.rq_wq_type) {
1641         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1642                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1643                          priv->params.mpwqe_log_num_strides - 9);
1644                 MLX5_SET(wq, wq, log_wqe_stride_size,
1645                          priv->params.mpwqe_log_stride_sz - 6);
1646                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1647                 break;
1648         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1649                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1650         }
1651
1652         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1653         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1654         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1655         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1656         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1657
1658         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1659         param->wq.linear = 1;
1660
1661         param->am_enabled = priv->params.rx_am_enabled;
1662 }
1663
1664 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1665 {
1666         void *rqc = param->rqc;
1667         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1668
1669         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1670         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1671 }
1672
1673 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1674                                         struct mlx5e_sq_param *param)
1675 {
1676         void *sqc = param->sqc;
1677         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1678
1679         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1680         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1681
1682         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1683 }
1684
1685 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1686                                  struct mlx5e_sq_param *param)
1687 {
1688         void *sqc = param->sqc;
1689         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1690
1691         mlx5e_build_sq_param_common(priv, param);
1692         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1693
1694         param->max_inline = priv->params.tx_max_inline;
1695         param->min_inline_mode = priv->params.tx_min_inline_mode;
1696         param->type = MLX5E_SQ_TXQ;
1697 }
1698
1699 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1700                                         struct mlx5e_cq_param *param)
1701 {
1702         void *cqc = param->cqc;
1703
1704         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1705 }
1706
1707 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1708                                     struct mlx5e_cq_param *param)
1709 {
1710         void *cqc = param->cqc;
1711         u8 log_cq_size;
1712
1713         switch (priv->params.rq_wq_type) {
1714         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1715                 log_cq_size = priv->params.log_rq_size +
1716                         priv->params.mpwqe_log_num_strides;
1717                 break;
1718         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1719                 log_cq_size = priv->params.log_rq_size;
1720         }
1721
1722         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1723         if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1724                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1725                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1726         }
1727
1728         mlx5e_build_common_cq_param(priv, param);
1729
1730         param->cq_period_mode = priv->params.rx_cq_period_mode;
1731 }
1732
1733 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1734                                     struct mlx5e_cq_param *param)
1735 {
1736         void *cqc = param->cqc;
1737
1738         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1739
1740         mlx5e_build_common_cq_param(priv, param);
1741
1742         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1743 }
1744
1745 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1746                                      struct mlx5e_cq_param *param,
1747                                      u8 log_wq_size)
1748 {
1749         void *cqc = param->cqc;
1750
1751         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1752
1753         mlx5e_build_common_cq_param(priv, param);
1754
1755         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1756 }
1757
1758 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1759                                     struct mlx5e_sq_param *param,
1760                                     u8 log_wq_size)
1761 {
1762         void *sqc = param->sqc;
1763         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1764
1765         mlx5e_build_sq_param_common(priv, param);
1766
1767         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1768         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1769
1770         param->type = MLX5E_SQ_ICO;
1771 }
1772
1773 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1774                                     struct mlx5e_sq_param *param)
1775 {
1776         void *sqc = param->sqc;
1777         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1778
1779         mlx5e_build_sq_param_common(priv, param);
1780         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1781
1782         param->max_inline = priv->params.tx_max_inline;
1783         /* FOR XDP SQs will support only L2 inline mode */
1784         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1785         param->type = MLX5E_SQ_XDP;
1786 }
1787
1788 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1789 {
1790         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1791
1792         mlx5e_build_rq_param(priv, &cparam->rq);
1793         mlx5e_build_sq_param(priv, &cparam->sq);
1794         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1795         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1796         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1797         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1798         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1799 }
1800
1801 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1802 {
1803         struct mlx5e_channel_param *cparam;
1804         int nch = priv->params.num_channels;
1805         int err = -ENOMEM;
1806         int i;
1807         int j;
1808
1809         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1810                                 GFP_KERNEL);
1811
1812         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1813                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1814
1815         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1816
1817         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1818                 goto err_free_txq_to_sq_map;
1819
1820         mlx5e_build_channel_param(priv, cparam);
1821
1822         for (i = 0; i < nch; i++) {
1823                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1824                 if (err)
1825                         goto err_close_channels;
1826         }
1827
1828         for (j = 0; j < nch; j++) {
1829                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1830                 if (err)
1831                         goto err_close_channels;
1832         }
1833
1834         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1835          * polling for inactive tx queues.
1836          */
1837         netif_tx_start_all_queues(priv->netdev);
1838
1839         kfree(cparam);
1840         return 0;
1841
1842 err_close_channels:
1843         for (i--; i >= 0; i--)
1844                 mlx5e_close_channel(priv->channel[i]);
1845
1846 err_free_txq_to_sq_map:
1847         kfree(priv->txq_to_sq_map);
1848         kfree(priv->channel);
1849         kfree(cparam);
1850
1851         return err;
1852 }
1853
1854 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1855 {
1856         int i;
1857
1858         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1859          * polling for inactive tx queues.
1860          */
1861         netif_tx_stop_all_queues(priv->netdev);
1862         netif_tx_disable(priv->netdev);
1863
1864         for (i = 0; i < priv->params.num_channels; i++)
1865                 mlx5e_close_channel(priv->channel[i]);
1866
1867         kfree(priv->txq_to_sq_map);
1868         kfree(priv->channel);
1869 }
1870
1871 static int mlx5e_rx_hash_fn(int hfunc)
1872 {
1873         return (hfunc == ETH_RSS_HASH_TOP) ?
1874                MLX5_RX_HASH_FN_TOEPLITZ :
1875                MLX5_RX_HASH_FN_INVERTED_XOR8;
1876 }
1877
1878 static int mlx5e_bits_invert(unsigned long a, int size)
1879 {
1880         int inv = 0;
1881         int i;
1882
1883         for (i = 0; i < size; i++)
1884                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1885
1886         return inv;
1887 }
1888
1889 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1890 {
1891         int i;
1892
1893         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1894                 int ix = i;
1895                 u32 rqn;
1896
1897                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1898                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1899
1900                 ix = priv->params.indirection_rqt[ix];
1901                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1902                                 priv->channel[ix]->rq.rqn :
1903                                 priv->drop_rq.rqn;
1904                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1905         }
1906 }
1907
1908 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1909                                       int ix)
1910 {
1911         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1912                         priv->channel[ix]->rq.rqn :
1913                         priv->drop_rq.rqn;
1914
1915         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1916 }
1917
1918 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1919                             int ix, struct mlx5e_rqt *rqt)
1920 {
1921         struct mlx5_core_dev *mdev = priv->mdev;
1922         void *rqtc;
1923         int inlen;
1924         int err;
1925         u32 *in;
1926
1927         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1928         in = mlx5_vzalloc(inlen);
1929         if (!in)
1930                 return -ENOMEM;
1931
1932         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1933
1934         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1935         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1936
1937         if (sz > 1) /* RSS */
1938                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1939         else
1940                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1941
1942         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1943         if (!err)
1944                 rqt->enabled = true;
1945
1946         kvfree(in);
1947         return err;
1948 }
1949
1950 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1951 {
1952         rqt->enabled = false;
1953         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1954 }
1955
1956 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1957 {
1958         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1959
1960         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1961 }
1962
1963 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1964 {
1965         struct mlx5e_rqt *rqt;
1966         int err;
1967         int ix;
1968
1969         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1970                 rqt = &priv->direct_tir[ix].rqt;
1971                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1972                 if (err)
1973                         goto err_destroy_rqts;
1974         }
1975
1976         return 0;
1977
1978 err_destroy_rqts:
1979         for (ix--; ix >= 0; ix--)
1980                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1981
1982         return err;
1983 }
1984
1985 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1986 {
1987         struct mlx5_core_dev *mdev = priv->mdev;
1988         void *rqtc;
1989         int inlen;
1990         u32 *in;
1991         int err;
1992
1993         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1994         in = mlx5_vzalloc(inlen);
1995         if (!in)
1996                 return -ENOMEM;
1997
1998         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1999
2000         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2001         if (sz > 1) /* RSS */
2002                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2003         else
2004                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2005
2006         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2007
2008         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2009
2010         kvfree(in);
2011
2012         return err;
2013 }
2014
2015 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2016 {
2017         u32 rqtn;
2018         int ix;
2019
2020         if (priv->indir_rqt.enabled) {
2021                 rqtn = priv->indir_rqt.rqtn;
2022                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2023         }
2024
2025         for (ix = 0; ix < priv->params.num_channels; ix++) {
2026                 if (!priv->direct_tir[ix].rqt.enabled)
2027                         continue;
2028                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2029                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2030         }
2031 }
2032
2033 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2034 {
2035         if (!priv->params.lro_en)
2036                 return;
2037
2038 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2039
2040         MLX5_SET(tirc, tirc, lro_enable_mask,
2041                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2042                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2043         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2044                  (priv->params.lro_wqe_sz -
2045                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2046         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2047 }
2048
2049 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2050 {
2051         MLX5_SET(tirc, tirc, rx_hash_fn,
2052                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2053         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2054                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2055                                              rx_hash_toeplitz_key);
2056                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2057                                                rx_hash_toeplitz_key);
2058
2059                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2060                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2061         }
2062 }
2063
2064 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2065 {
2066         struct mlx5_core_dev *mdev = priv->mdev;
2067
2068         void *in;
2069         void *tirc;
2070         int inlen;
2071         int err;
2072         int tt;
2073         int ix;
2074
2075         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2076         in = mlx5_vzalloc(inlen);
2077         if (!in)
2078                 return -ENOMEM;
2079
2080         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2081         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2082
2083         mlx5e_build_tir_ctx_lro(tirc, priv);
2084
2085         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2086                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2087                                            inlen);
2088                 if (err)
2089                         goto free_in;
2090         }
2091
2092         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2093                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2094                                            in, inlen);
2095                 if (err)
2096                         goto free_in;
2097         }
2098
2099 free_in:
2100         kvfree(in);
2101
2102         return err;
2103 }
2104
2105 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2106 {
2107         struct mlx5_core_dev *mdev = priv->mdev;
2108         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2109         int err;
2110
2111         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2112         if (err)
2113                 return err;
2114
2115         /* Update vport context MTU */
2116         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2117         return 0;
2118 }
2119
2120 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2121 {
2122         struct mlx5_core_dev *mdev = priv->mdev;
2123         u16 hw_mtu = 0;
2124         int err;
2125
2126         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2127         if (err || !hw_mtu) /* fallback to port oper mtu */
2128                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2129
2130         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2131 }
2132
2133 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2134 {
2135         struct mlx5e_priv *priv = netdev_priv(netdev);
2136         u16 mtu;
2137         int err;
2138
2139         err = mlx5e_set_mtu(priv, netdev->mtu);
2140         if (err)
2141                 return err;
2142
2143         mlx5e_query_mtu(priv, &mtu);
2144         if (mtu != netdev->mtu)
2145                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2146                             __func__, mtu, netdev->mtu);
2147
2148         netdev->mtu = mtu;
2149         return 0;
2150 }
2151
2152 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2153 {
2154         struct mlx5e_priv *priv = netdev_priv(netdev);
2155         int nch = priv->params.num_channels;
2156         int ntc = priv->params.num_tc;
2157         int tc;
2158
2159         netdev_reset_tc(netdev);
2160
2161         if (ntc == 1)
2162                 return;
2163
2164         netdev_set_num_tc(netdev, ntc);
2165
2166         /* Map netdev TCs to offset 0
2167          * We have our own UP to TXQ mapping for QoS
2168          */
2169         for (tc = 0; tc < ntc; tc++)
2170                 netdev_set_tc_queue(netdev, tc, nch, 0);
2171 }
2172
2173 int mlx5e_open_locked(struct net_device *netdev)
2174 {
2175         struct mlx5e_priv *priv = netdev_priv(netdev);
2176         struct mlx5_core_dev *mdev = priv->mdev;
2177         int num_txqs;
2178         int err;
2179
2180         set_bit(MLX5E_STATE_OPENED, &priv->state);
2181
2182         mlx5e_netdev_set_tcs(netdev);
2183
2184         num_txqs = priv->params.num_channels * priv->params.num_tc;
2185         netif_set_real_num_tx_queues(netdev, num_txqs);
2186         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2187
2188         err = mlx5e_open_channels(priv);
2189         if (err) {
2190                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2191                            __func__, err);
2192                 goto err_clear_state_opened_flag;
2193         }
2194
2195         err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2196         if (err) {
2197                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2198                            __func__, err);
2199                 goto err_close_channels;
2200         }
2201
2202         mlx5e_redirect_rqts(priv);
2203         mlx5e_update_carrier(priv);
2204         mlx5e_timestamp_init(priv);
2205 #ifdef CONFIG_RFS_ACCEL
2206         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2207 #endif
2208         if (priv->profile->update_stats)
2209                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2210
2211         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2212                 err = mlx5e_add_sqs_fwd_rules(priv);
2213                 if (err)
2214                         goto err_close_channels;
2215         }
2216         return 0;
2217
2218 err_close_channels:
2219         mlx5e_close_channels(priv);
2220 err_clear_state_opened_flag:
2221         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2222         return err;
2223 }
2224
2225 int mlx5e_open(struct net_device *netdev)
2226 {
2227         struct mlx5e_priv *priv = netdev_priv(netdev);
2228         int err;
2229
2230         mutex_lock(&priv->state_lock);
2231         err = mlx5e_open_locked(netdev);
2232         mutex_unlock(&priv->state_lock);
2233
2234         return err;
2235 }
2236
2237 int mlx5e_close_locked(struct net_device *netdev)
2238 {
2239         struct mlx5e_priv *priv = netdev_priv(netdev);
2240         struct mlx5_core_dev *mdev = priv->mdev;
2241
2242         /* May already be CLOSED in case a previous configuration operation
2243          * (e.g RX/TX queue size change) that involves close&open failed.
2244          */
2245         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2246                 return 0;
2247
2248         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2249
2250         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2251                 mlx5e_remove_sqs_fwd_rules(priv);
2252
2253         mlx5e_timestamp_cleanup(priv);
2254         netif_carrier_off(priv->netdev);
2255         mlx5e_redirect_rqts(priv);
2256         mlx5e_close_channels(priv);
2257
2258         return 0;
2259 }
2260
2261 int mlx5e_close(struct net_device *netdev)
2262 {
2263         struct mlx5e_priv *priv = netdev_priv(netdev);
2264         int err;
2265
2266         if (!netif_device_present(netdev))
2267                 return -ENODEV;
2268
2269         mutex_lock(&priv->state_lock);
2270         err = mlx5e_close_locked(netdev);
2271         mutex_unlock(&priv->state_lock);
2272
2273         return err;
2274 }
2275
2276 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2277                                 struct mlx5e_rq *rq,
2278                                 struct mlx5e_rq_param *param)
2279 {
2280         struct mlx5_core_dev *mdev = priv->mdev;
2281         void *rqc = param->rqc;
2282         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2283         int err;
2284
2285         param->wq.db_numa_node = param->wq.buf_numa_node;
2286
2287         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2288                                 &rq->wq_ctrl);
2289         if (err)
2290                 return err;
2291
2292         rq->priv = priv;
2293
2294         return 0;
2295 }
2296
2297 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2298                                 struct mlx5e_cq *cq,
2299                                 struct mlx5e_cq_param *param)
2300 {
2301         struct mlx5_core_dev *mdev = priv->mdev;
2302         struct mlx5_core_cq *mcq = &cq->mcq;
2303         int eqn_not_used;
2304         unsigned int irqn;
2305         int err;
2306
2307         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2308                                &cq->wq_ctrl);
2309         if (err)
2310                 return err;
2311
2312         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2313
2314         mcq->cqe_sz     = 64;
2315         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2316         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2317         *mcq->set_ci_db = 0;
2318         *mcq->arm_db    = 0;
2319         mcq->vector     = param->eq_ix;
2320         mcq->comp       = mlx5e_completion_event;
2321         mcq->event      = mlx5e_cq_error_event;
2322         mcq->irqn       = irqn;
2323         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2324
2325         cq->priv = priv;
2326
2327         return 0;
2328 }
2329
2330 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2331 {
2332         struct mlx5e_cq_param cq_param;
2333         struct mlx5e_rq_param rq_param;
2334         struct mlx5e_rq *rq = &priv->drop_rq;
2335         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2336         int err;
2337
2338         memset(&cq_param, 0, sizeof(cq_param));
2339         memset(&rq_param, 0, sizeof(rq_param));
2340         mlx5e_build_drop_rq_param(&rq_param);
2341
2342         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2343         if (err)
2344                 return err;
2345
2346         err = mlx5e_enable_cq(cq, &cq_param);
2347         if (err)
2348                 goto err_destroy_cq;
2349
2350         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2351         if (err)
2352                 goto err_disable_cq;
2353
2354         err = mlx5e_enable_rq(rq, &rq_param);
2355         if (err)
2356                 goto err_destroy_rq;
2357
2358         return 0;
2359
2360 err_destroy_rq:
2361         mlx5e_destroy_rq(&priv->drop_rq);
2362
2363 err_disable_cq:
2364         mlx5e_disable_cq(&priv->drop_rq.cq);
2365
2366 err_destroy_cq:
2367         mlx5e_destroy_cq(&priv->drop_rq.cq);
2368
2369         return err;
2370 }
2371
2372 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2373 {
2374         mlx5e_disable_rq(&priv->drop_rq);
2375         mlx5e_destroy_rq(&priv->drop_rq);
2376         mlx5e_disable_cq(&priv->drop_rq.cq);
2377         mlx5e_destroy_cq(&priv->drop_rq.cq);
2378 }
2379
2380 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2381 {
2382         struct mlx5_core_dev *mdev = priv->mdev;
2383         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2384         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2385
2386         MLX5_SET(tisc, tisc, prio, tc << 1);
2387         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2388
2389         if (mlx5_lag_is_lacp_owner(mdev))
2390                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2391
2392         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2393 }
2394
2395 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2396 {
2397         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2398 }
2399
2400 int mlx5e_create_tises(struct mlx5e_priv *priv)
2401 {
2402         int err;
2403         int tc;
2404
2405         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2406                 err = mlx5e_create_tis(priv, tc);
2407                 if (err)
2408                         goto err_close_tises;
2409         }
2410
2411         return 0;
2412
2413 err_close_tises:
2414         for (tc--; tc >= 0; tc--)
2415                 mlx5e_destroy_tis(priv, tc);
2416
2417         return err;
2418 }
2419
2420 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2421 {
2422         int tc;
2423
2424         for (tc = 0; tc < priv->profile->max_tc; tc++)
2425                 mlx5e_destroy_tis(priv, tc);
2426 }
2427
2428 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2429                                       enum mlx5e_traffic_types tt)
2430 {
2431         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2432
2433         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2434
2435 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2436                                  MLX5_HASH_FIELD_SEL_DST_IP)
2437
2438 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2439                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2440                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2441                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2442
2443 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2444                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2445                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2446
2447         mlx5e_build_tir_ctx_lro(tirc, priv);
2448
2449         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2450         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2451         mlx5e_build_tir_ctx_hash(tirc, priv);
2452
2453         switch (tt) {
2454         case MLX5E_TT_IPV4_TCP:
2455                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2456                          MLX5_L3_PROT_TYPE_IPV4);
2457                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2458                          MLX5_L4_PROT_TYPE_TCP);
2459                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2460                          MLX5_HASH_IP_L4PORTS);
2461                 break;
2462
2463         case MLX5E_TT_IPV6_TCP:
2464                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2465                          MLX5_L3_PROT_TYPE_IPV6);
2466                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2467                          MLX5_L4_PROT_TYPE_TCP);
2468                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2469                          MLX5_HASH_IP_L4PORTS);
2470                 break;
2471
2472         case MLX5E_TT_IPV4_UDP:
2473                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2474                          MLX5_L3_PROT_TYPE_IPV4);
2475                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2476                          MLX5_L4_PROT_TYPE_UDP);
2477                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2478                          MLX5_HASH_IP_L4PORTS);
2479                 break;
2480
2481         case MLX5E_TT_IPV6_UDP:
2482                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2483                          MLX5_L3_PROT_TYPE_IPV6);
2484                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2485                          MLX5_L4_PROT_TYPE_UDP);
2486                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2487                          MLX5_HASH_IP_L4PORTS);
2488                 break;
2489
2490         case MLX5E_TT_IPV4_IPSEC_AH:
2491                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2492                          MLX5_L3_PROT_TYPE_IPV4);
2493                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2494                          MLX5_HASH_IP_IPSEC_SPI);
2495                 break;
2496
2497         case MLX5E_TT_IPV6_IPSEC_AH:
2498                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2499                          MLX5_L3_PROT_TYPE_IPV6);
2500                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2501                          MLX5_HASH_IP_IPSEC_SPI);
2502                 break;
2503
2504         case MLX5E_TT_IPV4_IPSEC_ESP:
2505                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2506                          MLX5_L3_PROT_TYPE_IPV4);
2507                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2508                          MLX5_HASH_IP_IPSEC_SPI);
2509                 break;
2510
2511         case MLX5E_TT_IPV6_IPSEC_ESP:
2512                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2513                          MLX5_L3_PROT_TYPE_IPV6);
2514                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2515                          MLX5_HASH_IP_IPSEC_SPI);
2516                 break;
2517
2518         case MLX5E_TT_IPV4:
2519                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2520                          MLX5_L3_PROT_TYPE_IPV4);
2521                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2522                          MLX5_HASH_IP);
2523                 break;
2524
2525         case MLX5E_TT_IPV6:
2526                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2527                          MLX5_L3_PROT_TYPE_IPV6);
2528                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2529                          MLX5_HASH_IP);
2530                 break;
2531         default:
2532                 WARN_ONCE(true,
2533                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2534         }
2535 }
2536
2537 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2538                                        u32 rqtn)
2539 {
2540         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2541
2542         mlx5e_build_tir_ctx_lro(tirc, priv);
2543
2544         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2545         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2546         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2547 }
2548
2549 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2550 {
2551         struct mlx5e_tir *tir;
2552         void *tirc;
2553         int inlen;
2554         int err;
2555         u32 *in;
2556         int tt;
2557
2558         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2559         in = mlx5_vzalloc(inlen);
2560         if (!in)
2561                 return -ENOMEM;
2562
2563         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2564                 memset(in, 0, inlen);
2565                 tir = &priv->indir_tir[tt];
2566                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2567                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2568                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2569                 if (err)
2570                         goto err_destroy_tirs;
2571         }
2572
2573         kvfree(in);
2574
2575         return 0;
2576
2577 err_destroy_tirs:
2578         for (tt--; tt >= 0; tt--)
2579                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2580
2581         kvfree(in);
2582
2583         return err;
2584 }
2585
2586 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2587 {
2588         int nch = priv->profile->max_nch(priv->mdev);
2589         struct mlx5e_tir *tir;
2590         void *tirc;
2591         int inlen;
2592         int err;
2593         u32 *in;
2594         int ix;
2595
2596         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2597         in = mlx5_vzalloc(inlen);
2598         if (!in)
2599                 return -ENOMEM;
2600
2601         for (ix = 0; ix < nch; ix++) {
2602                 memset(in, 0, inlen);
2603                 tir = &priv->direct_tir[ix];
2604                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2605                 mlx5e_build_direct_tir_ctx(priv, tirc,
2606                                            priv->direct_tir[ix].rqt.rqtn);
2607                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2608                 if (err)
2609                         goto err_destroy_ch_tirs;
2610         }
2611
2612         kvfree(in);
2613
2614         return 0;
2615
2616 err_destroy_ch_tirs:
2617         for (ix--; ix >= 0; ix--)
2618                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2619
2620         kvfree(in);
2621
2622         return err;
2623 }
2624
2625 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2626 {
2627         int i;
2628
2629         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2630                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2631 }
2632
2633 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2634 {
2635         int nch = priv->profile->max_nch(priv->mdev);
2636         int i;
2637
2638         for (i = 0; i < nch; i++)
2639                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2640 }
2641
2642 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2643 {
2644         int err = 0;
2645         int i;
2646
2647         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2648                 return 0;
2649
2650         for (i = 0; i < priv->params.num_channels; i++) {
2651                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2652                 if (err)
2653                         return err;
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2660 {
2661         struct mlx5e_priv *priv = netdev_priv(netdev);
2662         bool was_opened;
2663         int err = 0;
2664
2665         if (tc && tc != MLX5E_MAX_NUM_TC)
2666                 return -EINVAL;
2667
2668         mutex_lock(&priv->state_lock);
2669
2670         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2671         if (was_opened)
2672                 mlx5e_close_locked(priv->netdev);
2673
2674         priv->params.num_tc = tc ? tc : 1;
2675
2676         if (was_opened)
2677                 err = mlx5e_open_locked(priv->netdev);
2678
2679         mutex_unlock(&priv->state_lock);
2680
2681         return err;
2682 }
2683
2684 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2685                               __be16 proto, struct tc_to_netdev *tc)
2686 {
2687         struct mlx5e_priv *priv = netdev_priv(dev);
2688
2689         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2690                 goto mqprio;
2691
2692         switch (tc->type) {
2693         case TC_SETUP_CLSFLOWER:
2694                 switch (tc->cls_flower->command) {
2695                 case TC_CLSFLOWER_REPLACE:
2696                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2697                 case TC_CLSFLOWER_DESTROY:
2698                         return mlx5e_delete_flower(priv, tc->cls_flower);
2699                 case TC_CLSFLOWER_STATS:
2700                         return mlx5e_stats_flower(priv, tc->cls_flower);
2701                 }
2702         default:
2703                 return -EOPNOTSUPP;
2704         }
2705
2706 mqprio:
2707         if (tc->type != TC_SETUP_MQPRIO)
2708                 return -EINVAL;
2709
2710         return mlx5e_setup_tc(dev, tc->tc);
2711 }
2712
2713 static struct rtnl_link_stats64 *
2714 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2715 {
2716         struct mlx5e_priv *priv = netdev_priv(dev);
2717         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2718         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2719         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2720
2721         if (mlx5e_is_uplink_rep(priv)) {
2722                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2723                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
2724                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2725                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2726         } else {
2727                 stats->rx_packets = sstats->rx_packets;
2728                 stats->rx_bytes   = sstats->rx_bytes;
2729                 stats->tx_packets = sstats->tx_packets;
2730                 stats->tx_bytes   = sstats->tx_bytes;
2731                 stats->tx_dropped = sstats->tx_queue_dropped;
2732         }
2733
2734         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2735
2736         stats->rx_length_errors =
2737                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2738                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2739                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2740         stats->rx_crc_errors =
2741                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2742         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2743         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2744         stats->tx_carrier_errors =
2745                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2746         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2747                            stats->rx_frame_errors;
2748         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2749
2750         /* vport multicast also counts packets that are dropped due to steering
2751          * or rx out of buffer
2752          */
2753         stats->multicast =
2754                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2755
2756         return stats;
2757 }
2758
2759 static void mlx5e_set_rx_mode(struct net_device *dev)
2760 {
2761         struct mlx5e_priv *priv = netdev_priv(dev);
2762
2763         queue_work(priv->wq, &priv->set_rx_mode_work);
2764 }
2765
2766 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2767 {
2768         struct mlx5e_priv *priv = netdev_priv(netdev);
2769         struct sockaddr *saddr = addr;
2770
2771         if (!is_valid_ether_addr(saddr->sa_data))
2772                 return -EADDRNOTAVAIL;
2773
2774         netif_addr_lock_bh(netdev);
2775         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2776         netif_addr_unlock_bh(netdev);
2777
2778         queue_work(priv->wq, &priv->set_rx_mode_work);
2779
2780         return 0;
2781 }
2782
2783 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2784         do {                                            \
2785                 if (enable)                             \
2786                         netdev->features |= feature;    \
2787                 else                                    \
2788                         netdev->features &= ~feature;   \
2789         } while (0)
2790
2791 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2792
2793 static int set_feature_lro(struct net_device *netdev, bool enable)
2794 {
2795         struct mlx5e_priv *priv = netdev_priv(netdev);
2796         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2797         int err;
2798
2799         mutex_lock(&priv->state_lock);
2800
2801         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2802                 mlx5e_close_locked(priv->netdev);
2803
2804         priv->params.lro_en = enable;
2805         err = mlx5e_modify_tirs_lro(priv);
2806         if (err) {
2807                 netdev_err(netdev, "lro modify failed, %d\n", err);
2808                 priv->params.lro_en = !enable;
2809         }
2810
2811         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2812                 mlx5e_open_locked(priv->netdev);
2813
2814         mutex_unlock(&priv->state_lock);
2815
2816         return err;
2817 }
2818
2819 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2820 {
2821         struct mlx5e_priv *priv = netdev_priv(netdev);
2822
2823         if (enable)
2824                 mlx5e_enable_vlan_filter(priv);
2825         else
2826                 mlx5e_disable_vlan_filter(priv);
2827
2828         return 0;
2829 }
2830
2831 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2832 {
2833         struct mlx5e_priv *priv = netdev_priv(netdev);
2834
2835         if (!enable && mlx5e_tc_num_filters(priv)) {
2836                 netdev_err(netdev,
2837                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2838                 return -EINVAL;
2839         }
2840
2841         return 0;
2842 }
2843
2844 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2845 {
2846         struct mlx5e_priv *priv = netdev_priv(netdev);
2847         struct mlx5_core_dev *mdev = priv->mdev;
2848
2849         return mlx5_set_port_fcs(mdev, !enable);
2850 }
2851
2852 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2853 {
2854         struct mlx5e_priv *priv = netdev_priv(netdev);
2855         int err;
2856
2857         mutex_lock(&priv->state_lock);
2858
2859         priv->params.vlan_strip_disable = !enable;
2860         err = mlx5e_modify_rqs_vsd(priv, !enable);
2861         if (err)
2862                 priv->params.vlan_strip_disable = enable;
2863
2864         mutex_unlock(&priv->state_lock);
2865
2866         return err;
2867 }
2868
2869 #ifdef CONFIG_RFS_ACCEL
2870 static int set_feature_arfs(struct net_device *netdev, bool enable)
2871 {
2872         struct mlx5e_priv *priv = netdev_priv(netdev);
2873         int err;
2874
2875         if (enable)
2876                 err = mlx5e_arfs_enable(priv);
2877         else
2878                 err = mlx5e_arfs_disable(priv);
2879
2880         return err;
2881 }
2882 #endif
2883
2884 static int mlx5e_handle_feature(struct net_device *netdev,
2885                                 netdev_features_t wanted_features,
2886                                 netdev_features_t feature,
2887                                 mlx5e_feature_handler feature_handler)
2888 {
2889         netdev_features_t changes = wanted_features ^ netdev->features;
2890         bool enable = !!(wanted_features & feature);
2891         int err;
2892
2893         if (!(changes & feature))
2894                 return 0;
2895
2896         err = feature_handler(netdev, enable);
2897         if (err) {
2898                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2899                            enable ? "Enable" : "Disable", feature, err);
2900                 return err;
2901         }
2902
2903         MLX5E_SET_FEATURE(netdev, feature, enable);
2904         return 0;
2905 }
2906
2907 static int mlx5e_set_features(struct net_device *netdev,
2908                               netdev_features_t features)
2909 {
2910         int err;
2911
2912         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2913                                     set_feature_lro);
2914         err |= mlx5e_handle_feature(netdev, features,
2915                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2916                                     set_feature_vlan_filter);
2917         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2918                                     set_feature_tc_num_filters);
2919         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2920                                     set_feature_rx_all);
2921         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2922                                     set_feature_rx_vlan);
2923 #ifdef CONFIG_RFS_ACCEL
2924         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2925                                     set_feature_arfs);
2926 #endif
2927
2928         return err ? -EINVAL : 0;
2929 }
2930
2931 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2932 {
2933         struct mlx5e_priv *priv = netdev_priv(netdev);
2934         bool was_opened;
2935         int err = 0;
2936         bool reset;
2937
2938         mutex_lock(&priv->state_lock);
2939
2940         reset = !priv->params.lro_en &&
2941                 (priv->params.rq_wq_type !=
2942                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2943
2944         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2945         if (was_opened && reset)
2946                 mlx5e_close_locked(netdev);
2947
2948         netdev->mtu = new_mtu;
2949         mlx5e_set_dev_port_mtu(netdev);
2950
2951         if (was_opened && reset)
2952                 err = mlx5e_open_locked(netdev);
2953
2954         mutex_unlock(&priv->state_lock);
2955
2956         return err;
2957 }
2958
2959 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2960 {
2961         switch (cmd) {
2962         case SIOCSHWTSTAMP:
2963                 return mlx5e_hwstamp_set(dev, ifr);
2964         case SIOCGHWTSTAMP:
2965                 return mlx5e_hwstamp_get(dev, ifr);
2966         default:
2967                 return -EOPNOTSUPP;
2968         }
2969 }
2970
2971 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2972 {
2973         struct mlx5e_priv *priv = netdev_priv(dev);
2974         struct mlx5_core_dev *mdev = priv->mdev;
2975
2976         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2977 }
2978
2979 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2980                              __be16 vlan_proto)
2981 {
2982         struct mlx5e_priv *priv = netdev_priv(dev);
2983         struct mlx5_core_dev *mdev = priv->mdev;
2984
2985         if (vlan_proto != htons(ETH_P_8021Q))
2986                 return -EPROTONOSUPPORT;
2987
2988         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2989                                            vlan, qos);
2990 }
2991
2992 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2993 {
2994         struct mlx5e_priv *priv = netdev_priv(dev);
2995         struct mlx5_core_dev *mdev = priv->mdev;
2996
2997         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2998 }
2999
3000 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3001 {
3002         struct mlx5e_priv *priv = netdev_priv(dev);
3003         struct mlx5_core_dev *mdev = priv->mdev;
3004
3005         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3006 }
3007
3008 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3009                              int max_tx_rate)
3010 {
3011         struct mlx5e_priv *priv = netdev_priv(dev);
3012         struct mlx5_core_dev *mdev = priv->mdev;
3013
3014         if (min_tx_rate)
3015                 return -EOPNOTSUPP;
3016
3017         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3018                                            max_tx_rate);
3019 }
3020
3021 static int mlx5_vport_link2ifla(u8 esw_link)
3022 {
3023         switch (esw_link) {
3024         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3025                 return IFLA_VF_LINK_STATE_DISABLE;
3026         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3027                 return IFLA_VF_LINK_STATE_ENABLE;
3028         }
3029         return IFLA_VF_LINK_STATE_AUTO;
3030 }
3031
3032 static int mlx5_ifla_link2vport(u8 ifla_link)
3033 {
3034         switch (ifla_link) {
3035         case IFLA_VF_LINK_STATE_DISABLE:
3036                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3037         case IFLA_VF_LINK_STATE_ENABLE:
3038                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3039         }
3040         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3041 }
3042
3043 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3044                                    int link_state)
3045 {
3046         struct mlx5e_priv *priv = netdev_priv(dev);
3047         struct mlx5_core_dev *mdev = priv->mdev;
3048
3049         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3050                                             mlx5_ifla_link2vport(link_state));
3051 }
3052
3053 static int mlx5e_get_vf_config(struct net_device *dev,
3054                                int vf, struct ifla_vf_info *ivi)
3055 {
3056         struct mlx5e_priv *priv = netdev_priv(dev);
3057         struct mlx5_core_dev *mdev = priv->mdev;
3058         int err;
3059
3060         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3061         if (err)
3062                 return err;
3063         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3064         return 0;
3065 }
3066
3067 static int mlx5e_get_vf_stats(struct net_device *dev,
3068                               int vf, struct ifla_vf_stats *vf_stats)
3069 {
3070         struct mlx5e_priv *priv = netdev_priv(dev);
3071         struct mlx5_core_dev *mdev = priv->mdev;
3072
3073         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3074                                             vf_stats);
3075 }
3076
3077 void mlx5e_add_vxlan_port(struct net_device *netdev,
3078                           struct udp_tunnel_info *ti)
3079 {
3080         struct mlx5e_priv *priv = netdev_priv(netdev);
3081
3082         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3083                 return;
3084
3085         if (!mlx5e_vxlan_allowed(priv->mdev))
3086                 return;
3087
3088         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3089 }
3090
3091 void mlx5e_del_vxlan_port(struct net_device *netdev,
3092                           struct udp_tunnel_info *ti)
3093 {
3094         struct mlx5e_priv *priv = netdev_priv(netdev);
3095
3096         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3097                 return;
3098
3099         if (!mlx5e_vxlan_allowed(priv->mdev))
3100                 return;
3101
3102         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3103 }
3104
3105 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3106                                                     struct sk_buff *skb,
3107                                                     netdev_features_t features)
3108 {
3109         struct udphdr *udph;
3110         u16 proto;
3111         u16 port = 0;
3112
3113         switch (vlan_get_protocol(skb)) {
3114         case htons(ETH_P_IP):
3115                 proto = ip_hdr(skb)->protocol;
3116                 break;
3117         case htons(ETH_P_IPV6):
3118                 proto = ipv6_hdr(skb)->nexthdr;
3119                 break;
3120         default:
3121                 goto out;
3122         }
3123
3124         if (proto == IPPROTO_UDP) {
3125                 udph = udp_hdr(skb);
3126                 port = be16_to_cpu(udph->dest);
3127         }
3128
3129         /* Verify if UDP port is being offloaded by HW */
3130         if (port && mlx5e_vxlan_lookup_port(priv, port))
3131                 return features;
3132
3133 out:
3134         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3135         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3136 }
3137
3138 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3139                                               struct net_device *netdev,
3140                                               netdev_features_t features)
3141 {
3142         struct mlx5e_priv *priv = netdev_priv(netdev);
3143
3144         features = vlan_features_check(skb, features);
3145         features = vxlan_features_check(skb, features);
3146
3147         /* Validate if the tunneled packet is being offloaded by HW */
3148         if (skb->encapsulation &&
3149             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3150                 return mlx5e_vxlan_features_check(priv, skb, features);
3151
3152         return features;
3153 }
3154
3155 static void mlx5e_tx_timeout(struct net_device *dev)
3156 {
3157         struct mlx5e_priv *priv = netdev_priv(dev);
3158         bool sched_work = false;
3159         int i;
3160
3161         netdev_err(dev, "TX timeout detected\n");
3162
3163         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3164                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3165
3166                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3167                         continue;
3168                 sched_work = true;
3169                 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3170                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3171                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3172         }
3173
3174         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3175                 schedule_work(&priv->tx_timeout_work);
3176 }
3177
3178 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3179 {
3180         struct mlx5e_priv *priv = netdev_priv(netdev);
3181         struct bpf_prog *old_prog;
3182         int err = 0;
3183         bool reset, was_opened;
3184         int i;
3185
3186         if (prog && prog->xdp_adjust_head) {
3187                 netdev_err(netdev, "Does not support bpf_xdp_adjust_head()\n");
3188                 return -EOPNOTSUPP;
3189         }
3190
3191         mutex_lock(&priv->state_lock);
3192
3193         if ((netdev->features & NETIF_F_LRO) && prog) {
3194                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3195                 err = -EINVAL;
3196                 goto unlock;
3197         }
3198
3199         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3200         /* no need for full reset when exchanging programs */
3201         reset = (!priv->xdp_prog || !prog);
3202
3203         if (was_opened && reset)
3204                 mlx5e_close_locked(netdev);
3205         if (was_opened && !reset) {
3206                 /* num_channels is invariant here, so we can take the
3207                  * batched reference right upfront.
3208                  */
3209                 prog = bpf_prog_add(prog, priv->params.num_channels);
3210                 if (IS_ERR(prog)) {
3211                         err = PTR_ERR(prog);
3212                         goto unlock;
3213                 }
3214         }
3215
3216         /* exchange programs, extra prog reference we got from caller
3217          * as long as we don't fail from this point onwards.
3218          */
3219         old_prog = xchg(&priv->xdp_prog, prog);
3220         if (old_prog)
3221                 bpf_prog_put(old_prog);
3222
3223         if (reset) /* change RQ type according to priv->xdp_prog */
3224                 mlx5e_set_rq_priv_params(priv);
3225
3226         if (was_opened && reset)
3227                 mlx5e_open_locked(netdev);
3228
3229         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3230                 goto unlock;
3231
3232         /* exchanging programs w/o reset, we update ref counts on behalf
3233          * of the channels RQs here.
3234          */
3235         for (i = 0; i < priv->params.num_channels; i++) {
3236                 struct mlx5e_channel *c = priv->channel[i];
3237
3238                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3239                 napi_synchronize(&c->napi);
3240                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3241
3242                 old_prog = xchg(&c->rq.xdp_prog, prog);
3243
3244                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3245                 /* napi_schedule in case we have missed anything */
3246                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3247                 napi_schedule(&c->napi);
3248
3249                 if (old_prog)
3250                         bpf_prog_put(old_prog);
3251         }
3252
3253 unlock:
3254         mutex_unlock(&priv->state_lock);
3255         return err;
3256 }
3257
3258 static bool mlx5e_xdp_attached(struct net_device *dev)
3259 {
3260         struct mlx5e_priv *priv = netdev_priv(dev);
3261
3262         return !!priv->xdp_prog;
3263 }
3264
3265 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3266 {
3267         switch (xdp->command) {
3268         case XDP_SETUP_PROG:
3269                 return mlx5e_xdp_set(dev, xdp->prog);
3270         case XDP_QUERY_PROG:
3271                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3272                 return 0;
3273         default:
3274                 return -EINVAL;
3275         }
3276 }
3277
3278 #ifdef CONFIG_NET_POLL_CONTROLLER
3279 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3280  * reenabling interrupts.
3281  */
3282 static void mlx5e_netpoll(struct net_device *dev)
3283 {
3284         struct mlx5e_priv *priv = netdev_priv(dev);
3285         int i;
3286
3287         for (i = 0; i < priv->params.num_channels; i++)
3288                 napi_schedule(&priv->channel[i]->napi);
3289 }
3290 #endif
3291
3292 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3293         .ndo_open                = mlx5e_open,
3294         .ndo_stop                = mlx5e_close,
3295         .ndo_start_xmit          = mlx5e_xmit,
3296         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3297         .ndo_select_queue        = mlx5e_select_queue,
3298         .ndo_get_stats64         = mlx5e_get_stats,
3299         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3300         .ndo_set_mac_address     = mlx5e_set_mac,
3301         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3302         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3303         .ndo_set_features        = mlx5e_set_features,
3304         .ndo_change_mtu          = mlx5e_change_mtu,
3305         .ndo_do_ioctl            = mlx5e_ioctl,
3306         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3307 #ifdef CONFIG_RFS_ACCEL
3308         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3309 #endif
3310         .ndo_tx_timeout          = mlx5e_tx_timeout,
3311         .ndo_xdp                 = mlx5e_xdp,
3312 #ifdef CONFIG_NET_POLL_CONTROLLER
3313         .ndo_poll_controller     = mlx5e_netpoll,
3314 #endif
3315 };
3316
3317 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3318         .ndo_open                = mlx5e_open,
3319         .ndo_stop                = mlx5e_close,
3320         .ndo_start_xmit          = mlx5e_xmit,
3321         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3322         .ndo_select_queue        = mlx5e_select_queue,
3323         .ndo_get_stats64         = mlx5e_get_stats,
3324         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3325         .ndo_set_mac_address     = mlx5e_set_mac,
3326         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3327         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3328         .ndo_set_features        = mlx5e_set_features,
3329         .ndo_change_mtu          = mlx5e_change_mtu,
3330         .ndo_do_ioctl            = mlx5e_ioctl,
3331         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3332         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3333         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3334         .ndo_features_check      = mlx5e_features_check,
3335 #ifdef CONFIG_RFS_ACCEL
3336         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3337 #endif
3338         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3339         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3340         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3341         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3342         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3343         .ndo_get_vf_config       = mlx5e_get_vf_config,
3344         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3345         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3346         .ndo_tx_timeout          = mlx5e_tx_timeout,
3347         .ndo_xdp                 = mlx5e_xdp,
3348 #ifdef CONFIG_NET_POLL_CONTROLLER
3349         .ndo_poll_controller     = mlx5e_netpoll,
3350 #endif
3351         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
3352         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
3353 };
3354
3355 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3356 {
3357         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3358                 return -ENOTSUPP;
3359         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3360             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3361             !MLX5_CAP_ETH(mdev, csum_cap) ||
3362             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3363             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3364             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3365             MLX5_CAP_FLOWTABLE(mdev,
3366                                flow_table_properties_nic_receive.max_ft_level)
3367                                < 3) {
3368                 mlx5_core_warn(mdev,
3369                                "Not creating net device, some required device capabilities are missing\n");
3370                 return -ENOTSUPP;
3371         }
3372         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3373                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3374         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3375                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3376
3377         return 0;
3378 }
3379
3380 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3381 {
3382         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3383
3384         return bf_buf_size -
3385                sizeof(struct mlx5e_tx_wqe) +
3386                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3387 }
3388
3389 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3390                                    u32 *indirection_rqt, int len,
3391                                    int num_channels)
3392 {
3393         int node = mdev->priv.numa_node;
3394         int node_num_of_cores;
3395         int i;
3396
3397         if (node == -1)
3398                 node = first_online_node;
3399
3400         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3401
3402         if (node_num_of_cores)
3403                 num_channels = min_t(int, num_channels, node_num_of_cores);
3404
3405         for (i = 0; i < len; i++)
3406                 indirection_rqt[i] = i % num_channels;
3407 }
3408
3409 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3410 {
3411         enum pcie_link_width width;
3412         enum pci_bus_speed speed;
3413         int err = 0;
3414
3415         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3416         if (err)
3417                 return err;
3418
3419         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3420                 return -EINVAL;
3421
3422         switch (speed) {
3423         case PCIE_SPEED_2_5GT:
3424                 *pci_bw = 2500 * width;
3425                 break;
3426         case PCIE_SPEED_5_0GT:
3427                 *pci_bw = 5000 * width;
3428                 break;
3429         case PCIE_SPEED_8_0GT:
3430                 *pci_bw = 8000 * width;
3431                 break;
3432         default:
3433                 return -EINVAL;
3434         }
3435
3436         return 0;
3437 }
3438
3439 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3440 {
3441         return (link_speed && pci_bw &&
3442                 (pci_bw < 40000) && (pci_bw < link_speed));
3443 }
3444
3445 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3446 {
3447         params->rx_cq_period_mode = cq_period_mode;
3448
3449         params->rx_cq_moderation.pkts =
3450                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3451         params->rx_cq_moderation.usec =
3452                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3453
3454         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3455                 params->rx_cq_moderation.usec =
3456                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3457 }
3458
3459 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3460                                    u8 *min_inline_mode)
3461 {
3462         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3463         case MLX5_CAP_INLINE_MODE_L2:
3464                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3465                 break;
3466         case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3467                 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
3468                 break;
3469         case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3470                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3471                 break;
3472         }
3473 }
3474
3475 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3476 {
3477         int i;
3478
3479         /* The supported periods are organized in ascending order */
3480         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3481                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3482                         break;
3483
3484         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3485 }
3486
3487 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3488                                         struct net_device *netdev,
3489                                         const struct mlx5e_profile *profile,
3490                                         void *ppriv)
3491 {
3492         struct mlx5e_priv *priv = netdev_priv(netdev);
3493         u32 link_speed = 0;
3494         u32 pci_bw = 0;
3495         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3496                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3497                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3498
3499         priv->mdev                         = mdev;
3500         priv->netdev                       = netdev;
3501         priv->params.num_channels          = profile->max_nch(mdev);
3502         priv->profile                      = profile;
3503         priv->ppriv                        = ppriv;
3504
3505         priv->params.lro_timeout =
3506                 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3507
3508         priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3509
3510         /* set CQE compression */
3511         priv->params.rx_cqe_compress_def = false;
3512         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3513             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3514                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3515                 mlx5e_get_pci_bw(mdev, &pci_bw);
3516                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3517                               link_speed, pci_bw);
3518                 priv->params.rx_cqe_compress_def =
3519                         cqe_compress_heuristic(link_speed, pci_bw);
3520         }
3521
3522         mlx5e_set_rq_priv_params(priv);
3523         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3524                 priv->params.lro_en = true;
3525
3526         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3527         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3528
3529         priv->params.tx_cq_moderation.usec =
3530                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3531         priv->params.tx_cq_moderation.pkts =
3532                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3533         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3534         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3535         priv->params.num_tc                = 1;
3536         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3537
3538         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3539                             sizeof(priv->params.toeplitz_hash_key));
3540
3541         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3542                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3543
3544         priv->params.lro_wqe_sz =
3545                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3546                 /* Extra room needed for build_skb */
3547                 MLX5_RX_HEADROOM -
3548                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3549
3550         /* Initialize pflags */
3551         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3552                         priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3553         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
3554
3555         mutex_init(&priv->state_lock);
3556
3557         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3558         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3559         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3560         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3561 }
3562
3563 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3564 {
3565         struct mlx5e_priv *priv = netdev_priv(netdev);
3566
3567         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3568         if (is_zero_ether_addr(netdev->dev_addr) &&
3569             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3570                 eth_hw_addr_random(netdev);
3571                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3572         }
3573 }
3574
3575 static const struct switchdev_ops mlx5e_switchdev_ops = {
3576         .switchdev_port_attr_get        = mlx5e_attr_get,
3577 };
3578
3579 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3580 {
3581         struct mlx5e_priv *priv = netdev_priv(netdev);
3582         struct mlx5_core_dev *mdev = priv->mdev;
3583         bool fcs_supported;
3584         bool fcs_enabled;
3585
3586         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3587
3588         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3589                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3590 #ifdef CONFIG_MLX5_CORE_EN_DCB
3591                 if (MLX5_CAP_GEN(mdev, qos))
3592                         netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3593 #endif
3594         } else {
3595                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3596         }
3597
3598         netdev->watchdog_timeo    = 15 * HZ;
3599
3600         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3601
3602         netdev->vlan_features    |= NETIF_F_SG;
3603         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3604         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3605         netdev->vlan_features    |= NETIF_F_GRO;
3606         netdev->vlan_features    |= NETIF_F_TSO;
3607         netdev->vlan_features    |= NETIF_F_TSO6;
3608         netdev->vlan_features    |= NETIF_F_RXCSUM;
3609         netdev->vlan_features    |= NETIF_F_RXHASH;
3610
3611         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3612                 netdev->vlan_features    |= NETIF_F_LRO;
3613
3614         netdev->hw_features       = netdev->vlan_features;
3615         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3616         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3617         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3618
3619         if (mlx5e_vxlan_allowed(mdev)) {
3620                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3621                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3622                                            NETIF_F_GSO_PARTIAL;
3623                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3624                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3625                 netdev->hw_enc_features |= NETIF_F_TSO;
3626                 netdev->hw_enc_features |= NETIF_F_TSO6;
3627                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3628                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3629                                            NETIF_F_GSO_PARTIAL;
3630                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3631         }
3632
3633         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3634
3635         if (fcs_supported)
3636                 netdev->hw_features |= NETIF_F_RXALL;
3637
3638         netdev->features          = netdev->hw_features;
3639         if (!priv->params.lro_en)
3640                 netdev->features  &= ~NETIF_F_LRO;
3641
3642         if (fcs_enabled)
3643                 netdev->features  &= ~NETIF_F_RXALL;
3644
3645 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3646         if (FT_CAP(flow_modify_en) &&
3647             FT_CAP(modify_root) &&
3648             FT_CAP(identified_miss_table_mode) &&
3649             FT_CAP(flow_table_modify)) {
3650                 netdev->hw_features      |= NETIF_F_HW_TC;
3651 #ifdef CONFIG_RFS_ACCEL
3652                 netdev->hw_features      |= NETIF_F_NTUPLE;
3653 #endif
3654         }
3655
3656         netdev->features         |= NETIF_F_HIGHDMA;
3657
3658         netdev->priv_flags       |= IFF_UNICAST_FLT;
3659
3660         mlx5e_set_netdev_dev_addr(netdev);
3661
3662 #ifdef CONFIG_NET_SWITCHDEV
3663         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3664                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3665 #endif
3666 }
3667
3668 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3669 {
3670         struct mlx5_core_dev *mdev = priv->mdev;
3671         int err;
3672
3673         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3674         if (err) {
3675                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3676                 priv->q_counter = 0;
3677         }
3678 }
3679
3680 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3681 {
3682         if (!priv->q_counter)
3683                 return;
3684
3685         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3686 }
3687
3688 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3689                            struct net_device *netdev,
3690                            const struct mlx5e_profile *profile,
3691                            void *ppriv)
3692 {
3693         struct mlx5e_priv *priv = netdev_priv(netdev);
3694
3695         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3696         mlx5e_build_nic_netdev(netdev);
3697         mlx5e_vxlan_init(priv);
3698 }
3699
3700 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3701 {
3702         struct mlx5_core_dev *mdev = priv->mdev;
3703         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3704
3705         mlx5e_vxlan_cleanup(priv);
3706
3707         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3708                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3709
3710         if (priv->xdp_prog)
3711                 bpf_prog_put(priv->xdp_prog);
3712 }
3713
3714 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3715 {
3716         struct mlx5_core_dev *mdev = priv->mdev;
3717         int err;
3718         int i;
3719
3720         err = mlx5e_create_indirect_rqts(priv);
3721         if (err) {
3722                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3723                 return err;
3724         }
3725
3726         err = mlx5e_create_direct_rqts(priv);
3727         if (err) {
3728                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3729                 goto err_destroy_indirect_rqts;
3730         }
3731
3732         err = mlx5e_create_indirect_tirs(priv);
3733         if (err) {
3734                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3735                 goto err_destroy_direct_rqts;
3736         }
3737
3738         err = mlx5e_create_direct_tirs(priv);
3739         if (err) {
3740                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3741                 goto err_destroy_indirect_tirs;
3742         }
3743
3744         err = mlx5e_create_flow_steering(priv);
3745         if (err) {
3746                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3747                 goto err_destroy_direct_tirs;
3748         }
3749
3750         err = mlx5e_tc_init(priv);
3751         if (err)
3752                 goto err_destroy_flow_steering;
3753
3754         return 0;
3755
3756 err_destroy_flow_steering:
3757         mlx5e_destroy_flow_steering(priv);
3758 err_destroy_direct_tirs:
3759         mlx5e_destroy_direct_tirs(priv);
3760 err_destroy_indirect_tirs:
3761         mlx5e_destroy_indirect_tirs(priv);
3762 err_destroy_direct_rqts:
3763         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3764                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3765 err_destroy_indirect_rqts:
3766         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3767         return err;
3768 }
3769
3770 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3771 {
3772         int i;
3773
3774         mlx5e_tc_cleanup(priv);
3775         mlx5e_destroy_flow_steering(priv);
3776         mlx5e_destroy_direct_tirs(priv);
3777         mlx5e_destroy_indirect_tirs(priv);
3778         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3779                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3780         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3781 }
3782
3783 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3784 {
3785         int err;
3786
3787         err = mlx5e_create_tises(priv);
3788         if (err) {
3789                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3790                 return err;
3791         }
3792
3793 #ifdef CONFIG_MLX5_CORE_EN_DCB
3794         mlx5e_dcbnl_initialize(priv);
3795 #endif
3796         return 0;
3797 }
3798
3799 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3800 {
3801         struct net_device *netdev = priv->netdev;
3802         struct mlx5_core_dev *mdev = priv->mdev;
3803         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3804         struct mlx5_eswitch_rep rep;
3805
3806         mlx5_lag_add(mdev, netdev);
3807
3808         if (mlx5e_vxlan_allowed(mdev)) {
3809                 rtnl_lock();
3810                 udp_tunnel_get_rx_info(netdev);
3811                 rtnl_unlock();
3812         }
3813
3814         mlx5e_enable_async_events(priv);
3815         queue_work(priv->wq, &priv->set_rx_mode_work);
3816
3817         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3818                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3819                 rep.load = mlx5e_nic_rep_load;
3820                 rep.unload = mlx5e_nic_rep_unload;
3821                 rep.vport = FDB_UPLINK_VPORT;
3822                 rep.netdev = netdev;
3823                 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3824         }
3825 }
3826
3827 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3828 {
3829         queue_work(priv->wq, &priv->set_rx_mode_work);
3830         mlx5e_disable_async_events(priv);
3831         mlx5_lag_remove(priv->mdev);
3832 }
3833
3834 static const struct mlx5e_profile mlx5e_nic_profile = {
3835         .init              = mlx5e_nic_init,
3836         .cleanup           = mlx5e_nic_cleanup,
3837         .init_rx           = mlx5e_init_nic_rx,
3838         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3839         .init_tx           = mlx5e_init_nic_tx,
3840         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3841         .enable            = mlx5e_nic_enable,
3842         .disable           = mlx5e_nic_disable,
3843         .update_stats      = mlx5e_update_stats,
3844         .max_nch           = mlx5e_get_max_num_channels,
3845         .max_tc            = MLX5E_MAX_NUM_TC,
3846 };
3847
3848 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3849                                        const struct mlx5e_profile *profile,
3850                                        void *ppriv)
3851 {
3852         int nch = profile->max_nch(mdev);
3853         struct net_device *netdev;
3854         struct mlx5e_priv *priv;
3855
3856         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3857                                     nch * profile->max_tc,
3858                                     nch);
3859         if (!netdev) {
3860                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3861                 return NULL;
3862         }
3863
3864         profile->init(mdev, netdev, profile, ppriv);
3865
3866         netif_carrier_off(netdev);
3867
3868         priv = netdev_priv(netdev);
3869
3870         priv->wq = create_singlethread_workqueue("mlx5e");
3871         if (!priv->wq)
3872                 goto err_cleanup_nic;
3873
3874         return netdev;
3875
3876 err_cleanup_nic:
3877         profile->cleanup(priv);
3878         free_netdev(netdev);
3879
3880         return NULL;
3881 }
3882
3883 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3884 {
3885         const struct mlx5e_profile *profile;
3886         struct mlx5e_priv *priv;
3887         u16 max_mtu;
3888         int err;
3889
3890         priv = netdev_priv(netdev);
3891         profile = priv->profile;
3892         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3893
3894         err = profile->init_tx(priv);
3895         if (err)
3896                 goto out;
3897
3898         err = mlx5e_open_drop_rq(priv);
3899         if (err) {
3900                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3901                 goto err_cleanup_tx;
3902         }
3903
3904         err = profile->init_rx(priv);
3905         if (err)
3906                 goto err_close_drop_rq;
3907
3908         mlx5e_create_q_counter(priv);
3909
3910         mlx5e_init_l2_addr(priv);
3911
3912         /* MTU range: 68 - hw-specific max */
3913         netdev->min_mtu = ETH_MIN_MTU;
3914         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3915         netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3916
3917         mlx5e_set_dev_port_mtu(netdev);
3918
3919         if (profile->enable)
3920                 profile->enable(priv);
3921
3922         rtnl_lock();
3923         if (netif_running(netdev))
3924                 mlx5e_open(netdev);
3925         netif_device_attach(netdev);
3926         rtnl_unlock();
3927
3928         return 0;
3929
3930 err_close_drop_rq:
3931         mlx5e_close_drop_rq(priv);
3932
3933 err_cleanup_tx:
3934         profile->cleanup_tx(priv);
3935
3936 out:
3937         return err;
3938 }
3939
3940 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3941 {
3942         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3943         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3944         int vport;
3945         u8 mac[ETH_ALEN];
3946
3947         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3948                 return;
3949
3950         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3951
3952         for (vport = 1; vport < total_vfs; vport++) {
3953                 struct mlx5_eswitch_rep rep;
3954
3955                 rep.load = mlx5e_vport_rep_load;
3956                 rep.unload = mlx5e_vport_rep_unload;
3957                 rep.vport = vport;
3958                 ether_addr_copy(rep.hw_id, mac);
3959                 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3960         }
3961 }
3962
3963 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3964 {
3965         struct mlx5e_priv *priv = netdev_priv(netdev);
3966         const struct mlx5e_profile *profile = priv->profile;
3967
3968         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3969         if (profile->disable)
3970                 profile->disable(priv);
3971
3972         flush_workqueue(priv->wq);
3973
3974         rtnl_lock();
3975         if (netif_running(netdev))
3976                 mlx5e_close(netdev);
3977         netif_device_detach(netdev);
3978         rtnl_unlock();
3979
3980         mlx5e_destroy_q_counter(priv);
3981         profile->cleanup_rx(priv);
3982         mlx5e_close_drop_rq(priv);
3983         profile->cleanup_tx(priv);
3984         cancel_delayed_work_sync(&priv->update_stats_work);
3985 }
3986
3987 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3988  * hardware contexts and to connect it to the current netdev.
3989  */
3990 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3991 {
3992         struct mlx5e_priv *priv = vpriv;
3993         struct net_device *netdev = priv->netdev;
3994         int err;
3995
3996         if (netif_device_present(netdev))
3997                 return 0;
3998
3999         err = mlx5e_create_mdev_resources(mdev);
4000         if (err)
4001                 return err;
4002
4003         err = mlx5e_attach_netdev(mdev, netdev);
4004         if (err) {
4005                 mlx5e_destroy_mdev_resources(mdev);
4006                 return err;
4007         }
4008
4009         return 0;
4010 }
4011
4012 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4013 {
4014         struct mlx5e_priv *priv = vpriv;
4015         struct net_device *netdev = priv->netdev;
4016
4017         if (!netif_device_present(netdev))
4018                 return;
4019
4020         mlx5e_detach_netdev(mdev, netdev);
4021         mlx5e_destroy_mdev_resources(mdev);
4022 }
4023
4024 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4025 {
4026         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4027         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4028         void *ppriv = NULL;
4029         void *priv;
4030         int vport;
4031         int err;
4032         struct net_device *netdev;
4033
4034         err = mlx5e_check_required_hca_cap(mdev);
4035         if (err)
4036                 return NULL;
4037
4038         mlx5e_register_vport_rep(mdev);
4039
4040         if (MLX5_CAP_GEN(mdev, vport_group_manager))
4041                 ppriv = &esw->offloads.vport_reps[0];
4042
4043         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4044         if (!netdev) {
4045                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4046                 goto err_unregister_reps;
4047         }
4048
4049         priv = netdev_priv(netdev);
4050
4051         err = mlx5e_attach(mdev, priv);
4052         if (err) {
4053                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4054                 goto err_destroy_netdev;
4055         }
4056
4057         err = register_netdev(netdev);
4058         if (err) {
4059                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4060                 goto err_detach;
4061         }
4062
4063         return priv;
4064
4065 err_detach:
4066         mlx5e_detach(mdev, priv);
4067
4068 err_destroy_netdev:
4069         mlx5e_destroy_netdev(mdev, priv);
4070
4071 err_unregister_reps:
4072         for (vport = 1; vport < total_vfs; vport++)
4073                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4074
4075         return NULL;
4076 }
4077
4078 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4079 {
4080         const struct mlx5e_profile *profile = priv->profile;
4081         struct net_device *netdev = priv->netdev;
4082
4083         destroy_workqueue(priv->wq);
4084         if (profile->cleanup)
4085                 profile->cleanup(priv);
4086         free_netdev(netdev);
4087 }
4088
4089 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4090 {
4091         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4092         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4093         struct mlx5e_priv *priv = vpriv;
4094         int vport;
4095
4096         for (vport = 1; vport < total_vfs; vport++)
4097                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4098
4099         unregister_netdev(priv->netdev);
4100         mlx5e_detach(mdev, vpriv);
4101         mlx5e_destroy_netdev(mdev, priv);
4102 }
4103
4104 static void *mlx5e_get_netdev(void *vpriv)
4105 {
4106         struct mlx5e_priv *priv = vpriv;
4107
4108         return priv->netdev;
4109 }
4110
4111 static struct mlx5_interface mlx5e_interface = {
4112         .add       = mlx5e_add,
4113         .remove    = mlx5e_remove,
4114         .attach    = mlx5e_attach,
4115         .detach    = mlx5e_detach,
4116         .event     = mlx5e_async_event,
4117         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4118         .get_dev   = mlx5e_get_netdev,
4119 };
4120
4121 void mlx5e_init(void)
4122 {
4123         mlx5e_build_ptys2ethtool_map();
4124         mlx5_register_interface(&mlx5e_interface);
4125 }
4126
4127 void mlx5e_cleanup(void)
4128 {
4129         mlx5_unregister_interface(&mlx5e_interface);
4130 }