2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
43 struct mlx5e_rq_param {
44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
49 struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
54 enum mlx5e_sq_type type;
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
87 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
88 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
89 MLX5_MPWRQ_LOG_STRIDE_SIZE;
90 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
91 priv->params.mpwqe_log_stride_sz;
93 default: /* MLX5_WQ_TYPE_LINKED_LIST */
94 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
97 BIT(priv->params.log_rq_size));
99 mlx5_core_info(priv->mdev,
100 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
101 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
102 BIT(priv->params.log_rq_size),
103 BIT(priv->params.mpwqe_log_stride_sz),
104 priv->params.rx_cqe_compress_admin);
107 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
109 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
111 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
112 MLX5_WQ_TYPE_LINKED_LIST;
113 mlx5e_set_rq_type_params(priv, rq_type);
116 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
118 struct mlx5_core_dev *mdev = priv->mdev;
121 port_state = mlx5_query_vport_state(mdev,
122 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
124 if (port_state == VPORT_STATE_UP) {
125 netdev_info(priv->netdev, "Link up\n");
126 netif_carrier_on(priv->netdev);
128 netdev_info(priv->netdev, "Link down\n");
129 netif_carrier_off(priv->netdev);
133 static void mlx5e_update_carrier_work(struct work_struct *work)
135 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
136 update_carrier_work);
138 mutex_lock(&priv->state_lock);
139 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
140 mlx5e_update_carrier(priv);
141 mutex_unlock(&priv->state_lock);
144 static void mlx5e_tx_timeout_work(struct work_struct *work)
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
151 mutex_lock(&priv->state_lock);
152 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
154 mlx5e_close_locked(priv->netdev);
155 err = mlx5e_open_locked(priv->netdev);
157 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
160 mutex_unlock(&priv->state_lock);
164 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
166 struct mlx5e_sw_stats *s = &priv->stats.sw;
167 struct mlx5e_rq_stats *rq_stats;
168 struct mlx5e_sq_stats *sq_stats;
169 u64 tx_offload_none = 0;
172 memset(s, 0, sizeof(*s));
173 for (i = 0; i < priv->params.num_channels; i++) {
174 rq_stats = &priv->channel[i]->rq.stats;
176 s->rx_packets += rq_stats->packets;
177 s->rx_bytes += rq_stats->bytes;
178 s->rx_lro_packets += rq_stats->lro_packets;
179 s->rx_lro_bytes += rq_stats->lro_bytes;
180 s->rx_csum_none += rq_stats->csum_none;
181 s->rx_csum_complete += rq_stats->csum_complete;
182 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
183 s->rx_xdp_drop += rq_stats->xdp_drop;
184 s->rx_xdp_tx += rq_stats->xdp_tx;
185 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
186 s->rx_wqe_err += rq_stats->wqe_err;
187 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
188 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
189 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
190 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
191 s->rx_cache_reuse += rq_stats->cache_reuse;
192 s->rx_cache_full += rq_stats->cache_full;
193 s->rx_cache_empty += rq_stats->cache_empty;
194 s->rx_cache_busy += rq_stats->cache_busy;
196 for (j = 0; j < priv->params.num_tc; j++) {
197 sq_stats = &priv->channel[i]->sq[j].stats;
199 s->tx_packets += sq_stats->packets;
200 s->tx_bytes += sq_stats->bytes;
201 s->tx_tso_packets += sq_stats->tso_packets;
202 s->tx_tso_bytes += sq_stats->tso_bytes;
203 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
204 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
205 s->tx_queue_stopped += sq_stats->stopped;
206 s->tx_queue_wake += sq_stats->wake;
207 s->tx_queue_dropped += sq_stats->dropped;
208 s->tx_xmit_more += sq_stats->xmit_more;
209 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
210 tx_offload_none += sq_stats->csum_none;
214 /* Update calculated offload counters */
215 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
216 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
218 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
219 priv->stats.pport.phy_counters,
220 counter_set.phys_layer_cntrs.link_down_events);
223 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
225 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
226 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
227 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
228 struct mlx5_core_dev *mdev = priv->mdev;
230 MLX5_SET(query_vport_counter_in, in, opcode,
231 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
232 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
233 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
235 memset(out, 0, outlen);
236 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
239 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
241 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
242 struct mlx5_core_dev *mdev = priv->mdev;
243 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
248 in = mlx5_vzalloc(sz);
252 MLX5_SET(ppcnt_reg, in, local_port, 1);
254 out = pstats->IEEE_802_3_counters;
255 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
256 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
258 out = pstats->RFC_2863_counters;
259 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
260 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
262 out = pstats->RFC_2819_counters;
263 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
264 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
266 out = pstats->phy_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
271 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
272 out = pstats->per_prio_counters[prio];
273 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
274 mlx5_core_access_reg(mdev, in, sz, out, sz,
275 MLX5_REG_PPCNT, 0, 0);
282 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
284 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
286 if (!priv->q_counter)
289 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
290 &qcnt->rx_out_of_buffer);
293 void mlx5e_update_stats(struct mlx5e_priv *priv)
295 mlx5e_update_q_counter(priv);
296 mlx5e_update_vport_counters(priv);
297 mlx5e_update_pport_counters(priv);
298 mlx5e_update_sw_counters(priv);
301 void mlx5e_update_stats_work(struct work_struct *work)
303 struct delayed_work *dwork = to_delayed_work(work);
304 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
306 mutex_lock(&priv->state_lock);
307 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
308 priv->profile->update_stats(priv);
309 queue_delayed_work(priv->wq, dwork,
310 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
312 mutex_unlock(&priv->state_lock);
315 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
316 enum mlx5_dev_event event, unsigned long param)
318 struct mlx5e_priv *priv = vpriv;
320 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
324 case MLX5_DEV_EVENT_PORT_UP:
325 case MLX5_DEV_EVENT_PORT_DOWN:
326 queue_work(priv->wq, &priv->update_carrier_work);
334 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
336 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
339 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
341 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
342 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
345 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
346 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
348 static inline int mlx5e_get_wqe_mtt_sz(void)
350 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
351 * To avoid copying garbage after the mtt array, we allocate
354 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
355 MLX5_UMR_MTT_ALIGNMENT);
358 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
359 struct mlx5e_umr_wqe *wqe, u16 ix)
361 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
362 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
363 struct mlx5_wqe_data_seg *dseg = &wqe->data;
364 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
365 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
366 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
368 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
370 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
371 cseg->imm = rq->mkey_be;
373 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
374 ucseg->klm_octowords =
375 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
376 ucseg->bsf_octowords =
377 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
378 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
380 dseg->lkey = sq->mkey_be;
381 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
384 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
385 struct mlx5e_channel *c)
387 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
388 int mtt_sz = mlx5e_get_wqe_mtt_sz();
389 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
392 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
393 GFP_KERNEL, cpu_to_node(c->cpu));
397 /* We allocate more than mtt_sz as we will align the pointer */
398 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
399 cpu_to_node(c->cpu));
400 if (unlikely(!rq->mpwqe.mtt_no_align))
401 goto err_free_wqe_info;
403 for (i = 0; i < wq_sz; i++) {
404 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
406 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
408 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
410 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
413 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
420 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
422 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
425 kfree(rq->mpwqe.mtt_no_align);
427 kfree(rq->mpwqe.info);
433 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
435 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
436 int mtt_sz = mlx5e_get_wqe_mtt_sz();
439 for (i = 0; i < wq_sz; i++) {
440 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
442 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
445 kfree(rq->mpwqe.mtt_no_align);
446 kfree(rq->mpwqe.info);
449 static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
451 struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
453 if (rep && rep->vport != FDB_UPLINK_VPORT)
459 static int mlx5e_create_rq(struct mlx5e_channel *c,
460 struct mlx5e_rq_param *param,
463 struct mlx5e_priv *priv = c->priv;
464 struct mlx5_core_dev *mdev = priv->mdev;
465 void *rqc = param->rqc;
466 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
474 param->wq.db_numa_node = cpu_to_node(c->cpu);
476 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
481 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
483 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
485 rq->wq_type = priv->params.rq_wq_type;
487 rq->netdev = c->netdev;
488 rq->tstamp = &priv->tstamp;
492 rq->xdp_prog = priv->xdp_prog;
494 rq->buff.map_dir = DMA_FROM_DEVICE;
496 rq->buff.map_dir = DMA_BIDIRECTIONAL;
498 switch (priv->params.rq_wq_type) {
499 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
500 if (mlx5e_is_vf_vport_rep(priv)) {
502 goto err_rq_wq_destroy;
505 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
506 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
507 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
509 rq->mpwqe.mtt_offset = c->ix *
510 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
512 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
513 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
515 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
516 byte_count = rq->buff.wqe_sz;
517 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
518 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
520 goto err_rq_wq_destroy;
522 default: /* MLX5_WQ_TYPE_LINKED_LIST */
523 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
524 GFP_KERNEL, cpu_to_node(c->cpu));
527 goto err_rq_wq_destroy;
530 if (mlx5e_is_vf_vport_rep(priv))
531 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
533 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
535 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
536 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
538 rq->buff.wqe_sz = (priv->params.lro_en) ?
539 priv->params.lro_wqe_sz :
540 MLX5E_SW2HW_MTU(priv->netdev->mtu);
541 byte_count = rq->buff.wqe_sz;
543 /* calc the required page order */
544 frag_sz = MLX5_RX_HEADROOM +
545 byte_count /* packet data */ +
546 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
547 frag_sz = SKB_DATA_ALIGN(frag_sz);
549 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
550 rq->buff.page_order = order_base_2(npages);
552 byte_count |= MLX5_HW_START_PADDING;
553 rq->mkey_be = c->mkey_be;
556 for (i = 0; i < wq_sz; i++) {
557 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
559 wqe->data.byte_count = cpu_to_be32(byte_count);
560 wqe->data.lkey = rq->mkey_be;
563 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
564 rq->am.mode = priv->params.rx_cq_period_mode;
566 rq->page_cache.head = 0;
567 rq->page_cache.tail = 0;
570 bpf_prog_add(rq->xdp_prog, 1);
575 mlx5_wq_destroy(&rq->wq_ctrl);
580 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
585 bpf_prog_put(rq->xdp_prog);
587 switch (rq->wq_type) {
588 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
589 mlx5e_rq_free_mpwqe_info(rq);
591 default: /* MLX5_WQ_TYPE_LINKED_LIST */
595 for (i = rq->page_cache.head; i != rq->page_cache.tail;
596 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
597 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
599 mlx5e_page_release(rq, dma_info, false);
601 mlx5_wq_destroy(&rq->wq_ctrl);
604 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
606 struct mlx5e_priv *priv = rq->priv;
607 struct mlx5_core_dev *mdev = priv->mdev;
615 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
616 sizeof(u64) * rq->wq_ctrl.buf.npages;
617 in = mlx5_vzalloc(inlen);
621 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
622 wq = MLX5_ADDR_OF(rqc, rqc, wq);
624 memcpy(rqc, param->rqc, sizeof(param->rqc));
626 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
627 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
628 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
629 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
630 MLX5_ADAPTER_PAGE_SHIFT);
631 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
633 mlx5_fill_page_array(&rq->wq_ctrl.buf,
634 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
636 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
643 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
646 struct mlx5e_channel *c = rq->channel;
647 struct mlx5e_priv *priv = c->priv;
648 struct mlx5_core_dev *mdev = priv->mdev;
655 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
656 in = mlx5_vzalloc(inlen);
660 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
662 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
663 MLX5_SET(rqc, rqc, state, next_state);
665 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
672 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
674 struct mlx5e_channel *c = rq->channel;
675 struct mlx5e_priv *priv = c->priv;
676 struct mlx5_core_dev *mdev = priv->mdev;
683 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
684 in = mlx5_vzalloc(inlen);
688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
690 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
691 MLX5_SET64(modify_rq_in, in, modify_bitmask,
692 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
693 MLX5_SET(rqc, rqc, vsd, vsd);
694 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
696 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
703 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
705 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
708 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
710 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
711 struct mlx5e_channel *c = rq->channel;
712 struct mlx5e_priv *priv = c->priv;
713 struct mlx5_wq_ll *wq = &rq->wq;
715 while (time_before(jiffies, exp_time)) {
716 if (wq->cur_sz >= priv->params.min_rx_wqes)
725 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
727 struct mlx5_wq_ll *wq = &rq->wq;
728 struct mlx5e_rx_wqe *wqe;
732 /* UMR WQE (if in progress) is always at wq->head */
733 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
734 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
736 while (!mlx5_wq_ll_is_empty(wq)) {
737 wqe_ix_be = *wq->tail_next;
738 wqe_ix = be16_to_cpu(wqe_ix_be);
739 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
740 rq->dealloc_wqe(rq, wqe_ix);
741 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
742 &wqe->next.next_wqe_index);
746 static int mlx5e_open_rq(struct mlx5e_channel *c,
747 struct mlx5e_rq_param *param,
750 struct mlx5e_sq *sq = &c->icosq;
751 u16 pi = sq->pc & sq->wq.sz_m1;
754 err = mlx5e_create_rq(c, param, rq);
758 err = mlx5e_enable_rq(rq, param);
762 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
766 if (param->am_enabled)
767 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
769 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
770 sq->db.ico_wqe[pi].num_wqebbs = 1;
771 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
776 mlx5e_disable_rq(rq);
778 mlx5e_destroy_rq(rq);
783 static void mlx5e_close_rq(struct mlx5e_rq *rq)
785 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
786 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
787 cancel_work_sync(&rq->am.work);
789 mlx5e_disable_rq(rq);
790 mlx5e_free_rx_descs(rq);
791 mlx5e_destroy_rq(rq);
794 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
796 kfree(sq->db.xdp.di);
797 kfree(sq->db.xdp.wqe_info);
800 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
802 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
804 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
806 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
808 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
809 mlx5e_free_sq_xdp_db(sq);
816 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
818 kfree(sq->db.ico_wqe);
821 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
823 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
825 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
833 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
835 kfree(sq->db.txq.wqe_info);
836 kfree(sq->db.txq.dma_fifo);
837 kfree(sq->db.txq.skb);
840 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
842 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
843 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
845 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
847 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
849 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
851 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
852 mlx5e_free_sq_txq_db(sq);
856 sq->dma_fifo_mask = df_sz - 1;
861 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
865 mlx5e_free_sq_txq_db(sq);
868 mlx5e_free_sq_ico_db(sq);
871 mlx5e_free_sq_xdp_db(sq);
876 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
880 return mlx5e_alloc_sq_txq_db(sq, numa);
882 return mlx5e_alloc_sq_ico_db(sq, numa);
884 return mlx5e_alloc_sq_xdp_db(sq, numa);
890 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
894 return MLX5E_ICOSQ_MAX_WQEBBS;
896 return MLX5E_XDP_TX_WQEBBS;
898 return MLX5_SEND_WQE_MAX_WQEBBS;
901 static int mlx5e_create_sq(struct mlx5e_channel *c,
903 struct mlx5e_sq_param *param,
906 struct mlx5e_priv *priv = c->priv;
907 struct mlx5_core_dev *mdev = priv->mdev;
909 void *sqc = param->sqc;
910 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
913 sq->type = param->type;
915 sq->tstamp = &priv->tstamp;
916 sq->mkey_be = c->mkey_be;
920 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
924 param->wq.db_numa_node = cpu_to_node(c->cpu);
926 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
929 goto err_unmap_free_uar;
931 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
932 if (sq->uar.bf_map) {
933 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
934 sq->uar_map = sq->uar.bf_map;
936 sq->uar_map = sq->uar.map;
938 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
939 sq->max_inline = param->max_inline;
940 sq->min_inline_mode =
941 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
942 param->min_inline_mode : 0;
944 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
946 goto err_sq_wq_destroy;
948 if (sq->type == MLX5E_SQ_TXQ) {
951 txq_ix = c->ix + tc * priv->params.num_channels;
952 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
953 priv->txq_to_sq_map[txq_ix] = sq;
956 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
957 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
962 mlx5_wq_destroy(&sq->wq_ctrl);
965 mlx5_unmap_free_uar(mdev, &sq->uar);
970 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
972 struct mlx5e_channel *c = sq->channel;
973 struct mlx5e_priv *priv = c->priv;
975 mlx5e_free_sq_db(sq);
976 mlx5_wq_destroy(&sq->wq_ctrl);
977 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
980 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
982 struct mlx5e_channel *c = sq->channel;
983 struct mlx5e_priv *priv = c->priv;
984 struct mlx5_core_dev *mdev = priv->mdev;
992 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
993 sizeof(u64) * sq->wq_ctrl.buf.npages;
994 in = mlx5_vzalloc(inlen);
998 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
999 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1001 memcpy(sqc, param->sqc, sizeof(param->sqc));
1003 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1004 0 : priv->tisn[sq->tc]);
1005 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1006 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
1007 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1008 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1009 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1011 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1012 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1013 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1014 MLX5_ADAPTER_PAGE_SHIFT);
1015 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1017 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1018 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1020 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1027 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1028 int next_state, bool update_rl, int rl_index)
1030 struct mlx5e_channel *c = sq->channel;
1031 struct mlx5e_priv *priv = c->priv;
1032 struct mlx5_core_dev *mdev = priv->mdev;
1039 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1040 in = mlx5_vzalloc(inlen);
1044 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1046 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1047 MLX5_SET(sqc, sqc, state, next_state);
1048 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1049 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1050 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1053 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1060 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1062 struct mlx5e_channel *c = sq->channel;
1063 struct mlx5e_priv *priv = c->priv;
1064 struct mlx5_core_dev *mdev = priv->mdev;
1066 mlx5_core_destroy_sq(mdev, sq->sqn);
1068 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1071 static int mlx5e_open_sq(struct mlx5e_channel *c,
1073 struct mlx5e_sq_param *param,
1074 struct mlx5e_sq *sq)
1078 err = mlx5e_create_sq(c, tc, param, sq);
1082 err = mlx5e_enable_sq(sq, param);
1084 goto err_destroy_sq;
1086 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1089 goto err_disable_sq;
1092 netdev_tx_reset_queue(sq->txq);
1093 netif_tx_start_queue(sq->txq);
1099 mlx5e_disable_sq(sq);
1101 mlx5e_destroy_sq(sq);
1106 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1108 __netif_tx_lock_bh(txq);
1109 netif_tx_stop_queue(txq);
1110 __netif_tx_unlock_bh(txq);
1113 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1115 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1116 /* prevent netif_tx_wake_queue */
1117 napi_synchronize(&sq->channel->napi);
1120 netif_tx_disable_queue(sq->txq);
1122 /* last doorbell out, godspeed .. */
1123 if (mlx5e_sq_has_room_for(sq, 1)) {
1124 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1125 mlx5e_send_nop(sq, true);
1129 mlx5e_disable_sq(sq);
1130 mlx5e_free_sq_descs(sq);
1131 mlx5e_destroy_sq(sq);
1134 static int mlx5e_create_cq(struct mlx5e_channel *c,
1135 struct mlx5e_cq_param *param,
1136 struct mlx5e_cq *cq)
1138 struct mlx5e_priv *priv = c->priv;
1139 struct mlx5_core_dev *mdev = priv->mdev;
1140 struct mlx5_core_cq *mcq = &cq->mcq;
1146 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1147 param->wq.db_numa_node = cpu_to_node(c->cpu);
1148 param->eq_ix = c->ix;
1150 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1155 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1157 cq->napi = &c->napi;
1160 mcq->set_ci_db = cq->wq_ctrl.db.db;
1161 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1162 *mcq->set_ci_db = 0;
1164 mcq->vector = param->eq_ix;
1165 mcq->comp = mlx5e_completion_event;
1166 mcq->event = mlx5e_cq_error_event;
1168 mcq->uar = &mdev->mlx5e_res.cq_uar;
1170 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1171 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1182 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1184 mlx5_wq_destroy(&cq->wq_ctrl);
1187 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1189 struct mlx5e_priv *priv = cq->priv;
1190 struct mlx5_core_dev *mdev = priv->mdev;
1191 struct mlx5_core_cq *mcq = &cq->mcq;
1196 unsigned int irqn_not_used;
1200 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1201 sizeof(u64) * cq->wq_ctrl.buf.npages;
1202 in = mlx5_vzalloc(inlen);
1206 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1208 memcpy(cqc, param->cqc, sizeof(param->cqc));
1210 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1211 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1213 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1215 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1216 MLX5_SET(cqc, cqc, c_eqn, eqn);
1217 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1218 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1219 MLX5_ADAPTER_PAGE_SHIFT);
1220 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1222 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1234 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1236 struct mlx5e_priv *priv = cq->priv;
1237 struct mlx5_core_dev *mdev = priv->mdev;
1239 mlx5_core_destroy_cq(mdev, &cq->mcq);
1242 static int mlx5e_open_cq(struct mlx5e_channel *c,
1243 struct mlx5e_cq_param *param,
1244 struct mlx5e_cq *cq,
1245 struct mlx5e_cq_moder moderation)
1248 struct mlx5e_priv *priv = c->priv;
1249 struct mlx5_core_dev *mdev = priv->mdev;
1251 err = mlx5e_create_cq(c, param, cq);
1255 err = mlx5e_enable_cq(cq, param);
1257 goto err_destroy_cq;
1259 if (MLX5_CAP_GEN(mdev, cq_moderation))
1260 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1266 mlx5e_destroy_cq(cq);
1271 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1273 mlx5e_disable_cq(cq);
1274 mlx5e_destroy_cq(cq);
1277 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1279 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1282 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1283 struct mlx5e_channel_param *cparam)
1285 struct mlx5e_priv *priv = c->priv;
1289 for (tc = 0; tc < c->num_tc; tc++) {
1290 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1291 priv->params.tx_cq_moderation);
1293 goto err_close_tx_cqs;
1299 for (tc--; tc >= 0; tc--)
1300 mlx5e_close_cq(&c->sq[tc].cq);
1305 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1309 for (tc = 0; tc < c->num_tc; tc++)
1310 mlx5e_close_cq(&c->sq[tc].cq);
1313 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1314 struct mlx5e_channel_param *cparam)
1319 for (tc = 0; tc < c->num_tc; tc++) {
1320 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1328 for (tc--; tc >= 0; tc--)
1329 mlx5e_close_sq(&c->sq[tc]);
1334 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1338 for (tc = 0; tc < c->num_tc; tc++)
1339 mlx5e_close_sq(&c->sq[tc]);
1342 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1346 for (i = 0; i < priv->profile->max_tc; i++)
1347 priv->channeltc_to_txq_map[ix][i] =
1348 ix + i * priv->params.num_channels;
1351 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1352 struct mlx5e_sq *sq, u32 rate)
1354 struct mlx5e_priv *priv = netdev_priv(dev);
1355 struct mlx5_core_dev *mdev = priv->mdev;
1359 if (rate == sq->rate_limit)
1364 /* remove current rl index to free space to next ones */
1365 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1370 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1372 netdev_err(dev, "Failed configuring rate %u: %d\n",
1378 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1379 MLX5_SQC_STATE_RDY, true, rl_index);
1381 netdev_err(dev, "Failed configuring rate %u: %d\n",
1383 /* remove the rate from the table */
1385 mlx5_rl_remove_rate(mdev, rate);
1389 sq->rate_limit = rate;
1393 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1395 struct mlx5e_priv *priv = netdev_priv(dev);
1396 struct mlx5_core_dev *mdev = priv->mdev;
1397 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1400 if (!mlx5_rl_is_supported(mdev)) {
1401 netdev_err(dev, "Rate limiting is not supported on this device\n");
1405 /* rate is given in Mb/sec, HW config is in Kb/sec */
1408 /* Check whether rate in valid range, 0 is always valid */
1409 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1410 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1414 mutex_lock(&priv->state_lock);
1415 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1416 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1418 priv->tx_rates[index] = rate;
1419 mutex_unlock(&priv->state_lock);
1424 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1425 struct mlx5e_channel_param *cparam,
1426 struct mlx5e_channel **cp)
1428 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1429 struct net_device *netdev = priv->netdev;
1430 struct mlx5e_cq_moder rx_cq_profile;
1431 int cpu = mlx5e_get_cpu(priv, ix);
1432 struct mlx5e_channel *c;
1433 struct mlx5e_sq *sq;
1437 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1444 c->pdev = &priv->mdev->pdev->dev;
1445 c->netdev = priv->netdev;
1446 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1447 c->num_tc = priv->params.num_tc;
1449 if (priv->params.rx_am_enabled)
1450 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1452 rx_cq_profile = priv->params.rx_cq_moderation;
1454 mlx5e_build_channeltc_to_txq_map(priv, ix);
1456 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1458 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1462 err = mlx5e_open_tx_cqs(c, cparam);
1464 goto err_close_icosq_cq;
1466 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1469 goto err_close_tx_cqs;
1471 napi_enable(&c->napi);
1473 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1475 goto err_disable_napi;
1477 err = mlx5e_open_sqs(c, cparam);
1479 goto err_close_icosq;
1481 for (i = 0; i < priv->params.num_tc; i++) {
1482 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1484 if (priv->tx_rates[txq_ix]) {
1485 sq = priv->txq_to_sq_map[txq_ix];
1486 mlx5e_set_sq_maxrate(priv->netdev, sq,
1487 priv->tx_rates[txq_ix]);
1491 if (priv->xdp_prog) {
1492 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1493 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1494 priv->params.tx_cq_moderation);
1498 err = mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq);
1500 mlx5e_close_cq(&c->xdp_sq.cq);
1505 c->xdp = !!priv->xdp_prog;
1506 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1508 goto err_close_xdp_sq;
1510 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1515 mlx5e_close_sq(&c->xdp_sq);
1521 mlx5e_close_sq(&c->icosq);
1524 napi_disable(&c->napi);
1525 mlx5e_close_cq(&c->rq.cq);
1528 mlx5e_close_tx_cqs(c);
1531 mlx5e_close_cq(&c->icosq.cq);
1534 netif_napi_del(&c->napi);
1535 napi_hash_del(&c->napi);
1541 static void mlx5e_close_channel(struct mlx5e_channel *c)
1543 mlx5e_close_rq(&c->rq);
1545 mlx5e_close_sq(&c->xdp_sq);
1547 mlx5e_close_sq(&c->icosq);
1548 napi_disable(&c->napi);
1550 mlx5e_close_cq(&c->xdp_sq.cq);
1551 mlx5e_close_cq(&c->rq.cq);
1552 mlx5e_close_tx_cqs(c);
1553 mlx5e_close_cq(&c->icosq.cq);
1554 netif_napi_del(&c->napi);
1556 napi_hash_del(&c->napi);
1562 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1563 struct mlx5e_rq_param *param)
1565 void *rqc = param->rqc;
1566 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1568 switch (priv->params.rq_wq_type) {
1569 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1570 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1571 priv->params.mpwqe_log_num_strides - 9);
1572 MLX5_SET(wq, wq, log_wqe_stride_size,
1573 priv->params.mpwqe_log_stride_sz - 6);
1574 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1576 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1577 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1580 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1581 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1582 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1583 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1584 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1586 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1587 param->wq.linear = 1;
1589 param->am_enabled = priv->params.rx_am_enabled;
1592 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1594 void *rqc = param->rqc;
1595 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1597 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1598 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1601 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1602 struct mlx5e_sq_param *param)
1604 void *sqc = param->sqc;
1605 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1607 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1608 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1610 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1613 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1614 struct mlx5e_sq_param *param)
1616 void *sqc = param->sqc;
1617 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1619 mlx5e_build_sq_param_common(priv, param);
1620 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1622 param->max_inline = priv->params.tx_max_inline;
1623 param->min_inline_mode = priv->params.tx_min_inline_mode;
1624 param->type = MLX5E_SQ_TXQ;
1627 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1628 struct mlx5e_cq_param *param)
1630 void *cqc = param->cqc;
1632 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1635 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1636 struct mlx5e_cq_param *param)
1638 void *cqc = param->cqc;
1641 switch (priv->params.rq_wq_type) {
1642 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1643 log_cq_size = priv->params.log_rq_size +
1644 priv->params.mpwqe_log_num_strides;
1646 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1647 log_cq_size = priv->params.log_rq_size;
1650 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1651 if (priv->params.rx_cqe_compress) {
1652 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1653 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1656 mlx5e_build_common_cq_param(priv, param);
1658 param->cq_period_mode = priv->params.rx_cq_period_mode;
1661 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1662 struct mlx5e_cq_param *param)
1664 void *cqc = param->cqc;
1666 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1668 mlx5e_build_common_cq_param(priv, param);
1670 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1673 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1674 struct mlx5e_cq_param *param,
1677 void *cqc = param->cqc;
1679 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1681 mlx5e_build_common_cq_param(priv, param);
1683 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1686 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1687 struct mlx5e_sq_param *param,
1690 void *sqc = param->sqc;
1691 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1693 mlx5e_build_sq_param_common(priv, param);
1695 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1696 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1698 param->type = MLX5E_SQ_ICO;
1701 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1702 struct mlx5e_sq_param *param)
1704 void *sqc = param->sqc;
1705 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1707 mlx5e_build_sq_param_common(priv, param);
1708 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1710 param->max_inline = priv->params.tx_max_inline;
1711 /* FOR XDP SQs will support only L2 inline mode */
1712 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1713 param->type = MLX5E_SQ_XDP;
1716 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1718 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1720 mlx5e_build_rq_param(priv, &cparam->rq);
1721 mlx5e_build_sq_param(priv, &cparam->sq);
1722 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1723 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1724 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1725 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1726 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1729 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1731 struct mlx5e_channel_param *cparam;
1732 int nch = priv->params.num_channels;
1737 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1740 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1741 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1743 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1745 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1746 goto err_free_txq_to_sq_map;
1748 mlx5e_build_channel_param(priv, cparam);
1750 for (i = 0; i < nch; i++) {
1751 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1753 goto err_close_channels;
1756 for (j = 0; j < nch; j++) {
1757 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1759 goto err_close_channels;
1762 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1763 * polling for inactive tx queues.
1765 netif_tx_start_all_queues(priv->netdev);
1771 for (i--; i >= 0; i--)
1772 mlx5e_close_channel(priv->channel[i]);
1774 err_free_txq_to_sq_map:
1775 kfree(priv->txq_to_sq_map);
1776 kfree(priv->channel);
1782 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1786 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1787 * polling for inactive tx queues.
1789 netif_tx_stop_all_queues(priv->netdev);
1790 netif_tx_disable(priv->netdev);
1792 for (i = 0; i < priv->params.num_channels; i++)
1793 mlx5e_close_channel(priv->channel[i]);
1795 kfree(priv->txq_to_sq_map);
1796 kfree(priv->channel);
1799 static int mlx5e_rx_hash_fn(int hfunc)
1801 return (hfunc == ETH_RSS_HASH_TOP) ?
1802 MLX5_RX_HASH_FN_TOEPLITZ :
1803 MLX5_RX_HASH_FN_INVERTED_XOR8;
1806 static int mlx5e_bits_invert(unsigned long a, int size)
1811 for (i = 0; i < size; i++)
1812 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1817 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1821 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1825 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1826 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1828 ix = priv->params.indirection_rqt[ix];
1829 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1830 priv->channel[ix]->rq.rqn :
1832 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1836 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1839 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1840 priv->channel[ix]->rq.rqn :
1843 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1846 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1847 int ix, struct mlx5e_rqt *rqt)
1849 struct mlx5_core_dev *mdev = priv->mdev;
1855 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1856 in = mlx5_vzalloc(inlen);
1860 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1862 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1863 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1865 if (sz > 1) /* RSS */
1866 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1868 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1870 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1872 rqt->enabled = true;
1878 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1880 rqt->enabled = false;
1881 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1884 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1886 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1888 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1891 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1893 struct mlx5e_rqt *rqt;
1897 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1898 rqt = &priv->direct_tir[ix].rqt;
1899 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1901 goto err_destroy_rqts;
1907 for (ix--; ix >= 0; ix--)
1908 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1913 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1915 struct mlx5_core_dev *mdev = priv->mdev;
1921 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1922 in = mlx5_vzalloc(inlen);
1926 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1928 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1929 if (sz > 1) /* RSS */
1930 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1932 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1934 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1936 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1943 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1948 if (priv->indir_rqt.enabled) {
1949 rqtn = priv->indir_rqt.rqtn;
1950 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1953 for (ix = 0; ix < priv->params.num_channels; ix++) {
1954 if (!priv->direct_tir[ix].rqt.enabled)
1956 rqtn = priv->direct_tir[ix].rqt.rqtn;
1957 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1961 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1963 if (!priv->params.lro_en)
1966 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1968 MLX5_SET(tirc, tirc, lro_enable_mask,
1969 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1970 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1971 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1972 (priv->params.lro_wqe_sz -
1973 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1974 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1975 MLX5_CAP_ETH(priv->mdev,
1976 lro_timer_supported_periods[2]));
1979 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1981 MLX5_SET(tirc, tirc, rx_hash_fn,
1982 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1983 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1984 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1985 rx_hash_toeplitz_key);
1986 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1987 rx_hash_toeplitz_key);
1989 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1990 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1994 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1996 struct mlx5_core_dev *mdev = priv->mdev;
2005 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2006 in = mlx5_vzalloc(inlen);
2010 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2011 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2013 mlx5e_build_tir_ctx_lro(tirc, priv);
2015 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2016 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2022 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2023 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2035 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2037 struct mlx5_core_dev *mdev = priv->mdev;
2038 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2041 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2045 /* Update vport context MTU */
2046 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2050 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2052 struct mlx5_core_dev *mdev = priv->mdev;
2056 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2057 if (err || !hw_mtu) /* fallback to port oper mtu */
2058 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2060 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2063 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2065 struct mlx5e_priv *priv = netdev_priv(netdev);
2069 err = mlx5e_set_mtu(priv, netdev->mtu);
2073 mlx5e_query_mtu(priv, &mtu);
2074 if (mtu != netdev->mtu)
2075 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2076 __func__, mtu, netdev->mtu);
2082 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2084 struct mlx5e_priv *priv = netdev_priv(netdev);
2085 int nch = priv->params.num_channels;
2086 int ntc = priv->params.num_tc;
2089 netdev_reset_tc(netdev);
2094 netdev_set_num_tc(netdev, ntc);
2096 /* Map netdev TCs to offset 0
2097 * We have our own UP to TXQ mapping for QoS
2099 for (tc = 0; tc < ntc; tc++)
2100 netdev_set_tc_queue(netdev, tc, nch, 0);
2103 int mlx5e_open_locked(struct net_device *netdev)
2105 struct mlx5e_priv *priv = netdev_priv(netdev);
2106 struct mlx5_core_dev *mdev = priv->mdev;
2110 set_bit(MLX5E_STATE_OPENED, &priv->state);
2112 mlx5e_netdev_set_tcs(netdev);
2114 num_txqs = priv->params.num_channels * priv->params.num_tc;
2115 netif_set_real_num_tx_queues(netdev, num_txqs);
2116 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2118 err = mlx5e_open_channels(priv);
2120 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2122 goto err_clear_state_opened_flag;
2125 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
2127 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2129 goto err_close_channels;
2132 mlx5e_redirect_rqts(priv);
2133 mlx5e_update_carrier(priv);
2134 mlx5e_timestamp_init(priv);
2135 #ifdef CONFIG_RFS_ACCEL
2136 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2138 if (priv->profile->update_stats)
2139 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2141 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2142 err = mlx5e_add_sqs_fwd_rules(priv);
2144 goto err_close_channels;
2149 mlx5e_close_channels(priv);
2150 err_clear_state_opened_flag:
2151 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2155 int mlx5e_open(struct net_device *netdev)
2157 struct mlx5e_priv *priv = netdev_priv(netdev);
2160 mutex_lock(&priv->state_lock);
2161 err = mlx5e_open_locked(netdev);
2162 mutex_unlock(&priv->state_lock);
2167 int mlx5e_close_locked(struct net_device *netdev)
2169 struct mlx5e_priv *priv = netdev_priv(netdev);
2170 struct mlx5_core_dev *mdev = priv->mdev;
2172 /* May already be CLOSED in case a previous configuration operation
2173 * (e.g RX/TX queue size change) that involves close&open failed.
2175 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2178 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2180 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2181 mlx5e_remove_sqs_fwd_rules(priv);
2183 mlx5e_timestamp_cleanup(priv);
2184 netif_carrier_off(priv->netdev);
2185 mlx5e_redirect_rqts(priv);
2186 mlx5e_close_channels(priv);
2191 int mlx5e_close(struct net_device *netdev)
2193 struct mlx5e_priv *priv = netdev_priv(netdev);
2196 if (!netif_device_present(netdev))
2199 mutex_lock(&priv->state_lock);
2200 err = mlx5e_close_locked(netdev);
2201 mutex_unlock(&priv->state_lock);
2206 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2207 struct mlx5e_rq *rq,
2208 struct mlx5e_rq_param *param)
2210 struct mlx5_core_dev *mdev = priv->mdev;
2211 void *rqc = param->rqc;
2212 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2215 param->wq.db_numa_node = param->wq.buf_numa_node;
2217 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2227 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2228 struct mlx5e_cq *cq,
2229 struct mlx5e_cq_param *param)
2231 struct mlx5_core_dev *mdev = priv->mdev;
2232 struct mlx5_core_cq *mcq = &cq->mcq;
2237 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2242 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2245 mcq->set_ci_db = cq->wq_ctrl.db.db;
2246 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2247 *mcq->set_ci_db = 0;
2249 mcq->vector = param->eq_ix;
2250 mcq->comp = mlx5e_completion_event;
2251 mcq->event = mlx5e_cq_error_event;
2253 mcq->uar = &mdev->mlx5e_res.cq_uar;
2260 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2262 struct mlx5e_cq_param cq_param;
2263 struct mlx5e_rq_param rq_param;
2264 struct mlx5e_rq *rq = &priv->drop_rq;
2265 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2268 memset(&cq_param, 0, sizeof(cq_param));
2269 memset(&rq_param, 0, sizeof(rq_param));
2270 mlx5e_build_drop_rq_param(&rq_param);
2272 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2276 err = mlx5e_enable_cq(cq, &cq_param);
2278 goto err_destroy_cq;
2280 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2282 goto err_disable_cq;
2284 err = mlx5e_enable_rq(rq, &rq_param);
2286 goto err_destroy_rq;
2291 mlx5e_destroy_rq(&priv->drop_rq);
2294 mlx5e_disable_cq(&priv->drop_rq.cq);
2297 mlx5e_destroy_cq(&priv->drop_rq.cq);
2302 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2304 mlx5e_disable_rq(&priv->drop_rq);
2305 mlx5e_destroy_rq(&priv->drop_rq);
2306 mlx5e_disable_cq(&priv->drop_rq.cq);
2307 mlx5e_destroy_cq(&priv->drop_rq.cq);
2310 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2312 struct mlx5_core_dev *mdev = priv->mdev;
2313 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2314 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2316 MLX5_SET(tisc, tisc, prio, tc << 1);
2317 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2319 if (mlx5_lag_is_lacp_owner(mdev))
2320 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2322 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2325 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2327 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2330 int mlx5e_create_tises(struct mlx5e_priv *priv)
2335 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2336 err = mlx5e_create_tis(priv, tc);
2338 goto err_close_tises;
2344 for (tc--; tc >= 0; tc--)
2345 mlx5e_destroy_tis(priv, tc);
2350 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2354 for (tc = 0; tc < priv->profile->max_tc; tc++)
2355 mlx5e_destroy_tis(priv, tc);
2358 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2359 enum mlx5e_traffic_types tt)
2361 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2363 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2365 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2366 MLX5_HASH_FIELD_SEL_DST_IP)
2368 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2369 MLX5_HASH_FIELD_SEL_DST_IP |\
2370 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2371 MLX5_HASH_FIELD_SEL_L4_DPORT)
2373 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2374 MLX5_HASH_FIELD_SEL_DST_IP |\
2375 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2377 mlx5e_build_tir_ctx_lro(tirc, priv);
2379 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2380 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2381 mlx5e_build_tir_ctx_hash(tirc, priv);
2384 case MLX5E_TT_IPV4_TCP:
2385 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2386 MLX5_L3_PROT_TYPE_IPV4);
2387 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2388 MLX5_L4_PROT_TYPE_TCP);
2389 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2390 MLX5_HASH_IP_L4PORTS);
2393 case MLX5E_TT_IPV6_TCP:
2394 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2395 MLX5_L3_PROT_TYPE_IPV6);
2396 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2397 MLX5_L4_PROT_TYPE_TCP);
2398 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2399 MLX5_HASH_IP_L4PORTS);
2402 case MLX5E_TT_IPV4_UDP:
2403 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2404 MLX5_L3_PROT_TYPE_IPV4);
2405 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2406 MLX5_L4_PROT_TYPE_UDP);
2407 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2408 MLX5_HASH_IP_L4PORTS);
2411 case MLX5E_TT_IPV6_UDP:
2412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2413 MLX5_L3_PROT_TYPE_IPV6);
2414 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2415 MLX5_L4_PROT_TYPE_UDP);
2416 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2417 MLX5_HASH_IP_L4PORTS);
2420 case MLX5E_TT_IPV4_IPSEC_AH:
2421 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2422 MLX5_L3_PROT_TYPE_IPV4);
2423 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2424 MLX5_HASH_IP_IPSEC_SPI);
2427 case MLX5E_TT_IPV6_IPSEC_AH:
2428 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2429 MLX5_L3_PROT_TYPE_IPV6);
2430 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2431 MLX5_HASH_IP_IPSEC_SPI);
2434 case MLX5E_TT_IPV4_IPSEC_ESP:
2435 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2436 MLX5_L3_PROT_TYPE_IPV4);
2437 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2438 MLX5_HASH_IP_IPSEC_SPI);
2441 case MLX5E_TT_IPV6_IPSEC_ESP:
2442 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2443 MLX5_L3_PROT_TYPE_IPV6);
2444 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2445 MLX5_HASH_IP_IPSEC_SPI);
2449 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2450 MLX5_L3_PROT_TYPE_IPV4);
2451 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2456 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2457 MLX5_L3_PROT_TYPE_IPV6);
2458 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2463 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2467 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2470 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2472 mlx5e_build_tir_ctx_lro(tirc, priv);
2474 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2475 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2476 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2479 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2481 struct mlx5e_tir *tir;
2488 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2489 in = mlx5_vzalloc(inlen);
2493 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2494 memset(in, 0, inlen);
2495 tir = &priv->indir_tir[tt];
2496 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2497 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2498 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2500 goto err_destroy_tirs;
2508 for (tt--; tt >= 0; tt--)
2509 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2516 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2518 int nch = priv->profile->max_nch(priv->mdev);
2519 struct mlx5e_tir *tir;
2526 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2527 in = mlx5_vzalloc(inlen);
2531 for (ix = 0; ix < nch; ix++) {
2532 memset(in, 0, inlen);
2533 tir = &priv->direct_tir[ix];
2534 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2535 mlx5e_build_direct_tir_ctx(priv, tirc,
2536 priv->direct_tir[ix].rqt.rqtn);
2537 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2539 goto err_destroy_ch_tirs;
2546 err_destroy_ch_tirs:
2547 for (ix--; ix >= 0; ix--)
2548 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2555 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2559 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2560 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2563 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2565 int nch = priv->profile->max_nch(priv->mdev);
2568 for (i = 0; i < nch; i++)
2569 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2572 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2577 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2580 for (i = 0; i < priv->params.num_channels; i++) {
2581 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2589 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2591 struct mlx5e_priv *priv = netdev_priv(netdev);
2595 if (tc && tc != MLX5E_MAX_NUM_TC)
2598 mutex_lock(&priv->state_lock);
2600 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2602 mlx5e_close_locked(priv->netdev);
2604 priv->params.num_tc = tc ? tc : 1;
2607 err = mlx5e_open_locked(priv->netdev);
2609 mutex_unlock(&priv->state_lock);
2614 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2615 __be16 proto, struct tc_to_netdev *tc)
2617 struct mlx5e_priv *priv = netdev_priv(dev);
2619 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2623 case TC_SETUP_CLSFLOWER:
2624 switch (tc->cls_flower->command) {
2625 case TC_CLSFLOWER_REPLACE:
2626 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2627 case TC_CLSFLOWER_DESTROY:
2628 return mlx5e_delete_flower(priv, tc->cls_flower);
2629 case TC_CLSFLOWER_STATS:
2630 return mlx5e_stats_flower(priv, tc->cls_flower);
2637 if (tc->type != TC_SETUP_MQPRIO)
2640 return mlx5e_setup_tc(dev, tc->tc);
2643 struct rtnl_link_stats64 *
2644 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2646 struct mlx5e_priv *priv = netdev_priv(dev);
2647 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2648 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2649 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2651 stats->rx_packets = sstats->rx_packets;
2652 stats->rx_bytes = sstats->rx_bytes;
2653 stats->tx_packets = sstats->tx_packets;
2654 stats->tx_bytes = sstats->tx_bytes;
2656 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2657 stats->tx_dropped = sstats->tx_queue_dropped;
2659 stats->rx_length_errors =
2660 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2661 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2662 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2663 stats->rx_crc_errors =
2664 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2665 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2666 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2667 stats->tx_carrier_errors =
2668 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2669 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2670 stats->rx_frame_errors;
2671 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2673 /* vport multicast also counts packets that are dropped due to steering
2674 * or rx out of buffer
2677 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2682 static void mlx5e_set_rx_mode(struct net_device *dev)
2684 struct mlx5e_priv *priv = netdev_priv(dev);
2686 queue_work(priv->wq, &priv->set_rx_mode_work);
2689 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2691 struct mlx5e_priv *priv = netdev_priv(netdev);
2692 struct sockaddr *saddr = addr;
2694 if (!is_valid_ether_addr(saddr->sa_data))
2695 return -EADDRNOTAVAIL;
2697 netif_addr_lock_bh(netdev);
2698 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2699 netif_addr_unlock_bh(netdev);
2701 queue_work(priv->wq, &priv->set_rx_mode_work);
2706 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2709 netdev->features |= feature; \
2711 netdev->features &= ~feature; \
2714 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2716 static int set_feature_lro(struct net_device *netdev, bool enable)
2718 struct mlx5e_priv *priv = netdev_priv(netdev);
2719 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2722 mutex_lock(&priv->state_lock);
2724 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2725 mlx5e_close_locked(priv->netdev);
2727 priv->params.lro_en = enable;
2728 err = mlx5e_modify_tirs_lro(priv);
2730 netdev_err(netdev, "lro modify failed, %d\n", err);
2731 priv->params.lro_en = !enable;
2734 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2735 mlx5e_open_locked(priv->netdev);
2737 mutex_unlock(&priv->state_lock);
2742 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2744 struct mlx5e_priv *priv = netdev_priv(netdev);
2747 mlx5e_enable_vlan_filter(priv);
2749 mlx5e_disable_vlan_filter(priv);
2754 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2756 struct mlx5e_priv *priv = netdev_priv(netdev);
2758 if (!enable && mlx5e_tc_num_filters(priv)) {
2760 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2767 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2769 struct mlx5e_priv *priv = netdev_priv(netdev);
2770 struct mlx5_core_dev *mdev = priv->mdev;
2772 return mlx5_set_port_fcs(mdev, !enable);
2775 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2777 struct mlx5e_priv *priv = netdev_priv(netdev);
2780 mutex_lock(&priv->state_lock);
2782 priv->params.vlan_strip_disable = !enable;
2783 err = mlx5e_modify_rqs_vsd(priv, !enable);
2785 priv->params.vlan_strip_disable = enable;
2787 mutex_unlock(&priv->state_lock);
2792 #ifdef CONFIG_RFS_ACCEL
2793 static int set_feature_arfs(struct net_device *netdev, bool enable)
2795 struct mlx5e_priv *priv = netdev_priv(netdev);
2799 err = mlx5e_arfs_enable(priv);
2801 err = mlx5e_arfs_disable(priv);
2807 static int mlx5e_handle_feature(struct net_device *netdev,
2808 netdev_features_t wanted_features,
2809 netdev_features_t feature,
2810 mlx5e_feature_handler feature_handler)
2812 netdev_features_t changes = wanted_features ^ netdev->features;
2813 bool enable = !!(wanted_features & feature);
2816 if (!(changes & feature))
2819 err = feature_handler(netdev, enable);
2821 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2822 enable ? "Enable" : "Disable", feature, err);
2826 MLX5E_SET_FEATURE(netdev, feature, enable);
2830 static int mlx5e_set_features(struct net_device *netdev,
2831 netdev_features_t features)
2835 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2837 err |= mlx5e_handle_feature(netdev, features,
2838 NETIF_F_HW_VLAN_CTAG_FILTER,
2839 set_feature_vlan_filter);
2840 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2841 set_feature_tc_num_filters);
2842 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2843 set_feature_rx_all);
2844 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2845 set_feature_rx_vlan);
2846 #ifdef CONFIG_RFS_ACCEL
2847 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2851 return err ? -EINVAL : 0;
2854 #define MXL5_HW_MIN_MTU 64
2855 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2857 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2859 struct mlx5e_priv *priv = netdev_priv(netdev);
2860 struct mlx5_core_dev *mdev = priv->mdev;
2867 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2869 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2870 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2872 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2874 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2875 __func__, new_mtu, min_mtu, max_mtu);
2879 mutex_lock(&priv->state_lock);
2881 reset = !priv->params.lro_en &&
2882 (priv->params.rq_wq_type !=
2883 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2885 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2886 if (was_opened && reset)
2887 mlx5e_close_locked(netdev);
2889 netdev->mtu = new_mtu;
2890 mlx5e_set_dev_port_mtu(netdev);
2892 if (was_opened && reset)
2893 err = mlx5e_open_locked(netdev);
2895 mutex_unlock(&priv->state_lock);
2900 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2904 return mlx5e_hwstamp_set(dev, ifr);
2906 return mlx5e_hwstamp_get(dev, ifr);
2912 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2914 struct mlx5e_priv *priv = netdev_priv(dev);
2915 struct mlx5_core_dev *mdev = priv->mdev;
2917 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2920 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2923 struct mlx5e_priv *priv = netdev_priv(dev);
2924 struct mlx5_core_dev *mdev = priv->mdev;
2926 if (vlan_proto != htons(ETH_P_8021Q))
2927 return -EPROTONOSUPPORT;
2929 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2933 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2935 struct mlx5e_priv *priv = netdev_priv(dev);
2936 struct mlx5_core_dev *mdev = priv->mdev;
2938 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2941 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2943 struct mlx5e_priv *priv = netdev_priv(dev);
2944 struct mlx5_core_dev *mdev = priv->mdev;
2946 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2948 static int mlx5_vport_link2ifla(u8 esw_link)
2951 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2952 return IFLA_VF_LINK_STATE_DISABLE;
2953 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2954 return IFLA_VF_LINK_STATE_ENABLE;
2956 return IFLA_VF_LINK_STATE_AUTO;
2959 static int mlx5_ifla_link2vport(u8 ifla_link)
2961 switch (ifla_link) {
2962 case IFLA_VF_LINK_STATE_DISABLE:
2963 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2964 case IFLA_VF_LINK_STATE_ENABLE:
2965 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2967 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2970 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2973 struct mlx5e_priv *priv = netdev_priv(dev);
2974 struct mlx5_core_dev *mdev = priv->mdev;
2976 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2977 mlx5_ifla_link2vport(link_state));
2980 static int mlx5e_get_vf_config(struct net_device *dev,
2981 int vf, struct ifla_vf_info *ivi)
2983 struct mlx5e_priv *priv = netdev_priv(dev);
2984 struct mlx5_core_dev *mdev = priv->mdev;
2987 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2990 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2994 static int mlx5e_get_vf_stats(struct net_device *dev,
2995 int vf, struct ifla_vf_stats *vf_stats)
2997 struct mlx5e_priv *priv = netdev_priv(dev);
2998 struct mlx5_core_dev *mdev = priv->mdev;
3000 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3004 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3005 struct udp_tunnel_info *ti)
3007 struct mlx5e_priv *priv = netdev_priv(netdev);
3009 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3012 if (!mlx5e_vxlan_allowed(priv->mdev))
3015 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3018 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3019 struct udp_tunnel_info *ti)
3021 struct mlx5e_priv *priv = netdev_priv(netdev);
3023 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3026 if (!mlx5e_vxlan_allowed(priv->mdev))
3029 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3032 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3033 struct sk_buff *skb,
3034 netdev_features_t features)
3036 struct udphdr *udph;
3040 switch (vlan_get_protocol(skb)) {
3041 case htons(ETH_P_IP):
3042 proto = ip_hdr(skb)->protocol;
3044 case htons(ETH_P_IPV6):
3045 proto = ipv6_hdr(skb)->nexthdr;
3051 if (proto == IPPROTO_UDP) {
3052 udph = udp_hdr(skb);
3053 port = be16_to_cpu(udph->dest);
3056 /* Verify if UDP port is being offloaded by HW */
3057 if (port && mlx5e_vxlan_lookup_port(priv, port))
3061 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3062 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3065 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3066 struct net_device *netdev,
3067 netdev_features_t features)
3069 struct mlx5e_priv *priv = netdev_priv(netdev);
3071 features = vlan_features_check(skb, features);
3072 features = vxlan_features_check(skb, features);
3074 /* Validate if the tunneled packet is being offloaded by HW */
3075 if (skb->encapsulation &&
3076 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3077 return mlx5e_vxlan_features_check(priv, skb, features);
3082 static void mlx5e_tx_timeout(struct net_device *dev)
3084 struct mlx5e_priv *priv = netdev_priv(dev);
3085 bool sched_work = false;
3088 netdev_err(dev, "TX timeout detected\n");
3090 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3091 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3093 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3096 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3097 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3098 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3101 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3102 schedule_work(&priv->tx_timeout_work);
3105 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3107 struct mlx5e_priv *priv = netdev_priv(netdev);
3108 struct bpf_prog *old_prog;
3110 bool reset, was_opened;
3113 mutex_lock(&priv->state_lock);
3115 if ((netdev->features & NETIF_F_LRO) && prog) {
3116 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3121 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3122 /* no need for full reset when exchanging programs */
3123 reset = (!priv->xdp_prog || !prog);
3125 if (was_opened && reset)
3126 mlx5e_close_locked(netdev);
3128 /* exchange programs */
3129 old_prog = xchg(&priv->xdp_prog, prog);
3131 bpf_prog_add(prog, 1);
3133 bpf_prog_put(old_prog);
3135 if (reset) /* change RQ type according to priv->xdp_prog */
3136 mlx5e_set_rq_priv_params(priv);
3138 if (was_opened && reset)
3139 mlx5e_open_locked(netdev);
3141 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3144 /* exchanging programs w/o reset, we update ref counts on behalf
3145 * of the channels RQs here.
3147 bpf_prog_add(prog, priv->params.num_channels);
3148 for (i = 0; i < priv->params.num_channels; i++) {
3149 struct mlx5e_channel *c = priv->channel[i];
3151 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3152 napi_synchronize(&c->napi);
3153 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3155 old_prog = xchg(&c->rq.xdp_prog, prog);
3157 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3158 /* napi_schedule in case we have missed anything */
3159 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3160 napi_schedule(&c->napi);
3163 bpf_prog_put(old_prog);
3167 mutex_unlock(&priv->state_lock);
3171 static bool mlx5e_xdp_attached(struct net_device *dev)
3173 struct mlx5e_priv *priv = netdev_priv(dev);
3175 return !!priv->xdp_prog;
3178 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3180 switch (xdp->command) {
3181 case XDP_SETUP_PROG:
3182 return mlx5e_xdp_set(dev, xdp->prog);
3183 case XDP_QUERY_PROG:
3184 xdp->prog_attached = mlx5e_xdp_attached(dev);
3191 #ifdef CONFIG_NET_POLL_CONTROLLER
3192 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3193 * reenabling interrupts.
3195 static void mlx5e_netpoll(struct net_device *dev)
3197 struct mlx5e_priv *priv = netdev_priv(dev);
3200 for (i = 0; i < priv->params.num_channels; i++)
3201 napi_schedule(&priv->channel[i]->napi);
3205 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3206 .ndo_open = mlx5e_open,
3207 .ndo_stop = mlx5e_close,
3208 .ndo_start_xmit = mlx5e_xmit,
3209 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3210 .ndo_select_queue = mlx5e_select_queue,
3211 .ndo_get_stats64 = mlx5e_get_stats,
3212 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3213 .ndo_set_mac_address = mlx5e_set_mac,
3214 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3215 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3216 .ndo_set_features = mlx5e_set_features,
3217 .ndo_change_mtu = mlx5e_change_mtu,
3218 .ndo_do_ioctl = mlx5e_ioctl,
3219 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3220 #ifdef CONFIG_RFS_ACCEL
3221 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3223 .ndo_tx_timeout = mlx5e_tx_timeout,
3224 .ndo_xdp = mlx5e_xdp,
3225 #ifdef CONFIG_NET_POLL_CONTROLLER
3226 .ndo_poll_controller = mlx5e_netpoll,
3230 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3231 .ndo_open = mlx5e_open,
3232 .ndo_stop = mlx5e_close,
3233 .ndo_start_xmit = mlx5e_xmit,
3234 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3235 .ndo_select_queue = mlx5e_select_queue,
3236 .ndo_get_stats64 = mlx5e_get_stats,
3237 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3238 .ndo_set_mac_address = mlx5e_set_mac,
3239 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3240 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3241 .ndo_set_features = mlx5e_set_features,
3242 .ndo_change_mtu = mlx5e_change_mtu,
3243 .ndo_do_ioctl = mlx5e_ioctl,
3244 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3245 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3246 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3247 .ndo_features_check = mlx5e_features_check,
3248 #ifdef CONFIG_RFS_ACCEL
3249 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3251 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3252 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3253 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3254 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3255 .ndo_get_vf_config = mlx5e_get_vf_config,
3256 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3257 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3258 .ndo_tx_timeout = mlx5e_tx_timeout,
3259 .ndo_xdp = mlx5e_xdp,
3260 #ifdef CONFIG_NET_POLL_CONTROLLER
3261 .ndo_poll_controller = mlx5e_netpoll,
3265 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3267 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3269 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3270 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3271 !MLX5_CAP_ETH(mdev, csum_cap) ||
3272 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3273 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3274 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3275 MLX5_CAP_FLOWTABLE(mdev,
3276 flow_table_properties_nic_receive.max_ft_level)
3278 mlx5_core_warn(mdev,
3279 "Not creating net device, some required device capabilities are missing\n");
3282 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3283 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3284 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3285 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3290 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3292 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3294 return bf_buf_size -
3295 sizeof(struct mlx5e_tx_wqe) +
3296 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3299 #ifdef CONFIG_MLX5_CORE_EN_DCB
3300 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3304 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3305 for (i = 0; i < priv->params.ets.ets_cap; i++) {
3306 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3307 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3308 priv->params.ets.prio_tc[i] = i;
3311 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3312 priv->params.ets.prio_tc[0] = 1;
3313 priv->params.ets.prio_tc[1] = 0;
3317 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3318 u32 *indirection_rqt, int len,
3321 int node = mdev->priv.numa_node;
3322 int node_num_of_cores;
3326 node = first_online_node;
3328 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3330 if (node_num_of_cores)
3331 num_channels = min_t(int, num_channels, node_num_of_cores);
3333 for (i = 0; i < len; i++)
3334 indirection_rqt[i] = i % num_channels;
3337 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3339 enum pcie_link_width width;
3340 enum pci_bus_speed speed;
3343 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3347 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3351 case PCIE_SPEED_2_5GT:
3352 *pci_bw = 2500 * width;
3354 case PCIE_SPEED_5_0GT:
3355 *pci_bw = 5000 * width;
3357 case PCIE_SPEED_8_0GT:
3358 *pci_bw = 8000 * width;
3367 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3369 return (link_speed && pci_bw &&
3370 (pci_bw < 40000) && (pci_bw < link_speed));
3373 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3375 params->rx_cq_period_mode = cq_period_mode;
3377 params->rx_cq_moderation.pkts =
3378 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3379 params->rx_cq_moderation.usec =
3380 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3382 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3383 params->rx_cq_moderation.usec =
3384 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3387 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3388 u8 *min_inline_mode)
3390 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3391 case MLX5E_INLINE_MODE_L2:
3392 *min_inline_mode = MLX5_INLINE_MODE_L2;
3394 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3395 mlx5_query_nic_vport_min_inline(mdev,
3398 case MLX5_INLINE_MODE_NOT_REQUIRED:
3399 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3404 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3405 struct net_device *netdev,
3406 const struct mlx5e_profile *profile,
3409 struct mlx5e_priv *priv = netdev_priv(netdev);
3412 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3413 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3414 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3417 priv->netdev = netdev;
3418 priv->params.num_channels = profile->max_nch(mdev);
3419 priv->profile = profile;
3420 priv->ppriv = ppriv;
3422 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3424 /* set CQE compression */
3425 priv->params.rx_cqe_compress_admin = false;
3426 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3427 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3428 mlx5e_get_max_linkspeed(mdev, &link_speed);
3429 mlx5e_get_pci_bw(mdev, &pci_bw);
3430 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3431 link_speed, pci_bw);
3432 priv->params.rx_cqe_compress_admin =
3433 cqe_compress_heuristic(link_speed, pci_bw);
3435 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3437 mlx5e_set_rq_priv_params(priv);
3438 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3439 priv->params.lro_en = true;
3441 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3442 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3444 priv->params.tx_cq_moderation.usec =
3445 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3446 priv->params.tx_cq_moderation.pkts =
3447 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3448 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3449 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3450 priv->params.num_tc = 1;
3451 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3453 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3454 sizeof(priv->params.toeplitz_hash_key));
3456 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3457 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3459 priv->params.lro_wqe_sz =
3460 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3461 /* Extra room needed for build_skb */
3463 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3465 /* Initialize pflags */
3466 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3467 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3469 #ifdef CONFIG_MLX5_CORE_EN_DCB
3470 mlx5e_ets_init(priv);
3473 mutex_init(&priv->state_lock);
3475 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3476 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3477 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3478 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3481 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3483 struct mlx5e_priv *priv = netdev_priv(netdev);
3485 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3486 if (is_zero_ether_addr(netdev->dev_addr) &&
3487 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3488 eth_hw_addr_random(netdev);
3489 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3493 static const struct switchdev_ops mlx5e_switchdev_ops = {
3494 .switchdev_port_attr_get = mlx5e_attr_get,
3497 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3499 struct mlx5e_priv *priv = netdev_priv(netdev);
3500 struct mlx5_core_dev *mdev = priv->mdev;
3504 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3506 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3507 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3508 #ifdef CONFIG_MLX5_CORE_EN_DCB
3509 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3512 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3515 netdev->watchdog_timeo = 15 * HZ;
3517 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3519 netdev->vlan_features |= NETIF_F_SG;
3520 netdev->vlan_features |= NETIF_F_IP_CSUM;
3521 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3522 netdev->vlan_features |= NETIF_F_GRO;
3523 netdev->vlan_features |= NETIF_F_TSO;
3524 netdev->vlan_features |= NETIF_F_TSO6;
3525 netdev->vlan_features |= NETIF_F_RXCSUM;
3526 netdev->vlan_features |= NETIF_F_RXHASH;
3528 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3529 netdev->vlan_features |= NETIF_F_LRO;
3531 netdev->hw_features = netdev->vlan_features;
3532 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3533 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3534 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3536 if (mlx5e_vxlan_allowed(mdev)) {
3537 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3538 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3539 NETIF_F_GSO_PARTIAL;
3540 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3541 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3542 netdev->hw_enc_features |= NETIF_F_TSO;
3543 netdev->hw_enc_features |= NETIF_F_TSO6;
3544 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3545 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3546 NETIF_F_GSO_PARTIAL;
3547 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3550 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3553 netdev->hw_features |= NETIF_F_RXALL;
3555 netdev->features = netdev->hw_features;
3556 if (!priv->params.lro_en)
3557 netdev->features &= ~NETIF_F_LRO;
3560 netdev->features &= ~NETIF_F_RXALL;
3562 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3563 if (FT_CAP(flow_modify_en) &&
3564 FT_CAP(modify_root) &&
3565 FT_CAP(identified_miss_table_mode) &&
3566 FT_CAP(flow_table_modify)) {
3567 netdev->hw_features |= NETIF_F_HW_TC;
3568 #ifdef CONFIG_RFS_ACCEL
3569 netdev->hw_features |= NETIF_F_NTUPLE;
3573 netdev->features |= NETIF_F_HIGHDMA;
3575 netdev->priv_flags |= IFF_UNICAST_FLT;
3577 mlx5e_set_netdev_dev_addr(netdev);
3579 #ifdef CONFIG_NET_SWITCHDEV
3580 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3581 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3585 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3587 struct mlx5_core_dev *mdev = priv->mdev;
3590 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3592 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3593 priv->q_counter = 0;
3597 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3599 if (!priv->q_counter)
3602 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3605 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3607 struct mlx5_core_dev *mdev = priv->mdev;
3608 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3609 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3610 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3615 in = mlx5_vzalloc(inlen);
3619 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3621 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3623 MLX5_SET(mkc, mkc, free, 1);
3624 MLX5_SET(mkc, mkc, umr_en, 1);
3625 MLX5_SET(mkc, mkc, lw, 1);
3626 MLX5_SET(mkc, mkc, lr, 1);
3627 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3629 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3630 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3631 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3632 MLX5_SET(mkc, mkc, translations_octword_size,
3633 MLX5_MTT_OCTW(npages));
3634 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3636 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3642 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3643 struct net_device *netdev,
3644 const struct mlx5e_profile *profile,
3647 struct mlx5e_priv *priv = netdev_priv(netdev);
3649 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3650 mlx5e_build_nic_netdev(netdev);
3651 mlx5e_vxlan_init(priv);
3654 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3656 struct mlx5_core_dev *mdev = priv->mdev;
3657 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3659 mlx5e_vxlan_cleanup(priv);
3661 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3662 mlx5_eswitch_unregister_vport_rep(esw, 0);
3665 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3667 struct mlx5_core_dev *mdev = priv->mdev;
3671 err = mlx5e_create_indirect_rqts(priv);
3673 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3677 err = mlx5e_create_direct_rqts(priv);
3679 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3680 goto err_destroy_indirect_rqts;
3683 err = mlx5e_create_indirect_tirs(priv);
3685 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3686 goto err_destroy_direct_rqts;
3689 err = mlx5e_create_direct_tirs(priv);
3691 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3692 goto err_destroy_indirect_tirs;
3695 err = mlx5e_create_flow_steering(priv);
3697 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3698 goto err_destroy_direct_tirs;
3701 err = mlx5e_tc_init(priv);
3703 goto err_destroy_flow_steering;
3707 err_destroy_flow_steering:
3708 mlx5e_destroy_flow_steering(priv);
3709 err_destroy_direct_tirs:
3710 mlx5e_destroy_direct_tirs(priv);
3711 err_destroy_indirect_tirs:
3712 mlx5e_destroy_indirect_tirs(priv);
3713 err_destroy_direct_rqts:
3714 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3715 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3716 err_destroy_indirect_rqts:
3717 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3721 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3725 mlx5e_tc_cleanup(priv);
3726 mlx5e_destroy_flow_steering(priv);
3727 mlx5e_destroy_direct_tirs(priv);
3728 mlx5e_destroy_indirect_tirs(priv);
3729 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3730 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3731 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3734 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3738 err = mlx5e_create_tises(priv);
3740 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3744 #ifdef CONFIG_MLX5_CORE_EN_DCB
3745 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3750 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3752 struct net_device *netdev = priv->netdev;
3753 struct mlx5_core_dev *mdev = priv->mdev;
3754 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3755 struct mlx5_eswitch_rep rep;
3757 mlx5_lag_add(mdev, netdev);
3759 if (mlx5e_vxlan_allowed(mdev)) {
3761 udp_tunnel_get_rx_info(netdev);
3765 mlx5e_enable_async_events(priv);
3766 queue_work(priv->wq, &priv->set_rx_mode_work);
3768 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3769 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3770 rep.load = mlx5e_nic_rep_load;
3771 rep.unload = mlx5e_nic_rep_unload;
3772 rep.vport = FDB_UPLINK_VPORT;
3773 rep.priv_data = priv;
3774 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3778 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3780 queue_work(priv->wq, &priv->set_rx_mode_work);
3781 mlx5e_disable_async_events(priv);
3782 mlx5_lag_remove(priv->mdev);
3785 static const struct mlx5e_profile mlx5e_nic_profile = {
3786 .init = mlx5e_nic_init,
3787 .cleanup = mlx5e_nic_cleanup,
3788 .init_rx = mlx5e_init_nic_rx,
3789 .cleanup_rx = mlx5e_cleanup_nic_rx,
3790 .init_tx = mlx5e_init_nic_tx,
3791 .cleanup_tx = mlx5e_cleanup_nic_tx,
3792 .enable = mlx5e_nic_enable,
3793 .disable = mlx5e_nic_disable,
3794 .update_stats = mlx5e_update_stats,
3795 .max_nch = mlx5e_get_max_num_channels,
3796 .max_tc = MLX5E_MAX_NUM_TC,
3799 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3800 const struct mlx5e_profile *profile,
3803 int nch = profile->max_nch(mdev);
3804 struct net_device *netdev;
3805 struct mlx5e_priv *priv;
3807 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3808 nch * profile->max_tc,
3811 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3815 profile->init(mdev, netdev, profile, ppriv);
3817 netif_carrier_off(netdev);
3819 priv = netdev_priv(netdev);
3821 priv->wq = create_singlethread_workqueue("mlx5e");
3823 goto err_cleanup_nic;
3828 profile->cleanup(priv);
3829 free_netdev(netdev);
3834 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3836 const struct mlx5e_profile *profile;
3837 struct mlx5e_priv *priv;
3840 priv = netdev_priv(netdev);
3841 profile = priv->profile;
3842 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3844 err = mlx5e_create_umr_mkey(priv);
3846 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3850 err = profile->init_tx(priv);
3852 goto err_destroy_umr_mkey;
3854 err = mlx5e_open_drop_rq(priv);
3856 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3857 goto err_cleanup_tx;
3860 err = profile->init_rx(priv);
3862 goto err_close_drop_rq;
3864 mlx5e_create_q_counter(priv);
3866 mlx5e_init_l2_addr(priv);
3868 mlx5e_set_dev_port_mtu(netdev);
3870 if (profile->enable)
3871 profile->enable(priv);
3874 if (netif_running(netdev))
3876 netif_device_attach(netdev);
3882 mlx5e_close_drop_rq(priv);
3885 profile->cleanup_tx(priv);
3887 err_destroy_umr_mkey:
3888 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3894 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3896 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3897 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3901 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3904 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3906 for (vport = 1; vport < total_vfs; vport++) {
3907 struct mlx5_eswitch_rep rep;
3909 rep.load = mlx5e_vport_rep_load;
3910 rep.unload = mlx5e_vport_rep_unload;
3912 ether_addr_copy(rep.hw_id, mac);
3913 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3917 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3919 struct mlx5e_priv *priv = netdev_priv(netdev);
3920 const struct mlx5e_profile *profile = priv->profile;
3922 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3923 if (profile->disable)
3924 profile->disable(priv);
3926 flush_workqueue(priv->wq);
3929 if (netif_running(netdev))
3930 mlx5e_close(netdev);
3931 netif_device_detach(netdev);
3934 mlx5e_destroy_q_counter(priv);
3935 profile->cleanup_rx(priv);
3936 mlx5e_close_drop_rq(priv);
3937 profile->cleanup_tx(priv);
3938 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3939 cancel_delayed_work_sync(&priv->update_stats_work);
3942 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3943 * hardware contexts and to connect it to the current netdev.
3945 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3947 struct mlx5e_priv *priv = vpriv;
3948 struct net_device *netdev = priv->netdev;
3951 if (netif_device_present(netdev))
3954 err = mlx5e_create_mdev_resources(mdev);
3958 err = mlx5e_attach_netdev(mdev, netdev);
3960 mlx5e_destroy_mdev_resources(mdev);
3967 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3969 struct mlx5e_priv *priv = vpriv;
3970 struct net_device *netdev = priv->netdev;
3972 if (!netif_device_present(netdev))
3975 mlx5e_detach_netdev(mdev, netdev);
3976 mlx5e_destroy_mdev_resources(mdev);
3979 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3981 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3982 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3987 struct net_device *netdev;
3989 err = mlx5e_check_required_hca_cap(mdev);
3993 mlx5e_register_vport_rep(mdev);
3995 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3996 ppriv = &esw->offloads.vport_reps[0];
3998 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4000 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4001 goto err_unregister_reps;
4004 priv = netdev_priv(netdev);
4006 err = mlx5e_attach(mdev, priv);
4008 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4009 goto err_destroy_netdev;
4012 err = register_netdev(netdev);
4014 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4021 mlx5e_detach(mdev, priv);
4024 mlx5e_destroy_netdev(mdev, priv);
4026 err_unregister_reps:
4027 for (vport = 1; vport < total_vfs; vport++)
4028 mlx5_eswitch_unregister_vport_rep(esw, vport);
4033 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4035 const struct mlx5e_profile *profile = priv->profile;
4036 struct net_device *netdev = priv->netdev;
4038 unregister_netdev(netdev);
4039 destroy_workqueue(priv->wq);
4040 if (profile->cleanup)
4041 profile->cleanup(priv);
4042 free_netdev(netdev);
4045 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4047 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4048 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4049 struct mlx5e_priv *priv = vpriv;
4052 for (vport = 1; vport < total_vfs; vport++)
4053 mlx5_eswitch_unregister_vport_rep(esw, vport);
4055 mlx5e_detach(mdev, vpriv);
4056 mlx5e_destroy_netdev(mdev, priv);
4059 static void *mlx5e_get_netdev(void *vpriv)
4061 struct mlx5e_priv *priv = vpriv;
4063 return priv->netdev;
4066 static struct mlx5_interface mlx5e_interface = {
4068 .remove = mlx5e_remove,
4069 .attach = mlx5e_attach,
4070 .detach = mlx5e_detach,
4071 .event = mlx5e_async_event,
4072 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4073 .get_dev = mlx5e_get_netdev,
4076 void mlx5e_init(void)
4078 mlx5e_build_ptys2ethtool_map();
4079 mlx5_register_interface(&mlx5e_interface);
4082 void mlx5e_cleanup(void)
4084 mlx5_unregister_interface(&mlx5e_interface);