2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <net/devlink.h>
39 #include <linux/mlx5/device.h>
41 #define MLX5_MAX_UC_PER_VPORT(dev) \
42 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
44 #define MLX5_MAX_MC_PER_VPORT(dev) \
45 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
47 #define MLX5_L2_ADDR_HASH_SIZE (BIT(BITS_PER_BYTE))
48 #define MLX5_L2_ADDR_HASH(addr) (addr[5])
50 #define FDB_UPLINK_VPORT 0xffff
52 /* L2 -mac address based- hash helpers */
54 struct hlist_node hlist;
58 #define for_each_l2hash_node(hn, tmp, hash, i) \
59 for (i = 0; i < MLX5_L2_ADDR_HASH_SIZE; i++) \
60 hlist_for_each_entry_safe(hn, tmp, &hash[i], hlist)
62 #define l2addr_hash_find(hash, mac, type) ({ \
63 int ix = MLX5_L2_ADDR_HASH(mac); \
67 hlist_for_each_entry(ptr, &hash[ix], node.hlist) \
68 if (ether_addr_equal(ptr->node.addr, mac)) {\
77 #define l2addr_hash_add(hash, mac, type, gfp) ({ \
78 int ix = MLX5_L2_ADDR_HASH(mac); \
81 ptr = kzalloc(sizeof(type), gfp); \
83 ether_addr_copy(ptr->node.addr, mac); \
84 hlist_add_head(&ptr->node.hlist, &hash[ix]);\
89 #define l2addr_hash_del(ptr) ({ \
90 hlist_del(&ptr->node.hlist); \
94 struct vport_ingress {
95 struct mlx5_flow_table *acl;
96 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
97 struct mlx5_flow_group *allow_spoofchk_only_grp;
98 struct mlx5_flow_group *allow_untagged_only_grp;
99 struct mlx5_flow_group *drop_grp;
100 struct mlx5_flow_rule *allow_rule;
101 struct mlx5_flow_rule *drop_rule;
104 struct vport_egress {
105 struct mlx5_flow_table *acl;
106 struct mlx5_flow_group *allowed_vlans_grp;
107 struct mlx5_flow_group *drop_grp;
108 struct mlx5_flow_rule *allowed_vlan;
109 struct mlx5_flow_rule *drop_rule;
112 struct mlx5_vport_info {
123 struct mlx5_core_dev *dev;
125 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
126 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
127 struct mlx5_flow_rule *promisc_rule;
128 struct mlx5_flow_rule *allmulti_rule;
129 struct work_struct vport_change_handler;
131 struct vport_ingress ingress;
132 struct vport_egress egress;
134 struct mlx5_vport_info info;
140 struct mlx5_l2_table {
141 struct hlist_head l2_hash[MLX5_L2_ADDR_HASH_SIZE];
143 unsigned long *bitmap;
146 struct mlx5_eswitch_fdb {
150 struct mlx5_flow_group *addr_grp;
151 struct mlx5_flow_group *allmulti_grp;
152 struct mlx5_flow_group *promisc_grp;
155 struct offloads_fdb {
156 struct mlx5_flow_table *fdb;
157 struct mlx5_flow_group *send_to_vport_grp;
158 struct mlx5_flow_group *miss_grp;
159 struct mlx5_flow_rule *miss_rule;
160 int vlan_push_pop_refcount;
172 struct mlx5_flow_rule *send_to_vport_rule;
173 struct list_head list;
176 struct mlx5_eswitch_rep {
177 int (*load)(struct mlx5_eswitch *esw,
178 struct mlx5_eswitch_rep *rep);
179 void (*unload)(struct mlx5_eswitch *esw,
180 struct mlx5_eswitch_rep *rep);
185 struct mlx5_flow_rule *vport_rx_rule;
186 struct list_head vport_sqs_list;
192 struct mlx5_esw_offload {
193 struct mlx5_flow_table *ft_offloads;
194 struct mlx5_flow_group *vport_rx_group;
195 struct mlx5_eswitch_rep *vport_reps;
198 struct mlx5_eswitch {
199 struct mlx5_core_dev *dev;
200 struct mlx5_l2_table l2_table;
201 struct mlx5_eswitch_fdb fdb_table;
202 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
203 struct workqueue_struct *work_queue;
204 struct mlx5_vport *vports;
207 /* Synchronize between vport change events
208 * and async SRIOV admin state changes
210 struct mutex state_lock;
211 struct esw_mc_addr *mc_promisc;
212 struct mlx5_esw_offload offloads;
216 void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
217 int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
220 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
221 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
222 void mlx5_eswitch_attach(struct mlx5_eswitch *esw);
223 void mlx5_eswitch_detach(struct mlx5_eswitch *esw);
224 void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe);
225 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
226 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
227 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
228 int vport, u8 mac[ETH_ALEN]);
229 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
230 int vport, int link_state);
231 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
232 int vport, u16 vlan, u8 qos);
233 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
234 int vport, bool spoofchk);
235 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
236 int vport_num, bool setting);
237 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
238 int vport, struct ifla_vf_info *ivi);
239 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
241 struct ifla_vf_stats *vf_stats);
243 struct mlx5_flow_spec;
244 struct mlx5_esw_flow_attr;
246 struct mlx5_flow_rule *
247 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
248 struct mlx5_flow_spec *spec,
249 struct mlx5_esw_flow_attr *attr);
250 struct mlx5_flow_rule *
251 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);
254 SET_VLAN_STRIP = BIT(0),
255 SET_VLAN_INSERT = BIT(1)
258 #define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP 0x40
259 #define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x80
261 struct mlx5_esw_flow_attr {
262 struct mlx5_eswitch_rep *in_rep;
263 struct mlx5_eswitch_rep *out_rep;
270 int mlx5_eswitch_sqs2vport_start(struct mlx5_eswitch *esw,
271 struct mlx5_eswitch_rep *rep,
272 u16 *sqns_array, int sqns_num);
273 void mlx5_eswitch_sqs2vport_stop(struct mlx5_eswitch *esw,
274 struct mlx5_eswitch_rep *rep);
276 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode);
277 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
278 void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
280 struct mlx5_eswitch_rep *rep);
281 void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
284 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
285 struct mlx5_esw_flow_attr *attr);
286 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
287 struct mlx5_esw_flow_attr *attr);
288 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
289 int vport, u16 vlan, u8 qos, u8 set_flags);
291 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
293 #define esw_info(dev, format, ...) \
294 pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
296 #define esw_warn(dev, format, ...) \
297 pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
299 #define esw_debug(dev, format, ...) \
300 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
301 #endif /* __MLX5_ESWITCH_H__ */