2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/etherdevice.h>
35 #include <linux/mlx5/driver.h>
37 #include "mlx5_core.h"
39 #include "fpga/core.h"
40 #include "fpga/conn.h"
42 static const char *const mlx5_fpga_error_strings[] = {
46 "Internal Link Error",
47 "Watchdog HW Failure",
50 "Temperature Critical",
53 static struct mlx5_fpga_device *mlx5_fpga_device_alloc(void)
55 struct mlx5_fpga_device *fdev = NULL;
57 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
61 spin_lock_init(&fdev->state_lock);
62 fdev->state = MLX5_FPGA_STATUS_NONE;
66 static const char *mlx5_fpga_image_name(enum mlx5_fpga_image image)
69 case MLX5_FPGA_IMAGE_USER:
71 case MLX5_FPGA_IMAGE_FACTORY:
78 static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev)
80 struct mlx5_fpga_query query;
83 err = mlx5_fpga_query(fdev->mdev, &query);
85 mlx5_fpga_err(fdev, "Failed to query status: %d\n", err);
89 fdev->last_admin_image = query.admin_image;
90 fdev->last_oper_image = query.oper_image;
92 mlx5_fpga_dbg(fdev, "Status %u; Admin image %u; Oper image %u\n",
93 query.status, query.admin_image, query.oper_image);
95 if (query.status != MLX5_FPGA_STATUS_SUCCESS) {
96 mlx5_fpga_err(fdev, "%s image failed to load; status %u\n",
97 mlx5_fpga_image_name(fdev->last_oper_image),
105 static int mlx5_fpga_device_brb(struct mlx5_fpga_device *fdev)
108 struct mlx5_core_dev *mdev = fdev->mdev;
110 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON);
112 mlx5_fpga_err(fdev, "Failed to set bypass on: %d\n", err);
115 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX);
117 mlx5_fpga_err(fdev, "Failed to reset SBU: %d\n", err);
120 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF);
122 mlx5_fpga_err(fdev, "Failed to set bypass off: %d\n", err);
128 int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
130 struct mlx5_fpga_device *fdev = mdev->fpga;
132 unsigned int max_num_qps;
138 err = mlx5_fpga_device_load_check(fdev);
142 err = mlx5_fpga_caps(fdev->mdev,
143 fdev->mdev->caps.hca_cur[MLX5_CAP_FPGA]);
147 mlx5_fpga_info(fdev, "device %u; %s image, version %u\n",
148 MLX5_CAP_FPGA(fdev->mdev, fpga_device),
149 mlx5_fpga_image_name(fdev->last_oper_image),
150 MLX5_CAP_FPGA(fdev->mdev, image_version));
152 max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);
153 err = mlx5_core_reserve_gids(mdev, max_num_qps);
157 err = mlx5_fpga_conn_device_init(fdev);
161 if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
162 err = mlx5_fpga_device_brb(fdev);
170 mlx5_fpga_conn_device_cleanup(fdev);
173 mlx5_core_unreserve_gids(mdev, max_num_qps);
175 spin_lock_irqsave(&fdev->state_lock, flags);
176 fdev->state = err ? MLX5_FPGA_STATUS_FAILURE : MLX5_FPGA_STATUS_SUCCESS;
177 spin_unlock_irqrestore(&fdev->state_lock, flags);
181 int mlx5_fpga_init(struct mlx5_core_dev *mdev)
183 struct mlx5_fpga_device *fdev = NULL;
185 if (!MLX5_CAP_GEN(mdev, fpga)) {
186 mlx5_core_dbg(mdev, "FPGA capability not present\n");
190 mlx5_core_dbg(mdev, "Initializing FPGA\n");
192 fdev = mlx5_fpga_device_alloc();
202 void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
204 struct mlx5_fpga_device *fdev = mdev->fpga;
205 unsigned int max_num_qps;
212 spin_lock_irqsave(&fdev->state_lock, flags);
213 if (fdev->state != MLX5_FPGA_STATUS_SUCCESS) {
214 spin_unlock_irqrestore(&fdev->state_lock, flags);
217 fdev->state = MLX5_FPGA_STATUS_NONE;
218 spin_unlock_irqrestore(&fdev->state_lock, flags);
220 if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
221 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON);
223 mlx5_fpga_err(fdev, "Failed to re-set SBU bypass on: %d\n",
227 mlx5_fpga_conn_device_cleanup(fdev);
228 max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);
229 mlx5_core_unreserve_gids(mdev, max_num_qps);
232 void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
234 struct mlx5_fpga_device *fdev = mdev->fpga;
236 mlx5_fpga_device_stop(mdev);
241 static const char *mlx5_fpga_syndrome_to_string(u8 syndrome)
243 if (syndrome < ARRAY_SIZE(mlx5_fpga_error_strings))
244 return mlx5_fpga_error_strings[syndrome];
248 void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event, void *data)
250 struct mlx5_fpga_device *fdev = mdev->fpga;
251 const char *event_name;
252 bool teardown = false;
256 if (event != MLX5_EVENT_TYPE_FPGA_ERROR) {
257 mlx5_fpga_warn_ratelimited(fdev, "Unexpected event %u\n",
262 syndrome = MLX5_GET(fpga_error_event, data, syndrome);
263 event_name = mlx5_fpga_syndrome_to_string(syndrome);
265 spin_lock_irqsave(&fdev->state_lock, flags);
266 switch (fdev->state) {
267 case MLX5_FPGA_STATUS_SUCCESS:
268 mlx5_fpga_warn(fdev, "Error %u: %s\n", syndrome, event_name);
272 mlx5_fpga_warn_ratelimited(fdev, "Unexpected error event %u: %s\n",
273 syndrome, event_name);
275 spin_unlock_irqrestore(&fdev->state_lock, flags);
276 /* We tear-down the card's interfaces and functionality because
277 * the FPGA bump-on-the-wire is misbehaving and we lose ability
278 * to communicate with the network. User may still be able to
279 * recover by re-programming or debugging the FPGA
282 mlx5_trigger_health_work(fdev->mdev);