2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #include "mlx5_core.h"
53 #ifdef CONFIG_MLX5_CORE_EN
57 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
58 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
59 MODULE_LICENSE("Dual BSD/GPL");
60 MODULE_VERSION(DRIVER_VERSION);
62 int mlx5_core_debug_mask;
63 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
64 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
66 #define MLX5_DEFAULT_PROF 2
67 static int prof_sel = MLX5_DEFAULT_PROF;
68 module_param_named(prof_sel, prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
71 static LIST_HEAD(intf_list);
72 static LIST_HEAD(dev_list);
73 static DEFINE_MUTEX(intf_mutex);
75 struct mlx5_device_context {
76 struct list_head list;
77 struct mlx5_interface *intf;
82 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
83 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
86 static struct mlx5_profile profile[] = {
91 .mask = MLX5_PROF_MASK_QP_SIZE,
95 .mask = MLX5_PROF_MASK_QP_SIZE |
96 MLX5_PROF_MASK_MR_CACHE,
165 #define FW_INIT_TIMEOUT_MILI 2000
166 #define FW_INIT_WAIT_MS 2
168 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
170 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
173 while (fw_initializing(dev)) {
174 if (time_after(jiffies, end)) {
178 msleep(FW_INIT_WAIT_MS);
184 static int set_dma_caps(struct pci_dev *pdev)
188 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
190 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
191 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
193 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
198 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
201 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
205 "Can't set consistent PCI DMA mask, aborting\n");
210 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
214 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
216 struct pci_dev *pdev = dev->pdev;
219 mutex_lock(&dev->pci_status_mutex);
220 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
221 err = pci_enable_device(pdev);
223 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
225 mutex_unlock(&dev->pci_status_mutex);
230 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
232 struct pci_dev *pdev = dev->pdev;
234 mutex_lock(&dev->pci_status_mutex);
235 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
236 pci_disable_device(pdev);
237 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
239 mutex_unlock(&dev->pci_status_mutex);
242 static int request_bar(struct pci_dev *pdev)
246 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
247 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
251 err = pci_request_regions(pdev, DRIVER_NAME);
253 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
258 static void release_bar(struct pci_dev *pdev)
260 pci_release_regions(pdev);
263 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
265 struct mlx5_priv *priv = &dev->priv;
266 struct mlx5_eq_table *table = &priv->eq_table;
267 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
271 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
272 MLX5_EQ_VEC_COMP_BASE;
273 nvec = min_t(int, nvec, num_eqs);
274 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
277 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
279 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
280 if (!priv->msix_arr || !priv->irq_info)
283 for (i = 0; i < nvec; i++)
284 priv->msix_arr[i].entry = i;
286 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
287 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
291 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
296 kfree(priv->irq_info);
297 kfree(priv->msix_arr);
301 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
303 struct mlx5_priv *priv = &dev->priv;
305 pci_disable_msix(dev->pdev);
306 kfree(priv->irq_info);
307 kfree(priv->msix_arr);
310 struct mlx5_reg_host_endianess {
316 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
319 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
320 MLX5_DEV_CAP_FLAG_DCT,
323 static u16 to_fw_pkey_sz(u32 size)
339 pr_warn("invalid pkey table size %d\n", size);
344 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
345 enum mlx5_cap_mode cap_mode)
347 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
348 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
349 void *out, *hca_caps;
350 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
353 memset(in, 0, sizeof(in));
354 out = kzalloc(out_sz, GFP_KERNEL);
358 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
359 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
360 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
364 err = mlx5_cmd_status_to_err_v2(out);
367 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
368 cap_type, cap_mode, err);
372 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
375 case HCA_CAP_OPMOD_GET_MAX:
376 memcpy(dev->hca_caps_max[cap_type], hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
379 case HCA_CAP_OPMOD_GET_CUR:
380 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
385 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
395 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
397 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
400 memset(out, 0, sizeof(out));
402 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
403 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
404 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
408 err = mlx5_cmd_status_to_err_v2(out);
413 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
417 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
421 if (MLX5_CAP_GEN(dev, atomic)) {
422 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
423 HCA_CAP_OPMOD_GET_CUR);
426 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
427 HCA_CAP_OPMOD_GET_MAX);
436 supported_atomic_req_8B_endianess_mode_1);
438 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
441 set_ctx = kzalloc(set_sz, GFP_KERNEL);
445 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
447 /* Set requestor to host endianness */
448 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
449 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
451 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
457 static int handle_hca_cap(struct mlx5_core_dev *dev)
459 void *set_ctx = NULL;
460 struct mlx5_profile *prof = dev->profile;
462 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
465 set_ctx = kzalloc(set_sz, GFP_KERNEL);
469 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
473 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
477 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
479 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
480 MLX5_ST_SZ_BYTES(cmd_hca_cap));
482 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
483 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
485 /* we limit the size of the pkey table to 128 entries for now */
486 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
489 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
490 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
493 /* disable cmdif checksum */
494 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
496 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
498 err = set_caps(dev, set_ctx, set_sz,
499 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
506 static int set_hca_ctrl(struct mlx5_core_dev *dev)
508 struct mlx5_reg_host_endianess he_in;
509 struct mlx5_reg_host_endianess he_out;
512 if (!mlx5_core_is_pf(dev))
515 memset(&he_in, 0, sizeof(he_in));
516 he_in.he = MLX5_SET_HOST_ENDIANNESS;
517 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
518 &he_out, sizeof(he_out),
519 MLX5_REG_HOST_ENDIANNESS, 0, 1);
523 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
525 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
526 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
529 memset(in, 0, sizeof(in));
530 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
531 MLX5_SET(enable_hca_in, in, function_id, func_id);
532 memset(out, 0, sizeof(out));
534 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
538 return mlx5_cmd_status_to_err_v2(out);
541 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
543 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
544 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
547 memset(in, 0, sizeof(in));
548 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
549 MLX5_SET(disable_hca_in, in, function_id, func_id);
550 memset(out, 0, sizeof(out));
551 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
555 return mlx5_cmd_status_to_err_v2(out);
558 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
560 u32 timer_h, timer_h1, timer_l;
562 timer_h = ioread32be(&dev->iseg->internal_timer_h);
563 timer_l = ioread32be(&dev->iseg->internal_timer_l);
564 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
565 if (timer_h != timer_h1) /* wrap around */
566 timer_l = ioread32be(&dev->iseg->internal_timer_l);
568 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
571 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
573 struct mlx5_priv *priv = &mdev->priv;
574 struct msix_entry *msix = priv->msix_arr;
575 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
576 int numa_node = priv->numa_node;
579 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
580 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
584 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
585 priv->irq_info[i].mask);
587 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
589 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
597 free_cpumask_var(priv->irq_info[i].mask);
601 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
603 struct mlx5_priv *priv = &mdev->priv;
604 struct msix_entry *msix = priv->msix_arr;
605 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
607 irq_set_affinity_hint(irq, NULL);
608 free_cpumask_var(priv->irq_info[i].mask);
611 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
616 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
617 err = mlx5_irq_set_affinity_hint(mdev, i);
625 for (i--; i >= 0; i--)
626 mlx5_irq_clear_affinity_hint(mdev, i);
631 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
635 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
636 mlx5_irq_clear_affinity_hint(mdev, i);
639 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
642 struct mlx5_eq_table *table = &dev->priv.eq_table;
643 struct mlx5_eq *eq, *n;
646 spin_lock(&table->lock);
647 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
648 if (eq->index == vector) {
655 spin_unlock(&table->lock);
659 EXPORT_SYMBOL(mlx5_vector2eqn);
661 static void free_comp_eqs(struct mlx5_core_dev *dev)
663 struct mlx5_eq_table *table = &dev->priv.eq_table;
664 struct mlx5_eq *eq, *n;
666 spin_lock(&table->lock);
667 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
669 spin_unlock(&table->lock);
670 if (mlx5_destroy_unmap_eq(dev, eq))
671 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
674 spin_lock(&table->lock);
676 spin_unlock(&table->lock);
679 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
681 struct mlx5_eq_table *table = &dev->priv.eq_table;
682 char name[MLX5_MAX_IRQ_NAME];
689 INIT_LIST_HEAD(&table->comp_eqs_list);
690 ncomp_vec = table->num_comp_vectors;
691 nent = MLX5_COMP_EQ_SIZE;
692 for (i = 0; i < ncomp_vec; i++) {
693 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
699 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
700 err = mlx5_create_map_eq(dev, eq,
701 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
702 name, &dev->priv.uuari.uars[0]);
707 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
709 spin_lock(&table->lock);
710 list_add_tail(&eq->list, &table->comp_eqs_list);
711 spin_unlock(&table->lock);
721 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
723 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
724 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
725 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
726 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
730 memset(query_in, 0, sizeof(query_in));
731 memset(query_out, 0, sizeof(query_out));
733 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
735 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
736 query_out, sizeof(query_out));
738 if (((struct mlx5_outbox_hdr *)query_out)->status ==
739 MLX5_CMD_STAT_BAD_OP_ERR) {
740 pr_debug("Only ISSI 0 is supported\n");
744 pr_err("failed to query ISSI\n");
748 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
750 if (sup_issi & (1 << 1)) {
751 memset(set_in, 0, sizeof(set_in));
752 memset(set_out, 0, sizeof(set_out));
754 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
755 MLX5_SET(set_issi_in, set_in, current_issi, 1);
757 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
758 set_out, sizeof(set_out));
760 pr_err("failed to set ISSI=1\n");
767 } else if (sup_issi & (1 << 0) || !sup_issi) {
774 static int map_bf_area(struct mlx5_core_dev *dev)
776 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
777 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
779 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
781 return dev->priv.bf_mapping ? 0 : -ENOMEM;
784 static void unmap_bf_area(struct mlx5_core_dev *dev)
786 if (dev->priv.bf_mapping)
787 io_mapping_free(dev->priv.bf_mapping);
790 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
792 struct mlx5_device_context *dev_ctx;
793 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
795 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
799 dev_ctx->intf = intf;
800 dev_ctx->context = intf->add(dev);
802 if (dev_ctx->context) {
803 spin_lock_irq(&priv->ctx_lock);
804 list_add_tail(&dev_ctx->list, &priv->ctx_list);
805 spin_unlock_irq(&priv->ctx_lock);
811 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
813 struct mlx5_device_context *dev_ctx;
814 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
816 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
817 if (dev_ctx->intf == intf) {
818 spin_lock_irq(&priv->ctx_lock);
819 list_del(&dev_ctx->list);
820 spin_unlock_irq(&priv->ctx_lock);
822 intf->remove(dev, dev_ctx->context);
828 static int mlx5_register_device(struct mlx5_core_dev *dev)
830 struct mlx5_priv *priv = &dev->priv;
831 struct mlx5_interface *intf;
833 mutex_lock(&intf_mutex);
834 list_add_tail(&priv->dev_list, &dev_list);
835 list_for_each_entry(intf, &intf_list, list)
836 mlx5_add_device(intf, priv);
837 mutex_unlock(&intf_mutex);
842 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
844 struct mlx5_priv *priv = &dev->priv;
845 struct mlx5_interface *intf;
847 mutex_lock(&intf_mutex);
848 list_for_each_entry(intf, &intf_list, list)
849 mlx5_remove_device(intf, priv);
850 list_del(&priv->dev_list);
851 mutex_unlock(&intf_mutex);
854 int mlx5_register_interface(struct mlx5_interface *intf)
856 struct mlx5_priv *priv;
858 if (!intf->add || !intf->remove)
861 mutex_lock(&intf_mutex);
862 list_add_tail(&intf->list, &intf_list);
863 list_for_each_entry(priv, &dev_list, dev_list)
864 mlx5_add_device(intf, priv);
865 mutex_unlock(&intf_mutex);
869 EXPORT_SYMBOL(mlx5_register_interface);
871 void mlx5_unregister_interface(struct mlx5_interface *intf)
873 struct mlx5_priv *priv;
875 mutex_lock(&intf_mutex);
876 list_for_each_entry(priv, &dev_list, dev_list)
877 mlx5_remove_device(intf, priv);
878 list_del(&intf->list);
879 mutex_unlock(&intf_mutex);
881 EXPORT_SYMBOL(mlx5_unregister_interface);
883 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
885 struct mlx5_priv *priv = &mdev->priv;
886 struct mlx5_device_context *dev_ctx;
890 spin_lock_irqsave(&priv->ctx_lock, flags);
892 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
893 if ((dev_ctx->intf->protocol == protocol) &&
894 dev_ctx->intf->get_dev) {
895 result = dev_ctx->intf->get_dev(dev_ctx->context);
899 spin_unlock_irqrestore(&priv->ctx_lock, flags);
903 EXPORT_SYMBOL(mlx5_get_protocol_dev);
905 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
907 struct pci_dev *pdev = dev->pdev;
910 pci_set_drvdata(dev->pdev, dev);
911 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
912 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
914 mutex_init(&priv->pgdir_mutex);
915 INIT_LIST_HEAD(&priv->pgdir_list);
916 spin_lock_init(&priv->mkey_lock);
918 mutex_init(&priv->alloc_mutex);
920 priv->numa_node = dev_to_node(&dev->pdev->dev);
922 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
926 err = mlx5_pci_enable_device(dev);
928 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
932 err = request_bar(pdev);
934 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
938 pci_set_master(pdev);
940 err = set_dma_caps(pdev);
942 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
946 dev->iseg_base = pci_resource_start(dev->pdev, 0);
947 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
950 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
957 pci_clear_master(dev->pdev);
958 release_bar(dev->pdev);
960 mlx5_pci_disable_device(dev);
963 debugfs_remove(priv->dbg_root);
967 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
970 pci_clear_master(dev->pdev);
971 release_bar(dev->pdev);
972 mlx5_pci_disable_device(dev);
973 debugfs_remove(priv->dbg_root);
976 #define MLX5_IB_MOD "mlx5_ib"
977 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
979 struct pci_dev *pdev = dev->pdev;
982 mutex_lock(&dev->intf_state_mutex);
983 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
984 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
989 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
990 fw_rev_min(dev), fw_rev_sub(dev));
992 /* on load removing any previous indication of internal error, device is
995 dev->state = MLX5_DEVICE_STATE_UP;
997 err = mlx5_cmd_init(dev);
999 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1003 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1005 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1006 FW_INIT_TIMEOUT_MILI);
1010 mlx5_pagealloc_init(dev);
1012 err = mlx5_core_enable_hca(dev, 0);
1014 dev_err(&pdev->dev, "enable hca failed\n");
1015 goto err_pagealloc_cleanup;
1018 err = mlx5_core_set_issi(dev);
1020 dev_err(&pdev->dev, "failed to set issi\n");
1021 goto err_disable_hca;
1024 err = mlx5_satisfy_startup_pages(dev, 1);
1026 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1027 goto err_disable_hca;
1030 err = set_hca_ctrl(dev);
1032 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1033 goto reclaim_boot_pages;
1036 err = handle_hca_cap(dev);
1038 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1039 goto reclaim_boot_pages;
1042 err = handle_hca_cap_atomic(dev);
1044 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1045 goto reclaim_boot_pages;
1048 err = mlx5_satisfy_startup_pages(dev, 0);
1050 dev_err(&pdev->dev, "failed to allocate init pages\n");
1051 goto reclaim_boot_pages;
1054 err = mlx5_pagealloc_start(dev);
1056 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1057 goto reclaim_boot_pages;
1060 err = mlx5_cmd_init_hca(dev);
1062 dev_err(&pdev->dev, "init hca failed\n");
1063 goto err_pagealloc_stop;
1066 mlx5_start_health_poll(dev);
1068 err = mlx5_query_hca_caps(dev);
1070 dev_err(&pdev->dev, "query hca failed\n");
1074 err = mlx5_query_board_id(dev);
1076 dev_err(&pdev->dev, "query board id failed\n");
1080 err = mlx5_enable_msix(dev);
1082 dev_err(&pdev->dev, "enable msix failed\n");
1086 err = mlx5_eq_init(dev);
1088 dev_err(&pdev->dev, "failed to initialize eq\n");
1092 err = mlx5_alloc_uuars(dev, &priv->uuari);
1094 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1095 goto err_eq_cleanup;
1098 err = mlx5_start_eqs(dev);
1100 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1104 err = alloc_comp_eqs(dev);
1106 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1110 if (map_bf_area(dev))
1111 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1113 err = mlx5_irq_set_affinity_hints(dev);
1115 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1116 goto err_unmap_bf_area;
1119 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1121 mlx5_init_cq_table(dev);
1122 mlx5_init_qp_table(dev);
1123 mlx5_init_srq_table(dev);
1124 mlx5_init_mkey_table(dev);
1126 err = mlx5_init_fs(dev);
1128 dev_err(&pdev->dev, "Failed to init flow steering\n");
1131 #ifdef CONFIG_MLX5_CORE_EN
1132 err = mlx5_eswitch_init(dev);
1134 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1139 err = mlx5_sriov_init(dev);
1141 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1145 err = mlx5_register_device(dev);
1147 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1151 err = request_module_nowait(MLX5_IB_MOD);
1153 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1155 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1157 mutex_unlock(&dev->intf_state_mutex);
1162 if (mlx5_sriov_cleanup(dev))
1163 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1165 #ifdef CONFIG_MLX5_CORE_EN
1166 mlx5_eswitch_cleanup(dev->priv.eswitch);
1169 mlx5_cleanup_fs(dev);
1171 mlx5_cleanup_mkey_table(dev);
1172 mlx5_cleanup_srq_table(dev);
1173 mlx5_cleanup_qp_table(dev);
1174 mlx5_cleanup_cq_table(dev);
1175 mlx5_irq_clear_affinity_hints(dev);
1186 mlx5_free_uuars(dev, &priv->uuari);
1189 mlx5_eq_cleanup(dev);
1192 mlx5_disable_msix(dev);
1195 mlx5_stop_health_poll(dev);
1196 if (mlx5_cmd_teardown_hca(dev)) {
1197 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1202 mlx5_pagealloc_stop(dev);
1205 mlx5_reclaim_startup_pages(dev);
1208 mlx5_core_disable_hca(dev, 0);
1210 err_pagealloc_cleanup:
1211 mlx5_pagealloc_cleanup(dev);
1212 mlx5_cmd_cleanup(dev);
1215 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1216 mutex_unlock(&dev->intf_state_mutex);
1221 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1225 err = mlx5_sriov_cleanup(dev);
1227 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1232 mutex_lock(&dev->intf_state_mutex);
1233 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1234 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1238 mlx5_unregister_device(dev);
1239 #ifdef CONFIG_MLX5_CORE_EN
1240 mlx5_eswitch_cleanup(dev->priv.eswitch);
1243 mlx5_cleanup_fs(dev);
1244 mlx5_cleanup_mkey_table(dev);
1245 mlx5_cleanup_srq_table(dev);
1246 mlx5_cleanup_qp_table(dev);
1247 mlx5_cleanup_cq_table(dev);
1248 mlx5_irq_clear_affinity_hints(dev);
1252 mlx5_free_uuars(dev, &priv->uuari);
1253 mlx5_eq_cleanup(dev);
1254 mlx5_disable_msix(dev);
1255 mlx5_stop_health_poll(dev);
1256 err = mlx5_cmd_teardown_hca(dev);
1258 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1261 mlx5_pagealloc_stop(dev);
1262 mlx5_reclaim_startup_pages(dev);
1263 mlx5_core_disable_hca(dev, 0);
1264 mlx5_pagealloc_cleanup(dev);
1265 mlx5_cmd_cleanup(dev);
1268 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1269 mutex_unlock(&dev->intf_state_mutex);
1273 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1274 unsigned long param)
1276 struct mlx5_priv *priv = &dev->priv;
1277 struct mlx5_device_context *dev_ctx;
1278 unsigned long flags;
1280 spin_lock_irqsave(&priv->ctx_lock, flags);
1282 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1283 if (dev_ctx->intf->event)
1284 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1286 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1289 struct mlx5_core_event_handler {
1290 void (*event)(struct mlx5_core_dev *dev,
1291 enum mlx5_dev_event event,
1296 static int init_one(struct pci_dev *pdev,
1297 const struct pci_device_id *id)
1299 struct mlx5_core_dev *dev;
1300 struct mlx5_priv *priv;
1303 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1305 dev_err(&pdev->dev, "kzalloc failed\n");
1309 priv->pci_dev_data = id->driver_data;
1311 pci_set_drvdata(pdev, dev);
1313 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1314 pr_warn("selected profile out of range, selecting default (%d)\n",
1316 prof_sel = MLX5_DEFAULT_PROF;
1318 dev->profile = &profile[prof_sel];
1320 dev->event = mlx5_core_event;
1322 INIT_LIST_HEAD(&priv->ctx_list);
1323 spin_lock_init(&priv->ctx_lock);
1324 mutex_init(&dev->pci_status_mutex);
1325 mutex_init(&dev->intf_state_mutex);
1326 err = mlx5_pci_init(dev, priv);
1328 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1332 err = mlx5_health_init(dev);
1334 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1338 err = mlx5_load_one(dev, priv);
1340 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1347 mlx5_health_cleanup(dev);
1349 mlx5_pci_close(dev, priv);
1351 pci_set_drvdata(pdev, NULL);
1357 static void remove_one(struct pci_dev *pdev)
1359 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1360 struct mlx5_priv *priv = &dev->priv;
1362 if (mlx5_unload_one(dev, priv)) {
1363 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1364 mlx5_health_cleanup(dev);
1367 mlx5_health_cleanup(dev);
1368 mlx5_pci_close(dev, priv);
1369 pci_set_drvdata(pdev, NULL);
1373 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1374 pci_channel_state_t state)
1376 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1377 struct mlx5_priv *priv = &dev->priv;
1379 dev_info(&pdev->dev, "%s was called\n", __func__);
1380 mlx5_enter_error_state(dev);
1381 mlx5_unload_one(dev, priv);
1382 mlx5_pci_disable_device(dev);
1383 return state == pci_channel_io_perm_failure ?
1384 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1387 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1389 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1392 dev_info(&pdev->dev, "%s was called\n", __func__);
1394 err = mlx5_pci_enable_device(dev);
1396 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1398 return PCI_ERS_RESULT_DISCONNECT;
1400 pci_set_master(pdev);
1401 pci_set_power_state(pdev, PCI_D0);
1402 pci_restore_state(pdev);
1404 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1407 void mlx5_disable_device(struct mlx5_core_dev *dev)
1409 mlx5_pci_err_detected(dev->pdev, 0);
1412 /* wait for the device to show vital signs. For now we check
1413 * that we can read the device ID and that the health buffer
1414 * shows a non zero value which is different than 0xffffffff
1416 static void wait_vital(struct pci_dev *pdev)
1418 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1419 struct mlx5_core_health *health = &dev->priv.health;
1420 const int niter = 100;
1425 /* Wait for firmware to be ready after reset */
1427 for (i = 0; i < niter; i++) {
1428 if (pci_read_config_word(pdev, 2, &did)) {
1429 dev_warn(&pdev->dev, "failed reading config word\n");
1432 if (did == pdev->device) {
1433 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1439 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1441 for (i = 0; i < niter; i++) {
1442 count = ioread32be(health->health_counter);
1443 if (count && count != 0xffffffff) {
1444 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1451 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1454 static void mlx5_pci_resume(struct pci_dev *pdev)
1456 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1457 struct mlx5_priv *priv = &dev->priv;
1460 dev_info(&pdev->dev, "%s was called\n", __func__);
1462 pci_save_state(pdev);
1465 err = mlx5_load_one(dev, priv);
1467 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1470 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1473 static const struct pci_error_handlers mlx5_err_handler = {
1474 .error_detected = mlx5_pci_err_detected,
1475 .slot_reset = mlx5_pci_slot_reset,
1476 .resume = mlx5_pci_resume
1479 static const struct pci_device_id mlx5_core_pci_table[] = {
1480 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1481 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1482 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1483 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1484 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1485 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1489 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1491 static struct pci_driver mlx5_core_driver = {
1492 .name = DRIVER_NAME,
1493 .id_table = mlx5_core_pci_table,
1495 .remove = remove_one,
1496 .err_handler = &mlx5_err_handler,
1497 .sriov_configure = mlx5_core_sriov_configure,
1500 static int __init init(void)
1504 mlx5_register_debugfs();
1506 err = pci_register_driver(&mlx5_core_driver);
1510 #ifdef CONFIG_MLX5_CORE_EN
1517 mlx5_unregister_debugfs();
1521 static void __exit cleanup(void)
1523 #ifdef CONFIG_MLX5_CORE_EN
1526 pci_unregister_driver(&mlx5_core_driver);
1527 mlx5_unregister_debugfs();
1531 module_exit(cleanup);