2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/ethtool.h>
43 #include <linux/slab.h>
44 #include <linux/device.h>
45 #include <linux/skbuff.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/workqueue.h>
49 #include <linux/jiffies.h>
50 #include <linux/bitops.h>
51 #include <linux/list.h>
52 #include <linux/notifier.h>
53 #include <linux/dcbnl.h>
54 #include <net/switchdev.h>
55 #include <generated/utsrelease.h>
64 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65 static const char mlxsw_sp_driver_version[] = "1.0";
71 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
78 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
81 * Packet protocol type. Must be set to 1 (Ethernet).
83 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
85 /* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
88 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
94 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
97 * Switch partition ID. Must be set to 0.
99 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
101 /* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
105 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
108 * Egress TClass to be used on the egress device on the egress port.
110 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
120 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
127 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
131 * 6 - Control packets
133 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
135 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
151 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
153 char spad_pl[MLXSW_REG_SPAD_LEN];
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
163 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
175 static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
192 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
203 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
213 static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
230 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
251 static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
260 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
268 static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
278 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
290 static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
308 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
317 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
334 static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
350 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
359 static int mlxsw_sp_port_open(struct net_device *dev)
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
367 netif_start_queue(dev);
371 static int mlxsw_sp_port_stop(struct net_device *dev)
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
379 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
393 return NETDEV_TX_BUSY;
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
413 /* Due to a race we might fail here because of a full queue. In that
414 * unlikely case we simply drop the packet.
416 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
419 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
420 u64_stats_update_begin(&pcpu_stats->syncp);
421 pcpu_stats->tx_packets++;
422 pcpu_stats->tx_bytes += len;
423 u64_stats_update_end(&pcpu_stats->syncp);
425 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
426 dev_kfree_skb_any(skb);
431 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
435 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
437 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
438 struct sockaddr *addr = p;
441 if (!is_valid_ether_addr(addr->sa_data))
442 return -EADDRNOTAVAIL;
444 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
447 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
451 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
452 bool pause_en, bool pfc_en, u16 delay)
454 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
456 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
457 MLXSW_SP_PAUSE_DELAY;
459 if (pause_en || pfc_en)
460 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
461 pg_size + delay, pg_size);
463 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
466 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
467 u8 *prio_tc, bool pause_en,
468 struct ieee_pfc *my_pfc)
470 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
471 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
472 u16 delay = !!my_pfc ? my_pfc->delay : 0;
473 char pbmc_pl[MLXSW_REG_PBMC_LEN];
476 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
477 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
481 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
482 bool configure = false;
485 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
486 if (prio_tc[j] == i) {
487 pfc = pfc_en & BIT(j);
495 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
501 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 int mtu, bool pause_en)
504 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
505 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
506 struct ieee_pfc *my_pfc;
509 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
510 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
512 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
516 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
519 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
522 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
525 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
527 goto err_port_mtu_set;
532 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
536 static struct rtnl_link_stats64 *
537 mlxsw_sp_port_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *stats)
540 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
541 struct mlxsw_sp_port_pcpu_stats *p;
542 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
547 for_each_possible_cpu(i) {
548 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
550 start = u64_stats_fetch_begin_irq(&p->syncp);
551 rx_packets = p->rx_packets;
552 rx_bytes = p->rx_bytes;
553 tx_packets = p->tx_packets;
554 tx_bytes = p->tx_bytes;
555 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
557 stats->rx_packets += rx_packets;
558 stats->rx_bytes += rx_bytes;
559 stats->tx_packets += tx_packets;
560 stats->tx_bytes += tx_bytes;
561 /* tx_dropped is u32, updated without syncp protection. */
562 tx_dropped += p->tx_dropped;
564 stats->tx_dropped = tx_dropped;
568 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
569 u16 vid_end, bool is_member, bool untagged)
571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
575 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
579 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
580 vid_end, is_member, untagged);
581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
586 static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
588 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
589 u16 vid, last_visited_vid;
592 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
593 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
596 last_visited_vid = vid;
597 goto err_port_vid_to_fid_set;
601 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
603 last_visited_vid = VLAN_N_VID;
604 goto err_port_vid_to_fid_set;
609 err_port_vid_to_fid_set:
610 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
611 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
616 static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
618 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
622 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
626 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
627 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
636 static struct mlxsw_sp_fid *
637 mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
639 struct mlxsw_sp_fid *f;
641 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
649 static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
651 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
652 MLXSW_SP_VFID_PORT_MAX);
655 static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
657 char sfmr_pl[MLXSW_REG_SFMR_LEN];
659 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
660 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
663 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
665 static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
668 struct device *dev = mlxsw_sp->bus_info->dev;
669 struct mlxsw_sp_fid *f;
673 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
674 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
675 dev_err(dev, "No available vFIDs\n");
676 return ERR_PTR(-ERANGE);
679 fid = mlxsw_sp_vfid_to_fid(vfid);
680 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
682 dev_err(dev, "Failed to create FID=%d\n", fid);
686 f = kzalloc(sizeof(*f), GFP_KERNEL);
688 goto err_allocate_vfid;
690 f->leave = mlxsw_sp_vport_vfid_leave;
694 list_add(&f->list, &mlxsw_sp->port_vfids.list);
695 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
700 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
701 return ERR_PTR(-ENOMEM);
704 static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
705 struct mlxsw_sp_fid *f)
707 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
709 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
712 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
717 static struct mlxsw_sp_port *
718 mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
720 struct mlxsw_sp_port *mlxsw_sp_vport;
722 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
726 /* dev will be set correctly after the VLAN device is linked
727 * with the real device. In case of bridge SELF invocation, dev
730 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
731 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
732 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
733 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
734 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
735 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
736 mlxsw_sp_vport->vport.vid = vid;
738 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
740 return mlxsw_sp_vport;
743 static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
745 list_del(&mlxsw_sp_vport->vport.list);
746 kfree(mlxsw_sp_vport);
749 static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
752 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
753 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
755 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
759 static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport)
761 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
762 struct mlxsw_sp_fid *f;
765 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, vid);
767 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, vid);
773 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
775 goto err_vport_flood_set;
778 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
780 goto err_vport_fid_map;
782 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
789 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
792 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
796 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
798 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
800 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
802 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
804 if (--f->ref_count == 0) {
805 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
806 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
810 int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
813 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
814 struct mlxsw_sp_port *mlxsw_sp_vport;
817 /* VLAN 0 is added to HW filter when device goes up, but it is
818 * reserved in our case, so simply return.
823 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
824 netdev_warn(dev, "VID=%d already configured\n", vid);
828 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
829 if (!mlxsw_sp_vport) {
830 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
834 /* When adding the first VLAN interface on a bridged port we need to
835 * transition all the active 802.1Q bridge VLANs to use explicit
836 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
838 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
839 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
841 netdev_err(dev, "Failed to set to Virtual mode\n");
842 goto err_port_vp_mode_trans;
846 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
848 netdev_err(dev, "Failed to join vFID\n");
849 goto err_vport_vfid_join;
852 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
854 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
855 goto err_port_vid_learning_set;
858 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
860 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
862 goto err_port_add_vid;
865 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
866 MLXSW_REG_SPMS_STATE_FORWARDING);
868 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
869 goto err_port_stp_state_set;
874 err_port_stp_state_set:
875 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
877 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
878 err_port_vid_learning_set:
879 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
881 if (list_is_singular(&mlxsw_sp_port->vports_list))
882 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
883 err_port_vp_mode_trans:
884 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
888 int mlxsw_sp_port_kill_vid(struct net_device *dev,
889 __be16 __always_unused proto, u16 vid)
891 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
892 struct mlxsw_sp_port *mlxsw_sp_vport;
893 struct mlxsw_sp_fid *f;
896 /* VLAN 0 is removed from HW filter when device goes down, but
897 * it is reserved in our case, so simply return.
902 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
903 if (!mlxsw_sp_vport) {
904 netdev_warn(dev, "VID=%d does not exist\n", vid);
908 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
909 MLXSW_REG_SPMS_STATE_DISCARDING);
911 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
915 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
917 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
922 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
924 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
928 /* Drop FID reference. If this was the last reference the
929 * resources will be freed.
931 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
932 if (f && !WARN_ON(!f->leave))
933 f->leave(mlxsw_sp_vport);
935 /* When removing the last VLAN interface on a bridged port we need to
936 * transition all active 802.1Q bridge VLANs to use VID to FID
937 * mappings and set port's mode to VLAN mode.
939 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
940 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
942 netdev_err(dev, "Failed to set to VLAN mode\n");
947 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
952 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
955 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
956 u8 module = mlxsw_sp_port->mapping.module;
957 u8 width = mlxsw_sp_port->mapping.width;
958 u8 lane = mlxsw_sp_port->mapping.lane;
961 if (!mlxsw_sp_port->split)
962 err = snprintf(name, len, "p%d", module + 1);
964 err = snprintf(name, len, "p%ds%d", module + 1,
973 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
974 .ndo_open = mlxsw_sp_port_open,
975 .ndo_stop = mlxsw_sp_port_stop,
976 .ndo_start_xmit = mlxsw_sp_port_xmit,
977 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
978 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
979 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
980 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
981 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
982 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
983 .ndo_fdb_add = switchdev_port_fdb_add,
984 .ndo_fdb_del = switchdev_port_fdb_del,
985 .ndo_fdb_dump = switchdev_port_fdb_dump,
986 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
987 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
988 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
989 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
992 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
993 struct ethtool_drvinfo *drvinfo)
995 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
996 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
998 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
999 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1000 sizeof(drvinfo->version));
1001 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1003 mlxsw_sp->bus_info->fw_rev.major,
1004 mlxsw_sp->bus_info->fw_rev.minor,
1005 mlxsw_sp->bus_info->fw_rev.subminor);
1006 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1007 sizeof(drvinfo->bus_info));
1010 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1011 struct ethtool_pauseparam *pause)
1013 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1015 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1016 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1019 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1020 struct ethtool_pauseparam *pause)
1022 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1024 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1025 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1026 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1028 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1032 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1033 struct ethtool_pauseparam *pause)
1035 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1036 bool pause_en = pause->tx_pause || pause->rx_pause;
1039 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1040 netdev_err(dev, "PFC already enabled on port\n");
1044 if (pause->autoneg) {
1045 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1049 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1051 netdev_err(dev, "Failed to configure port's headroom\n");
1055 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1057 netdev_err(dev, "Failed to set PAUSE parameters\n");
1058 goto err_port_pause_configure;
1061 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1062 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1066 err_port_pause_configure:
1067 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1068 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1072 struct mlxsw_sp_port_hw_stats {
1073 char str[ETH_GSTRING_LEN];
1074 u64 (*getter)(char *payload);
1077 static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1079 .str = "a_frames_transmitted_ok",
1080 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1083 .str = "a_frames_received_ok",
1084 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1087 .str = "a_frame_check_sequence_errors",
1088 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1091 .str = "a_alignment_errors",
1092 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1095 .str = "a_octets_transmitted_ok",
1096 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1099 .str = "a_octets_received_ok",
1100 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1103 .str = "a_multicast_frames_xmitted_ok",
1104 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1107 .str = "a_broadcast_frames_xmitted_ok",
1108 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1111 .str = "a_multicast_frames_received_ok",
1112 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1115 .str = "a_broadcast_frames_received_ok",
1116 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1119 .str = "a_in_range_length_errors",
1120 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1123 .str = "a_out_of_range_length_field",
1124 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1127 .str = "a_frame_too_long_errors",
1128 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1131 .str = "a_symbol_error_during_carrier",
1132 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1135 .str = "a_mac_control_frames_transmitted",
1136 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1139 .str = "a_mac_control_frames_received",
1140 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1143 .str = "a_unsupported_opcodes_received",
1144 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1147 .str = "a_pause_mac_ctrl_frames_received",
1148 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1151 .str = "a_pause_mac_ctrl_frames_xmitted",
1152 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1156 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1158 static void mlxsw_sp_port_get_strings(struct net_device *dev,
1159 u32 stringset, u8 *data)
1164 switch (stringset) {
1166 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1167 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1169 p += ETH_GSTRING_LEN;
1175 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1176 enum ethtool_phys_id_state state)
1178 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1179 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1180 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1184 case ETHTOOL_ID_ACTIVE:
1187 case ETHTOOL_ID_INACTIVE:
1194 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1195 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1198 static void mlxsw_sp_port_get_stats(struct net_device *dev,
1199 struct ethtool_stats *stats, u64 *data)
1201 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1202 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1203 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1207 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1208 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
1209 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1210 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1211 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1214 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1218 return MLXSW_SP_PORT_HW_STATS_LEN;
1224 struct mlxsw_sp_port_link_mode {
1231 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1233 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1234 .supported = SUPPORTED_100baseT_Full,
1235 .advertised = ADVERTISED_100baseT_Full,
1239 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1243 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1244 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1245 .supported = SUPPORTED_1000baseKX_Full,
1246 .advertised = ADVERTISED_1000baseKX_Full,
1250 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1251 .supported = SUPPORTED_10000baseT_Full,
1252 .advertised = ADVERTISED_10000baseT_Full,
1256 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1257 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1258 .supported = SUPPORTED_10000baseKX4_Full,
1259 .advertised = ADVERTISED_10000baseKX4_Full,
1263 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1264 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1265 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1266 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1267 .supported = SUPPORTED_10000baseKR_Full,
1268 .advertised = ADVERTISED_10000baseKR_Full,
1272 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1273 .supported = SUPPORTED_20000baseKR2_Full,
1274 .advertised = ADVERTISED_20000baseKR2_Full,
1278 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1279 .supported = SUPPORTED_40000baseCR4_Full,
1280 .advertised = ADVERTISED_40000baseCR4_Full,
1284 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1285 .supported = SUPPORTED_40000baseKR4_Full,
1286 .advertised = ADVERTISED_40000baseKR4_Full,
1290 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1291 .supported = SUPPORTED_40000baseSR4_Full,
1292 .advertised = ADVERTISED_40000baseSR4_Full,
1296 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1297 .supported = SUPPORTED_40000baseLR4_Full,
1298 .advertised = ADVERTISED_40000baseLR4_Full,
1302 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1303 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1304 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1308 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1309 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1310 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1314 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1315 .supported = SUPPORTED_56000baseKR4_Full,
1316 .advertised = ADVERTISED_56000baseKR4_Full,
1320 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1321 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1322 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1323 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1328 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1330 static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1332 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1333 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1334 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1335 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1336 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1337 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1338 return SUPPORTED_FIBRE;
1340 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1341 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1342 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1343 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1344 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1345 return SUPPORTED_Backplane;
1349 static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1354 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1355 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1356 modes |= mlxsw_sp_port_link_mode[i].supported;
1361 static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1366 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1367 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1368 modes |= mlxsw_sp_port_link_mode[i].advertised;
1373 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1374 struct ethtool_cmd *cmd)
1376 u32 speed = SPEED_UNKNOWN;
1377 u8 duplex = DUPLEX_UNKNOWN;
1383 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1384 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1385 speed = mlxsw_sp_port_link_mode[i].speed;
1386 duplex = DUPLEX_FULL;
1391 ethtool_cmd_speed_set(cmd, speed);
1392 cmd->duplex = duplex;
1395 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1397 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1398 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1399 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1400 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1403 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1404 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1405 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1409 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1410 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1411 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1417 static int mlxsw_sp_port_get_settings(struct net_device *dev,
1418 struct ethtool_cmd *cmd)
1420 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1422 char ptys_pl[MLXSW_REG_PTYS_LEN];
1424 u32 eth_proto_admin;
1428 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1429 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1431 netdev_err(dev, "Failed to get proto");
1434 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap,
1435 ð_proto_admin, ð_proto_oper);
1437 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1438 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1439 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1440 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1441 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1442 eth_proto_oper, cmd);
1444 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1445 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1446 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1448 cmd->transceiver = XCVR_INTERNAL;
1452 static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1457 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1458 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1459 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1464 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1469 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1470 if (speed == mlxsw_sp_port_link_mode[i].speed)
1471 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1476 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1481 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1482 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1483 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1488 static int mlxsw_sp_port_set_settings(struct net_device *dev,
1489 struct ethtool_cmd *cmd)
1491 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1492 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1493 char ptys_pl[MLXSW_REG_PTYS_LEN];
1497 u32 eth_proto_admin;
1501 speed = ethtool_cmd_speed(cmd);
1503 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1504 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1505 mlxsw_sp_to_ptys_speed(speed);
1507 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1508 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1510 netdev_err(dev, "Failed to get proto");
1513 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, NULL);
1515 eth_proto_new = eth_proto_new & eth_proto_cap;
1516 if (!eth_proto_new) {
1517 netdev_err(dev, "Not supported proto admin requested");
1520 if (eth_proto_new == eth_proto_admin)
1523 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1524 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1526 netdev_err(dev, "Failed to set proto admin");
1530 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1532 netdev_err(dev, "Failed to get oper status");
1538 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1540 netdev_err(dev, "Failed to set admin status");
1544 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1546 netdev_err(dev, "Failed to set admin status");
1553 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1554 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1555 .get_link = ethtool_op_get_link,
1556 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1557 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
1558 .get_strings = mlxsw_sp_port_get_strings,
1559 .set_phys_id = mlxsw_sp_port_set_phys_id,
1560 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1561 .get_sset_count = mlxsw_sp_port_get_sset_count,
1562 .get_settings = mlxsw_sp_port_get_settings,
1563 .set_settings = mlxsw_sp_port_set_settings,
1567 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1570 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1571 char ptys_pl[MLXSW_REG_PTYS_LEN];
1572 u32 eth_proto_admin;
1574 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1575 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1577 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1580 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1581 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1582 bool dwrr, u8 dwrr_weight)
1584 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1585 char qeec_pl[MLXSW_REG_QEEC_LEN];
1587 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1589 mlxsw_reg_qeec_de_set(qeec_pl, true);
1590 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1591 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1592 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1595 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1596 enum mlxsw_reg_qeec_hr hr, u8 index,
1597 u8 next_index, u32 maxrate)
1599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1600 char qeec_pl[MLXSW_REG_QEEC_LEN];
1602 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1604 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1605 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1606 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1609 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1610 u8 switch_prio, u8 tclass)
1612 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1613 char qtct_pl[MLXSW_REG_QTCT_LEN];
1615 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1617 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1620 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1624 /* Setup the elements hierarcy, so that each TC is linked to
1625 * one subgroup, which are all member in the same group.
1627 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1628 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1632 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1633 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1634 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1639 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1640 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1641 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1647 /* Make sure the max shaper is disabled in all hierarcies that
1650 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1651 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1652 MLXSW_REG_QEEC_MAS_DIS);
1655 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1656 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1657 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1659 MLXSW_REG_QEEC_MAS_DIS);
1663 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1664 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1665 MLXSW_REG_QEEC_HIERARCY_TC,
1667 MLXSW_REG_QEEC_MAS_DIS);
1672 /* Map all priorities to traffic class 0. */
1673 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1674 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1682 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1683 bool split, u8 module, u8 width, u8 lane)
1685 struct mlxsw_sp_port *mlxsw_sp_port;
1686 struct net_device *dev;
1690 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1693 mlxsw_sp_port = netdev_priv(dev);
1694 mlxsw_sp_port->dev = dev;
1695 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1696 mlxsw_sp_port->local_port = local_port;
1697 mlxsw_sp_port->split = split;
1698 mlxsw_sp_port->mapping.module = module;
1699 mlxsw_sp_port->mapping.width = width;
1700 mlxsw_sp_port->mapping.lane = lane;
1701 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1702 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1703 if (!mlxsw_sp_port->active_vlans) {
1705 goto err_port_active_vlans_alloc;
1707 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1708 if (!mlxsw_sp_port->untagged_vlans) {
1710 goto err_port_untagged_vlans_alloc;
1712 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
1714 mlxsw_sp_port->pcpu_stats =
1715 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1716 if (!mlxsw_sp_port->pcpu_stats) {
1718 goto err_alloc_stats;
1721 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1722 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1724 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1726 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1727 mlxsw_sp_port->local_port);
1728 goto err_dev_addr_init;
1731 netif_carrier_off(dev);
1733 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1734 NETIF_F_HW_VLAN_CTAG_FILTER;
1736 /* Each packet needs to have a Tx header (metadata) on top all other
1739 dev->hard_header_len += MLXSW_TXHDR_LEN;
1741 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1743 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1744 mlxsw_sp_port->local_port);
1745 goto err_port_system_port_mapping_set;
1748 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1750 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1751 mlxsw_sp_port->local_port);
1752 goto err_port_swid_set;
1755 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1757 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1758 mlxsw_sp_port->local_port);
1759 goto err_port_speed_by_width_set;
1762 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1765 mlxsw_sp_port->local_port);
1766 goto err_port_mtu_set;
1769 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1771 goto err_port_admin_status_set;
1773 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1775 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1776 mlxsw_sp_port->local_port);
1777 goto err_port_buffers_init;
1780 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1782 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1783 mlxsw_sp_port->local_port);
1784 goto err_port_ets_init;
1787 /* ETS and buffers must be initialized before DCB. */
1788 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1790 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1791 mlxsw_sp_port->local_port);
1792 goto err_port_dcb_init;
1795 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1796 err = register_netdev(dev);
1798 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1799 mlxsw_sp_port->local_port);
1800 goto err_register_netdev;
1803 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1804 mlxsw_sp_port->local_port, dev,
1805 mlxsw_sp_port->split, module);
1807 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1808 mlxsw_sp_port->local_port);
1809 goto err_core_port_init;
1812 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1814 goto err_port_vlan_init;
1816 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1820 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1822 unregister_netdev(dev);
1823 err_register_netdev:
1826 err_port_buffers_init:
1827 err_port_admin_status_set:
1829 err_port_speed_by_width_set:
1831 err_port_system_port_mapping_set:
1833 free_percpu(mlxsw_sp_port->pcpu_stats);
1835 kfree(mlxsw_sp_port->untagged_vlans);
1836 err_port_untagged_vlans_alloc:
1837 kfree(mlxsw_sp_port->active_vlans);
1838 err_port_active_vlans_alloc:
1843 static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
1845 struct net_device *dev = mlxsw_sp_port->dev;
1846 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
1848 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1849 &mlxsw_sp_port->vports_list, vport.list) {
1850 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1852 /* vPorts created for VLAN devices should already be gone
1853 * by now, since we unregistered the port netdev.
1855 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1856 mlxsw_sp_port_kill_vid(dev, 0, vid);
1860 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1862 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1866 mlxsw_sp->ports[local_port] = NULL;
1867 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1868 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
1869 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1870 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
1871 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
1872 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1873 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
1874 free_percpu(mlxsw_sp_port->pcpu_stats);
1875 kfree(mlxsw_sp_port->untagged_vlans);
1876 kfree(mlxsw_sp_port->active_vlans);
1877 free_netdev(mlxsw_sp_port->dev);
1880 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1884 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1885 mlxsw_sp_port_remove(mlxsw_sp, i);
1886 kfree(mlxsw_sp->ports);
1889 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1891 u8 module, width, lane;
1896 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1897 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1898 if (!mlxsw_sp->ports)
1901 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1902 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
1905 goto err_port_module_info_get;
1908 mlxsw_sp->port_to_module[i] = module;
1909 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1912 goto err_port_create;
1917 err_port_module_info_get:
1918 for (i--; i >= 1; i--)
1919 mlxsw_sp_port_remove(mlxsw_sp, i);
1920 kfree(mlxsw_sp->ports);
1924 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1926 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1928 return local_port - offset;
1931 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1932 u8 module, unsigned int count)
1934 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1937 for (i = 0; i < count; i++) {
1938 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1941 goto err_port_module_map;
1944 for (i = 0; i < count; i++) {
1945 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1947 goto err_port_swid_set;
1950 for (i = 0; i < count; i++) {
1951 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
1952 module, width, i * width);
1954 goto err_port_create;
1960 for (i--; i >= 0; i--)
1961 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1964 for (i--; i >= 0; i--)
1965 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1966 MLXSW_PORT_SWID_DISABLED_PORT);
1968 err_port_module_map:
1969 for (i--; i >= 0; i--)
1970 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1974 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1975 u8 base_port, unsigned int count)
1977 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1980 /* Split by four means we need to re-create two ports, otherwise
1985 for (i = 0; i < count; i++) {
1986 local_port = base_port + i * 2;
1987 module = mlxsw_sp->port_to_module[local_port];
1989 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1993 for (i = 0; i < count; i++)
1994 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1996 for (i = 0; i < count; i++) {
1997 local_port = base_port + i * 2;
1998 module = mlxsw_sp->port_to_module[local_port];
2000 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
2005 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2008 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2009 struct mlxsw_sp_port *mlxsw_sp_port;
2010 u8 module, cur_width, base_port;
2014 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2015 if (!mlxsw_sp_port) {
2016 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2021 module = mlxsw_sp_port->mapping.module;
2022 cur_width = mlxsw_sp_port->mapping.width;
2024 if (count != 2 && count != 4) {
2025 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2029 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2030 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2034 /* Make sure we have enough slave (even) ports for the split. */
2036 base_port = local_port;
2037 if (mlxsw_sp->ports[base_port + 1]) {
2038 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2042 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2043 if (mlxsw_sp->ports[base_port + 1] ||
2044 mlxsw_sp->ports[base_port + 3]) {
2045 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2050 for (i = 0; i < count; i++)
2051 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2053 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2055 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2056 goto err_port_split_create;
2061 err_port_split_create:
2062 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2066 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
2068 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2069 struct mlxsw_sp_port *mlxsw_sp_port;
2070 u8 cur_width, base_port;
2074 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2075 if (!mlxsw_sp_port) {
2076 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2081 if (!mlxsw_sp_port->split) {
2082 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2086 cur_width = mlxsw_sp_port->mapping.width;
2087 count = cur_width == 1 ? 4 : 2;
2089 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2091 /* Determine which ports to remove. */
2092 if (count == 2 && local_port >= base_port + 2)
2093 base_port = base_port + 2;
2095 for (i = 0; i < count; i++)
2096 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2098 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2103 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2104 char *pude_pl, void *priv)
2106 struct mlxsw_sp *mlxsw_sp = priv;
2107 struct mlxsw_sp_port *mlxsw_sp_port;
2108 enum mlxsw_reg_pude_oper_status status;
2111 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2112 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2113 if (!mlxsw_sp_port) {
2114 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2119 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2120 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2121 netdev_info(mlxsw_sp_port->dev, "link up\n");
2122 netif_carrier_on(mlxsw_sp_port->dev);
2124 netdev_info(mlxsw_sp_port->dev, "link down\n");
2125 netif_carrier_off(mlxsw_sp_port->dev);
2129 static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2130 .func = mlxsw_sp_pude_event_func,
2131 .trap_id = MLXSW_TRAP_ID_PUDE,
2134 static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2135 enum mlxsw_event_trap_id trap_id)
2137 struct mlxsw_event_listener *el;
2138 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2142 case MLXSW_TRAP_ID_PUDE:
2143 el = &mlxsw_sp_pude_event;
2146 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2150 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2151 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2153 goto err_event_trap_set;
2158 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2162 static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2163 enum mlxsw_event_trap_id trap_id)
2165 struct mlxsw_event_listener *el;
2168 case MLXSW_TRAP_ID_PUDE:
2169 el = &mlxsw_sp_pude_event;
2172 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2175 static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2178 struct mlxsw_sp *mlxsw_sp = priv;
2179 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2180 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2182 if (unlikely(!mlxsw_sp_port)) {
2183 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2188 skb->dev = mlxsw_sp_port->dev;
2190 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2191 u64_stats_update_begin(&pcpu_stats->syncp);
2192 pcpu_stats->rx_packets++;
2193 pcpu_stats->rx_bytes += skb->len;
2194 u64_stats_update_end(&pcpu_stats->syncp);
2196 skb->protocol = eth_type_trans(skb, skb->dev);
2197 netif_receive_skb(skb);
2200 static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2202 .func = mlxsw_sp_rx_listener_func,
2203 .local_port = MLXSW_PORT_DONT_CARE,
2204 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2206 /* Traps for specific L2 packet types, not trapped as FDB MC */
2208 .func = mlxsw_sp_rx_listener_func,
2209 .local_port = MLXSW_PORT_DONT_CARE,
2210 .trap_id = MLXSW_TRAP_ID_STP,
2213 .func = mlxsw_sp_rx_listener_func,
2214 .local_port = MLXSW_PORT_DONT_CARE,
2215 .trap_id = MLXSW_TRAP_ID_LACP,
2218 .func = mlxsw_sp_rx_listener_func,
2219 .local_port = MLXSW_PORT_DONT_CARE,
2220 .trap_id = MLXSW_TRAP_ID_EAPOL,
2223 .func = mlxsw_sp_rx_listener_func,
2224 .local_port = MLXSW_PORT_DONT_CARE,
2225 .trap_id = MLXSW_TRAP_ID_LLDP,
2228 .func = mlxsw_sp_rx_listener_func,
2229 .local_port = MLXSW_PORT_DONT_CARE,
2230 .trap_id = MLXSW_TRAP_ID_MMRP,
2233 .func = mlxsw_sp_rx_listener_func,
2234 .local_port = MLXSW_PORT_DONT_CARE,
2235 .trap_id = MLXSW_TRAP_ID_MVRP,
2238 .func = mlxsw_sp_rx_listener_func,
2239 .local_port = MLXSW_PORT_DONT_CARE,
2240 .trap_id = MLXSW_TRAP_ID_RPVST,
2243 .func = mlxsw_sp_rx_listener_func,
2244 .local_port = MLXSW_PORT_DONT_CARE,
2245 .trap_id = MLXSW_TRAP_ID_DHCP,
2248 .func = mlxsw_sp_rx_listener_func,
2249 .local_port = MLXSW_PORT_DONT_CARE,
2250 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2253 .func = mlxsw_sp_rx_listener_func,
2254 .local_port = MLXSW_PORT_DONT_CARE,
2255 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2258 .func = mlxsw_sp_rx_listener_func,
2259 .local_port = MLXSW_PORT_DONT_CARE,
2260 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2263 .func = mlxsw_sp_rx_listener_func,
2264 .local_port = MLXSW_PORT_DONT_CARE,
2265 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2268 .func = mlxsw_sp_rx_listener_func,
2269 .local_port = MLXSW_PORT_DONT_CARE,
2270 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2274 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2276 char htgt_pl[MLXSW_REG_HTGT_LEN];
2277 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2281 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2282 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2286 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2287 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2291 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2292 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2293 &mlxsw_sp_rx_listener[i],
2296 goto err_rx_listener_register;
2298 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2299 mlxsw_sp_rx_listener[i].trap_id);
2300 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2302 goto err_rx_trap_set;
2307 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2308 &mlxsw_sp_rx_listener[i],
2310 err_rx_listener_register:
2311 for (i--; i >= 0; i--) {
2312 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2313 mlxsw_sp_rx_listener[i].trap_id);
2314 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2316 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2317 &mlxsw_sp_rx_listener[i],
2323 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2325 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2328 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2329 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2330 mlxsw_sp_rx_listener[i].trap_id);
2331 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2333 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2334 &mlxsw_sp_rx_listener[i],
2339 static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2340 enum mlxsw_reg_sfgc_type type,
2341 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2343 enum mlxsw_flood_table_type table_type;
2344 enum mlxsw_sp_flood_table flood_table;
2345 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2347 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
2348 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
2350 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
2352 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2353 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2355 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
2357 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2359 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2362 static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2366 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2367 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2370 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2371 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2375 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2376 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2384 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2386 char slcr_pl[MLXSW_REG_SLCR_LEN];
2388 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2389 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2390 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2391 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2392 MLXSW_REG_SLCR_LAG_HASH_SIP |
2393 MLXSW_REG_SLCR_LAG_HASH_DIP |
2394 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2395 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2396 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2400 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
2401 const struct mlxsw_bus_info *mlxsw_bus_info)
2403 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2406 mlxsw_sp->core = mlxsw_core;
2407 mlxsw_sp->bus_info = mlxsw_bus_info;
2408 INIT_LIST_HEAD(&mlxsw_sp->fids);
2409 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
2410 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
2411 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
2413 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2415 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2419 err = mlxsw_sp_ports_create(mlxsw_sp);
2421 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2425 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2427 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2428 goto err_event_register;
2431 err = mlxsw_sp_traps_init(mlxsw_sp);
2433 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2434 goto err_rx_listener_register;
2437 err = mlxsw_sp_flood_init(mlxsw_sp);
2439 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2440 goto err_flood_init;
2443 err = mlxsw_sp_buffers_init(mlxsw_sp);
2445 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2446 goto err_buffers_init;
2449 err = mlxsw_sp_lag_init(mlxsw_sp);
2451 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2455 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2457 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2458 goto err_switchdev_init;
2465 mlxsw_sp_buffers_fini(mlxsw_sp);
2468 mlxsw_sp_traps_fini(mlxsw_sp);
2469 err_rx_listener_register:
2470 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2472 mlxsw_sp_ports_remove(mlxsw_sp);
2476 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
2478 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2480 mlxsw_sp_switchdev_fini(mlxsw_sp);
2481 mlxsw_sp_buffers_fini(mlxsw_sp);
2482 mlxsw_sp_traps_fini(mlxsw_sp);
2483 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2484 mlxsw_sp_ports_remove(mlxsw_sp);
2485 WARN_ON(!list_empty(&mlxsw_sp->fids));
2488 static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2489 .used_max_vepa_channels = 1,
2490 .max_vepa_channels = 0,
2492 .max_lag = MLXSW_SP_LAG_MAX,
2493 .used_max_port_per_lag = 1,
2494 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
2496 .max_mid = MLXSW_SP_MID_MAX,
2499 .used_max_system_port = 1,
2500 .max_system_port = 64,
2501 .used_max_vlan_groups = 1,
2502 .max_vlan_groups = 127,
2503 .used_max_regions = 1,
2505 .used_flood_tables = 1,
2506 .used_flood_mode = 1,
2508 .max_fid_offset_flood_tables = 2,
2509 .fid_offset_flood_table_size = VLAN_N_VID - 1,
2510 .max_fid_flood_tables = 2,
2511 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
2512 .used_max_ib_mc = 1,
2519 .type = MLXSW_PORT_SWID_TYPE_ETH,
2524 static struct mlxsw_driver mlxsw_sp_driver = {
2525 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2526 .owner = THIS_MODULE,
2527 .priv_size = sizeof(struct mlxsw_sp),
2528 .init = mlxsw_sp_init,
2529 .fini = mlxsw_sp_fini,
2530 .port_split = mlxsw_sp_port_split,
2531 .port_unsplit = mlxsw_sp_port_unsplit,
2532 .sb_pool_get = mlxsw_sp_sb_pool_get,
2533 .sb_pool_set = mlxsw_sp_sb_pool_set,
2534 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2535 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2536 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2537 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2538 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2539 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2540 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2541 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2542 .txhdr_construct = mlxsw_sp_txhdr_construct,
2543 .txhdr_len = MLXSW_TXHDR_LEN,
2544 .profile = &mlxsw_sp_config_profile,
2547 static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
2550 if (mlxsw_sp_fid_is_vfid(fid))
2551 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
2553 return test_bit(fid, lag_port->active_vlans);
2556 static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
2559 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2560 u8 local_port = mlxsw_sp_port->local_port;
2561 u16 lag_id = mlxsw_sp_port->lag_id;
2564 if (!mlxsw_sp_port->lagged)
2567 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2568 struct mlxsw_sp_port *lag_port;
2570 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
2571 if (!lag_port || lag_port->local_port == local_port)
2573 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
2581 mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2584 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2585 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2587 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2588 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2589 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2590 mlxsw_sp_port->local_port);
2592 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2596 mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2600 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2602 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2603 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2604 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2606 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2609 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
2611 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
2614 if (mlxsw_sp_port->lagged)
2615 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
2618 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
2621 static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2623 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2626 static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2627 struct net_device *br_dev)
2629 return !mlxsw_sp->master_bridge.dev ||
2630 mlxsw_sp->master_bridge.dev == br_dev;
2633 static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2634 struct net_device *br_dev)
2636 mlxsw_sp->master_bridge.dev = br_dev;
2637 mlxsw_sp->master_bridge.ref_count++;
2640 static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2642 if (--mlxsw_sp->master_bridge.ref_count == 0)
2643 mlxsw_sp->master_bridge.dev = NULL;
2646 static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2647 struct net_device *br_dev)
2649 struct net_device *dev = mlxsw_sp_port->dev;
2652 /* When port is not bridged untagged packets are tagged with
2653 * PVID=VID=1, thereby creating an implicit VLAN interface in
2654 * the device. Remove it and let bridge code take care of its
2657 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
2661 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2663 mlxsw_sp_port->learning = 1;
2664 mlxsw_sp_port->learning_sync = 1;
2665 mlxsw_sp_port->uc_flood = 1;
2666 mlxsw_sp_port->bridged = 1;
2671 static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
2673 struct net_device *dev = mlxsw_sp_port->dev;
2675 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2677 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2679 mlxsw_sp_port->learning = 0;
2680 mlxsw_sp_port->learning_sync = 0;
2681 mlxsw_sp_port->uc_flood = 0;
2682 mlxsw_sp_port->bridged = 0;
2684 /* Add implicit VLAN interface in the device, so that untagged
2685 * packets will be classified to the default vFID.
2687 mlxsw_sp_port_add_vid(dev, 0, 1);
2690 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2692 char sldr_pl[MLXSW_REG_SLDR_LEN];
2694 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2695 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2698 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2700 char sldr_pl[MLXSW_REG_SLDR_LEN];
2702 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2703 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2706 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2707 u16 lag_id, u8 port_index)
2709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2710 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2712 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2713 lag_id, port_index);
2714 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2717 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2720 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2721 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2723 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2725 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2728 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2731 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2732 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2734 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2736 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2739 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2742 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2743 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2745 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2747 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2750 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2751 struct net_device *lag_dev,
2754 struct mlxsw_sp_upper *lag;
2755 int free_lag_id = -1;
2758 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2759 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2760 if (lag->ref_count) {
2761 if (lag->dev == lag_dev) {
2765 } else if (free_lag_id < 0) {
2769 if (free_lag_id < 0)
2771 *p_lag_id = free_lag_id;
2776 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2777 struct net_device *lag_dev,
2778 struct netdev_lag_upper_info *lag_upper_info)
2782 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2784 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2789 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2790 u16 lag_id, u8 *p_port_index)
2794 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2795 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2803 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2804 struct net_device *lag_dev)
2806 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2807 struct mlxsw_sp_upper *lag;
2812 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2815 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2816 if (!lag->ref_count) {
2817 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2823 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2826 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2828 goto err_col_port_add;
2829 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2831 goto err_col_port_enable;
2833 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2834 mlxsw_sp_port->local_port);
2835 mlxsw_sp_port->lag_id = lag_id;
2836 mlxsw_sp_port->lagged = 1;
2840 err_col_port_enable:
2841 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2843 if (!lag->ref_count)
2844 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2848 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2849 struct net_device *lag_dev)
2851 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2852 u16 lag_id = mlxsw_sp_port->lag_id;
2853 struct mlxsw_sp_upper *lag;
2855 if (!mlxsw_sp_port->lagged)
2857 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2858 WARN_ON(lag->ref_count == 0);
2860 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2861 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2863 if (mlxsw_sp_port->bridged) {
2864 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
2865 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
2868 if (lag->ref_count == 1)
2869 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2871 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2872 mlxsw_sp_port->local_port);
2873 mlxsw_sp_port->lagged = 0;
2877 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2881 char sldr_pl[MLXSW_REG_SLDR_LEN];
2883 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2884 mlxsw_sp_port->local_port);
2885 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2888 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2891 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2892 char sldr_pl[MLXSW_REG_SLDR_LEN];
2894 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2895 mlxsw_sp_port->local_port);
2896 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2899 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2900 bool lag_tx_enabled)
2903 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2904 mlxsw_sp_port->lag_id);
2906 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2907 mlxsw_sp_port->lag_id);
2910 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2911 struct netdev_lag_lower_state_info *info)
2913 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2916 static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2917 struct net_device *vlan_dev)
2919 struct mlxsw_sp_port *mlxsw_sp_vport;
2920 u16 vid = vlan_dev_vlan_id(vlan_dev);
2922 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2923 if (WARN_ON(!mlxsw_sp_vport))
2926 mlxsw_sp_vport->dev = vlan_dev;
2931 static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2932 struct net_device *vlan_dev)
2934 struct mlxsw_sp_port *mlxsw_sp_vport;
2935 u16 vid = vlan_dev_vlan_id(vlan_dev);
2937 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2938 if (WARN_ON(!mlxsw_sp_vport))
2941 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
2944 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2945 unsigned long event, void *ptr)
2947 struct netdev_notifier_changeupper_info *info;
2948 struct mlxsw_sp_port *mlxsw_sp_port;
2949 struct net_device *upper_dev;
2950 struct mlxsw_sp *mlxsw_sp;
2953 mlxsw_sp_port = netdev_priv(dev);
2954 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2958 case NETDEV_PRECHANGEUPPER:
2959 upper_dev = info->upper_dev;
2960 if (!is_vlan_dev(upper_dev) &&
2961 !netif_is_lag_master(upper_dev) &&
2962 !netif_is_bridge_master(upper_dev))
2966 /* HW limitation forbids to put ports to multiple bridges. */
2967 if (netif_is_bridge_master(upper_dev) &&
2968 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
2970 if (netif_is_lag_master(upper_dev) &&
2971 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
2974 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
2976 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
2977 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
2980 case NETDEV_CHANGEUPPER:
2981 upper_dev = info->upper_dev;
2982 if (is_vlan_dev(upper_dev)) {
2984 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
2987 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
2989 } else if (netif_is_bridge_master(upper_dev)) {
2991 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
2994 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
2995 } else if (netif_is_lag_master(upper_dev)) {
2997 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3000 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3012 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3013 unsigned long event, void *ptr)
3015 struct netdev_notifier_changelowerstate_info *info;
3016 struct mlxsw_sp_port *mlxsw_sp_port;
3019 mlxsw_sp_port = netdev_priv(dev);
3023 case NETDEV_CHANGELOWERSTATE:
3024 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3025 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3026 info->lower_state_info);
3028 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3036 static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3037 unsigned long event, void *ptr)
3040 case NETDEV_PRECHANGEUPPER:
3041 case NETDEV_CHANGEUPPER:
3042 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3043 case NETDEV_CHANGELOWERSTATE:
3044 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3050 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3051 unsigned long event, void *ptr)
3053 struct net_device *dev;
3054 struct list_head *iter;
3057 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3058 if (mlxsw_sp_port_dev_check(dev)) {
3059 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3068 static struct mlxsw_sp_fid *
3069 mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3070 const struct net_device *br_dev)
3072 struct mlxsw_sp_fid *f;
3074 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3075 if (f->dev == br_dev)
3082 static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3084 return vfid - MLXSW_SP_VFID_PORT_MAX;
3087 static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3089 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3092 static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3094 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3095 MLXSW_SP_VFID_BR_MAX);
3098 static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3100 static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3101 struct net_device *br_dev)
3103 struct device *dev = mlxsw_sp->bus_info->dev;
3104 struct mlxsw_sp_fid *f;
3108 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3109 if (vfid == MLXSW_SP_VFID_MAX) {
3110 dev_err(dev, "No available vFIDs\n");
3111 return ERR_PTR(-ERANGE);
3114 fid = mlxsw_sp_vfid_to_fid(vfid);
3115 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
3117 dev_err(dev, "Failed to create FID=%d\n", fid);
3118 return ERR_PTR(err);
3121 f = kzalloc(sizeof(*f), GFP_KERNEL);
3123 goto err_allocate_vfid;
3125 f->leave = mlxsw_sp_vport_br_vfid_leave;
3129 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3130 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
3135 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
3136 return ERR_PTR(-ENOMEM);
3139 static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3140 struct mlxsw_sp_fid *f)
3142 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3143 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
3145 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3148 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
3153 static int mlxsw_sp_vport_br_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3154 struct net_device *br_dev)
3156 struct mlxsw_sp_fid *f;
3159 f = mlxsw_sp_br_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
3161 f = mlxsw_sp_br_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
3166 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3168 goto err_vport_flood_set;
3170 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3172 goto err_vport_fid_map;
3174 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
3180 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3181 err_vport_flood_set:
3183 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3187 static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3189 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3191 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
3193 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3195 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
3197 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3198 if (--f->ref_count == 0)
3199 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3202 static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3203 struct net_device *br_dev)
3205 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3206 struct net_device *dev = mlxsw_sp_vport->dev;
3209 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
3211 err = mlxsw_sp_vport_br_vfid_join(mlxsw_sp_vport, br_dev);
3213 netdev_err(dev, "Failed to join vFID\n");
3214 goto err_vport_br_vfid_join;
3217 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3219 netdev_err(dev, "Failed to enable learning\n");
3220 goto err_port_vid_learning_set;
3223 mlxsw_sp_vport->learning = 1;
3224 mlxsw_sp_vport->learning_sync = 1;
3225 mlxsw_sp_vport->uc_flood = 1;
3226 mlxsw_sp_vport->bridged = 1;
3230 err_port_vid_learning_set:
3231 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3232 err_vport_br_vfid_join:
3233 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3237 static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3239 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3241 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3243 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3245 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3247 mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3248 MLXSW_REG_SPMS_STATE_FORWARDING);
3250 mlxsw_sp_vport->learning = 0;
3251 mlxsw_sp_vport->learning_sync = 0;
3252 mlxsw_sp_vport->uc_flood = 0;
3253 mlxsw_sp_vport->bridged = 0;
3257 mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3258 const struct net_device *br_dev)
3260 struct mlxsw_sp_port *mlxsw_sp_vport;
3262 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3264 struct net_device *dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
3266 if (dev && dev == br_dev)
3273 static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3274 unsigned long event, void *ptr,
3277 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3278 struct netdev_notifier_changeupper_info *info = ptr;
3279 struct mlxsw_sp_port *mlxsw_sp_vport;
3280 struct net_device *upper_dev;
3283 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3286 case NETDEV_PRECHANGEUPPER:
3287 upper_dev = info->upper_dev;
3288 if (!netif_is_bridge_master(upper_dev))
3292 /* We can't have multiple VLAN interfaces configured on
3293 * the same port and being members in the same bridge.
3295 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3299 case NETDEV_CHANGEUPPER:
3300 upper_dev = info->upper_dev;
3301 if (info->linking) {
3302 if (WARN_ON(!mlxsw_sp_vport))
3304 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3307 if (!mlxsw_sp_vport)
3309 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
3316 static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3317 unsigned long event, void *ptr,
3320 struct net_device *dev;
3321 struct list_head *iter;
3324 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3325 if (mlxsw_sp_port_dev_check(dev)) {
3326 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3336 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3337 unsigned long event, void *ptr)
3339 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3340 u16 vid = vlan_dev_vlan_id(vlan_dev);
3342 if (mlxsw_sp_port_dev_check(real_dev))
3343 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3345 else if (netif_is_lag_master(real_dev))
3346 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3352 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3353 unsigned long event, void *ptr)
3355 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3358 if (mlxsw_sp_port_dev_check(dev))
3359 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3360 else if (netif_is_lag_master(dev))
3361 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3362 else if (is_vlan_dev(dev))
3363 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
3365 return notifier_from_errno(err);
3368 static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3369 .notifier_call = mlxsw_sp_netdevice_event,
3372 static int __init mlxsw_sp_module_init(void)
3376 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3377 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3379 goto err_core_driver_register;
3382 err_core_driver_register:
3383 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3387 static void __exit mlxsw_sp_module_exit(void)
3389 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3390 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3393 module_init(mlxsw_sp_module_init);
3394 module_exit(mlxsw_sp_module_exit);
3396 MODULE_LICENSE("Dual BSD/GPL");
3397 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3398 MODULE_DESCRIPTION("Mellanox Spectrum driver");
3399 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);