2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #ifndef _MLXSW_SPECTRUM_H
38 #define _MLXSW_SPECTRUM_H
40 #include <linux/types.h>
41 #include <linux/netdevice.h>
42 #include <linux/rhashtable.h>
43 #include <linux/bitops.h>
44 #include <linux/if_vlan.h>
45 #include <linux/list.h>
46 #include <linux/dcbnl.h>
47 #include <linux/in6.h>
48 #include <linux/notifier.h>
49 #include <net/psample.h>
50 #include <net/pkt_cls.h>
54 #include "core_acl_flex_keys.h"
55 #include "core_acl_flex_actions.h"
57 #define MLXSW_SP_VFID_BASE VLAN_N_VID
58 #define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
60 #define MLXSW_SP_RFID_BASE 15360
61 #define MLXSW_SP_INVALID_RIF 0xffff
63 #define MLXSW_SP_MID_MAX 7000
65 #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
67 #define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
68 #define MLXSW_SP_LPM_TREE_MAX 22
69 #define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
71 #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
73 #define MLXSW_SP_BYTES_PER_CELL 96
75 #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
76 #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
78 #define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */
79 #define MLXSW_SP_KVD_GRANULARITY 128
81 /* Maximum delay buffer needed in case of PAUSE frames, in cells.
82 * Assumes 100m cable and maximum MTU.
84 #define MLXSW_SP_PAUSE_DELAY 612
86 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
88 static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
90 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
91 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
96 struct mlxsw_sp_upper {
97 struct net_device *dev;
98 unsigned int ref_count;
101 struct mlxsw_sp_fid {
102 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
103 struct list_head list;
104 unsigned int ref_count;
105 struct net_device *dev;
106 struct mlxsw_sp_rif *r;
110 struct mlxsw_sp_rif {
111 struct net_device *dev;
112 unsigned int ref_count;
113 struct mlxsw_sp_fid *f;
114 unsigned char addr[ETH_ALEN];
119 struct mlxsw_sp_mid {
120 struct list_head list;
121 unsigned char addr[ETH_ALEN];
124 unsigned int ref_count;
127 static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
129 return MLXSW_SP_VFID_BASE + vfid;
132 static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
134 return fid - MLXSW_SP_VFID_BASE;
137 static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
139 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
142 static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
144 return fid >= MLXSW_SP_RFID_BASE;
147 static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
149 return MLXSW_SP_RFID_BASE + rif;
152 struct mlxsw_sp_sb_pr {
153 enum mlxsw_reg_sbpr_mode mode;
157 struct mlxsw_cp_sb_occ {
162 struct mlxsw_sp_sb_cm {
166 struct mlxsw_cp_sb_occ occ;
169 struct mlxsw_sp_sb_pm {
172 struct mlxsw_cp_sb_occ occ;
175 #define MLXSW_SP_SB_POOL_COUNT 4
176 #define MLXSW_SP_SB_TC_COUNT 8
179 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
181 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
182 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
183 } ports[MLXSW_PORT_MAX_PORTS];
186 #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
188 struct mlxsw_sp_prefix_usage {
189 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
192 enum mlxsw_sp_l3proto {
193 MLXSW_SP_L3_PROTO_IPV4,
194 MLXSW_SP_L3_PROTO_IPV6,
197 struct mlxsw_sp_lpm_tree {
199 unsigned int ref_count;
200 enum mlxsw_sp_l3proto proto;
201 struct mlxsw_sp_prefix_usage prefix_usage;
207 u16 id; /* virtual router ID */
209 enum mlxsw_sp_l3proto proto;
210 u32 tb_id; /* kernel fib table id */
211 struct mlxsw_sp_lpm_tree *lpm_tree;
212 struct mlxsw_sp_fib *fib;
215 enum mlxsw_sp_span_type {
216 MLXSW_SP_SPAN_EGRESS,
217 MLXSW_SP_SPAN_INGRESS
220 struct mlxsw_sp_span_inspected_port {
221 struct list_head list;
222 enum mlxsw_sp_span_type type;
226 struct mlxsw_sp_span_entry {
229 struct list_head bound_ports_list;
234 enum mlxsw_sp_port_mall_action_type {
235 MLXSW_SP_PORT_MALL_MIRROR,
236 MLXSW_SP_PORT_MALL_SAMPLE,
239 struct mlxsw_sp_port_mall_mirror_tc_entry {
244 struct mlxsw_sp_port_mall_tc_entry {
245 struct list_head list;
246 unsigned long cookie;
247 enum mlxsw_sp_port_mall_action_type type;
249 struct mlxsw_sp_port_mall_mirror_tc_entry mirror;
253 struct mlxsw_sp_router {
254 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
255 struct mlxsw_sp_vr *vrs;
256 struct rhashtable neigh_ht;
257 struct rhashtable nexthop_group_ht;
259 struct delayed_work dw;
260 unsigned long interval; /* ms */
262 struct delayed_work nexthop_probe_dw;
263 #define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */
264 struct list_head nexthop_neighs_list;
272 struct list_head list;
273 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
276 struct list_head list;
277 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
279 struct list_head fids; /* VLAN-aware bridge FIDs */
280 struct mlxsw_sp_rif **rifs;
281 struct mlxsw_sp_port **ports;
282 struct mlxsw_core *core;
283 const struct mlxsw_bus_info *bus_info;
284 unsigned char base_mac[ETH_ALEN];
286 struct delayed_work dw;
287 #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
288 unsigned int interval; /* ms */
290 #define MLXSW_SP_MIN_AGEING_TIME 10
291 #define MLXSW_SP_MAX_AGEING_TIME 1000000
292 #define MLXSW_SP_DEFAULT_AGEING_TIME 300
294 struct mlxsw_sp_upper master_bridge;
295 struct mlxsw_sp_upper *lags;
296 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
297 struct mlxsw_sp_sb sb;
298 struct mlxsw_sp_router router;
299 struct mlxsw_sp_acl *acl;
301 DECLARE_BITMAP(usage, MLXSW_SP_KVD_LINEAR_SIZE);
305 struct mlxsw_sp_span_entry *entries;
308 struct notifier_block fib_nb;
311 static inline struct mlxsw_sp_upper *
312 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
314 return &mlxsw_sp->lags[lag_id];
317 struct mlxsw_sp_port_pcpu_stats {
322 struct u64_stats_sync syncp;
326 struct mlxsw_sp_port_sample {
327 struct psample_group __rcu *psample_group;
333 struct mlxsw_sp_port {
334 struct net_device *dev;
335 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
336 struct mlxsw_sp *mlxsw_sp;
348 struct list_head list;
349 struct mlxsw_sp_fid *f;
358 struct ieee_ets *ets;
359 struct ieee_maxrate *maxrate;
360 struct ieee_pfc *pfc;
367 /* 802.1Q bridge VLANs */
368 unsigned long *active_vlans;
369 unsigned long *untagged_vlans;
370 /* VLAN interfaces */
371 struct list_head vports_list;
373 struct list_head mall_tc_list;
375 #define MLXSW_HW_STATS_UPDATE_TIME HZ
376 struct rtnl_link_stats64 *cache;
377 struct delayed_work update_dw;
379 struct mlxsw_sp_port_sample *sample;
382 bool mlxsw_sp_port_dev_check(const struct net_device *dev);
383 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
384 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
387 mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
389 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
392 static inline struct mlxsw_sp_port *
393 mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
395 struct mlxsw_sp_port *mlxsw_sp_port;
398 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
400 mlxsw_sp_port = mlxsw_sp->ports[local_port];
401 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
405 mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
407 return mlxsw_sp_vport->vport.vid;
411 mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
413 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
418 static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
419 struct mlxsw_sp_fid *f)
421 mlxsw_sp_vport->vport.f = f;
424 static inline struct mlxsw_sp_fid *
425 mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
427 return mlxsw_sp_vport->vport.f;
430 static inline struct net_device *
431 mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
433 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
435 return f ? f->dev : NULL;
438 static inline struct mlxsw_sp_port *
439 mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
441 struct mlxsw_sp_port *mlxsw_sp_vport;
443 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
445 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
446 return mlxsw_sp_vport;
452 static inline struct mlxsw_sp_port *
453 mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
456 struct mlxsw_sp_port *mlxsw_sp_vport;
458 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
460 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
462 if (f && f->fid == fid)
463 return mlxsw_sp_vport;
469 static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp,
472 struct mlxsw_sp_fid *f;
474 list_for_each_entry(f, &mlxsw_sp->fids, list)
481 static inline struct mlxsw_sp_fid *
482 mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp,
483 const struct net_device *br_dev)
485 struct mlxsw_sp_fid *f;
487 list_for_each_entry(f, &mlxsw_sp->vfids.list, list)
488 if (f->dev == br_dev)
494 static inline struct mlxsw_sp_rif *
495 mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
496 const struct net_device *dev)
500 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
501 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
502 return mlxsw_sp->rifs[i];
507 enum mlxsw_sp_flood_table {
508 MLXSW_SP_FLOOD_TABLE_UC,
509 MLXSW_SP_FLOOD_TABLE_BM,
512 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
513 void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
514 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
515 int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
516 unsigned int sb_index, u16 pool_index,
517 struct devlink_sb_pool_info *pool_info);
518 int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
519 unsigned int sb_index, u16 pool_index, u32 size,
520 enum devlink_sb_threshold_type threshold_type);
521 int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
522 unsigned int sb_index, u16 pool_index,
524 int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
525 unsigned int sb_index, u16 pool_index,
527 int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
528 unsigned int sb_index, u16 tc_index,
529 enum devlink_sb_pool_type pool_type,
530 u16 *p_pool_index, u32 *p_threshold);
531 int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
532 unsigned int sb_index, u16 tc_index,
533 enum devlink_sb_pool_type pool_type,
534 u16 pool_index, u32 threshold);
535 int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
536 unsigned int sb_index);
537 int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
538 unsigned int sb_index);
539 int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
540 unsigned int sb_index, u16 pool_index,
541 u32 *p_cur, u32 *p_max);
542 int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
543 unsigned int sb_index, u16 tc_index,
544 enum devlink_sb_pool_type pool_type,
545 u32 *p_cur, u32 *p_max);
547 int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
548 void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
549 int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
550 void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
551 void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
552 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
553 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
555 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
556 u16 vid_end, bool is_member, bool untagged);
557 int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
559 void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
560 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
561 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
562 int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
564 struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid);
565 void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f);
566 void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
567 struct mlxsw_sp_rif *r);
568 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
569 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
570 bool dwrr, u8 dwrr_weight);
571 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
572 u8 switch_prio, u8 tclass);
573 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
574 u8 *prio_tc, bool pause_en,
575 struct ieee_pfc *my_pfc);
576 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
577 enum mlxsw_reg_qeec_hr hr, u8 index,
578 u8 next_index, u32 maxrate);
579 int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
580 u16 vid_begin, u16 vid_end,
583 #ifdef CONFIG_MLXSW_SPECTRUM_DCB
585 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
586 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
590 static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
595 static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
600 int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
601 void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
602 int mlxsw_sp_router_netevent_event(struct notifier_block *unused,
603 unsigned long event, void *ptr);
605 int mlxsw_sp_kvdl_alloc(struct mlxsw_sp *mlxsw_sp, unsigned int entry_count);
606 void mlxsw_sp_kvdl_free(struct mlxsw_sp *mlxsw_sp, int entry_index);
608 struct mlxsw_afk *mlxsw_sp_acl_afk(struct mlxsw_sp_acl *acl);
610 struct mlxsw_sp_acl_rule_info {
611 unsigned int priority;
612 struct mlxsw_afk_element_values values;
613 struct mlxsw_afa_block *act_block;
616 enum mlxsw_sp_acl_profile {
617 MLXSW_SP_ACL_PROFILE_FLOWER,
620 struct mlxsw_sp_acl_profile_ops {
621 size_t ruleset_priv_size;
622 int (*ruleset_add)(struct mlxsw_sp *mlxsw_sp,
623 void *priv, void *ruleset_priv);
624 void (*ruleset_del)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv);
625 int (*ruleset_bind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv,
626 struct net_device *dev, bool ingress);
627 void (*ruleset_unbind)(struct mlxsw_sp *mlxsw_sp, void *ruleset_priv);
628 size_t rule_priv_size;
629 int (*rule_add)(struct mlxsw_sp *mlxsw_sp,
630 void *ruleset_priv, void *rule_priv,
631 struct mlxsw_sp_acl_rule_info *rulei);
632 void (*rule_del)(struct mlxsw_sp *mlxsw_sp, void *rule_priv);
635 struct mlxsw_sp_acl_ops {
637 int (*init)(struct mlxsw_sp *mlxsw_sp, void *priv);
638 void (*fini)(struct mlxsw_sp *mlxsw_sp, void *priv);
639 const struct mlxsw_sp_acl_profile_ops *
640 (*profile_ops)(struct mlxsw_sp *mlxsw_sp,
641 enum mlxsw_sp_acl_profile profile);
644 struct mlxsw_sp_acl_ruleset;
646 struct mlxsw_sp_acl_ruleset *
647 mlxsw_sp_acl_ruleset_get(struct mlxsw_sp *mlxsw_sp,
648 struct net_device *dev, bool ingress,
649 enum mlxsw_sp_acl_profile profile);
650 void mlxsw_sp_acl_ruleset_put(struct mlxsw_sp *mlxsw_sp,
651 struct mlxsw_sp_acl_ruleset *ruleset);
653 struct mlxsw_sp_acl_rule_info *
654 mlxsw_sp_acl_rulei_create(struct mlxsw_sp_acl *acl);
655 void mlxsw_sp_acl_rulei_destroy(struct mlxsw_sp_acl_rule_info *rulei);
656 int mlxsw_sp_acl_rulei_commit(struct mlxsw_sp_acl_rule_info *rulei);
657 void mlxsw_sp_acl_rulei_priority(struct mlxsw_sp_acl_rule_info *rulei,
658 unsigned int priority);
659 void mlxsw_sp_acl_rulei_keymask_u32(struct mlxsw_sp_acl_rule_info *rulei,
660 enum mlxsw_afk_element element,
661 u32 key_value, u32 mask_value);
662 void mlxsw_sp_acl_rulei_keymask_buf(struct mlxsw_sp_acl_rule_info *rulei,
663 enum mlxsw_afk_element element,
664 const char *key_value,
665 const char *mask_value, unsigned int len);
666 void mlxsw_sp_acl_rulei_act_continue(struct mlxsw_sp_acl_rule_info *rulei);
667 void mlxsw_sp_acl_rulei_act_jump(struct mlxsw_sp_acl_rule_info *rulei,
669 int mlxsw_sp_acl_rulei_act_drop(struct mlxsw_sp_acl_rule_info *rulei);
670 int mlxsw_sp_acl_rulei_act_fwd(struct mlxsw_sp *mlxsw_sp,
671 struct mlxsw_sp_acl_rule_info *rulei,
672 struct net_device *out_dev);
674 struct mlxsw_sp_acl_rule;
676 struct mlxsw_sp_acl_rule *
677 mlxsw_sp_acl_rule_create(struct mlxsw_sp *mlxsw_sp,
678 struct mlxsw_sp_acl_ruleset *ruleset,
679 unsigned long cookie);
680 void mlxsw_sp_acl_rule_destroy(struct mlxsw_sp *mlxsw_sp,
681 struct mlxsw_sp_acl_rule *rule);
682 int mlxsw_sp_acl_rule_add(struct mlxsw_sp *mlxsw_sp,
683 struct mlxsw_sp_acl_rule *rule);
684 void mlxsw_sp_acl_rule_del(struct mlxsw_sp *mlxsw_sp,
685 struct mlxsw_sp_acl_rule *rule);
686 struct mlxsw_sp_acl_rule *
687 mlxsw_sp_acl_rule_lookup(struct mlxsw_sp *mlxsw_sp,
688 struct mlxsw_sp_acl_ruleset *ruleset,
689 unsigned long cookie);
690 struct mlxsw_sp_acl_rule_info *
691 mlxsw_sp_acl_rule_rulei(struct mlxsw_sp_acl_rule *rule);
693 int mlxsw_sp_acl_init(struct mlxsw_sp *mlxsw_sp);
694 void mlxsw_sp_acl_fini(struct mlxsw_sp *mlxsw_sp);
696 extern const struct mlxsw_sp_acl_ops mlxsw_sp_acl_tcam_ops;
698 int mlxsw_sp_flower_replace(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress,
699 __be16 protocol, struct tc_cls_flower_offload *f);
700 void mlxsw_sp_flower_destroy(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress,
701 struct tc_cls_flower_offload *f);