drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/dcbnl.h>
  38 #include <linux/if_ether.h>
  39
  40 #include "spectrum.h"
  41 #include "core.h"
  42 #include "port.h"
  43 #include "reg.h"
  44
  45 static struct mlxsw_sp_sb_pr *mlxsw_sp_sb_pr_get(struct mlxsw_sp *mlxsw_sp,
  46                                                  u8 pool,
  47                                                  enum mlxsw_reg_sbxx_dir dir)
  48 {
  49         return &mlxsw_sp->sb.prs[dir][pool];
  50 }
  51
  52 static struct mlxsw_sp_sb_cm *mlxsw_sp_sb_cm_get(struct mlxsw_sp *mlxsw_sp,
  53                                                  u8 local_port, u8 pg_buff,
  54                                                  enum mlxsw_reg_sbxx_dir dir)
  55 {
  56         return &mlxsw_sp->sb.ports[local_port].cms[dir][pg_buff];
  57 }
  58
  59 static struct mlxsw_sp_sb_pm *mlxsw_sp_sb_pm_get(struct mlxsw_sp *mlxsw_sp,
  60                                                  u8 local_port, u8 pool,
  61                                                  enum mlxsw_reg_sbxx_dir dir)
  62 {
  63         return &mlxsw_sp->sb.ports[local_port].pms[dir][pool];
  64 }
  65
  66 static int mlxsw_sp_sb_pr_write(struct mlxsw_sp *mlxsw_sp, u8 pool,
  67                                 enum mlxsw_reg_sbxx_dir dir,
  68                                 enum mlxsw_reg_sbpr_mode mode, u32 size)
  69 {
  70         char sbpr_pl[MLXSW_REG_SBPR_LEN];
  71         struct mlxsw_sp_sb_pr *pr;
  72         int err;
  73
  74         mlxsw_reg_sbpr_pack(sbpr_pl, pool, dir, mode, size);
  75         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
  76         if (err)
  77                 return err;
  78
  79         pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
  80         pr->mode = mode;
  81         pr->size = size;
  82         return 0;
  83 }
  84
  85 static int mlxsw_sp_sb_cm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  86                                 u8 pg_buff, enum mlxsw_reg_sbxx_dir dir,
  87                                 u32 min_buff, u32 max_buff, u8 pool)
  88 {
  89         char sbcm_pl[MLXSW_REG_SBCM_LEN];
  90         int err;
  91
  92         mlxsw_reg_sbcm_pack(sbcm_pl, local_port, pg_buff, dir,
  93                             min_buff, max_buff, pool);
  94         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
  95         if (err)
  96                 return err;
  97         if (pg_buff < MLXSW_SP_SB_TC_COUNT) {
  98                 struct mlxsw_sp_sb_cm *cm;
  99
 100                 cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, pg_buff, dir);
 101                 cm->min_buff = min_buff;
 102                 cm->max_buff = max_buff;
 103                 cm->pool = pool;
 104         }
 105         return 0;
 106 }
 107
 108 static int mlxsw_sp_sb_pm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 109                                 u8 pool, enum mlxsw_reg_sbxx_dir dir,
 110                                 u32 min_buff, u32 max_buff)
 111 {
 112         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 113         struct mlxsw_sp_sb_pm *pm;
 114         int err;
 115
 116         mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, min_buff, max_buff);
 117         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl);
 118         if (err)
 119                 return err;
 120
 121         pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool, dir);
 122         pm->min_buff = min_buff;
 123         pm->max_buff = max_buff;
 124         return 0;
 125 }
 126
 127 static const u16 mlxsw_sp_pbs[] = {
 128         2 * MLXSW_SP_BYTES_TO_CELLS(ETH_FRAME_LEN),
 129         0,
 130         0,
 131         0,
 132         0,
 133         0,
 134         0,
 135         0,
 136         0, /* Unused */
 137         2 * MLXSW_SP_BYTES_TO_CELLS(MLXSW_PORT_MAX_MTU),
 138 };
 139
 140 #define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
 141
 142 static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
 143 {
 144         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 145         int i;
 146
 147         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
 148                             0xffff, 0xffff / 2);
 149         for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
 150                 if (i == 8)
 151                         continue;
 152                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, i, mlxsw_sp_pbs[i]);
 153         }
 154         mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl,
 155                                          MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX, 0);
 156         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
 157                                MLXSW_REG(pbmc), pbmc_pl);
 158 }
 159
 160 static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
 161 {
 162         char pptb_pl[MLXSW_REG_PPTB_LEN];
 163         int i;
 164
 165         mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
 166         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
 167                 mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, 0);
 168         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
 169                                pptb_pl);
 170 }
 171
 172 static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
 173 {
 174         int err;
 175
 176         err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
 177         if (err)
 178                 return err;
 179         return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
 180 }
 181
 182 #define MLXSW_SP_SB_PR_INGRESS_SIZE                             \
 183         (15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS))
 184 #define MLXSW_SP_SB_PR_EGRESS_SIZE                              \
 185         (14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS))
 186
 187 #define MLXSW_SP_SB_PR(_mode, _size)    \
 188         {                               \
 189                 .mode = _mode,          \
 190                 .size = _size,          \
 191         }
 192
 193 static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_ingress[] = {
 194         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 195                        MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_INGRESS_SIZE)),
 196         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 197         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 198         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 199 };
 200
 201 #define MLXSW_SP_SB_PRS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_ingress)
 202
 203 static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_egress[] = {
 204         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 205                        MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_EGRESS_SIZE)),
 206         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 207         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 208         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 209 };
 210
 211 #define MLXSW_SP_SB_PRS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_egress)
 212
 213 static int __mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
 214                                   enum mlxsw_reg_sbxx_dir dir,
 215                                   const struct mlxsw_sp_sb_pr *prs,
 216                                   size_t prs_len)
 217 {
 218         int i;
 219         int err;
 220
 221         for (i = 0; i < prs_len; i++) {
 222                 const struct mlxsw_sp_sb_pr *pr;
 223
 224                 pr = &prs[i];
 225                 err = mlxsw_sp_sb_pr_write(mlxsw_sp, i, dir,
 226                                            pr->mode, pr->size);
 227                 if (err)
 228                         return err;
 229         }
 230         return 0;
 231 }
 232
 233 static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp)
 234 {
 235         int err;
 236
 237         err = __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_INGRESS,
 238                                      mlxsw_sp_sb_prs_ingress,
 239                                      MLXSW_SP_SB_PRS_INGRESS_LEN);
 240         if (err)
 241                 return err;
 242         return __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_EGRESS,
 243                                       mlxsw_sp_sb_prs_egress,
 244                                       MLXSW_SP_SB_PRS_EGRESS_LEN);
 245 }
 246
 247 #define MLXSW_SP_SB_CM(_min_buff, _max_buff, _pool)     \
 248         {                                               \
 249                 .min_buff = _min_buff,                  \
 250                 .max_buff = _max_buff,                  \
 251                 .pool = _pool,                          \
 252         }
 253
 254 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
 255         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(10000), 8, 0),
 256         MLXSW_SP_SB_CM(0, 0, 0),
 257         MLXSW_SP_SB_CM(0, 0, 0),
 258         MLXSW_SP_SB_CM(0, 0, 0),
 259         MLXSW_SP_SB_CM(0, 0, 0),
 260         MLXSW_SP_SB_CM(0, 0, 0),
 261         MLXSW_SP_SB_CM(0, 0, 0),
 262         MLXSW_SP_SB_CM(0, 0, 0),
 263         MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
 264         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 265 };
 266
 267 #define MLXSW_SP_SB_CMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_ingress)
 268
 269 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
 270         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 271         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 272         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 273         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 274         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 275         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 276         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 277         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 278         MLXSW_SP_SB_CM(0, 0, 0),
 279         MLXSW_SP_SB_CM(0, 0, 0),
 280         MLXSW_SP_SB_CM(0, 0, 0),
 281         MLXSW_SP_SB_CM(0, 0, 0),
 282         MLXSW_SP_SB_CM(0, 0, 0),
 283         MLXSW_SP_SB_CM(0, 0, 0),
 284         MLXSW_SP_SB_CM(0, 0, 0),
 285         MLXSW_SP_SB_CM(0, 0, 0),
 286         MLXSW_SP_SB_CM(1, 0xff, 0),
 287 };
 288
 289 #define MLXSW_SP_SB_CMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_egress)
 290
 291 #define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 0)
 292
 293 static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
 294         MLXSW_SP_CPU_PORT_SB_CM,
 295         MLXSW_SP_CPU_PORT_SB_CM,
 296         MLXSW_SP_CPU_PORT_SB_CM,
 297         MLXSW_SP_CPU_PORT_SB_CM,
 298         MLXSW_SP_CPU_PORT_SB_CM,
 299         MLXSW_SP_CPU_PORT_SB_CM,
 300         MLXSW_SP_CPU_PORT_SB_CM,
 301         MLXSW_SP_CPU_PORT_SB_CM,
 302         MLXSW_SP_CPU_PORT_SB_CM,
 303         MLXSW_SP_CPU_PORT_SB_CM,
 304         MLXSW_SP_CPU_PORT_SB_CM,
 305         MLXSW_SP_CPU_PORT_SB_CM,
 306         MLXSW_SP_CPU_PORT_SB_CM,
 307         MLXSW_SP_CPU_PORT_SB_CM,
 308         MLXSW_SP_CPU_PORT_SB_CM,
 309         MLXSW_SP_CPU_PORT_SB_CM,
 310         MLXSW_SP_CPU_PORT_SB_CM,
 311         MLXSW_SP_CPU_PORT_SB_CM,
 312         MLXSW_SP_CPU_PORT_SB_CM,
 313         MLXSW_SP_CPU_PORT_SB_CM,
 314         MLXSW_SP_CPU_PORT_SB_CM,
 315         MLXSW_SP_CPU_PORT_SB_CM,
 316         MLXSW_SP_CPU_PORT_SB_CM,
 317         MLXSW_SP_CPU_PORT_SB_CM,
 318         MLXSW_SP_CPU_PORT_SB_CM,
 319         MLXSW_SP_CPU_PORT_SB_CM,
 320         MLXSW_SP_CPU_PORT_SB_CM,
 321         MLXSW_SP_CPU_PORT_SB_CM,
 322         MLXSW_SP_CPU_PORT_SB_CM,
 323         MLXSW_SP_CPU_PORT_SB_CM,
 324         MLXSW_SP_CPU_PORT_SB_CM,
 325         MLXSW_SP_CPU_PORT_SB_CM,
 326 };
 327
 328 #define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
 329         ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
 330
 331 static int __mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 332                                   enum mlxsw_reg_sbxx_dir dir,
 333                                   const struct mlxsw_sp_sb_cm *cms,
 334                                   size_t cms_len)
 335 {
 336         int i;
 337         int err;
 338
 339         for (i = 0; i < cms_len; i++) {
 340                 const struct mlxsw_sp_sb_cm *cm;
 341
 342                 if (i == 8 && dir == MLXSW_REG_SBXX_DIR_INGRESS)
 343                         continue; /* PG number 8 does not exist, skip it */
 344                 cm = &cms[i];
 345                 err = mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, i, dir,
 346                                            cm->min_buff, cm->max_buff,
 347                                            cm->pool);
 348                 if (err)
 349                         return err;
 350         }
 351         return 0;
 352 }
 353
 354 static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 355 {
 356         int err;
 357
 358         err = __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 359                                      mlxsw_sp_port->local_port,
 360                                      MLXSW_REG_SBXX_DIR_INGRESS,
 361                                      mlxsw_sp_sb_cms_ingress,
 362                                      MLXSW_SP_SB_CMS_INGRESS_LEN);
 363         if (err)
 364                 return err;
 365         return __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 366                                       mlxsw_sp_port->local_port,
 367                                       MLXSW_REG_SBXX_DIR_EGRESS,
 368                                       mlxsw_sp_sb_cms_egress,
 369                                       MLXSW_SP_SB_CMS_EGRESS_LEN);
 370 }
 371
 372 static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
 373 {
 374         return __mlxsw_sp_sb_cms_init(mlxsw_sp, 0, MLXSW_REG_SBXX_DIR_EGRESS,
 375                                       mlxsw_sp_cpu_port_sb_cms,
 376                                       MLXSW_SP_CPU_PORT_SB_MCS_LEN);
 377 }
 378
 379 #define MLXSW_SP_SB_PM(_min_buff, _max_buff)    \
 380         {                                       \
 381                 .min_buff = _min_buff,          \
 382                 .max_buff = _max_buff,          \
 383         }
 384
 385 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_ingress[] = {
 386         MLXSW_SP_SB_PM(0, 0xff),
 387         MLXSW_SP_SB_PM(0, 0),
 388         MLXSW_SP_SB_PM(0, 0),
 389         MLXSW_SP_SB_PM(0, 0),
 390 };
 391
 392 #define MLXSW_SP_SB_PMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_ingress)
 393
 394 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_egress[] = {
 395         MLXSW_SP_SB_PM(0, 7),
 396         MLXSW_SP_SB_PM(0, 0),
 397         MLXSW_SP_SB_PM(0, 0),
 398         MLXSW_SP_SB_PM(0, 0),
 399 };
 400
 401 #define MLXSW_SP_SB_PMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_egress)
 402
 403 static int __mlxsw_sp_port_sb_pms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 404                                        enum mlxsw_reg_sbxx_dir dir,
 405                                        const struct mlxsw_sp_sb_pm *pms,
 406                                        size_t pms_len)
 407 {
 408         int i;
 409         int err;
 410
 411         for (i = 0; i < pms_len; i++) {
 412                 const struct mlxsw_sp_sb_pm *pm;
 413
 414                 pm = &pms[i];
 415                 err = mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, i, dir,
 416                                            pm->min_buff, pm->max_buff);
 417                 if (err)
 418                         return err;
 419         }
 420         return 0;
 421 }
 422
 423 static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 424 {
 425         int err;
 426
 427         err = __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
 428                                           mlxsw_sp_port->local_port,
 429                                           MLXSW_REG_SBXX_DIR_INGRESS,
 430                                           mlxsw_sp_sb_pms_ingress,
 431                                           MLXSW_SP_SB_PMS_INGRESS_LEN);
 432         if (err)
 433                 return err;
 434         return __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
 435                                            mlxsw_sp_port->local_port,
 436                                            MLXSW_REG_SBXX_DIR_EGRESS,
 437                                            mlxsw_sp_sb_pms_egress,
 438                                            MLXSW_SP_SB_PMS_EGRESS_LEN);
 439 }
 440
 441 struct mlxsw_sp_sb_mm {
 442         u32 min_buff;
 443         u32 max_buff;
 444         u8 pool;
 445 };
 446
 447 #define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool)     \
 448         {                                               \
 449                 .min_buff = _min_buff,                  \
 450                 .max_buff = _max_buff,                  \
 451                 .pool = _pool,                          \
 452         }
 453
 454 static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
 455         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 456         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 457         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 458         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 459         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 460         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 461         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 462         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 463         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 464         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 465         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 466         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 467         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 468         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 469         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 470 };
 471
 472 #define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
 473
 474 static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
 475 {
 476         char sbmm_pl[MLXSW_REG_SBMM_LEN];
 477         int i;
 478         int err;
 479
 480         for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
 481                 const struct mlxsw_sp_sb_mm *mc;
 482
 483                 mc = &mlxsw_sp_sb_mms[i];
 484                 mlxsw_reg_sbmm_pack(sbmm_pl, i, mc->min_buff,
 485                                     mc->max_buff, mc->pool);
 486                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
 487                 if (err)
 488                         return err;
 489         }
 490         return 0;
 491 }
 492
 493 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
 494 {
 495         int err;
 496
 497         err = mlxsw_sp_sb_prs_init(mlxsw_sp);
 498         if (err)
 499                 return err;
 500         err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
 501         if (err)
 502                 return err;
 503         err = mlxsw_sp_sb_mms_init(mlxsw_sp);
 504
 505         return err;
 506 }
 507
 508 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
 509 {
 510         int err;
 511
 512         err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
 513         if (err)
 514                 return err;
 515         err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
 516         if (err)
 517                 return err;
 518         err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
 519
 520         return err;
 521 }