drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/dcbnl.h>
  38 #include <linux/if_ether.h>
  39
  40 #include "spectrum.h"
  41 #include "core.h"
  42 #include "port.h"
  43 #include "reg.h"
  44
  45 static struct mlxsw_sp_sb_pr *mlxsw_sp_sb_pr_get(struct mlxsw_sp *mlxsw_sp,
  46                                                  u8 pool,
  47                                                  enum mlxsw_reg_sbxx_dir dir)
  48 {
  49         return &mlxsw_sp->sb.prs[dir][pool];
  50 }
  51
  52 static struct mlxsw_sp_sb_cm *mlxsw_sp_sb_cm_get(struct mlxsw_sp *mlxsw_sp,
  53                                                  u8 local_port, u8 pg_buff,
  54                                                  enum mlxsw_reg_sbxx_dir dir)
  55 {
  56         return &mlxsw_sp->sb.ports[local_port].cms[dir][pg_buff];
  57 }
  58
  59 static struct mlxsw_sp_sb_pm *mlxsw_sp_sb_pm_get(struct mlxsw_sp *mlxsw_sp,
  60                                                  u8 local_port, u8 pool,
  61                                                  enum mlxsw_reg_sbxx_dir dir)
  62 {
  63         return &mlxsw_sp->sb.ports[local_port].pms[dir][pool];
  64 }
  65
  66 static int mlxsw_sp_sb_pr_write(struct mlxsw_sp *mlxsw_sp, u8 pool,
  67                                 enum mlxsw_reg_sbxx_dir dir,
  68                                 enum mlxsw_reg_sbpr_mode mode, u32 size)
  69 {
  70         char sbpr_pl[MLXSW_REG_SBPR_LEN];
  71         struct mlxsw_sp_sb_pr *pr;
  72         int err;
  73
  74         mlxsw_reg_sbpr_pack(sbpr_pl, pool, dir, mode, size);
  75         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
  76         if (err)
  77                 return err;
  78
  79         pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
  80         pr->mode = mode;
  81         pr->size = size;
  82         return 0;
  83 }
  84
  85 static int mlxsw_sp_sb_cm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  86                                 u8 pg_buff, enum mlxsw_reg_sbxx_dir dir,
  87                                 u32 min_buff, u32 max_buff, u8 pool)
  88 {
  89         char sbcm_pl[MLXSW_REG_SBCM_LEN];
  90         int err;
  91
  92         mlxsw_reg_sbcm_pack(sbcm_pl, local_port, pg_buff, dir,
  93                             min_buff, max_buff, pool);
  94         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
  95         if (err)
  96                 return err;
  97         if (pg_buff < MLXSW_SP_SB_TC_COUNT) {
  98                 struct mlxsw_sp_sb_cm *cm;
  99
 100                 cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, pg_buff, dir);
 101                 cm->min_buff = min_buff;
 102                 cm->max_buff = max_buff;
 103                 cm->pool = pool;
 104         }
 105         return 0;
 106 }
 107
 108 static int mlxsw_sp_sb_pm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 109                                 u8 pool, enum mlxsw_reg_sbxx_dir dir,
 110                                 u32 min_buff, u32 max_buff)
 111 {
 112         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 113         struct mlxsw_sp_sb_pm *pm;
 114         int err;
 115
 116         mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, min_buff, max_buff);
 117         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl);
 118         if (err)
 119                 return err;
 120
 121         pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool, dir);
 122         pm->min_buff = min_buff;
 123         pm->max_buff = max_buff;
 124         return 0;
 125 }
 126
 127 static const u16 mlxsw_sp_pbs[] = {
 128         2 * MLXSW_SP_BYTES_TO_CELLS(ETH_FRAME_LEN),
 129         0,
 130         0,
 131         0,
 132         0,
 133         0,
 134         0,
 135         0,
 136         0, /* Unused */
 137         2 * MLXSW_SP_BYTES_TO_CELLS(MLXSW_PORT_MAX_MTU),
 138 };
 139
 140 #define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
 141
 142 static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
 143 {
 144         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 145         int i;
 146
 147         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
 148                             0xffff, 0xffff / 2);
 149         for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
 150                 if (i == 8)
 151                         continue;
 152                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, i, mlxsw_sp_pbs[i]);
 153         }
 154         mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl,
 155                                          MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX, 0);
 156         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
 157                                MLXSW_REG(pbmc), pbmc_pl);
 158 }
 159
 160 static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
 161 {
 162         char pptb_pl[MLXSW_REG_PPTB_LEN];
 163         int i;
 164
 165         mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
 166         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
 167                 mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, 0);
 168         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
 169                                pptb_pl);
 170 }
 171
 172 static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
 173 {
 174         int err;
 175
 176         err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
 177         if (err)
 178                 return err;
 179         return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
 180 }
 181
 182 #define MLXSW_SP_SB_PR_INGRESS_SIZE                             \
 183         (15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS))
 184 #define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
 185 #define MLXSW_SP_SB_PR_EGRESS_SIZE                              \
 186         (14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS))
 187
 188 #define MLXSW_SP_SB_PR(_mode, _size)    \
 189         {                               \
 190                 .mode = _mode,          \
 191                 .size = _size,          \
 192         }
 193
 194 static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_ingress[] = {
 195         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 196                        MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_INGRESS_SIZE)),
 197         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 198         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 199         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 200                        MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_INGRESS_MNG_SIZE)),
 201 };
 202
 203 #define MLXSW_SP_SB_PRS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_ingress)
 204
 205 static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_egress[] = {
 206         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 207                        MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_PR_EGRESS_SIZE)),
 208         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 209         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 210         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 211 };
 212
 213 #define MLXSW_SP_SB_PRS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_egress)
 214
 215 static int __mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
 216                                   enum mlxsw_reg_sbxx_dir dir,
 217                                   const struct mlxsw_sp_sb_pr *prs,
 218                                   size_t prs_len)
 219 {
 220         int i;
 221         int err;
 222
 223         for (i = 0; i < prs_len; i++) {
 224                 const struct mlxsw_sp_sb_pr *pr;
 225
 226                 pr = &prs[i];
 227                 err = mlxsw_sp_sb_pr_write(mlxsw_sp, i, dir,
 228                                            pr->mode, pr->size);
 229                 if (err)
 230                         return err;
 231         }
 232         return 0;
 233 }
 234
 235 static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp)
 236 {
 237         int err;
 238
 239         err = __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_INGRESS,
 240                                      mlxsw_sp_sb_prs_ingress,
 241                                      MLXSW_SP_SB_PRS_INGRESS_LEN);
 242         if (err)
 243                 return err;
 244         return __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_EGRESS,
 245                                       mlxsw_sp_sb_prs_egress,
 246                                       MLXSW_SP_SB_PRS_EGRESS_LEN);
 247 }
 248
 249 #define MLXSW_SP_SB_CM(_min_buff, _max_buff, _pool)     \
 250         {                                               \
 251                 .min_buff = _min_buff,                  \
 252                 .max_buff = _max_buff,                  \
 253                 .pool = _pool,                          \
 254         }
 255
 256 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
 257         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(10000), 8, 0),
 258         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 259         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 260         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 261         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 262         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 263         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 264         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 265         MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
 266         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(20000), 1, 3),
 267 };
 268
 269 #define MLXSW_SP_SB_CMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_ingress)
 270
 271 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
 272         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 273         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 274         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 275         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 276         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 277         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 278         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 279         MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(1500), 9, 0),
 280         MLXSW_SP_SB_CM(0, 0, 0),
 281         MLXSW_SP_SB_CM(0, 0, 0),
 282         MLXSW_SP_SB_CM(0, 0, 0),
 283         MLXSW_SP_SB_CM(0, 0, 0),
 284         MLXSW_SP_SB_CM(0, 0, 0),
 285         MLXSW_SP_SB_CM(0, 0, 0),
 286         MLXSW_SP_SB_CM(0, 0, 0),
 287         MLXSW_SP_SB_CM(0, 0, 0),
 288         MLXSW_SP_SB_CM(1, 0xff, 0),
 289 };
 290
 291 #define MLXSW_SP_SB_CMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_egress)
 292
 293 #define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 0)
 294
 295 static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
 296         MLXSW_SP_CPU_PORT_SB_CM,
 297         MLXSW_SP_CPU_PORT_SB_CM,
 298         MLXSW_SP_CPU_PORT_SB_CM,
 299         MLXSW_SP_CPU_PORT_SB_CM,
 300         MLXSW_SP_CPU_PORT_SB_CM,
 301         MLXSW_SP_CPU_PORT_SB_CM,
 302         MLXSW_SP_CPU_PORT_SB_CM,
 303         MLXSW_SP_CPU_PORT_SB_CM,
 304         MLXSW_SP_CPU_PORT_SB_CM,
 305         MLXSW_SP_CPU_PORT_SB_CM,
 306         MLXSW_SP_CPU_PORT_SB_CM,
 307         MLXSW_SP_CPU_PORT_SB_CM,
 308         MLXSW_SP_CPU_PORT_SB_CM,
 309         MLXSW_SP_CPU_PORT_SB_CM,
 310         MLXSW_SP_CPU_PORT_SB_CM,
 311         MLXSW_SP_CPU_PORT_SB_CM,
 312         MLXSW_SP_CPU_PORT_SB_CM,
 313         MLXSW_SP_CPU_PORT_SB_CM,
 314         MLXSW_SP_CPU_PORT_SB_CM,
 315         MLXSW_SP_CPU_PORT_SB_CM,
 316         MLXSW_SP_CPU_PORT_SB_CM,
 317         MLXSW_SP_CPU_PORT_SB_CM,
 318         MLXSW_SP_CPU_PORT_SB_CM,
 319         MLXSW_SP_CPU_PORT_SB_CM,
 320         MLXSW_SP_CPU_PORT_SB_CM,
 321         MLXSW_SP_CPU_PORT_SB_CM,
 322         MLXSW_SP_CPU_PORT_SB_CM,
 323         MLXSW_SP_CPU_PORT_SB_CM,
 324         MLXSW_SP_CPU_PORT_SB_CM,
 325         MLXSW_SP_CPU_PORT_SB_CM,
 326         MLXSW_SP_CPU_PORT_SB_CM,
 327         MLXSW_SP_CPU_PORT_SB_CM,
 328 };
 329
 330 #define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
 331         ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
 332
 333 static int __mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 334                                   enum mlxsw_reg_sbxx_dir dir,
 335                                   const struct mlxsw_sp_sb_cm *cms,
 336                                   size_t cms_len)
 337 {
 338         int i;
 339         int err;
 340
 341         for (i = 0; i < cms_len; i++) {
 342                 const struct mlxsw_sp_sb_cm *cm;
 343
 344                 if (i == 8 && dir == MLXSW_REG_SBXX_DIR_INGRESS)
 345                         continue; /* PG number 8 does not exist, skip it */
 346                 cm = &cms[i];
 347                 err = mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, i, dir,
 348                                            cm->min_buff, cm->max_buff,
 349                                            cm->pool);
 350                 if (err)
 351                         return err;
 352         }
 353         return 0;
 354 }
 355
 356 static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 357 {
 358         int err;
 359
 360         err = __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 361                                      mlxsw_sp_port->local_port,
 362                                      MLXSW_REG_SBXX_DIR_INGRESS,
 363                                      mlxsw_sp_sb_cms_ingress,
 364                                      MLXSW_SP_SB_CMS_INGRESS_LEN);
 365         if (err)
 366                 return err;
 367         return __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 368                                       mlxsw_sp_port->local_port,
 369                                       MLXSW_REG_SBXX_DIR_EGRESS,
 370                                       mlxsw_sp_sb_cms_egress,
 371                                       MLXSW_SP_SB_CMS_EGRESS_LEN);
 372 }
 373
 374 static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
 375 {
 376         return __mlxsw_sp_sb_cms_init(mlxsw_sp, 0, MLXSW_REG_SBXX_DIR_EGRESS,
 377                                       mlxsw_sp_cpu_port_sb_cms,
 378                                       MLXSW_SP_CPU_PORT_SB_MCS_LEN);
 379 }
 380
 381 #define MLXSW_SP_SB_PM(_min_buff, _max_buff)    \
 382         {                                       \
 383                 .min_buff = _min_buff,          \
 384                 .max_buff = _max_buff,          \
 385         }
 386
 387 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_ingress[] = {
 388         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
 389         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 390         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 391         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
 392 };
 393
 394 #define MLXSW_SP_SB_PMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_ingress)
 395
 396 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_egress[] = {
 397         MLXSW_SP_SB_PM(0, 7),
 398         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 399         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 400         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 401 };
 402
 403 #define MLXSW_SP_SB_PMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_egress)
 404
 405 static int __mlxsw_sp_port_sb_pms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 406                                        enum mlxsw_reg_sbxx_dir dir,
 407                                        const struct mlxsw_sp_sb_pm *pms,
 408                                        size_t pms_len)
 409 {
 410         int i;
 411         int err;
 412
 413         for (i = 0; i < pms_len; i++) {
 414                 const struct mlxsw_sp_sb_pm *pm;
 415
 416                 pm = &pms[i];
 417                 err = mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, i, dir,
 418                                            pm->min_buff, pm->max_buff);
 419                 if (err)
 420                         return err;
 421         }
 422         return 0;
 423 }
 424
 425 static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 426 {
 427         int err;
 428
 429         err = __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
 430                                           mlxsw_sp_port->local_port,
 431                                           MLXSW_REG_SBXX_DIR_INGRESS,
 432                                           mlxsw_sp_sb_pms_ingress,
 433                                           MLXSW_SP_SB_PMS_INGRESS_LEN);
 434         if (err)
 435                 return err;
 436         return __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
 437                                            mlxsw_sp_port->local_port,
 438                                            MLXSW_REG_SBXX_DIR_EGRESS,
 439                                            mlxsw_sp_sb_pms_egress,
 440                                            MLXSW_SP_SB_PMS_EGRESS_LEN);
 441 }
 442
 443 struct mlxsw_sp_sb_mm {
 444         u32 min_buff;
 445         u32 max_buff;
 446         u8 pool;
 447 };
 448
 449 #define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool)     \
 450         {                                               \
 451                 .min_buff = _min_buff,                  \
 452                 .max_buff = _max_buff,                  \
 453                 .pool = _pool,                          \
 454         }
 455
 456 static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
 457         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 458         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 459         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 460         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 461         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 462         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 463         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 464         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 465         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 466         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 467         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 468         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 469         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 470         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 471         MLXSW_SP_SB_MM(MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 472 };
 473
 474 #define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
 475
 476 static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
 477 {
 478         char sbmm_pl[MLXSW_REG_SBMM_LEN];
 479         int i;
 480         int err;
 481
 482         for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
 483                 const struct mlxsw_sp_sb_mm *mc;
 484
 485                 mc = &mlxsw_sp_sb_mms[i];
 486                 mlxsw_reg_sbmm_pack(sbmm_pl, i, mc->min_buff,
 487                                     mc->max_buff, mc->pool);
 488                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
 489                 if (err)
 490                         return err;
 491         }
 492         return 0;
 493 }
 494
 495 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
 496 {
 497         int err;
 498
 499         err = mlxsw_sp_sb_prs_init(mlxsw_sp);
 500         if (err)
 501                 return err;
 502         err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
 503         if (err)
 504                 return err;
 505         err = mlxsw_sp_sb_mms_init(mlxsw_sp);
 506
 507         return err;
 508 }
 509
 510 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
 511 {
 512         int err;
 513
 514         err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
 515         if (err)
 516                 return err;
 517         err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
 518         if (err)
 519                 return err;
 520         err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
 521
 522         return err;
 523 }