2 * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/slab.h>
43 #include <linux/device.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <net/switchdev.h>
47 #include <generated/utsrelease.h>
55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
56 static const char mlxsw_sx_driver_version[] = "1.0";
61 struct mlxsw_sx_port **ports;
62 struct mlxsw_core *core;
63 const struct mlxsw_bus_info *bus_info;
67 struct mlxsw_sx_port_pcpu_stats {
72 struct u64_stats_sync syncp;
76 struct mlxsw_sx_port {
77 struct mlxsw_core_port core_port; /* must be first */
78 struct net_device *dev;
79 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
80 struct mlxsw_sx *mlxsw_sx;
88 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
91 * Packet control type.
92 * 0 - Ethernet control (e.g. EMADs, LACP)
95 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
98 * Packet protocol type. Must be set to 1 (Ethernet).
100 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
103 * Egress TClass to be used on the egress device on the egress port.
104 * The MSB is specified in the 'ctclass3' field.
105 * Range is 0-15, where 15 is the highest priority.
107 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
110 * Switch partition ID.
112 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
115 * Destination local port for unicast packets.
116 * Destination multicast ID for multicast packets.
118 * Control packets are directed to a specific egress port, while data
119 * packets are transmitted through the CPU port (0) into the switch partition,
120 * where forwarding rules are applied.
122 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
125 * See field 'etclass'.
127 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
130 * RDQ for control packets sent to remote CPU.
131 * Must be set to 0x1F for EMADs, otherwise 0.
133 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
136 * Signature control for packets going to CPU. Must be set to 0.
138 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
141 * Stacking protocl signature. Must be set to 0xE0E0.
143 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
148 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
151 * EMAD bit. Must be set for EMADs.
153 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
157 * 6 - Control packets
159 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
162 const struct mlxsw_tx_info *tx_info)
164 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
165 bool is_emad = tx_info->is_emad;
167 memset(txhdr, 0, MLXSW_TXHDR_LEN);
169 /* We currently set default values for the egress tclass (QoS). */
170 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
171 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
172 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
173 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
174 MLXSW_TXHDR_ETCLASS_5);
175 mlxsw_tx_hdr_swid_set(txhdr, 0);
176 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
177 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
178 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
179 MLXSW_TXHDR_RDQ_OTHER);
180 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
181 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
182 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
183 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
184 MLXSW_TXHDR_NOT_EMAD);
185 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
188 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
191 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
192 char paos_pl[MLXSW_REG_PAOS_LEN];
194 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
195 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
196 MLXSW_PORT_ADMIN_STATUS_DOWN);
197 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
200 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
203 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
204 char paos_pl[MLXSW_REG_PAOS_LEN];
208 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
209 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
212 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
213 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
217 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
219 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
220 char pmtu_pl[MLXSW_REG_PMTU_LEN];
224 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
225 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
226 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
229 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
234 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
235 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
238 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
240 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
241 char pspa_pl[MLXSW_REG_PSPA_LEN];
243 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
244 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
248 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
250 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
251 char sspr_pl[MLXSW_REG_SSPR_LEN];
253 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
254 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
257 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
260 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
261 char pmlp_pl[MLXSW_REG_PMLP_LEN];
264 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
265 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
268 *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
272 static int mlxsw_sx_port_open(struct net_device *dev)
274 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
277 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
280 netif_start_queue(dev);
284 static int mlxsw_sx_port_stop(struct net_device *dev)
286 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
288 netif_stop_queue(dev);
289 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
292 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
293 struct net_device *dev)
295 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
296 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
297 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
298 const struct mlxsw_tx_info tx_info = {
299 .local_port = mlxsw_sx_port->local_port,
305 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
306 return NETDEV_TX_BUSY;
308 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
309 struct sk_buff *skb_orig = skb;
311 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
313 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
314 dev_kfree_skb_any(skb_orig);
318 mlxsw_sx_txhdr_construct(skb, &tx_info);
320 /* Due to a race we might fail here because of a full queue. In that
321 * unlikely case we simply drop the packet.
323 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
326 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
327 u64_stats_update_begin(&pcpu_stats->syncp);
328 pcpu_stats->tx_packets++;
329 pcpu_stats->tx_bytes += len;
330 u64_stats_update_end(&pcpu_stats->syncp);
332 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
333 dev_kfree_skb_any(skb);
338 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
340 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
343 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
350 static struct rtnl_link_stats64 *
351 mlxsw_sx_port_get_stats64(struct net_device *dev,
352 struct rtnl_link_stats64 *stats)
354 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
355 struct mlxsw_sx_port_pcpu_stats *p;
356 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
361 for_each_possible_cpu(i) {
362 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
364 start = u64_stats_fetch_begin_irq(&p->syncp);
365 rx_packets = p->rx_packets;
366 rx_bytes = p->rx_bytes;
367 tx_packets = p->tx_packets;
368 tx_bytes = p->tx_bytes;
369 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
371 stats->rx_packets += rx_packets;
372 stats->rx_bytes += rx_bytes;
373 stats->tx_packets += tx_packets;
374 stats->tx_bytes += tx_bytes;
375 /* tx_dropped is u32, updated without syncp protection. */
376 tx_dropped += p->tx_dropped;
378 stats->tx_dropped = tx_dropped;
382 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
383 .ndo_open = mlxsw_sx_port_open,
384 .ndo_stop = mlxsw_sx_port_stop,
385 .ndo_start_xmit = mlxsw_sx_port_xmit,
386 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
387 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
390 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
391 struct ethtool_drvinfo *drvinfo)
393 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
394 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
396 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
397 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
398 sizeof(drvinfo->version));
399 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
401 mlxsw_sx->bus_info->fw_rev.major,
402 mlxsw_sx->bus_info->fw_rev.minor,
403 mlxsw_sx->bus_info->fw_rev.subminor);
404 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
405 sizeof(drvinfo->bus_info));
408 struct mlxsw_sx_port_hw_stats {
409 char str[ETH_GSTRING_LEN];
410 u64 (*getter)(char *payload);
413 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
415 .str = "a_frames_transmitted_ok",
416 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
419 .str = "a_frames_received_ok",
420 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
423 .str = "a_frame_check_sequence_errors",
424 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
427 .str = "a_alignment_errors",
428 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
431 .str = "a_octets_transmitted_ok",
432 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
435 .str = "a_octets_received_ok",
436 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
439 .str = "a_multicast_frames_xmitted_ok",
440 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
443 .str = "a_broadcast_frames_xmitted_ok",
444 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
447 .str = "a_multicast_frames_received_ok",
448 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
451 .str = "a_broadcast_frames_received_ok",
452 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
455 .str = "a_in_range_length_errors",
456 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
459 .str = "a_out_of_range_length_field",
460 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
463 .str = "a_frame_too_long_errors",
464 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
467 .str = "a_symbol_error_during_carrier",
468 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
471 .str = "a_mac_control_frames_transmitted",
472 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
475 .str = "a_mac_control_frames_received",
476 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
479 .str = "a_unsupported_opcodes_received",
480 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
483 .str = "a_pause_mac_ctrl_frames_received",
484 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
487 .str = "a_pause_mac_ctrl_frames_xmitted",
488 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
492 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
494 static void mlxsw_sx_port_get_strings(struct net_device *dev,
495 u32 stringset, u8 *data)
502 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
503 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
505 p += ETH_GSTRING_LEN;
511 static void mlxsw_sx_port_get_stats(struct net_device *dev,
512 struct ethtool_stats *stats, u64 *data)
514 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
515 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
516 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
520 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
521 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
522 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
523 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
524 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
527 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
531 return MLXSW_SX_PORT_HW_STATS_LEN;
537 struct mlxsw_sx_port_link_mode {
544 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
546 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
547 .supported = SUPPORTED_100baseT_Full,
548 .advertised = ADVERTISED_100baseT_Full,
552 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
556 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
557 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
558 .supported = SUPPORTED_1000baseKX_Full,
559 .advertised = ADVERTISED_1000baseKX_Full,
563 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
564 .supported = SUPPORTED_10000baseT_Full,
565 .advertised = ADVERTISED_10000baseT_Full,
569 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
570 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
571 .supported = SUPPORTED_10000baseKX4_Full,
572 .advertised = ADVERTISED_10000baseKX4_Full,
576 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
577 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
578 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
579 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
580 .supported = SUPPORTED_10000baseKR_Full,
581 .advertised = ADVERTISED_10000baseKR_Full,
585 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
586 .supported = SUPPORTED_20000baseKR2_Full,
587 .advertised = ADVERTISED_20000baseKR2_Full,
591 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
592 .supported = SUPPORTED_40000baseCR4_Full,
593 .advertised = ADVERTISED_40000baseCR4_Full,
597 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
598 .supported = SUPPORTED_40000baseKR4_Full,
599 .advertised = ADVERTISED_40000baseKR4_Full,
603 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
604 .supported = SUPPORTED_40000baseSR4_Full,
605 .advertised = ADVERTISED_40000baseSR4_Full,
609 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
610 .supported = SUPPORTED_40000baseLR4_Full,
611 .advertised = ADVERTISED_40000baseLR4_Full,
615 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
616 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
617 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
621 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
622 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
623 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
627 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
628 .supported = SUPPORTED_56000baseKR4_Full,
629 .advertised = ADVERTISED_56000baseKR4_Full,
633 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
634 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
635 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
636 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
641 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
643 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
645 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
646 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
647 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
648 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
649 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
650 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
651 return SUPPORTED_FIBRE;
653 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
654 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
655 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
656 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
657 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
658 return SUPPORTED_Backplane;
662 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
667 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
668 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
669 modes |= mlxsw_sx_port_link_mode[i].supported;
674 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
679 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
680 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
681 modes |= mlxsw_sx_port_link_mode[i].advertised;
686 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
687 struct ethtool_cmd *cmd)
689 u32 speed = SPEED_UNKNOWN;
690 u8 duplex = DUPLEX_UNKNOWN;
696 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
697 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
698 speed = mlxsw_sx_port_link_mode[i].speed;
699 duplex = DUPLEX_FULL;
704 ethtool_cmd_speed_set(cmd, speed);
705 cmd->duplex = duplex;
708 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
710 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
711 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
712 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
713 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
716 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
717 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
718 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
721 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
722 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
723 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
724 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
730 static int mlxsw_sx_port_get_settings(struct net_device *dev,
731 struct ethtool_cmd *cmd)
733 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
734 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
735 char ptys_pl[MLXSW_REG_PTYS_LEN];
741 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
742 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
744 netdev_err(dev, "Failed to get proto");
747 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap,
748 ð_proto_admin, ð_proto_oper);
750 cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
751 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
752 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
753 cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
754 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
755 eth_proto_oper, cmd);
757 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
758 cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
759 cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
761 cmd->transceiver = XCVR_INTERNAL;
765 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
770 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
771 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
772 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
777 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
782 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
783 if (speed == mlxsw_sx_port_link_mode[i].speed)
784 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
789 static int mlxsw_sx_port_set_settings(struct net_device *dev,
790 struct ethtool_cmd *cmd)
792 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
793 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
794 char ptys_pl[MLXSW_REG_PTYS_LEN];
802 speed = ethtool_cmd_speed(cmd);
804 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
805 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
806 mlxsw_sx_to_ptys_speed(speed);
808 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
809 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
811 netdev_err(dev, "Failed to get proto");
814 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, NULL);
816 eth_proto_new = eth_proto_new & eth_proto_cap;
817 if (!eth_proto_new) {
818 netdev_err(dev, "Not supported proto admin requested");
821 if (eth_proto_new == eth_proto_admin)
824 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
825 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
827 netdev_err(dev, "Failed to set proto admin");
831 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
833 netdev_err(dev, "Failed to get oper status");
839 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
841 netdev_err(dev, "Failed to set admin status");
845 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
847 netdev_err(dev, "Failed to set admin status");
854 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
855 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
856 .get_link = ethtool_op_get_link,
857 .get_strings = mlxsw_sx_port_get_strings,
858 .get_ethtool_stats = mlxsw_sx_port_get_stats,
859 .get_sset_count = mlxsw_sx_port_get_sset_count,
860 .get_settings = mlxsw_sx_port_get_settings,
861 .set_settings = mlxsw_sx_port_set_settings,
864 static int mlxsw_sx_port_attr_get(struct net_device *dev,
865 struct switchdev_attr *attr)
867 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
868 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
871 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
872 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
873 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
882 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
883 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
886 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
888 char spad_pl[MLXSW_REG_SPAD_LEN];
891 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
894 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
898 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
900 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
901 struct net_device *dev = mlxsw_sx_port->dev;
902 char ppad_pl[MLXSW_REG_PPAD_LEN];
905 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
906 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
909 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
910 /* The last byte value in base mac address is guaranteed
911 * to be such it does not overflow when adding local_port
914 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
918 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
919 u16 vid, enum mlxsw_reg_spms_state state)
921 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
925 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
928 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
929 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
930 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
935 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
938 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
939 char ptys_pl[MLXSW_REG_PTYS_LEN];
941 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
942 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
946 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
947 enum mlxsw_reg_spmlr_learn_mode mode)
949 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
950 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
952 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
953 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
956 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
958 struct mlxsw_sx_port *mlxsw_sx_port;
959 struct net_device *dev;
963 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
966 mlxsw_sx_port = netdev_priv(dev);
967 mlxsw_sx_port->dev = dev;
968 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
969 mlxsw_sx_port->local_port = local_port;
971 mlxsw_sx_port->pcpu_stats =
972 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
973 if (!mlxsw_sx_port->pcpu_stats) {
975 goto err_alloc_stats;
978 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
979 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
980 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
982 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
984 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
985 mlxsw_sx_port->local_port);
986 goto err_dev_addr_get;
989 netif_carrier_off(dev);
991 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
992 NETIF_F_VLAN_CHALLENGED;
994 /* Each packet needs to have a Tx header (metadata) on top all other
997 dev->hard_header_len += MLXSW_TXHDR_LEN;
999 err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
1001 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
1002 mlxsw_sx_port->local_port);
1003 goto err_port_module_check;
1007 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1008 mlxsw_sx_port->local_port);
1009 goto port_not_usable;
1012 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1014 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1015 mlxsw_sx_port->local_port);
1016 goto err_port_system_port_mapping_set;
1019 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1021 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1022 mlxsw_sx_port->local_port);
1023 goto err_port_swid_set;
1026 err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1027 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1029 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1030 mlxsw_sx_port->local_port);
1031 goto err_port_speed_set;
1034 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1036 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1037 mlxsw_sx_port->local_port);
1038 goto err_port_mtu_set;
1041 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1043 goto err_port_admin_status_set;
1045 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1046 MLXSW_PORT_DEFAULT_VID,
1047 MLXSW_REG_SPMS_STATE_FORWARDING);
1049 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1050 mlxsw_sx_port->local_port);
1051 goto err_port_stp_state_set;
1054 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1055 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1057 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1058 mlxsw_sx_port->local_port);
1059 goto err_port_mac_learning_mode_set;
1062 err = register_netdev(dev);
1064 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1065 mlxsw_sx_port->local_port);
1066 goto err_register_netdev;
1069 err = mlxsw_core_port_init(mlxsw_sx->core, &mlxsw_sx_port->core_port,
1070 mlxsw_sx_port->local_port, dev, false, 0);
1072 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1073 mlxsw_sx_port->local_port);
1074 goto err_core_port_init;
1077 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1081 unregister_netdev(dev);
1082 err_register_netdev:
1083 err_port_mac_learning_mode_set:
1084 err_port_stp_state_set:
1085 err_port_admin_status_set:
1089 err_port_system_port_mapping_set:
1091 err_port_module_check:
1093 free_percpu(mlxsw_sx_port->pcpu_stats);
1099 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1101 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1105 mlxsw_core_port_fini(&mlxsw_sx_port->core_port);
1106 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1107 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1108 free_percpu(mlxsw_sx_port->pcpu_stats);
1109 free_netdev(mlxsw_sx_port->dev);
1112 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1116 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1117 mlxsw_sx_port_remove(mlxsw_sx, i);
1118 kfree(mlxsw_sx->ports);
1121 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1127 alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1128 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1129 if (!mlxsw_sx->ports)
1132 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1133 err = mlxsw_sx_port_create(mlxsw_sx, i);
1135 goto err_port_create;
1140 for (i--; i >= 1; i--)
1141 mlxsw_sx_port_remove(mlxsw_sx, i);
1142 kfree(mlxsw_sx->ports);
1146 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1147 char *pude_pl, void *priv)
1149 struct mlxsw_sx *mlxsw_sx = priv;
1150 struct mlxsw_sx_port *mlxsw_sx_port;
1151 enum mlxsw_reg_pude_oper_status status;
1154 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1155 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1156 if (!mlxsw_sx_port) {
1157 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1162 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1163 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1164 netdev_info(mlxsw_sx_port->dev, "link up\n");
1165 netif_carrier_on(mlxsw_sx_port->dev);
1167 netdev_info(mlxsw_sx_port->dev, "link down\n");
1168 netif_carrier_off(mlxsw_sx_port->dev);
1172 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1173 .func = mlxsw_sx_pude_event_func,
1174 .trap_id = MLXSW_TRAP_ID_PUDE,
1177 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1178 enum mlxsw_event_trap_id trap_id)
1180 struct mlxsw_event_listener *el;
1181 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1185 case MLXSW_TRAP_ID_PUDE:
1186 el = &mlxsw_sx_pude_event;
1189 err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1193 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
1194 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1196 goto err_event_trap_set;
1201 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1205 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1206 enum mlxsw_event_trap_id trap_id)
1208 struct mlxsw_event_listener *el;
1211 case MLXSW_TRAP_ID_PUDE:
1212 el = &mlxsw_sx_pude_event;
1215 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1218 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1221 struct mlxsw_sx *mlxsw_sx = priv;
1222 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1223 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1225 if (unlikely(!mlxsw_sx_port)) {
1226 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1231 skb->dev = mlxsw_sx_port->dev;
1233 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1234 u64_stats_update_begin(&pcpu_stats->syncp);
1235 pcpu_stats->rx_packets++;
1236 pcpu_stats->rx_bytes += skb->len;
1237 u64_stats_update_end(&pcpu_stats->syncp);
1239 skb->protocol = eth_type_trans(skb, skb->dev);
1240 netif_receive_skb(skb);
1243 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1245 .func = mlxsw_sx_rx_listener_func,
1246 .local_port = MLXSW_PORT_DONT_CARE,
1247 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1249 /* Traps for specific L2 packet types, not trapped as FDB MC */
1251 .func = mlxsw_sx_rx_listener_func,
1252 .local_port = MLXSW_PORT_DONT_CARE,
1253 .trap_id = MLXSW_TRAP_ID_STP,
1256 .func = mlxsw_sx_rx_listener_func,
1257 .local_port = MLXSW_PORT_DONT_CARE,
1258 .trap_id = MLXSW_TRAP_ID_LACP,
1261 .func = mlxsw_sx_rx_listener_func,
1262 .local_port = MLXSW_PORT_DONT_CARE,
1263 .trap_id = MLXSW_TRAP_ID_EAPOL,
1266 .func = mlxsw_sx_rx_listener_func,
1267 .local_port = MLXSW_PORT_DONT_CARE,
1268 .trap_id = MLXSW_TRAP_ID_LLDP,
1271 .func = mlxsw_sx_rx_listener_func,
1272 .local_port = MLXSW_PORT_DONT_CARE,
1273 .trap_id = MLXSW_TRAP_ID_MMRP,
1276 .func = mlxsw_sx_rx_listener_func,
1277 .local_port = MLXSW_PORT_DONT_CARE,
1278 .trap_id = MLXSW_TRAP_ID_MVRP,
1281 .func = mlxsw_sx_rx_listener_func,
1282 .local_port = MLXSW_PORT_DONT_CARE,
1283 .trap_id = MLXSW_TRAP_ID_RPVST,
1286 .func = mlxsw_sx_rx_listener_func,
1287 .local_port = MLXSW_PORT_DONT_CARE,
1288 .trap_id = MLXSW_TRAP_ID_DHCP,
1291 .func = mlxsw_sx_rx_listener_func,
1292 .local_port = MLXSW_PORT_DONT_CARE,
1293 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1296 .func = mlxsw_sx_rx_listener_func,
1297 .local_port = MLXSW_PORT_DONT_CARE,
1298 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1301 .func = mlxsw_sx_rx_listener_func,
1302 .local_port = MLXSW_PORT_DONT_CARE,
1303 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1306 .func = mlxsw_sx_rx_listener_func,
1307 .local_port = MLXSW_PORT_DONT_CARE,
1308 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1311 .func = mlxsw_sx_rx_listener_func,
1312 .local_port = MLXSW_PORT_DONT_CARE,
1313 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1317 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1319 char htgt_pl[MLXSW_REG_HTGT_LEN];
1320 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1324 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1325 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1329 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
1330 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1334 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1335 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1336 &mlxsw_sx_rx_listener[i],
1339 goto err_rx_listener_register;
1341 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1342 mlxsw_sx_rx_listener[i].trap_id);
1343 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1345 goto err_rx_trap_set;
1350 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1351 &mlxsw_sx_rx_listener[i],
1353 err_rx_listener_register:
1354 for (i--; i >= 0; i--) {
1355 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1356 mlxsw_sx_rx_listener[i].trap_id);
1357 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1359 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1360 &mlxsw_sx_rx_listener[i],
1366 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1368 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1371 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1372 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1373 mlxsw_sx_rx_listener[i].trap_id);
1374 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1376 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1377 &mlxsw_sx_rx_listener[i],
1382 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1384 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1385 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1389 /* Configure a flooding table, which includes only CPU port. */
1390 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1393 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1394 MLXSW_PORT_CPU_PORT, true);
1395 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1400 /* Flood different packet types using the flooding table. */
1401 mlxsw_reg_sfgc_pack(sfgc_pl,
1402 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1403 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1404 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1406 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1410 mlxsw_reg_sfgc_pack(sfgc_pl,
1411 MLXSW_REG_SFGC_TYPE_BROADCAST,
1412 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1413 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1415 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1419 mlxsw_reg_sfgc_pack(sfgc_pl,
1420 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1421 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1422 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1424 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1428 mlxsw_reg_sfgc_pack(sfgc_pl,
1429 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1430 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1431 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1433 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1437 mlxsw_reg_sfgc_pack(sfgc_pl,
1438 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1439 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1440 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1442 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1446 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1447 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1450 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1451 const struct mlxsw_bus_info *mlxsw_bus_info)
1453 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1456 mlxsw_sx->core = mlxsw_core;
1457 mlxsw_sx->bus_info = mlxsw_bus_info;
1459 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1461 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1465 err = mlxsw_sx_ports_create(mlxsw_sx);
1467 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1471 err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1473 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1474 goto err_event_register;
1477 err = mlxsw_sx_traps_init(mlxsw_sx);
1479 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1480 goto err_rx_listener_register;
1483 err = mlxsw_sx_flood_init(mlxsw_sx);
1485 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1486 goto err_flood_init;
1492 mlxsw_sx_traps_fini(mlxsw_sx);
1493 err_rx_listener_register:
1494 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1496 mlxsw_sx_ports_remove(mlxsw_sx);
1500 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1502 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1504 mlxsw_sx_traps_fini(mlxsw_sx);
1505 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1506 mlxsw_sx_ports_remove(mlxsw_sx);
1509 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1510 .used_max_vepa_channels = 1,
1511 .max_vepa_channels = 0,
1514 .used_max_port_per_lag = 1,
1515 .max_port_per_lag = 16,
1520 .used_max_system_port = 1,
1521 .max_system_port = 48000,
1522 .used_max_vlan_groups = 1,
1523 .max_vlan_groups = 127,
1524 .used_max_regions = 1,
1526 .used_flood_tables = 1,
1527 .max_flood_tables = 2,
1528 .max_vid_flood_tables = 1,
1529 .used_flood_mode = 1,
1531 .used_max_ib_mc = 1,
1538 .type = MLXSW_PORT_SWID_TYPE_ETH,
1543 static struct mlxsw_driver mlxsw_sx_driver = {
1544 .kind = MLXSW_DEVICE_KIND_SWITCHX2,
1545 .owner = THIS_MODULE,
1546 .priv_size = sizeof(struct mlxsw_sx),
1547 .init = mlxsw_sx_init,
1548 .fini = mlxsw_sx_fini,
1549 .txhdr_construct = mlxsw_sx_txhdr_construct,
1550 .txhdr_len = MLXSW_TXHDR_LEN,
1551 .profile = &mlxsw_sx_config_profile,
1554 static int __init mlxsw_sx_module_init(void)
1556 return mlxsw_core_driver_register(&mlxsw_sx_driver);
1559 static void __exit mlxsw_sx_module_exit(void)
1561 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1564 module_init(mlxsw_sx_module_init);
1565 module_exit(mlxsw_sx_module_exit);
1567 MODULE_LICENSE("Dual BSD/GPL");
1568 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1569 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1570 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);