2 * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/slab.h>
43 #include <linux/device.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <net/switchdev.h>
47 #include <generated/utsrelease.h>
55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
56 static const char mlxsw_sx_driver_version[] = "1.0";
60 #define MLXSW_SW_HW_ID_LEN 6
63 struct mlxsw_sx_port **ports;
64 struct mlxsw_core *core;
65 const struct mlxsw_bus_info *bus_info;
66 u8 hw_id[MLXSW_SW_HW_ID_LEN];
69 struct mlxsw_sx_port_pcpu_stats {
74 struct u64_stats_sync syncp;
78 struct mlxsw_sx_port {
79 struct net_device *dev;
80 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
81 struct mlxsw_sx *mlxsw_sx;
89 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
92 * Packet control type.
93 * 0 - Ethernet control (e.g. EMADs, LACP)
96 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
99 * Packet protocol type. Must be set to 1 (Ethernet).
101 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
104 * Egress TClass to be used on the egress device on the egress port.
105 * The MSB is specified in the 'ctclass3' field.
106 * Range is 0-15, where 15 is the highest priority.
108 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
111 * Switch partition ID.
113 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
116 * Destination local port for unicast packets.
117 * Destination multicast ID for multicast packets.
119 * Control packets are directed to a specific egress port, while data
120 * packets are transmitted through the CPU port (0) into the switch partition,
121 * where forwarding rules are applied.
123 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
126 * See field 'etclass'.
128 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
131 * RDQ for control packets sent to remote CPU.
132 * Must be set to 0x1F for EMADs, otherwise 0.
134 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
137 * Signature control for packets going to CPU. Must be set to 0.
139 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
142 * Stacking protocl signature. Must be set to 0xE0E0.
144 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
149 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
152 * EMAD bit. Must be set for EMADs.
154 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
158 * 6 - Control packets
160 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
162 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
163 const struct mlxsw_tx_info *tx_info)
165 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
166 bool is_emad = tx_info->is_emad;
168 memset(txhdr, 0, MLXSW_TXHDR_LEN);
170 /* We currently set default values for the egress tclass (QoS). */
171 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
172 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
173 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
174 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
175 MLXSW_TXHDR_ETCLASS_5);
176 mlxsw_tx_hdr_swid_set(txhdr, 0);
177 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
178 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
179 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
180 MLXSW_TXHDR_RDQ_OTHER);
181 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
182 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
183 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
184 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
185 MLXSW_TXHDR_NOT_EMAD);
186 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
189 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
192 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
193 char paos_pl[MLXSW_REG_PAOS_LEN];
195 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
196 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
197 MLXSW_PORT_ADMIN_STATUS_DOWN);
198 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
201 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
204 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
205 char paos_pl[MLXSW_REG_PAOS_LEN];
209 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
210 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
213 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
214 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
218 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
220 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
221 char pmtu_pl[MLXSW_REG_PMTU_LEN];
225 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
226 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
227 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
230 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
235 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
236 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
239 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
241 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
242 char pspa_pl[MLXSW_REG_PSPA_LEN];
244 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
245 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
249 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
251 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
252 char sspr_pl[MLXSW_REG_SSPR_LEN];
254 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
255 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
258 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
261 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
262 char pmlp_pl[MLXSW_REG_PMLP_LEN];
265 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
266 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
269 *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
273 static int mlxsw_sx_port_open(struct net_device *dev)
275 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
278 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
281 netif_start_queue(dev);
285 static int mlxsw_sx_port_stop(struct net_device *dev)
287 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
289 netif_stop_queue(dev);
290 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
293 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
294 struct net_device *dev)
296 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
297 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
298 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
299 const struct mlxsw_tx_info tx_info = {
300 .local_port = mlxsw_sx_port->local_port,
306 if (mlxsw_core_skb_transmit_busy(mlxsw_sx, &tx_info))
307 return NETDEV_TX_BUSY;
309 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
310 struct sk_buff *skb_orig = skb;
312 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
314 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
315 dev_kfree_skb_any(skb_orig);
319 mlxsw_sx_txhdr_construct(skb, &tx_info);
321 /* Due to a race we might fail here because of a full queue. In that
322 * unlikely case we simply drop the packet.
324 err = mlxsw_core_skb_transmit(mlxsw_sx, skb, &tx_info);
327 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
328 u64_stats_update_begin(&pcpu_stats->syncp);
329 pcpu_stats->tx_packets++;
330 pcpu_stats->tx_bytes += len;
331 u64_stats_update_end(&pcpu_stats->syncp);
333 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
334 dev_kfree_skb_any(skb);
339 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
341 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
344 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
351 static struct rtnl_link_stats64 *
352 mlxsw_sx_port_get_stats64(struct net_device *dev,
353 struct rtnl_link_stats64 *stats)
355 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
356 struct mlxsw_sx_port_pcpu_stats *p;
357 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
362 for_each_possible_cpu(i) {
363 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
365 start = u64_stats_fetch_begin_irq(&p->syncp);
366 rx_packets = p->rx_packets;
367 rx_bytes = p->rx_bytes;
368 tx_packets = p->tx_packets;
369 tx_bytes = p->tx_bytes;
370 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
372 stats->rx_packets += rx_packets;
373 stats->rx_bytes += rx_bytes;
374 stats->tx_packets += tx_packets;
375 stats->tx_bytes += tx_bytes;
376 /* tx_dropped is u32, updated without syncp protection. */
377 tx_dropped += p->tx_dropped;
379 stats->tx_dropped = tx_dropped;
383 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
384 .ndo_open = mlxsw_sx_port_open,
385 .ndo_stop = mlxsw_sx_port_stop,
386 .ndo_start_xmit = mlxsw_sx_port_xmit,
387 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
388 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
391 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
392 struct ethtool_drvinfo *drvinfo)
394 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
395 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
397 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
398 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
399 sizeof(drvinfo->version));
400 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
402 mlxsw_sx->bus_info->fw_rev.major,
403 mlxsw_sx->bus_info->fw_rev.minor,
404 mlxsw_sx->bus_info->fw_rev.subminor);
405 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
406 sizeof(drvinfo->bus_info));
409 struct mlxsw_sx_port_hw_stats {
410 char str[ETH_GSTRING_LEN];
411 u64 (*getter)(char *payload);
414 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
416 .str = "a_frames_transmitted_ok",
417 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
420 .str = "a_frames_received_ok",
421 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
424 .str = "a_frame_check_sequence_errors",
425 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
428 .str = "a_alignment_errors",
429 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
432 .str = "a_octets_transmitted_ok",
433 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
436 .str = "a_octets_received_ok",
437 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
440 .str = "a_multicast_frames_xmitted_ok",
441 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
444 .str = "a_broadcast_frames_xmitted_ok",
445 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
448 .str = "a_multicast_frames_received_ok",
449 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
452 .str = "a_broadcast_frames_received_ok",
453 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
456 .str = "a_in_range_length_errors",
457 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
460 .str = "a_out_of_range_length_field",
461 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
464 .str = "a_frame_too_long_errors",
465 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
468 .str = "a_symbol_error_during_carrier",
469 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
472 .str = "a_mac_control_frames_transmitted",
473 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
476 .str = "a_mac_control_frames_received",
477 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
480 .str = "a_unsupported_opcodes_received",
481 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
484 .str = "a_pause_mac_ctrl_frames_received",
485 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
488 .str = "a_pause_mac_ctrl_frames_xmitted",
489 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
493 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
495 static void mlxsw_sx_port_get_strings(struct net_device *dev,
496 u32 stringset, u8 *data)
503 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
504 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
506 p += ETH_GSTRING_LEN;
512 static void mlxsw_sx_port_get_stats(struct net_device *dev,
513 struct ethtool_stats *stats, u64 *data)
515 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
516 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
517 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
521 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port);
522 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
523 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
524 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
527 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
531 return MLXSW_SX_PORT_HW_STATS_LEN;
537 struct mlxsw_sx_port_link_mode {
544 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
546 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
547 .supported = SUPPORTED_100baseT_Full,
548 .advertised = ADVERTISED_100baseT_Full,
552 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
556 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
557 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
558 .supported = SUPPORTED_1000baseKX_Full,
559 .advertised = ADVERTISED_1000baseKX_Full,
563 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
564 .supported = SUPPORTED_10000baseT_Full,
565 .advertised = ADVERTISED_10000baseT_Full,
569 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
570 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
571 .supported = SUPPORTED_10000baseKX4_Full,
572 .advertised = ADVERTISED_10000baseKX4_Full,
576 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
577 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
578 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
579 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
580 .supported = SUPPORTED_10000baseKR_Full,
581 .advertised = ADVERTISED_10000baseKR_Full,
585 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
586 .supported = SUPPORTED_20000baseKR2_Full,
587 .advertised = ADVERTISED_20000baseKR2_Full,
591 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
592 .supported = SUPPORTED_40000baseCR4_Full,
593 .advertised = ADVERTISED_40000baseCR4_Full,
597 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
598 .supported = SUPPORTED_40000baseKR4_Full,
599 .advertised = ADVERTISED_40000baseKR4_Full,
603 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
604 .supported = SUPPORTED_40000baseSR4_Full,
605 .advertised = ADVERTISED_40000baseSR4_Full,
609 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
610 .supported = SUPPORTED_40000baseLR4_Full,
611 .advertised = ADVERTISED_40000baseLR4_Full,
615 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
616 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
617 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
621 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
622 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
623 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
627 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
628 .supported = SUPPORTED_56000baseKR4_Full,
629 .advertised = ADVERTISED_56000baseKR4_Full,
633 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
634 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
635 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
636 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
641 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
643 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
645 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
646 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
647 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
648 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
649 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
650 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
651 return SUPPORTED_FIBRE;
653 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
654 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
655 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
656 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
657 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
658 return SUPPORTED_Backplane;
662 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
667 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
668 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
669 modes |= mlxsw_sx_port_link_mode[i].supported;
674 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
679 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
680 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
681 modes |= mlxsw_sx_port_link_mode[i].advertised;
686 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
687 struct ethtool_cmd *cmd)
689 u32 speed = SPEED_UNKNOWN;
690 u8 duplex = DUPLEX_UNKNOWN;
696 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
697 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
698 speed = mlxsw_sx_port_link_mode[i].speed;
699 duplex = DUPLEX_FULL;
704 ethtool_cmd_speed_set(cmd, speed);
705 cmd->duplex = duplex;
708 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
710 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
711 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
712 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
713 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
716 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
717 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
718 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
721 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
722 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
723 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
724 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
730 static int mlxsw_sx_port_get_settings(struct net_device *dev,
731 struct ethtool_cmd *cmd)
733 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
734 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
735 char ptys_pl[MLXSW_REG_PTYS_LEN];
741 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
742 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
744 netdev_err(dev, "Failed to get proto");
747 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap,
748 ð_proto_admin, ð_proto_oper);
750 cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
751 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
752 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
753 cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
754 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
755 eth_proto_oper, cmd);
757 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
758 cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
759 cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
761 cmd->transceiver = XCVR_INTERNAL;
765 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
770 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
771 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
772 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
777 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
782 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
783 if (speed == mlxsw_sx_port_link_mode[i].speed)
784 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
789 static int mlxsw_sx_port_set_settings(struct net_device *dev,
790 struct ethtool_cmd *cmd)
792 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
793 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
794 char ptys_pl[MLXSW_REG_PTYS_LEN];
802 speed = ethtool_cmd_speed(cmd);
804 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
805 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
806 mlxsw_sx_to_ptys_speed(speed);
808 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
809 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
811 netdev_err(dev, "Failed to get proto");
814 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, NULL);
816 eth_proto_new = eth_proto_new & eth_proto_cap;
817 if (!eth_proto_new) {
818 netdev_err(dev, "Not supported proto admin requested");
821 if (eth_proto_new == eth_proto_admin)
824 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
825 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
827 netdev_err(dev, "Failed to set proto admin");
831 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
833 netdev_err(dev, "Failed to get oper status");
839 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
841 netdev_err(dev, "Failed to set admin status");
845 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
847 netdev_err(dev, "Failed to set admin status");
854 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
855 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
856 .get_link = ethtool_op_get_link,
857 .get_strings = mlxsw_sx_port_get_strings,
858 .get_ethtool_stats = mlxsw_sx_port_get_stats,
859 .get_sset_count = mlxsw_sx_port_get_sset_count,
860 .get_settings = mlxsw_sx_port_get_settings,
861 .set_settings = mlxsw_sx_port_set_settings,
864 static int mlxsw_sx_port_attr_get(struct net_device *dev,
865 struct switchdev_attr *attr)
867 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
868 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
871 case SWITCHDEV_ATTR_PORT_PARENT_ID:
872 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
873 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
882 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
883 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
886 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
888 char spad_pl[MLXSW_REG_SPAD_LEN];
891 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
894 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
898 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
900 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
901 struct net_device *dev = mlxsw_sx_port->dev;
902 char ppad_pl[MLXSW_REG_PPAD_LEN];
905 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
906 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
909 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
910 /* The last byte value in base mac address is guaranteed
911 * to be such it does not overflow when adding local_port
914 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
918 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
919 u16 vid, enum mlxsw_reg_spms_state state)
921 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
925 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
928 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port, vid, state);
929 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
934 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
937 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
938 char ptys_pl[MLXSW_REG_PTYS_LEN];
940 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
941 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
945 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
946 enum mlxsw_reg_spmlr_learn_mode mode)
948 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
949 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
951 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
952 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
955 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
957 struct mlxsw_sx_port *mlxsw_sx_port;
958 struct net_device *dev;
962 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
965 mlxsw_sx_port = netdev_priv(dev);
966 mlxsw_sx_port->dev = dev;
967 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
968 mlxsw_sx_port->local_port = local_port;
970 mlxsw_sx_port->pcpu_stats =
971 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
972 if (!mlxsw_sx_port->pcpu_stats) {
974 goto err_alloc_stats;
977 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
978 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
979 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
981 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
983 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
984 mlxsw_sx_port->local_port);
985 goto err_dev_addr_get;
988 netif_carrier_off(dev);
990 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
991 NETIF_F_VLAN_CHALLENGED;
993 /* Each packet needs to have a Tx header (metadata) on top all other
996 dev->hard_header_len += MLXSW_TXHDR_LEN;
998 err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
1000 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
1001 mlxsw_sx_port->local_port);
1002 goto err_port_module_check;
1006 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1007 mlxsw_sx_port->local_port);
1008 goto port_not_usable;
1011 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1013 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1014 mlxsw_sx_port->local_port);
1015 goto err_port_system_port_mapping_set;
1018 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1020 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1021 mlxsw_sx_port->local_port);
1022 goto err_port_swid_set;
1025 err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1026 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1028 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1029 mlxsw_sx_port->local_port);
1030 goto err_port_speed_set;
1033 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1035 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1036 mlxsw_sx_port->local_port);
1037 goto err_port_mtu_set;
1040 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1042 goto err_port_admin_status_set;
1044 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1045 MLXSW_PORT_DEFAULT_VID,
1046 MLXSW_REG_SPMS_STATE_FORWARDING);
1048 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1049 mlxsw_sx_port->local_port);
1050 goto err_port_stp_state_set;
1053 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1054 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1056 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1057 mlxsw_sx_port->local_port);
1058 goto err_port_mac_learning_mode_set;
1061 err = register_netdev(dev);
1063 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1064 mlxsw_sx_port->local_port);
1065 goto err_register_netdev;
1068 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1071 err_register_netdev:
1072 err_port_admin_status_set:
1073 err_port_mac_learning_mode_set:
1074 err_port_stp_state_set:
1078 err_port_system_port_mapping_set:
1080 err_port_module_check:
1082 free_percpu(mlxsw_sx_port->pcpu_stats);
1088 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1090 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1094 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1095 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1096 free_percpu(mlxsw_sx_port->pcpu_stats);
1097 free_netdev(mlxsw_sx_port->dev);
1100 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1104 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1105 mlxsw_sx_port_remove(mlxsw_sx, i);
1106 kfree(mlxsw_sx->ports);
1109 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1115 alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1116 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1117 if (!mlxsw_sx->ports)
1120 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1121 err = mlxsw_sx_port_create(mlxsw_sx, i);
1123 goto err_port_create;
1128 for (i--; i >= 1; i--)
1129 mlxsw_sx_port_remove(mlxsw_sx, i);
1130 kfree(mlxsw_sx->ports);
1134 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1135 char *pude_pl, void *priv)
1137 struct mlxsw_sx *mlxsw_sx = priv;
1138 struct mlxsw_sx_port *mlxsw_sx_port;
1139 enum mlxsw_reg_pude_oper_status status;
1142 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1143 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1144 if (!mlxsw_sx_port) {
1145 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1150 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1151 if (MLXSW_PORT_OPER_STATUS_UP == status) {
1152 netdev_info(mlxsw_sx_port->dev, "link up\n");
1153 netif_carrier_on(mlxsw_sx_port->dev);
1155 netdev_info(mlxsw_sx_port->dev, "link down\n");
1156 netif_carrier_off(mlxsw_sx_port->dev);
1160 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1161 .func = mlxsw_sx_pude_event_func,
1162 .trap_id = MLXSW_TRAP_ID_PUDE,
1165 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1166 enum mlxsw_event_trap_id trap_id)
1168 struct mlxsw_event_listener *el;
1169 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1173 case MLXSW_TRAP_ID_PUDE:
1174 el = &mlxsw_sx_pude_event;
1177 err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1181 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1182 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, trap_id);
1183 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1185 goto err_event_trap_set;
1190 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1194 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1195 enum mlxsw_event_trap_id trap_id)
1197 struct mlxsw_event_listener *el;
1200 case MLXSW_TRAP_ID_PUDE:
1201 el = &mlxsw_sx_pude_event;
1204 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1207 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1210 struct mlxsw_sx *mlxsw_sx = priv;
1211 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1212 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1214 if (unlikely(!mlxsw_sx_port)) {
1215 if (net_ratelimit())
1216 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1221 skb->dev = mlxsw_sx_port->dev;
1223 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1224 u64_stats_update_begin(&pcpu_stats->syncp);
1225 pcpu_stats->rx_packets++;
1226 pcpu_stats->rx_bytes += skb->len;
1227 u64_stats_update_end(&pcpu_stats->syncp);
1229 skb->protocol = eth_type_trans(skb, skb->dev);
1230 netif_receive_skb(skb);
1233 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1235 .func = mlxsw_sx_rx_listener_func,
1236 .local_port = MLXSW_PORT_DONT_CARE,
1237 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1239 /* Traps for specific L2 packet types, not trapped as FDB MC */
1241 .func = mlxsw_sx_rx_listener_func,
1242 .local_port = MLXSW_PORT_DONT_CARE,
1243 .trap_id = MLXSW_TRAP_ID_STP,
1246 .func = mlxsw_sx_rx_listener_func,
1247 .local_port = MLXSW_PORT_DONT_CARE,
1248 .trap_id = MLXSW_TRAP_ID_LACP,
1251 .func = mlxsw_sx_rx_listener_func,
1252 .local_port = MLXSW_PORT_DONT_CARE,
1253 .trap_id = MLXSW_TRAP_ID_EAPOL,
1256 .func = mlxsw_sx_rx_listener_func,
1257 .local_port = MLXSW_PORT_DONT_CARE,
1258 .trap_id = MLXSW_TRAP_ID_LLDP,
1261 .func = mlxsw_sx_rx_listener_func,
1262 .local_port = MLXSW_PORT_DONT_CARE,
1263 .trap_id = MLXSW_TRAP_ID_MMRP,
1266 .func = mlxsw_sx_rx_listener_func,
1267 .local_port = MLXSW_PORT_DONT_CARE,
1268 .trap_id = MLXSW_TRAP_ID_MVRP,
1271 .func = mlxsw_sx_rx_listener_func,
1272 .local_port = MLXSW_PORT_DONT_CARE,
1273 .trap_id = MLXSW_TRAP_ID_RPVST,
1276 .func = mlxsw_sx_rx_listener_func,
1277 .local_port = MLXSW_PORT_DONT_CARE,
1278 .trap_id = MLXSW_TRAP_ID_DHCP,
1281 .func = mlxsw_sx_rx_listener_func,
1282 .local_port = MLXSW_PORT_DONT_CARE,
1283 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1286 .func = mlxsw_sx_rx_listener_func,
1287 .local_port = MLXSW_PORT_DONT_CARE,
1288 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1291 .func = mlxsw_sx_rx_listener_func,
1292 .local_port = MLXSW_PORT_DONT_CARE,
1293 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1296 .func = mlxsw_sx_rx_listener_func,
1297 .local_port = MLXSW_PORT_DONT_CARE,
1298 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1301 .func = mlxsw_sx_rx_listener_func,
1302 .local_port = MLXSW_PORT_DONT_CARE,
1303 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1307 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1309 char htgt_pl[MLXSW_REG_HTGT_LEN];
1310 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1314 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1315 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1319 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1320 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1321 &mlxsw_sx_rx_listener[i],
1324 goto err_rx_listener_register;
1326 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1327 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1328 mlxsw_sx_rx_listener[i].trap_id);
1329 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1331 goto err_rx_trap_set;
1336 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1337 &mlxsw_sx_rx_listener[i],
1339 err_rx_listener_register:
1340 for (i--; i >= 0; i--) {
1341 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1342 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1343 mlxsw_sx_rx_listener[i].trap_id);
1344 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1346 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1347 &mlxsw_sx_rx_listener[i],
1353 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1355 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1358 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1359 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1360 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1361 mlxsw_sx_rx_listener[i].trap_id);
1362 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1364 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1365 &mlxsw_sx_rx_listener[i],
1370 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1372 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1373 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1378 /* Due to FW bug, we must configure SMID. */
1379 smid_pl = kmalloc(MLXSW_REG_SMID_LEN, GFP_KERNEL);
1382 mlxsw_reg_smid_pack(smid_pl, MLXSW_PORT_MID);
1383 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(smid), smid_pl);
1388 /* Configure a flooding table, which includes only CPU port. */
1389 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1392 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0);
1393 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1398 /* Flood different packet types using the flooding table. */
1399 mlxsw_reg_sfgc_pack(sfgc_pl,
1400 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1401 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1402 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1404 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1408 mlxsw_reg_sfgc_pack(sfgc_pl,
1409 MLXSW_REG_SFGC_TYPE_BROADCAST,
1410 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1411 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1413 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1417 mlxsw_reg_sfgc_pack(sfgc_pl,
1418 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1419 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1420 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1422 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1426 mlxsw_reg_sfgc_pack(sfgc_pl,
1427 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1428 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1429 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1431 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1435 mlxsw_reg_sfgc_pack(sfgc_pl,
1436 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1437 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1438 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1440 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1444 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1445 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1448 static int mlxsw_sx_init(void *priv, struct mlxsw_core *mlxsw_core,
1449 const struct mlxsw_bus_info *mlxsw_bus_info)
1451 struct mlxsw_sx *mlxsw_sx = priv;
1454 mlxsw_sx->core = mlxsw_core;
1455 mlxsw_sx->bus_info = mlxsw_bus_info;
1457 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1459 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1463 err = mlxsw_sx_ports_create(mlxsw_sx);
1465 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1469 err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1471 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1472 goto err_event_register;
1475 err = mlxsw_sx_traps_init(mlxsw_sx);
1477 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1478 goto err_rx_listener_register;
1481 err = mlxsw_sx_flood_init(mlxsw_sx);
1483 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1484 goto err_flood_init;
1490 mlxsw_sx_traps_fini(mlxsw_sx);
1491 err_rx_listener_register:
1492 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1494 mlxsw_sx_ports_remove(mlxsw_sx);
1498 static void mlxsw_sx_fini(void *priv)
1500 struct mlxsw_sx *mlxsw_sx = priv;
1502 mlxsw_sx_traps_fini(mlxsw_sx);
1503 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1504 mlxsw_sx_ports_remove(mlxsw_sx);
1507 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1508 .used_max_vepa_channels = 1,
1509 .max_vepa_channels = 0,
1512 .used_max_port_per_lag = 1,
1513 .max_port_per_lag = 16,
1518 .used_max_system_port = 1,
1519 .max_system_port = 48000,
1520 .used_max_vlan_groups = 1,
1521 .max_vlan_groups = 127,
1522 .used_max_regions = 1,
1524 .used_flood_tables = 1,
1525 .max_flood_tables = 2,
1526 .max_vid_flood_tables = 1,
1527 .used_flood_mode = 1,
1529 .used_max_ib_mc = 1,
1536 .type = MLXSW_PORT_SWID_TYPE_ETH,
1541 static struct mlxsw_driver mlxsw_sx_driver = {
1542 .kind = MLXSW_DEVICE_KIND_SWITCHX2,
1543 .owner = THIS_MODULE,
1544 .priv_size = sizeof(struct mlxsw_sx),
1545 .init = mlxsw_sx_init,
1546 .fini = mlxsw_sx_fini,
1547 .txhdr_construct = mlxsw_sx_txhdr_construct,
1548 .txhdr_len = MLXSW_TXHDR_LEN,
1549 .profile = &mlxsw_sx_config_profile,
1552 static int __init mlxsw_sx_module_init(void)
1554 return mlxsw_core_driver_register(&mlxsw_sx_driver);
1557 static void __exit mlxsw_sx_module_exit(void)
1559 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1562 module_init(mlxsw_sx_module_init);
1563 module_exit(mlxsw_sx_module_exit);
1565 MODULE_LICENSE("Dual BSD/GPL");
1566 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1567 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1568 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);