1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
27 * big endian support with CFG:BEM instead of cpu_to_le32
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/rtnetlink.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/bitops.h>
50 #include <linux/prefetch.h>
51 #include <asm/processor.h> /* Processor type for cache alignment. */
54 #include <linux/uaccess.h>
56 #define DRV_NAME "natsemi"
57 #define DRV_VERSION "2.1"
58 #define DRV_RELDATE "Sept 11, 2006"
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78 static const int multicast_filter_limit = 100;
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82 static int rx_copybreak;
84 static int dspcfg_workaround = 1;
86 /* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
89 The media type is usually passed in 'options[]'.
91 #define MAX_UNITS 8 /* More are supported, limit only on options */
92 static int options[MAX_UNITS];
93 static int full_duplex[MAX_UNITS];
95 /* Operational parameters that are set at compile time. */
97 /* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102 #define TX_RING_SIZE 16
103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104 #define RX_RING_SIZE 32
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
110 #define NATSEMI_HW_TIMEOUT 400
111 #define NATSEMI_TIMER_FREQ 5*HZ
112 #define NATSEMI_PG0_NREGS 64
113 #define NATSEMI_RFDR_NREGS 8
114 #define NATSEMI_PG1_NREGS 4
115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
129 /* These identify the driver base version and may not be removed. */
130 static const char version[] =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138 MODULE_LICENSE("GPL");
140 module_param(mtu, int, 0);
141 module_param(debug, int, 0);
142 module_param(rx_copybreak, int, 0);
143 module_param(dspcfg_workaround, int, 0);
144 module_param_array(options, int, NULL, 0);
145 module_param_array(full_duplex, int, NULL, 0);
146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147 MODULE_PARM_DESC(debug, "DP8381x default debug level");
148 MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151 MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
158 I. Board Compatibility
160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161 It also works with other chips in in the DP83810 series.
163 II. Board-specific settings
165 This driver requires the PCI interrupt line to be valid.
166 It honors the EEPROM-set values.
168 III. Driver operation
172 This driver uses two statically allocated fixed-size descriptor lists
173 formed into rings by a branch from the final descriptor to the beginning of
174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175 The NatSemi design uses a 'next descriptor' pointer that the driver forms
178 IIIb/c. Transmit/Receive Structure
180 This driver uses a zero-copy receive and transmit scheme.
181 The driver allocates full frame size skbuffs for the Rx ring buffers at
182 open() time and passes the skb->data field to the chip as receive data
183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184 a fresh skbuff is allocated and the frame is copied to the new skbuff.
185 When the incoming frame is larger, the skbuff is passed directly up the
186 protocol stack. Buffers consumed this way are replaced by newly allocated
187 skbuffs in a later phase of receives.
189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190 using a full-sized skbuff for small frames vs. the copying costs of larger
191 frames. New boards are typically used in generously configured machines
192 and the underfilled buffers have negligible impact compared to the benefit of
193 a single allocation size, so the default value of zero results in never
194 copying packets. When copying is done, the cost is usually mitigated by using
195 a combined copy/checksum routine. Copying also preloads the cache, which is
196 most useful with small frames.
198 A subtle aspect of the operation is that unaligned buffers are not permitted
199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200 longword aligned for further processing. On copies frames are put into the
201 skbuff at an offset of "+2", 16-byte aligning the IP header.
203 IIId. Synchronization
205 Most operations are synchronized on the np->lock irq spinlock, except the
206 receive and transmit paths which are synchronised using a combination of
207 hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
211 http://www.scyld.com/expert/100mbps.html
212 http://www.scyld.com/expert/NWay.html
213 Datasheet is available from:
214 http://www.national.com/pf/DP/DP83815.html
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
228 #define PHYID_AM79C874 0x0022561b
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
240 /* array of board data directly indexed by pci_tbl[x].driver_data */
244 unsigned int eeprom_size;
245 } natsemi_pci_info[] = {
246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
247 { "NatSemi DP8381[56]", 0, 24 },
250 static const struct pci_device_id natsemi_pci_tbl[] = {
251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
253 { } /* terminate list */
255 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
257 /* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
262 enum register_offsets {
270 IntrHoldoff = 0x1C, /* DP83816 only */
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
305 /* the values for the 'magic' registers above (PGSEL=1) */
306 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307 #define TSTDAT_VAL 0x0
308 #define DSPCFG_VAL 0x5040
309 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
314 /* misc PCI space registers */
315 enum pci_register_offsets {
329 enum ChipConfig_bits {
333 CfgAnegEnable = 0x2000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
345 EE_ChipSelect = 0x08,
352 enum PCIBusCfg_bits {
356 /* Bits in the interrupt status/mask registers. */
357 enum IntrStatus_bits {
361 IntrRxEarly = 0x0008,
363 IntrRxOverrun = 0x0020,
368 IntrTxUnderrun = 0x0400,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
390 #define DEFAULT_INTR 0x00f1cd65
395 TxMxdmaMask = 0x700000,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
422 #define TX_FLTH_VAL ((512/32) << 8)
423 #define TX_DRTH_VAL_START (64/32)
424 #define TX_DRTH_VAL_INC 2
425 #define TX_DRTH_VAL_LIMIT (1472/32)
429 RxMxdmaMask = 0x700000,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
443 #define RX_DRTH_VAL (128/8)
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
476 enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
486 enum StatsCtrl_bits {
493 enum MIntrCtrl_bits {
501 #define PHY_ADDR_NONE 32
502 #define PHY_ADDR_INTERNAL 1
504 /* values we might find in the silicon revision register */
505 #define SRR_DP83815_C 0x0302
506 #define SRR_DP83815_D 0x0403
507 #define SRR_DP83816_A4 0x0504
508 #define SRR_DP83816_A5 0x0505
510 /* The Rx and Tx buffer descriptors. */
511 /* Note that using only 32 bit fields simplifies conversion to big-endian
520 /* Bits in network_desc.status */
521 enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
538 struct netdev_private {
539 /* Descriptor rings first for alignment */
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
549 struct net_device *dev;
550 void __iomem *ioaddr;
551 struct napi_struct napi;
552 /* Media monitoring timer */
553 struct timer_list timer;
554 /* Frequently used values: keep some adjacent for cache effect */
555 struct pci_dev *pci_dev;
556 struct netdev_desc *rx_head_desc;
557 /* Producer/consumer ring indices */
558 unsigned int cur_rx, dirty_rx;
559 unsigned int cur_tx, dirty_tx;
560 /* Based on MTU+slack. */
561 unsigned int rx_buf_sz;
563 /* Interrupt status */
565 /* Do not touch the nic registers */
567 /* Don't pay attention to the reported link state. */
569 /* external phy that is used: only valid if dev->if_port != PORT_TP */
571 int phy_addr_external;
572 unsigned int full_duplex;
576 /* FIFO and PCI burst thresholds */
577 u32 tx_config, rx_config;
578 /* original contents of ClkRun register */
580 /* silicon revision */
582 /* expected DSPCFG value */
584 int dspcfg_workaround;
585 /* parms saved in ethtool format */
586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
587 u8 duplex; /* Duplex, half or full */
588 u8 autoneg; /* Autonegotiation enabled */
589 /* MII transceiver section */
598 static void move_int_phy(struct net_device *dev, int addr);
599 static int eeprom_read(void __iomem *ioaddr, int location);
600 static int mdio_read(struct net_device *dev, int reg);
601 static void mdio_write(struct net_device *dev, int reg, u16 data);
602 static void init_phy_fixup(struct net_device *dev);
603 static int miiport_read(struct net_device *dev, int phy_id, int reg);
604 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
605 static int find_mii(struct net_device *dev);
606 static void natsemi_reset(struct net_device *dev);
607 static void natsemi_reload_eeprom(struct net_device *dev);
608 static void natsemi_stop_rxtx(struct net_device *dev);
609 static int netdev_open(struct net_device *dev);
610 static void do_cable_magic(struct net_device *dev);
611 static void undo_cable_magic(struct net_device *dev);
612 static void check_link(struct net_device *dev);
613 static void netdev_timer(unsigned long data);
614 static void dump_ring(struct net_device *dev);
615 static void ns_tx_timeout(struct net_device *dev);
616 static int alloc_ring(struct net_device *dev);
617 static void refill_rx(struct net_device *dev);
618 static void init_ring(struct net_device *dev);
619 static void drain_tx(struct net_device *dev);
620 static void drain_ring(struct net_device *dev);
621 static void free_ring(struct net_device *dev);
622 static void reinit_ring(struct net_device *dev);
623 static void init_registers(struct net_device *dev);
624 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
625 static irqreturn_t intr_handler(int irq, void *dev_instance);
626 static void netdev_error(struct net_device *dev, int intr_status);
627 static int natsemi_poll(struct napi_struct *napi, int budget);
628 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
629 static void netdev_tx_done(struct net_device *dev);
630 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
631 #ifdef CONFIG_NET_POLL_CONTROLLER
632 static void natsemi_poll_controller(struct net_device *dev);
634 static void __set_rx_mode(struct net_device *dev);
635 static void set_rx_mode(struct net_device *dev);
636 static void __get_stats(struct net_device *dev);
637 static struct net_device_stats *get_stats(struct net_device *dev);
638 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
639 static int netdev_set_wol(struct net_device *dev, u32 newval);
640 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
641 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
642 static int netdev_get_sopass(struct net_device *dev, u8 *data);
643 static int netdev_get_ecmd(struct net_device *dev,
644 struct ethtool_link_ksettings *ecmd);
645 static int netdev_set_ecmd(struct net_device *dev,
646 const struct ethtool_link_ksettings *ecmd);
647 static void enable_wol_mode(struct net_device *dev, int enable_intr);
648 static int netdev_close(struct net_device *dev);
649 static int netdev_get_regs(struct net_device *dev, u8 *buf);
650 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
651 static const struct ethtool_ops ethtool_ops;
653 #define NATSEMI_ATTR(_name) \
654 static ssize_t natsemi_show_##_name(struct device *dev, \
655 struct device_attribute *attr, char *buf); \
656 static ssize_t natsemi_set_##_name(struct device *dev, \
657 struct device_attribute *attr, \
658 const char *buf, size_t count); \
659 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
661 #define NATSEMI_CREATE_FILE(_dev, _name) \
662 device_create_file(&_dev->dev, &dev_attr_##_name)
663 #define NATSEMI_REMOVE_FILE(_dev, _name) \
664 device_remove_file(&_dev->dev, &dev_attr_##_name)
666 NATSEMI_ATTR(dspcfg_workaround);
668 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
669 struct device_attribute *attr,
672 struct netdev_private *np = netdev_priv(to_net_dev(dev));
674 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
677 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
678 struct device_attribute *attr,
679 const char *buf, size_t count)
681 struct netdev_private *np = netdev_priv(to_net_dev(dev));
685 /* Find out the new setting */
686 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
688 else if (!strncmp("off", buf, count - 1) ||
689 !strncmp("0", buf, count - 1))
694 spin_lock_irqsave(&np->lock, flags);
696 np->dspcfg_workaround = new_setting;
698 spin_unlock_irqrestore(&np->lock, flags);
703 static inline void __iomem *ns_ioaddr(struct net_device *dev)
705 struct netdev_private *np = netdev_priv(dev);
710 static inline void natsemi_irq_enable(struct net_device *dev)
712 writel(1, ns_ioaddr(dev) + IntrEnable);
713 readl(ns_ioaddr(dev) + IntrEnable);
716 static inline void natsemi_irq_disable(struct net_device *dev)
718 writel(0, ns_ioaddr(dev) + IntrEnable);
719 readl(ns_ioaddr(dev) + IntrEnable);
722 static void move_int_phy(struct net_device *dev, int addr)
724 struct netdev_private *np = netdev_priv(dev);
725 void __iomem *ioaddr = ns_ioaddr(dev);
729 * The internal phy is visible on the external mii bus. Therefore we must
730 * move it away before we can send commands to an external phy.
731 * There are two addresses we must avoid:
732 * - the address on the external phy that is used for transmission.
733 * - the address that we want to access. User space can access phys
734 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the
735 * phy that is used for transmission.
740 if (target == np->phy_addr_external)
742 writew(target, ioaddr + PhyCtrl);
743 readw(ioaddr + PhyCtrl);
747 static void natsemi_init_media(struct net_device *dev)
749 struct netdev_private *np = netdev_priv(dev);
753 netif_carrier_on(dev);
755 netif_carrier_off(dev);
757 /* get the initial settings from hardware */
758 tmp = mdio_read(dev, MII_BMCR);
759 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
760 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
761 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
762 np->advertising= mdio_read(dev, MII_ADVERTISE);
764 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
765 netif_msg_probe(np)) {
766 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
768 pci_name(np->pci_dev),
769 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
770 "enabled, advertise" : "disabled, force",
772 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
775 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
778 if (netif_msg_probe(np))
780 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
781 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
786 static const struct net_device_ops natsemi_netdev_ops = {
787 .ndo_open = netdev_open,
788 .ndo_stop = netdev_close,
789 .ndo_start_xmit = start_tx,
790 .ndo_get_stats = get_stats,
791 .ndo_set_rx_mode = set_rx_mode,
792 .ndo_change_mtu = natsemi_change_mtu,
793 .ndo_do_ioctl = netdev_ioctl,
794 .ndo_tx_timeout = ns_tx_timeout,
795 .ndo_set_mac_address = eth_mac_addr,
796 .ndo_validate_addr = eth_validate_addr,
797 #ifdef CONFIG_NET_POLL_CONTROLLER
798 .ndo_poll_controller = natsemi_poll_controller,
802 static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
804 struct net_device *dev;
805 struct netdev_private *np;
806 int i, option, irq, chip_idx = ent->driver_data;
807 static int find_cnt = -1;
808 resource_size_t iostart;
809 unsigned long iosize;
810 void __iomem *ioaddr;
811 const int pcibar = 1; /* PCI base address register */
815 /* when built into the kernel, we only print version if device is found */
817 static int printed_version;
818 if (!printed_version++)
822 i = pci_enable_device(pdev);
825 /* natsemi has a non-standard PM control register
826 * in PCI config space. Some boards apparently need
827 * to be brought to D0 in this manner.
829 pci_read_config_dword(pdev, PCIPM, &tmp);
830 if (tmp & PCI_PM_CTRL_STATE_MASK) {
831 /* D0 state, disable PME assertion */
832 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
833 pci_write_config_dword(pdev, PCIPM, newtmp);
837 iostart = pci_resource_start(pdev, pcibar);
838 iosize = pci_resource_len(pdev, pcibar);
841 pci_set_master(pdev);
843 dev = alloc_etherdev(sizeof (struct netdev_private));
846 SET_NETDEV_DEV(dev, &pdev->dev);
848 i = pci_request_regions(pdev, DRV_NAME);
850 goto err_pci_request_regions;
852 ioaddr = ioremap(iostart, iosize);
858 /* Work around the dropped serial bit. */
859 prev_eedata = eeprom_read(ioaddr, 6);
860 for (i = 0; i < 3; i++) {
861 int eedata = eeprom_read(ioaddr, i + 7);
862 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
863 dev->dev_addr[i*2+1] = eedata >> 7;
864 prev_eedata = eedata;
867 np = netdev_priv(dev);
870 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
874 pci_set_drvdata(pdev, dev);
876 spin_lock_init(&np->lock);
877 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
880 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
881 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
885 np->dspcfg_workaround = dspcfg_workaround;
888 * - If configured to ignore the PHY set up for external.
889 * - If the nic was configured to use an external phy and if find_mii
890 * finds a phy: use external port, first phy that replies.
891 * - Otherwise: internal port.
892 * Note that the phy address for the internal phy doesn't matter:
893 * The address would be used to access a phy over the mii bus, but
894 * the internal phy is accessed through mapped registers.
896 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
897 dev->if_port = PORT_MII;
899 dev->if_port = PORT_TP;
900 /* Reset the chip to erase previous misconfiguration. */
901 natsemi_reload_eeprom(dev);
904 if (dev->if_port != PORT_TP) {
905 np->phy_addr_external = find_mii(dev);
906 /* If we're ignoring the PHY it doesn't matter if we can't
908 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
909 dev->if_port = PORT_TP;
910 np->phy_addr_external = PHY_ADDR_INTERNAL;
913 np->phy_addr_external = PHY_ADDR_INTERNAL;
916 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
917 /* The lower four bits are the media type. */
923 "natsemi %s: ignoring user supplied media type %d",
924 pci_name(np->pci_dev), option & 15);
926 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
929 dev->netdev_ops = &natsemi_netdev_ops;
930 dev->watchdog_timeo = TX_TIMEOUT;
932 dev->ethtool_ops = ðtool_ops;
934 /* MTU range: 64 - 2024 */
935 dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
936 dev->max_mtu = NATSEMI_RX_LIMIT - NATSEMI_HEADERS;
941 natsemi_init_media(dev);
943 /* save the silicon revision for later querying */
944 np->srr = readl(ioaddr + SiliconRev);
945 if (netif_msg_hw(np))
946 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
947 pci_name(np->pci_dev), np->srr);
949 i = register_netdev(dev);
951 goto err_register_netdev;
952 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround);
954 goto err_create_file;
956 if (netif_msg_drv(np)) {
957 printk(KERN_INFO "natsemi %s: %s at %#08llx "
959 dev->name, natsemi_pci_info[chip_idx].name,
960 (unsigned long long)iostart, pci_name(np->pci_dev),
962 if (dev->if_port == PORT_TP)
963 printk(", port TP.\n");
964 else if (np->ignore_phy)
965 printk(", port MII, ignoring PHY\n");
967 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
972 unregister_netdev(dev);
978 pci_release_regions(pdev);
980 err_pci_request_regions:
986 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
987 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
989 /* Delay between EEPROM clock transitions.
990 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
991 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
992 made udelay() unreliable.
993 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
996 #define eeprom_delay(ee_addr) readl(ee_addr)
998 #define EE_Write0 (EE_ChipSelect)
999 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
1001 /* The EEPROM commands include the alway-set leading bit. */
1003 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1006 static int eeprom_read(void __iomem *addr, int location)
1010 void __iomem *ee_addr = addr + EECtrl;
1011 int read_cmd = location | EE_ReadCmd;
1013 writel(EE_Write0, ee_addr);
1015 /* Shift the read command bits out. */
1016 for (i = 10; i >= 0; i--) {
1017 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1018 writel(dataval, ee_addr);
1019 eeprom_delay(ee_addr);
1020 writel(dataval | EE_ShiftClk, ee_addr);
1021 eeprom_delay(ee_addr);
1023 writel(EE_ChipSelect, ee_addr);
1024 eeprom_delay(ee_addr);
1026 for (i = 0; i < 16; i++) {
1027 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1028 eeprom_delay(ee_addr);
1029 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1030 writel(EE_ChipSelect, ee_addr);
1031 eeprom_delay(ee_addr);
1034 /* Terminate the EEPROM access. */
1035 writel(EE_Write0, ee_addr);
1040 /* MII transceiver control section.
1041 * The 83815 series has an internal transceiver, and we present the
1042 * internal management registers as if they were MII connected.
1043 * External Phy registers are referenced through the MII interface.
1046 /* clock transitions >= 20ns (25MHz)
1047 * One readl should be good to PCI @ 100MHz
1049 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1051 static int mii_getbit (struct net_device *dev)
1054 void __iomem *ioaddr = ns_ioaddr(dev);
1056 writel(MII_ShiftClk, ioaddr + EECtrl);
1057 data = readl(ioaddr + EECtrl);
1058 writel(0, ioaddr + EECtrl);
1060 return (data & MII_Data)? 1 : 0;
1063 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1066 void __iomem *ioaddr = ns_ioaddr(dev);
1068 for (i = (1 << (len-1)); i; i >>= 1)
1070 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1071 writel(mdio_val, ioaddr + EECtrl);
1073 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1076 writel(0, ioaddr + EECtrl);
1080 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1087 mii_send_bits (dev, 0xffffffff, 32);
1088 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1089 /* ST,OP = 0110'b for read operation */
1090 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1091 mii_send_bits (dev, cmd, 14);
1093 if (mii_getbit (dev))
1096 for (i = 0; i < 16; i++) {
1098 retval |= mii_getbit (dev);
1105 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1110 mii_send_bits (dev, 0xffffffff, 32);
1111 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1112 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1113 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1114 mii_send_bits (dev, cmd, 32);
1119 static int mdio_read(struct net_device *dev, int reg)
1121 struct netdev_private *np = netdev_priv(dev);
1122 void __iomem *ioaddr = ns_ioaddr(dev);
1124 /* The 83815 series has two ports:
1125 * - an internal transceiver
1126 * - an external mii bus
1128 if (dev->if_port == PORT_TP)
1129 return readw(ioaddr+BasicControl+(reg<<2));
1131 return miiport_read(dev, np->phy_addr_external, reg);
1134 static void mdio_write(struct net_device *dev, int reg, u16 data)
1136 struct netdev_private *np = netdev_priv(dev);
1137 void __iomem *ioaddr = ns_ioaddr(dev);
1139 /* The 83815 series has an internal transceiver; handle separately */
1140 if (dev->if_port == PORT_TP)
1141 writew(data, ioaddr+BasicControl+(reg<<2));
1143 miiport_write(dev, np->phy_addr_external, reg, data);
1146 static void init_phy_fixup(struct net_device *dev)
1148 struct netdev_private *np = netdev_priv(dev);
1149 void __iomem *ioaddr = ns_ioaddr(dev);
1154 /* restore stuff lost when power was out */
1155 tmp = mdio_read(dev, MII_BMCR);
1156 if (np->autoneg == AUTONEG_ENABLE) {
1157 /* renegotiate if something changed */
1158 if ((tmp & BMCR_ANENABLE) == 0 ||
1159 np->advertising != mdio_read(dev, MII_ADVERTISE))
1161 /* turn on autonegotiation and force negotiation */
1162 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1163 mdio_write(dev, MII_ADVERTISE, np->advertising);
1166 /* turn off auto negotiation, set speed and duplexity */
1167 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1168 if (np->speed == SPEED_100)
1169 tmp |= BMCR_SPEED100;
1170 if (np->duplex == DUPLEX_FULL)
1171 tmp |= BMCR_FULLDPLX;
1173 * Note: there is no good way to inform the link partner
1174 * that our capabilities changed. The user has to unplug
1175 * and replug the network cable after some changes, e.g.
1176 * after switching from 10HD, autoneg off to 100 HD,
1180 mdio_write(dev, MII_BMCR, tmp);
1181 readl(ioaddr + ChipConfig);
1184 /* find out what phy this is */
1185 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1186 + mdio_read(dev, MII_PHYSID2);
1188 /* handle external phys here */
1190 case PHYID_AM79C874:
1191 /* phy specific configuration for fibre/tp operation */
1192 tmp = mdio_read(dev, MII_MCTRL);
1193 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1194 if (dev->if_port == PORT_FIBRE)
1198 mdio_write(dev, MII_MCTRL, tmp);
1203 cfg = readl(ioaddr + ChipConfig);
1204 if (cfg & CfgExtPhy)
1207 /* On page 78 of the spec, they recommend some settings for "optimum
1208 performance" to be done in sequence. These settings optimize some
1209 of the 100Mbit autodetection circuitry. They say we only want to
1210 do this for rev C of the chip, but engineers at NSC (Bradley
1211 Kennedy) recommends always setting them. If you don't, you get
1212 errors on some autonegotiations that make the device unusable.
1214 It seems that the DSP needs a few usec to reinitialize after
1215 the start of the phy. Just retry writing these values until they
1218 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1221 writew(1, ioaddr + PGSEL);
1222 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1223 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1224 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1225 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1226 writew(np->dspcfg, ioaddr + DSPCFG);
1227 writew(SDCFG_VAL, ioaddr + SDCFG);
1228 writew(0, ioaddr + PGSEL);
1229 readl(ioaddr + ChipConfig);
1232 writew(1, ioaddr + PGSEL);
1233 dspcfg = readw(ioaddr + DSPCFG);
1234 writew(0, ioaddr + PGSEL);
1235 if (np->dspcfg == dspcfg)
1239 if (netif_msg_link(np)) {
1240 if (i==NATSEMI_HW_TIMEOUT) {
1242 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1246 "%s: DSPCFG accepted after %d usec.\n",
1251 * Enable PHY Specific event based interrupts. Link state change
1252 * and Auto-Negotiation Completion are among the affected.
1253 * Read the intr status to clear it (needed for wake events).
1255 readw(ioaddr + MIntrStatus);
1256 writew(MICRIntEn, ioaddr + MIntrCtrl);
1259 static int switch_port_external(struct net_device *dev)
1261 struct netdev_private *np = netdev_priv(dev);
1262 void __iomem *ioaddr = ns_ioaddr(dev);
1265 cfg = readl(ioaddr + ChipConfig);
1266 if (cfg & CfgExtPhy)
1269 if (netif_msg_link(np)) {
1270 printk(KERN_INFO "%s: switching to external transceiver.\n",
1274 /* 1) switch back to external phy */
1275 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1276 readl(ioaddr + ChipConfig);
1279 /* 2) reset the external phy: */
1280 /* resetting the external PHY has been known to cause a hub supplying
1281 * power over Ethernet to kill the power. We don't want to kill
1282 * power to this computer, so we avoid resetting the phy.
1285 /* 3) reinit the phy fixup, it got lost during power down. */
1286 move_int_phy(dev, np->phy_addr_external);
1287 init_phy_fixup(dev);
1292 static int switch_port_internal(struct net_device *dev)
1294 struct netdev_private *np = netdev_priv(dev);
1295 void __iomem *ioaddr = ns_ioaddr(dev);
1300 cfg = readl(ioaddr + ChipConfig);
1301 if (!(cfg &CfgExtPhy))
1304 if (netif_msg_link(np)) {
1305 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1308 /* 1) switch back to internal phy: */
1309 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1310 writel(cfg, ioaddr + ChipConfig);
1311 readl(ioaddr + ChipConfig);
1314 /* 2) reset the internal phy: */
1315 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1316 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1317 readl(ioaddr + ChipConfig);
1319 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1320 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1321 if (!(bmcr & BMCR_RESET))
1325 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1327 "%s: phy reset did not complete in %d usec.\n",
1330 /* 3) reinit the phy fixup, it got lost during power down. */
1331 init_phy_fixup(dev);
1336 /* Scan for a PHY on the external mii bus.
1337 * There are two tricky points:
1338 * - Do not scan while the internal phy is enabled. The internal phy will
1339 * crash: e.g. reads from the DSPCFG register will return odd values and
1340 * the nasty random phy reset code will reset the nic every few seconds.
1341 * - The internal phy must be moved around, an external phy could
1342 * have the same address as the internal phy.
1344 static int find_mii(struct net_device *dev)
1346 struct netdev_private *np = netdev_priv(dev);
1351 /* Switch to external phy */
1352 did_switch = switch_port_external(dev);
1354 /* Scan the possible phy addresses:
1356 * PHY address 0 means that the phy is in isolate mode. Not yet
1357 * supported due to lack of test hardware. User space should
1358 * handle it through ethtool.
1360 for (i = 1; i <= 31; i++) {
1361 move_int_phy(dev, i);
1362 tmp = miiport_read(dev, i, MII_BMSR);
1363 if (tmp != 0xffff && tmp != 0x0000) {
1364 /* found something! */
1365 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1366 + mdio_read(dev, MII_PHYSID2);
1367 if (netif_msg_probe(np)) {
1368 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1369 pci_name(np->pci_dev), np->mii, i);
1374 /* And switch back to internal phy: */
1376 switch_port_internal(dev);
1380 /* CFG bits [13:16] [18:23] */
1381 #define CFG_RESET_SAVE 0xfde000
1382 /* WCSR bits [0:4] [9:10] */
1383 #define WCSR_RESET_SAVE 0x61f
1384 /* RFCR bits [20] [22] [27:31] */
1385 #define RFCR_RESET_SAVE 0xf8500000
1387 static void natsemi_reset(struct net_device *dev)
1395 struct netdev_private *np = netdev_priv(dev);
1396 void __iomem *ioaddr = ns_ioaddr(dev);
1399 * Resetting the chip causes some registers to be lost.
1400 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1401 * we save the state that would have been loaded from EEPROM
1402 * on a normal power-up (see the spec EEPROM map). This assumes
1403 * whoever calls this will follow up with init_registers() eventually.
1407 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1409 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1411 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1413 for (i = 0; i < 3; i++) {
1414 writel(i*2, ioaddr + RxFilterAddr);
1415 pmatch[i] = readw(ioaddr + RxFilterData);
1418 for (i = 0; i < 3; i++) {
1419 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1420 sopass[i] = readw(ioaddr + RxFilterData);
1423 /* now whack the chip */
1424 writel(ChipReset, ioaddr + ChipCmd);
1425 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1426 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1430 if (i==NATSEMI_HW_TIMEOUT) {
1431 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1433 } else if (netif_msg_hw(np)) {
1434 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1439 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1440 /* turn on external phy if it was selected */
1441 if (dev->if_port == PORT_TP)
1442 cfg &= ~(CfgExtPhy | CfgPhyDis);
1444 cfg |= (CfgExtPhy | CfgPhyDis);
1445 writel(cfg, ioaddr + ChipConfig);
1447 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1448 writel(wcsr, ioaddr + WOLCmd);
1450 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1451 /* restore PMATCH */
1452 for (i = 0; i < 3; i++) {
1453 writel(i*2, ioaddr + RxFilterAddr);
1454 writew(pmatch[i], ioaddr + RxFilterData);
1456 for (i = 0; i < 3; i++) {
1457 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1458 writew(sopass[i], ioaddr + RxFilterData);
1461 writel(rfcr, ioaddr + RxFilterAddr);
1464 static void reset_rx(struct net_device *dev)
1467 struct netdev_private *np = netdev_priv(dev);
1468 void __iomem *ioaddr = ns_ioaddr(dev);
1470 np->intr_status &= ~RxResetDone;
1472 writel(RxReset, ioaddr + ChipCmd);
1474 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1475 np->intr_status |= readl(ioaddr + IntrStatus);
1476 if (np->intr_status & RxResetDone)
1480 if (i==NATSEMI_HW_TIMEOUT) {
1481 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1483 } else if (netif_msg_hw(np)) {
1484 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1489 static void natsemi_reload_eeprom(struct net_device *dev)
1491 struct netdev_private *np = netdev_priv(dev);
1492 void __iomem *ioaddr = ns_ioaddr(dev);
1495 writel(EepromReload, ioaddr + PCIBusCfg);
1496 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1498 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1501 if (i==NATSEMI_HW_TIMEOUT) {
1502 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1503 pci_name(np->pci_dev), i*50);
1504 } else if (netif_msg_hw(np)) {
1505 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1506 pci_name(np->pci_dev), i*50);
1510 static void natsemi_stop_rxtx(struct net_device *dev)
1512 void __iomem * ioaddr = ns_ioaddr(dev);
1513 struct netdev_private *np = netdev_priv(dev);
1516 writel(RxOff | TxOff, ioaddr + ChipCmd);
1517 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1518 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1522 if (i==NATSEMI_HW_TIMEOUT) {
1523 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1525 } else if (netif_msg_hw(np)) {
1526 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1531 static int netdev_open(struct net_device *dev)
1533 struct netdev_private *np = netdev_priv(dev);
1534 void __iomem * ioaddr = ns_ioaddr(dev);
1535 const int irq = np->pci_dev->irq;
1538 /* Reset the chip, just in case. */
1541 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
1544 if (netif_msg_ifup(np))
1545 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1547 i = alloc_ring(dev);
1552 napi_enable(&np->napi);
1555 spin_lock_irq(&np->lock);
1556 init_registers(dev);
1557 /* now set the MAC address according to dev->dev_addr */
1558 for (i = 0; i < 3; i++) {
1559 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1561 writel(i*2, ioaddr + RxFilterAddr);
1562 writew(mac, ioaddr + RxFilterData);
1564 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1565 spin_unlock_irq(&np->lock);
1567 netif_start_queue(dev);
1569 if (netif_msg_ifup(np))
1570 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1571 dev->name, (int)readl(ioaddr + ChipCmd));
1573 /* Set the timer to check for link beat. */
1574 init_timer(&np->timer);
1575 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1576 np->timer.data = (unsigned long)dev;
1577 np->timer.function = netdev_timer; /* timer handler */
1578 add_timer(&np->timer);
1583 static void do_cable_magic(struct net_device *dev)
1585 struct netdev_private *np = netdev_priv(dev);
1586 void __iomem *ioaddr = ns_ioaddr(dev);
1588 if (dev->if_port != PORT_TP)
1591 if (np->srr >= SRR_DP83816_A5)
1595 * 100 MBit links with short cables can trip an issue with the chip.
1596 * The problem manifests as lots of CRC errors and/or flickering
1597 * activity LED while idle. This process is based on instructions
1598 * from engineers at National.
1600 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1603 writew(1, ioaddr + PGSEL);
1605 * coefficient visibility should already be enabled via
1608 data = readw(ioaddr + TSTDAT) & 0xff;
1610 * the value must be negative, and within certain values
1611 * (these values all come from National)
1613 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1614 np = netdev_priv(dev);
1616 /* the bug has been triggered - fix the coefficient */
1617 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1618 /* lock the value */
1619 data = readw(ioaddr + DSPCFG);
1620 np->dspcfg = data | DSPCFG_LOCK;
1621 writew(np->dspcfg, ioaddr + DSPCFG);
1623 writew(0, ioaddr + PGSEL);
1627 static void undo_cable_magic(struct net_device *dev)
1630 struct netdev_private *np = netdev_priv(dev);
1631 void __iomem * ioaddr = ns_ioaddr(dev);
1633 if (dev->if_port != PORT_TP)
1636 if (np->srr >= SRR_DP83816_A5)
1639 writew(1, ioaddr + PGSEL);
1640 /* make sure the lock bit is clear */
1641 data = readw(ioaddr + DSPCFG);
1642 np->dspcfg = data & ~DSPCFG_LOCK;
1643 writew(np->dspcfg, ioaddr + DSPCFG);
1644 writew(0, ioaddr + PGSEL);
1647 static void check_link(struct net_device *dev)
1649 struct netdev_private *np = netdev_priv(dev);
1650 void __iomem * ioaddr = ns_ioaddr(dev);
1651 int duplex = np->duplex;
1654 /* If we are ignoring the PHY then don't try reading it. */
1656 goto propagate_state;
1658 /* The link status field is latched: it remains low after a temporary
1659 * link failure until it's read. We need the current link status,
1662 mdio_read(dev, MII_BMSR);
1663 bmsr = mdio_read(dev, MII_BMSR);
1665 if (!(bmsr & BMSR_LSTATUS)) {
1666 if (netif_carrier_ok(dev)) {
1667 if (netif_msg_link(np))
1668 printk(KERN_NOTICE "%s: link down.\n",
1670 netif_carrier_off(dev);
1671 undo_cable_magic(dev);
1675 if (!netif_carrier_ok(dev)) {
1676 if (netif_msg_link(np))
1677 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1678 netif_carrier_on(dev);
1679 do_cable_magic(dev);
1682 duplex = np->full_duplex;
1684 if (bmsr & BMSR_ANEGCOMPLETE) {
1685 int tmp = mii_nway_result(
1686 np->advertising & mdio_read(dev, MII_LPA));
1687 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1689 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1694 /* if duplex is set then bit 28 must be set, too */
1695 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1696 if (netif_msg_link(np))
1698 "%s: Setting %s-duplex based on negotiated "
1699 "link capability.\n", dev->name,
1700 duplex ? "full" : "half");
1702 np->rx_config |= RxAcceptTx;
1703 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1705 np->rx_config &= ~RxAcceptTx;
1706 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1708 writel(np->tx_config, ioaddr + TxConfig);
1709 writel(np->rx_config, ioaddr + RxConfig);
1713 static void init_registers(struct net_device *dev)
1715 struct netdev_private *np = netdev_priv(dev);
1716 void __iomem * ioaddr = ns_ioaddr(dev);
1718 init_phy_fixup(dev);
1720 /* clear any interrupts that are pending, such as wake events */
1721 readl(ioaddr + IntrStatus);
1723 writel(np->ring_dma, ioaddr + RxRingPtr);
1724 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1725 ioaddr + TxRingPtr);
1727 /* Initialize other registers.
1728 * Configure the PCI bus bursts and FIFO thresholds.
1729 * Configure for standard, in-spec Ethernet.
1730 * Start with half-duplex. check_link will update
1731 * to the correct settings.
1734 /* DRTH: 2: start tx if 64 bytes are in the fifo
1735 * FLTH: 0x10: refill with next packet if 512 bytes are free
1736 * MXDMA: 0: up to 256 byte bursts.
1737 * MXDMA must be <= FLTH
1741 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1742 TX_FLTH_VAL | TX_DRTH_VAL_START;
1743 writel(np->tx_config, ioaddr + TxConfig);
1745 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1746 * MXDMA 0: up to 256 byte bursts
1748 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1749 /* if receive ring now has bigger buffers than normal, enable jumbo */
1750 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1751 np->rx_config |= RxAcceptLong;
1753 writel(np->rx_config, ioaddr + RxConfig);
1756 * The PME bit is initialized from the EEPROM contents.
1757 * PCI cards probably have PME disabled, but motherboard
1758 * implementations may have PME set to enable WakeOnLan.
1759 * With PME set the chip will scan incoming packets but
1760 * nothing will be written to memory. */
1761 np->SavedClkRun = readl(ioaddr + ClkRun);
1762 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1763 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1764 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1765 dev->name, readl(ioaddr + WOLCmd));
1771 /* Enable interrupts by setting the interrupt mask. */
1772 writel(DEFAULT_INTR, ioaddr + IntrMask);
1773 natsemi_irq_enable(dev);
1775 writel(RxOn | TxOn, ioaddr + ChipCmd);
1776 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1782 * 1) check for link changes. Usually they are handled by the MII interrupt
1783 * but it doesn't hurt to check twice.
1784 * 2) check for sudden death of the NIC:
1785 * It seems that a reference set for this chip went out with incorrect info,
1786 * and there exist boards that aren't quite right. An unexpected voltage
1787 * drop can cause the PHY to get itself in a weird state (basically reset).
1788 * NOTE: this only seems to affect revC chips. The user can disable
1789 * this check via dspcfg_workaround sysfs option.
1790 * 3) check of death of the RX path due to OOM
1792 static void netdev_timer(unsigned long data)
1794 struct net_device *dev = (struct net_device *)data;
1795 struct netdev_private *np = netdev_priv(dev);
1796 void __iomem * ioaddr = ns_ioaddr(dev);
1797 int next_tick = NATSEMI_TIMER_FREQ;
1798 const int irq = np->pci_dev->irq;
1800 if (netif_msg_timer(np)) {
1801 /* DO NOT read the IntrStatus register,
1802 * a read clears any pending interrupts.
1804 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1808 if (dev->if_port == PORT_TP) {
1811 spin_lock_irq(&np->lock);
1812 /* check for a nasty random phy-reset - use dspcfg as a flag */
1813 writew(1, ioaddr+PGSEL);
1814 dspcfg = readw(ioaddr+DSPCFG);
1815 writew(0, ioaddr+PGSEL);
1816 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1817 if (!netif_queue_stopped(dev)) {
1818 spin_unlock_irq(&np->lock);
1819 if (netif_msg_drv(np))
1820 printk(KERN_NOTICE "%s: possible phy reset: "
1821 "re-initializing\n", dev->name);
1823 spin_lock_irq(&np->lock);
1824 natsemi_stop_rxtx(dev);
1827 init_registers(dev);
1828 spin_unlock_irq(&np->lock);
1833 spin_unlock_irq(&np->lock);
1836 /* init_registers() calls check_link() for the above case */
1838 spin_unlock_irq(&np->lock);
1841 spin_lock_irq(&np->lock);
1843 spin_unlock_irq(&np->lock);
1851 writel(RxOn, ioaddr + ChipCmd);
1858 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1860 mod_timer(&np->timer, jiffies + next_tick);
1863 static void dump_ring(struct net_device *dev)
1865 struct netdev_private *np = netdev_priv(dev);
1867 if (netif_msg_pktdata(np)) {
1869 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1870 for (i = 0; i < TX_RING_SIZE; i++) {
1871 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1872 i, np->tx_ring[i].next_desc,
1873 np->tx_ring[i].cmd_status,
1874 np->tx_ring[i].addr);
1876 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1877 for (i = 0; i < RX_RING_SIZE; i++) {
1878 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1879 i, np->rx_ring[i].next_desc,
1880 np->rx_ring[i].cmd_status,
1881 np->rx_ring[i].addr);
1886 static void ns_tx_timeout(struct net_device *dev)
1888 struct netdev_private *np = netdev_priv(dev);
1889 void __iomem * ioaddr = ns_ioaddr(dev);
1890 const int irq = np->pci_dev->irq;
1893 spin_lock_irq(&np->lock);
1894 if (!np->hands_off) {
1895 if (netif_msg_tx_err(np))
1897 "%s: Transmit timed out, status %#08x,"
1899 dev->name, readl(ioaddr + IntrStatus));
1904 init_registers(dev);
1907 "%s: tx_timeout while in hands_off state?\n",
1910 spin_unlock_irq(&np->lock);
1913 netif_trans_update(dev); /* prevent tx timeout */
1914 dev->stats.tx_errors++;
1915 netif_wake_queue(dev);
1918 static int alloc_ring(struct net_device *dev)
1920 struct netdev_private *np = netdev_priv(dev);
1921 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1922 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1926 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1930 static void refill_rx(struct net_device *dev)
1932 struct netdev_private *np = netdev_priv(dev);
1934 /* Refill the Rx ring buffers. */
1935 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1936 struct sk_buff *skb;
1937 int entry = np->dirty_rx % RX_RING_SIZE;
1938 if (np->rx_skbuff[entry] == NULL) {
1939 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1940 skb = netdev_alloc_skb(dev, buflen);
1941 np->rx_skbuff[entry] = skb;
1943 break; /* Better luck next round. */
1944 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1945 skb->data, buflen, PCI_DMA_FROMDEVICE);
1946 if (pci_dma_mapping_error(np->pci_dev,
1947 np->rx_dma[entry])) {
1948 dev_kfree_skb_any(skb);
1949 np->rx_skbuff[entry] = NULL;
1950 break; /* Better luck next round. */
1952 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1954 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1956 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1957 if (netif_msg_rx_err(np))
1958 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1963 static void set_bufsize(struct net_device *dev)
1965 struct netdev_private *np = netdev_priv(dev);
1966 if (dev->mtu <= ETH_DATA_LEN)
1967 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1969 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1972 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1973 static void init_ring(struct net_device *dev)
1975 struct netdev_private *np = netdev_priv(dev);
1979 np->dirty_tx = np->cur_tx = 0;
1980 for (i = 0; i < TX_RING_SIZE; i++) {
1981 np->tx_skbuff[i] = NULL;
1982 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1983 +sizeof(struct netdev_desc)
1984 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1985 np->tx_ring[i].cmd_status = 0;
1990 np->cur_rx = RX_RING_SIZE;
1994 np->rx_head_desc = &np->rx_ring[0];
1996 /* Please be careful before changing this loop - at least gcc-2.95.1
1997 * miscompiles it otherwise.
1999 /* Initialize all Rx descriptors. */
2000 for (i = 0; i < RX_RING_SIZE; i++) {
2001 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2002 +sizeof(struct netdev_desc)
2003 *((i+1)%RX_RING_SIZE));
2004 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2005 np->rx_skbuff[i] = NULL;
2011 static void drain_tx(struct net_device *dev)
2013 struct netdev_private *np = netdev_priv(dev);
2016 for (i = 0; i < TX_RING_SIZE; i++) {
2017 if (np->tx_skbuff[i]) {
2018 pci_unmap_single(np->pci_dev,
2019 np->tx_dma[i], np->tx_skbuff[i]->len,
2021 dev_kfree_skb(np->tx_skbuff[i]);
2022 dev->stats.tx_dropped++;
2024 np->tx_skbuff[i] = NULL;
2028 static void drain_rx(struct net_device *dev)
2030 struct netdev_private *np = netdev_priv(dev);
2031 unsigned int buflen = np->rx_buf_sz;
2034 /* Free all the skbuffs in the Rx queue. */
2035 for (i = 0; i < RX_RING_SIZE; i++) {
2036 np->rx_ring[i].cmd_status = 0;
2037 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
2038 if (np->rx_skbuff[i]) {
2039 pci_unmap_single(np->pci_dev, np->rx_dma[i],
2040 buflen + NATSEMI_PADDING,
2041 PCI_DMA_FROMDEVICE);
2042 dev_kfree_skb(np->rx_skbuff[i]);
2044 np->rx_skbuff[i] = NULL;
2048 static void drain_ring(struct net_device *dev)
2054 static void free_ring(struct net_device *dev)
2056 struct netdev_private *np = netdev_priv(dev);
2057 pci_free_consistent(np->pci_dev,
2058 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2059 np->rx_ring, np->ring_dma);
2062 static void reinit_rx(struct net_device *dev)
2064 struct netdev_private *np = netdev_priv(dev);
2069 np->cur_rx = RX_RING_SIZE;
2070 np->rx_head_desc = &np->rx_ring[0];
2071 /* Initialize all Rx descriptors. */
2072 for (i = 0; i < RX_RING_SIZE; i++)
2073 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2078 static void reinit_ring(struct net_device *dev)
2080 struct netdev_private *np = netdev_priv(dev);
2085 np->dirty_tx = np->cur_tx = 0;
2086 for (i=0;i<TX_RING_SIZE;i++)
2087 np->tx_ring[i].cmd_status = 0;
2092 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
2094 struct netdev_private *np = netdev_priv(dev);
2095 void __iomem * ioaddr = ns_ioaddr(dev);
2097 unsigned long flags;
2099 /* Note: Ordering is important here, set the field with the
2100 "ownership" bit last, and only then increment cur_tx. */
2102 /* Calculate the next Tx descriptor entry. */
2103 entry = np->cur_tx % TX_RING_SIZE;
2105 np->tx_skbuff[entry] = skb;
2106 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2107 skb->data,skb->len, PCI_DMA_TODEVICE);
2108 if (pci_dma_mapping_error(np->pci_dev, np->tx_dma[entry])) {
2109 np->tx_skbuff[entry] = NULL;
2110 dev_kfree_skb_irq(skb);
2111 dev->stats.tx_dropped++;
2112 return NETDEV_TX_OK;
2115 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2117 spin_lock_irqsave(&np->lock, flags);
2119 if (!np->hands_off) {
2120 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2121 /* StrongARM: Explicitly cache flush np->tx_ring and
2122 * skb->data,skb->len. */
2125 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2126 netdev_tx_done(dev);
2127 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2128 netif_stop_queue(dev);
2130 /* Wake the potentially-idle transmit channel. */
2131 writel(TxOn, ioaddr + ChipCmd);
2133 dev_kfree_skb_irq(skb);
2134 dev->stats.tx_dropped++;
2136 spin_unlock_irqrestore(&np->lock, flags);
2138 if (netif_msg_tx_queued(np)) {
2139 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2140 dev->name, np->cur_tx, entry);
2142 return NETDEV_TX_OK;
2145 static void netdev_tx_done(struct net_device *dev)
2147 struct netdev_private *np = netdev_priv(dev);
2149 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2150 int entry = np->dirty_tx % TX_RING_SIZE;
2151 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2153 if (netif_msg_tx_done(np))
2155 "%s: tx frame #%d finished, status %#08x.\n",
2156 dev->name, np->dirty_tx,
2157 le32_to_cpu(np->tx_ring[entry].cmd_status));
2158 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2159 dev->stats.tx_packets++;
2160 dev->stats.tx_bytes += np->tx_skbuff[entry]->len;
2161 } else { /* Various Tx errors */
2163 le32_to_cpu(np->tx_ring[entry].cmd_status);
2164 if (tx_status & (DescTxAbort|DescTxExcColl))
2165 dev->stats.tx_aborted_errors++;
2166 if (tx_status & DescTxFIFO)
2167 dev->stats.tx_fifo_errors++;
2168 if (tx_status & DescTxCarrier)
2169 dev->stats.tx_carrier_errors++;
2170 if (tx_status & DescTxOOWCol)
2171 dev->stats.tx_window_errors++;
2172 dev->stats.tx_errors++;
2174 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2175 np->tx_skbuff[entry]->len,
2177 /* Free the original skb. */
2178 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2179 np->tx_skbuff[entry] = NULL;
2181 if (netif_queue_stopped(dev) &&
2182 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2183 /* The ring is no longer full, wake queue. */
2184 netif_wake_queue(dev);
2188 /* The interrupt handler doesn't actually handle interrupts itself, it
2189 * schedules a NAPI poll if there is anything to do. */
2190 static irqreturn_t intr_handler(int irq, void *dev_instance)
2192 struct net_device *dev = dev_instance;
2193 struct netdev_private *np = netdev_priv(dev);
2194 void __iomem * ioaddr = ns_ioaddr(dev);
2196 /* Reading IntrStatus automatically acknowledges so don't do
2197 * that while interrupts are disabled, (for example, while a
2198 * poll is scheduled). */
2199 if (np->hands_off || !readl(ioaddr + IntrEnable))
2202 np->intr_status = readl(ioaddr + IntrStatus);
2204 if (!np->intr_status)
2207 if (netif_msg_intr(np))
2209 "%s: Interrupt, status %#08x, mask %#08x.\n",
2210 dev->name, np->intr_status,
2211 readl(ioaddr + IntrMask));
2213 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2215 if (napi_schedule_prep(&np->napi)) {
2216 /* Disable interrupts and register for poll */
2217 natsemi_irq_disable(dev);
2218 __napi_schedule(&np->napi);
2221 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2222 dev->name, np->intr_status,
2223 readl(ioaddr + IntrMask));
2228 /* This is the NAPI poll routine. As well as the standard RX handling
2229 * it also handles all other interrupts that the chip might raise.
2231 static int natsemi_poll(struct napi_struct *napi, int budget)
2233 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2234 struct net_device *dev = np->dev;
2235 void __iomem * ioaddr = ns_ioaddr(dev);
2239 if (netif_msg_intr(np))
2241 "%s: Poll, status %#08x, mask %#08x.\n",
2242 dev->name, np->intr_status,
2243 readl(ioaddr + IntrMask));
2245 /* netdev_rx() may read IntrStatus again if the RX state
2246 * machine falls over so do it first. */
2247 if (np->intr_status &
2248 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2249 IntrRxErr | IntrRxOverrun)) {
2250 netdev_rx(dev, &work_done, budget);
2253 if (np->intr_status &
2254 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2255 spin_lock(&np->lock);
2256 netdev_tx_done(dev);
2257 spin_unlock(&np->lock);
2260 /* Abnormal error summary/uncommon events handlers. */
2261 if (np->intr_status & IntrAbnormalSummary)
2262 netdev_error(dev, np->intr_status);
2264 if (work_done >= budget)
2267 np->intr_status = readl(ioaddr + IntrStatus);
2268 } while (np->intr_status);
2270 napi_complete_done(napi, work_done);
2272 /* Reenable interrupts providing nothing is trying to shut
2274 spin_lock(&np->lock);
2276 natsemi_irq_enable(dev);
2277 spin_unlock(&np->lock);
2282 /* This routine is logically part of the interrupt handler, but separated
2283 for clarity and better register allocation. */
2284 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2286 struct netdev_private *np = netdev_priv(dev);
2287 int entry = np->cur_rx % RX_RING_SIZE;
2288 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2289 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2290 unsigned int buflen = np->rx_buf_sz;
2291 void __iomem * ioaddr = ns_ioaddr(dev);
2293 /* If the driver owns the next entry it's a new packet. Send it up. */
2294 while (desc_status < 0) { /* e.g. & DescOwn */
2296 if (netif_msg_rx_status(np))
2298 " netdev_rx() entry %d status was %#08x.\n",
2299 entry, desc_status);
2303 if (*work_done >= work_to_do)
2308 pkt_len = (desc_status & DescSizeMask) - 4;
2309 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2310 if (desc_status & DescMore) {
2311 unsigned long flags;
2313 if (netif_msg_rx_err(np))
2315 "%s: Oversized(?) Ethernet "
2316 "frame spanned multiple "
2317 "buffers, entry %#08x "
2318 "status %#08x.\n", dev->name,
2319 np->cur_rx, desc_status);
2320 dev->stats.rx_length_errors++;
2322 /* The RX state machine has probably
2323 * locked up beneath us. Follow the
2324 * reset procedure documented in
2327 spin_lock_irqsave(&np->lock, flags);
2330 writel(np->ring_dma, ioaddr + RxRingPtr);
2332 spin_unlock_irqrestore(&np->lock, flags);
2334 /* We'll enable RX on exit from this
2339 /* There was an error. */
2340 dev->stats.rx_errors++;
2341 if (desc_status & (DescRxAbort|DescRxOver))
2342 dev->stats.rx_over_errors++;
2343 if (desc_status & (DescRxLong|DescRxRunt))
2344 dev->stats.rx_length_errors++;
2345 if (desc_status & (DescRxInvalid|DescRxAlign))
2346 dev->stats.rx_frame_errors++;
2347 if (desc_status & DescRxCRC)
2348 dev->stats.rx_crc_errors++;
2350 } else if (pkt_len > np->rx_buf_sz) {
2351 /* if this is the tail of a double buffer
2352 * packet, we've already counted the error
2353 * on the first part. Ignore the second half.
2356 struct sk_buff *skb;
2357 /* Omit CRC size. */
2358 /* Check if the packet is long enough to accept
2359 * without copying to a minimally-sized skbuff. */
2360 if (pkt_len < rx_copybreak &&
2361 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) {
2362 /* 16 byte align the IP header */
2363 skb_reserve(skb, RX_OFFSET);
2364 pci_dma_sync_single_for_cpu(np->pci_dev,
2367 PCI_DMA_FROMDEVICE);
2368 skb_copy_to_linear_data(skb,
2369 np->rx_skbuff[entry]->data, pkt_len);
2370 skb_put(skb, pkt_len);
2371 pci_dma_sync_single_for_device(np->pci_dev,
2374 PCI_DMA_FROMDEVICE);
2376 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2377 buflen + NATSEMI_PADDING,
2378 PCI_DMA_FROMDEVICE);
2379 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2380 np->rx_skbuff[entry] = NULL;
2382 skb->protocol = eth_type_trans(skb, dev);
2383 netif_receive_skb(skb);
2384 dev->stats.rx_packets++;
2385 dev->stats.rx_bytes += pkt_len;
2387 entry = (++np->cur_rx) % RX_RING_SIZE;
2388 np->rx_head_desc = &np->rx_ring[entry];
2389 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2393 /* Restart Rx engine if stopped. */
2395 mod_timer(&np->timer, jiffies + 1);
2397 writel(RxOn, ioaddr + ChipCmd);
2400 static void netdev_error(struct net_device *dev, int intr_status)
2402 struct netdev_private *np = netdev_priv(dev);
2403 void __iomem * ioaddr = ns_ioaddr(dev);
2405 spin_lock(&np->lock);
2406 if (intr_status & LinkChange) {
2407 u16 lpa = mdio_read(dev, MII_LPA);
2408 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2409 netif_msg_link(np)) {
2411 "%s: Autonegotiation advertising"
2412 " %#04x partner %#04x.\n", dev->name,
2413 np->advertising, lpa);
2416 /* read MII int status to clear the flag */
2417 readw(ioaddr + MIntrStatus);
2420 if (intr_status & StatsMax) {
2423 if (intr_status & IntrTxUnderrun) {
2424 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2425 np->tx_config += TX_DRTH_VAL_INC;
2426 if (netif_msg_tx_err(np))
2428 "%s: increased tx threshold, txcfg %#08x.\n",
2429 dev->name, np->tx_config);
2431 if (netif_msg_tx_err(np))
2433 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2434 dev->name, np->tx_config);
2436 writel(np->tx_config, ioaddr + TxConfig);
2438 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2439 int wol_status = readl(ioaddr + WOLCmd);
2440 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2441 dev->name, wol_status);
2443 if (intr_status & RxStatusFIFOOver) {
2444 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2445 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2448 dev->stats.rx_fifo_errors++;
2449 dev->stats.rx_errors++;
2451 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2452 if (intr_status & IntrPCIErr) {
2453 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2454 intr_status & IntrPCIErr);
2455 dev->stats.tx_fifo_errors++;
2456 dev->stats.tx_errors++;
2457 dev->stats.rx_fifo_errors++;
2458 dev->stats.rx_errors++;
2460 spin_unlock(&np->lock);
2463 static void __get_stats(struct net_device *dev)
2465 void __iomem * ioaddr = ns_ioaddr(dev);
2467 /* The chip only need report frame silently dropped. */
2468 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2469 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2472 static struct net_device_stats *get_stats(struct net_device *dev)
2474 struct netdev_private *np = netdev_priv(dev);
2476 /* The chip only need report frame silently dropped. */
2477 spin_lock_irq(&np->lock);
2478 if (netif_running(dev) && !np->hands_off)
2480 spin_unlock_irq(&np->lock);
2485 #ifdef CONFIG_NET_POLL_CONTROLLER
2486 static void natsemi_poll_controller(struct net_device *dev)
2488 struct netdev_private *np = netdev_priv(dev);
2489 const int irq = np->pci_dev->irq;
2492 intr_handler(irq, dev);
2497 #define HASH_TABLE 0x200
2498 static void __set_rx_mode(struct net_device *dev)
2500 void __iomem * ioaddr = ns_ioaddr(dev);
2501 struct netdev_private *np = netdev_priv(dev);
2502 u8 mc_filter[64]; /* Multicast hash filter */
2505 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2506 rx_mode = RxFilterEnable | AcceptBroadcast
2507 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2508 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2509 (dev->flags & IFF_ALLMULTI)) {
2510 rx_mode = RxFilterEnable | AcceptBroadcast
2511 | AcceptAllMulticast | AcceptMyPhys;
2513 struct netdev_hw_addr *ha;
2516 memset(mc_filter, 0, sizeof(mc_filter));
2517 netdev_for_each_mc_addr(ha, dev) {
2518 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
2519 mc_filter[b/8] |= (1 << (b & 0x07));
2521 rx_mode = RxFilterEnable | AcceptBroadcast
2522 | AcceptMulticast | AcceptMyPhys;
2523 for (i = 0; i < 64; i += 2) {
2524 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2525 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2526 ioaddr + RxFilterData);
2529 writel(rx_mode, ioaddr + RxFilterAddr);
2530 np->cur_rx_mode = rx_mode;
2533 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2537 /* synchronized against open : rtnl_lock() held by caller */
2538 if (netif_running(dev)) {
2539 struct netdev_private *np = netdev_priv(dev);
2540 void __iomem * ioaddr = ns_ioaddr(dev);
2541 const int irq = np->pci_dev->irq;
2544 spin_lock(&np->lock);
2546 natsemi_stop_rxtx(dev);
2547 /* drain rx queue */
2549 /* change buffers */
2552 writel(np->ring_dma, ioaddr + RxRingPtr);
2553 /* restart engines */
2554 writel(RxOn | TxOn, ioaddr + ChipCmd);
2555 spin_unlock(&np->lock);
2561 static void set_rx_mode(struct net_device *dev)
2563 struct netdev_private *np = netdev_priv(dev);
2564 spin_lock_irq(&np->lock);
2567 spin_unlock_irq(&np->lock);
2570 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2572 struct netdev_private *np = netdev_priv(dev);
2573 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2574 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2575 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
2578 static int get_regs_len(struct net_device *dev)
2580 return NATSEMI_REGS_SIZE;
2583 static int get_eeprom_len(struct net_device *dev)
2585 struct netdev_private *np = netdev_priv(dev);
2586 return np->eeprom_size;
2589 static int get_link_ksettings(struct net_device *dev,
2590 struct ethtool_link_ksettings *ecmd)
2592 struct netdev_private *np = netdev_priv(dev);
2593 spin_lock_irq(&np->lock);
2594 netdev_get_ecmd(dev, ecmd);
2595 spin_unlock_irq(&np->lock);
2599 static int set_link_ksettings(struct net_device *dev,
2600 const struct ethtool_link_ksettings *ecmd)
2602 struct netdev_private *np = netdev_priv(dev);
2604 spin_lock_irq(&np->lock);
2605 res = netdev_set_ecmd(dev, ecmd);
2606 spin_unlock_irq(&np->lock);
2610 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2612 struct netdev_private *np = netdev_priv(dev);
2613 spin_lock_irq(&np->lock);
2614 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2615 netdev_get_sopass(dev, wol->sopass);
2616 spin_unlock_irq(&np->lock);
2619 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2621 struct netdev_private *np = netdev_priv(dev);
2623 spin_lock_irq(&np->lock);
2624 netdev_set_wol(dev, wol->wolopts);
2625 res = netdev_set_sopass(dev, wol->sopass);
2626 spin_unlock_irq(&np->lock);
2630 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2632 struct netdev_private *np = netdev_priv(dev);
2633 regs->version = NATSEMI_REGS_VER;
2634 spin_lock_irq(&np->lock);
2635 netdev_get_regs(dev, buf);
2636 spin_unlock_irq(&np->lock);
2639 static u32 get_msglevel(struct net_device *dev)
2641 struct netdev_private *np = netdev_priv(dev);
2642 return np->msg_enable;
2645 static void set_msglevel(struct net_device *dev, u32 val)
2647 struct netdev_private *np = netdev_priv(dev);
2648 np->msg_enable = val;
2651 static int nway_reset(struct net_device *dev)
2655 /* if autoneg is off, it's an error */
2656 tmp = mdio_read(dev, MII_BMCR);
2657 if (tmp & BMCR_ANENABLE) {
2658 tmp |= (BMCR_ANRESTART);
2659 mdio_write(dev, MII_BMCR, tmp);
2665 static u32 get_link(struct net_device *dev)
2667 /* LSTATUS is latched low until a read - so read twice */
2668 mdio_read(dev, MII_BMSR);
2669 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2672 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2674 struct netdev_private *np = netdev_priv(dev);
2678 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2682 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2683 spin_lock_irq(&np->lock);
2684 res = netdev_get_eeprom(dev, eebuf);
2685 spin_unlock_irq(&np->lock);
2687 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2692 static const struct ethtool_ops ethtool_ops = {
2693 .get_drvinfo = get_drvinfo,
2694 .get_regs_len = get_regs_len,
2695 .get_eeprom_len = get_eeprom_len,
2698 .get_regs = get_regs,
2699 .get_msglevel = get_msglevel,
2700 .set_msglevel = set_msglevel,
2701 .nway_reset = nway_reset,
2702 .get_link = get_link,
2703 .get_eeprom = get_eeprom,
2704 .get_link_ksettings = get_link_ksettings,
2705 .set_link_ksettings = set_link_ksettings,
2708 static int netdev_set_wol(struct net_device *dev, u32 newval)
2710 struct netdev_private *np = netdev_priv(dev);
2711 void __iomem * ioaddr = ns_ioaddr(dev);
2712 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2714 /* translate to bitmasks this chip understands */
2715 if (newval & WAKE_PHY)
2717 if (newval & WAKE_UCAST)
2718 data |= WakeUnicast;
2719 if (newval & WAKE_MCAST)
2720 data |= WakeMulticast;
2721 if (newval & WAKE_BCAST)
2722 data |= WakeBroadcast;
2723 if (newval & WAKE_ARP)
2725 if (newval & WAKE_MAGIC)
2727 if (np->srr >= SRR_DP83815_D) {
2728 if (newval & WAKE_MAGICSECURE) {
2729 data |= WakeMagicSecure;
2733 writel(data, ioaddr + WOLCmd);
2738 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2740 struct netdev_private *np = netdev_priv(dev);
2741 void __iomem * ioaddr = ns_ioaddr(dev);
2742 u32 regval = readl(ioaddr + WOLCmd);
2744 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2745 | WAKE_ARP | WAKE_MAGIC);
2747 if (np->srr >= SRR_DP83815_D) {
2748 /* SOPASS works on revD and higher */
2749 *supported |= WAKE_MAGICSECURE;
2753 /* translate from chip bitmasks */
2754 if (regval & WakePhy)
2756 if (regval & WakeUnicast)
2758 if (regval & WakeMulticast)
2760 if (regval & WakeBroadcast)
2762 if (regval & WakeArp)
2764 if (regval & WakeMagic)
2766 if (regval & WakeMagicSecure) {
2767 /* this can be on in revC, but it's broken */
2768 *cur |= WAKE_MAGICSECURE;
2774 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2776 struct netdev_private *np = netdev_priv(dev);
2777 void __iomem * ioaddr = ns_ioaddr(dev);
2778 u16 *sval = (u16 *)newval;
2781 if (np->srr < SRR_DP83815_D) {
2785 /* enable writing to these registers by disabling the RX filter */
2786 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2787 addr &= ~RxFilterEnable;
2788 writel(addr, ioaddr + RxFilterAddr);
2790 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2791 writel(addr | 0xa, ioaddr + RxFilterAddr);
2792 writew(sval[0], ioaddr + RxFilterData);
2794 writel(addr | 0xc, ioaddr + RxFilterAddr);
2795 writew(sval[1], ioaddr + RxFilterData);
2797 writel(addr | 0xe, ioaddr + RxFilterAddr);
2798 writew(sval[2], ioaddr + RxFilterData);
2800 /* re-enable the RX filter */
2801 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2806 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2808 struct netdev_private *np = netdev_priv(dev);
2809 void __iomem * ioaddr = ns_ioaddr(dev);
2810 u16 *sval = (u16 *)data;
2813 if (np->srr < SRR_DP83815_D) {
2814 sval[0] = sval[1] = sval[2] = 0;
2818 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2819 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2821 writel(addr | 0xa, ioaddr + RxFilterAddr);
2822 sval[0] = readw(ioaddr + RxFilterData);
2824 writel(addr | 0xc, ioaddr + RxFilterAddr);
2825 sval[1] = readw(ioaddr + RxFilterData);
2827 writel(addr | 0xe, ioaddr + RxFilterAddr);
2828 sval[2] = readw(ioaddr + RxFilterData);
2830 writel(addr, ioaddr + RxFilterAddr);
2835 static int netdev_get_ecmd(struct net_device *dev,
2836 struct ethtool_link_ksettings *ecmd)
2838 struct netdev_private *np = netdev_priv(dev);
2839 u32 supported, advertising;
2842 ecmd->base.port = dev->if_port;
2843 ecmd->base.speed = np->speed;
2844 ecmd->base.duplex = np->duplex;
2845 ecmd->base.autoneg = np->autoneg;
2848 if (np->advertising & ADVERTISE_10HALF)
2849 advertising |= ADVERTISED_10baseT_Half;
2850 if (np->advertising & ADVERTISE_10FULL)
2851 advertising |= ADVERTISED_10baseT_Full;
2852 if (np->advertising & ADVERTISE_100HALF)
2853 advertising |= ADVERTISED_100baseT_Half;
2854 if (np->advertising & ADVERTISE_100FULL)
2855 advertising |= ADVERTISED_100baseT_Full;
2856 supported = (SUPPORTED_Autoneg |
2857 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2858 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2859 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2860 ecmd->base.phy_address = np->phy_addr_external;
2862 * We intentionally report the phy address of the external
2863 * phy, even if the internal phy is used. This is necessary
2864 * to work around a deficiency of the ethtool interface:
2865 * It's only possible to query the settings of the active
2867 * # ethtool -s ethX port mii
2868 * actually sends an ioctl to switch to port mii with the
2869 * settings that are used for the current active port.
2870 * If we would report a different phy address in this
2872 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2873 * would unintentionally change the phy address.
2875 * Fortunately the phy address doesn't matter with the
2879 /* set information based on active port type */
2880 switch (ecmd->base.port) {
2883 advertising |= ADVERTISED_TP;
2886 advertising |= ADVERTISED_MII;
2889 advertising |= ADVERTISED_FIBRE;
2893 /* if autonegotiation is on, try to return the active speed/duplex */
2894 if (ecmd->base.autoneg == AUTONEG_ENABLE) {
2895 advertising |= ADVERTISED_Autoneg;
2896 tmp = mii_nway_result(
2897 np->advertising & mdio_read(dev, MII_LPA));
2898 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2899 ecmd->base.speed = SPEED_100;
2901 ecmd->base.speed = SPEED_10;
2902 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2903 ecmd->base.duplex = DUPLEX_FULL;
2905 ecmd->base.duplex = DUPLEX_HALF;
2908 /* ignore maxtxpkt, maxrxpkt for now */
2910 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported,
2912 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising,
2918 static int netdev_set_ecmd(struct net_device *dev,
2919 const struct ethtool_link_ksettings *ecmd)
2921 struct netdev_private *np = netdev_priv(dev);
2924 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2925 ecmd->link_modes.advertising);
2927 if (ecmd->base.port != PORT_TP &&
2928 ecmd->base.port != PORT_MII &&
2929 ecmd->base.port != PORT_FIBRE)
2931 if (ecmd->base.autoneg == AUTONEG_ENABLE) {
2932 if ((advertising & (ADVERTISED_10baseT_Half |
2933 ADVERTISED_10baseT_Full |
2934 ADVERTISED_100baseT_Half |
2935 ADVERTISED_100baseT_Full)) == 0) {
2938 } else if (ecmd->base.autoneg == AUTONEG_DISABLE) {
2939 u32 speed = ecmd->base.speed;
2940 if (speed != SPEED_10 && speed != SPEED_100)
2942 if (ecmd->base.duplex != DUPLEX_HALF &&
2943 ecmd->base.duplex != DUPLEX_FULL)
2950 * If we're ignoring the PHY then autoneg and the internal
2951 * transceiver are really not going to work so don't let the
2954 if (np->ignore_phy && (ecmd->base.autoneg == AUTONEG_ENABLE ||
2955 ecmd->base.port == PORT_TP))
2959 * maxtxpkt, maxrxpkt: ignored for now.
2962 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2963 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2964 * selects based on ecmd->port.
2966 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2967 * phys that are connected to the mii bus. It's used to apply fibre
2971 /* WHEW! now lets bang some bits */
2973 /* save the parms */
2974 dev->if_port = ecmd->base.port;
2975 np->autoneg = ecmd->base.autoneg;
2976 np->phy_addr_external = ecmd->base.phy_address & PhyAddrMask;
2977 if (np->autoneg == AUTONEG_ENABLE) {
2978 /* advertise only what has been requested */
2979 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2980 if (advertising & ADVERTISED_10baseT_Half)
2981 np->advertising |= ADVERTISE_10HALF;
2982 if (advertising & ADVERTISED_10baseT_Full)
2983 np->advertising |= ADVERTISE_10FULL;
2984 if (advertising & ADVERTISED_100baseT_Half)
2985 np->advertising |= ADVERTISE_100HALF;
2986 if (advertising & ADVERTISED_100baseT_Full)
2987 np->advertising |= ADVERTISE_100FULL;
2989 np->speed = ecmd->base.speed;
2990 np->duplex = ecmd->base.duplex;
2991 /* user overriding the initial full duplex parm? */
2992 if (np->duplex == DUPLEX_HALF)
2993 np->full_duplex = 0;
2996 /* get the right phy enabled */
2997 if (ecmd->base.port == PORT_TP)
2998 switch_port_internal(dev);
3000 switch_port_external(dev);
3002 /* set parms and see how this affected our link status */
3003 init_phy_fixup(dev);
3008 static int netdev_get_regs(struct net_device *dev, u8 *buf)
3013 u32 *rbuf = (u32 *)buf;
3014 void __iomem * ioaddr = ns_ioaddr(dev);
3016 /* read non-mii page 0 of registers */
3017 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
3018 rbuf[i] = readl(ioaddr + i*4);
3021 /* read current mii registers */
3022 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3023 rbuf[i] = mdio_read(dev, i & 0x1f);
3025 /* read only the 'magic' registers from page 1 */
3026 writew(1, ioaddr + PGSEL);
3027 rbuf[i++] = readw(ioaddr + PMDCSR);
3028 rbuf[i++] = readw(ioaddr + TSTDAT);
3029 rbuf[i++] = readw(ioaddr + DSPCFG);
3030 rbuf[i++] = readw(ioaddr + SDCFG);
3031 writew(0, ioaddr + PGSEL);
3033 /* read RFCR indexed registers */
3034 rfcr = readl(ioaddr + RxFilterAddr);
3035 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3036 writel(j*2, ioaddr + RxFilterAddr);
3037 rbuf[i++] = readw(ioaddr + RxFilterData);
3039 writel(rfcr, ioaddr + RxFilterAddr);
3041 /* the interrupt status is clear-on-read - see if we missed any */
3042 if (rbuf[4] & rbuf[5]) {
3044 "%s: shoot, we dropped an interrupt (%#08x)\n",
3045 dev->name, rbuf[4] & rbuf[5]);
3051 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3052 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3053 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3054 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3055 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3056 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3057 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3058 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3060 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3063 u16 *ebuf = (u16 *)buf;
3064 void __iomem * ioaddr = ns_ioaddr(dev);
3065 struct netdev_private *np = netdev_priv(dev);
3067 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3068 for (i = 0; i < np->eeprom_size/2; i++) {
3069 ebuf[i] = eeprom_read(ioaddr, i);
3070 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3071 * reads it back "sanely". So we swap it back here in order to
3072 * present it to userland as it is stored. */
3073 ebuf[i] = SWAP_BITS(ebuf[i]);
3078 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3080 struct mii_ioctl_data *data = if_mii(rq);
3081 struct netdev_private *np = netdev_priv(dev);
3084 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3085 data->phy_id = np->phy_addr_external;
3088 case SIOCGMIIREG: /* Read MII PHY register. */
3089 /* The phy_id is not enough to uniquely identify
3090 * the intended target. Therefore the command is sent to
3091 * the given mii on the current port.
3093 if (dev->if_port == PORT_TP) {
3094 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3095 data->val_out = mdio_read(dev,
3096 data->reg_num & 0x1f);
3100 move_int_phy(dev, data->phy_id & 0x1f);
3101 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3102 data->reg_num & 0x1f);
3106 case SIOCSMIIREG: /* Write MII PHY register. */
3107 if (dev->if_port == PORT_TP) {
3108 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3109 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3110 np->advertising = data->val_in;
3111 mdio_write(dev, data->reg_num & 0x1f,
3115 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3116 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3117 np->advertising = data->val_in;
3119 move_int_phy(dev, data->phy_id & 0x1f);
3120 miiport_write(dev, data->phy_id & 0x1f,
3121 data->reg_num & 0x1f,
3130 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3132 void __iomem * ioaddr = ns_ioaddr(dev);
3133 struct netdev_private *np = netdev_priv(dev);
3135 if (netif_msg_wol(np))
3136 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3139 /* For WOL we must restart the rx process in silent mode.
3140 * Write NULL to the RxRingPtr. Only possible if
3141 * rx process is stopped
3143 writel(0, ioaddr + RxRingPtr);
3145 /* read WoL status to clear */
3146 readl(ioaddr + WOLCmd);
3148 /* PME on, clear status */
3149 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3151 /* and restart the rx process */
3152 writel(RxOn, ioaddr + ChipCmd);
3155 /* enable the WOL interrupt.
3156 * Could be used to send a netlink message.
3158 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3159 natsemi_irq_enable(dev);
3163 static int netdev_close(struct net_device *dev)
3165 void __iomem * ioaddr = ns_ioaddr(dev);
3166 struct netdev_private *np = netdev_priv(dev);
3167 const int irq = np->pci_dev->irq;
3169 if (netif_msg_ifdown(np))
3171 "%s: Shutting down ethercard, status was %#04x.\n",
3172 dev->name, (int)readl(ioaddr + ChipCmd));
3173 if (netif_msg_pktdata(np))
3175 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3176 dev->name, np->cur_tx, np->dirty_tx,
3177 np->cur_rx, np->dirty_rx);
3179 napi_disable(&np->napi);
3182 * FIXME: what if someone tries to close a device
3183 * that is suspended?
3184 * Should we reenable the nic to switch to
3185 * the final WOL settings?
3188 del_timer_sync(&np->timer);
3190 spin_lock_irq(&np->lock);
3191 natsemi_irq_disable(dev);
3193 spin_unlock_irq(&np->lock);
3198 /* Interrupt disabled, interrupt handler released,
3199 * queue stopped, timer deleted, rtnl_lock held
3200 * All async codepaths that access the driver are disabled.
3202 spin_lock_irq(&np->lock);
3204 readl(ioaddr + IntrMask);
3205 readw(ioaddr + MIntrStatus);
3208 writel(StatsFreeze, ioaddr + StatsCtrl);
3210 /* Stop the chip's Tx and Rx processes. */
3211 natsemi_stop_rxtx(dev);
3214 spin_unlock_irq(&np->lock);
3216 /* clear the carrier last - an interrupt could reenable it otherwise */
3217 netif_carrier_off(dev);
3218 netif_stop_queue(dev);
3225 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3227 /* restart the NIC in WOL mode.
3228 * The nic must be stopped for this.
3230 enable_wol_mode(dev, 0);
3232 /* Restore PME enable bit unmolested */
3233 writel(np->SavedClkRun, ioaddr + ClkRun);
3240 static void natsemi_remove1(struct pci_dev *pdev)
3242 struct net_device *dev = pci_get_drvdata(pdev);
3243 void __iomem * ioaddr = ns_ioaddr(dev);
3245 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3246 unregister_netdev (dev);
3247 pci_release_regions (pdev);
3255 * The ns83815 chip doesn't have explicit RxStop bits.
3256 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3257 * of the nic, thus this function must be very careful:
3259 * suspend/resume synchronization:
3261 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3262 * start_tx, ns_tx_timeout
3264 * No function accesses the hardware without checking np->hands_off.
3265 * the check occurs under spin_lock_irq(&np->lock);
3267 * * netdev_ioctl: noncritical access.
3268 * * netdev_open: cannot happen due to the device_detach
3269 * * netdev_close: doesn't hurt.
3270 * * netdev_timer: timer stopped by natsemi_suspend.
3271 * * intr_handler: doesn't acquire the spinlock. suspend calls
3272 * disable_irq() to enforce synchronization.
3273 * * natsemi_poll: checks before reenabling interrupts. suspend
3274 * sets hands_off, disables interrupts and then waits with
3277 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3280 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3282 struct net_device *dev = pci_get_drvdata (pdev);
3283 struct netdev_private *np = netdev_priv(dev);
3284 void __iomem * ioaddr = ns_ioaddr(dev);
3287 if (netif_running (dev)) {
3288 const int irq = np->pci_dev->irq;
3290 del_timer_sync(&np->timer);
3293 spin_lock_irq(&np->lock);
3295 natsemi_irq_disable(dev);
3297 natsemi_stop_rxtx(dev);
3298 netif_stop_queue(dev);
3300 spin_unlock_irq(&np->lock);
3303 napi_disable(&np->napi);
3305 /* Update the error counts. */
3308 /* pci_power_off(pdev, -1); */
3311 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3312 /* Restore PME enable bit */
3314 /* restart the NIC in WOL mode.
3315 * The nic must be stopped for this.
3316 * FIXME: use the WOL interrupt
3318 enable_wol_mode(dev, 0);
3320 /* Restore PME enable bit unmolested */
3321 writel(np->SavedClkRun, ioaddr + ClkRun);
3325 netif_device_detach(dev);
3331 static int natsemi_resume (struct pci_dev *pdev)
3333 struct net_device *dev = pci_get_drvdata (pdev);
3334 struct netdev_private *np = netdev_priv(dev);
3338 if (netif_device_present(dev))
3340 if (netif_running(dev)) {
3341 const int irq = np->pci_dev->irq;
3343 BUG_ON(!np->hands_off);
3344 ret = pci_enable_device(pdev);
3347 "pci_enable_device() failed: %d\n", ret);
3350 /* pci_power_on(pdev); */
3352 napi_enable(&np->napi);
3357 spin_lock_irq(&np->lock);
3359 init_registers(dev);
3360 netif_device_attach(dev);
3361 spin_unlock_irq(&np->lock);
3364 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
3366 netif_device_attach(dev);
3372 #endif /* CONFIG_PM */
3374 static struct pci_driver natsemi_driver = {
3376 .id_table = natsemi_pci_tbl,
3377 .probe = natsemi_probe1,
3378 .remove = natsemi_remove1,
3380 .suspend = natsemi_suspend,
3381 .resume = natsemi_resume,
3385 static int __init natsemi_init_mod (void)
3387 /* when a module, this is printed whether or not devices are found in probe */
3392 return pci_register_driver(&natsemi_driver);
3395 static void __exit natsemi_exit_mod (void)
3397 pci_unregister_driver (&natsemi_driver);
3400 module_init(natsemi_init_mod);
3401 module_exit(natsemi_exit_mod);