1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
27 * big endian support with CFG:BEM instead of cpu_to_le32
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/rtnetlink.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/bitops.h>
50 #include <linux/prefetch.h>
51 #include <asm/processor.h> /* Processor type for cache alignment. */
54 #include <linux/uaccess.h>
56 #define DRV_NAME "natsemi"
57 #define DRV_VERSION "2.1"
58 #define DRV_RELDATE "Sept 11, 2006"
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78 static const int multicast_filter_limit = 100;
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82 static int rx_copybreak;
84 static int dspcfg_workaround = 1;
86 /* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
89 The media type is usually passed in 'options[]'.
91 #define MAX_UNITS 8 /* More are supported, limit only on options */
92 static int options[MAX_UNITS];
93 static int full_duplex[MAX_UNITS];
95 /* Operational parameters that are set at compile time. */
97 /* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102 #define TX_RING_SIZE 16
103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104 #define RX_RING_SIZE 32
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
110 #define NATSEMI_HW_TIMEOUT 400
111 #define NATSEMI_TIMER_FREQ 5*HZ
112 #define NATSEMI_PG0_NREGS 64
113 #define NATSEMI_RFDR_NREGS 8
114 #define NATSEMI_PG1_NREGS 4
115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
129 /* These identify the driver base version and may not be removed. */
130 static const char version[] =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138 MODULE_LICENSE("GPL");
140 module_param(mtu, int, 0);
141 module_param(debug, int, 0);
142 module_param(rx_copybreak, int, 0);
143 module_param(dspcfg_workaround, int, 0);
144 module_param_array(options, int, NULL, 0);
145 module_param_array(full_duplex, int, NULL, 0);
146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147 MODULE_PARM_DESC(debug, "DP8381x default debug level");
148 MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151 MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
158 I. Board Compatibility
160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161 It also works with other chips in in the DP83810 series.
163 II. Board-specific settings
165 This driver requires the PCI interrupt line to be valid.
166 It honors the EEPROM-set values.
168 III. Driver operation
172 This driver uses two statically allocated fixed-size descriptor lists
173 formed into rings by a branch from the final descriptor to the beginning of
174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175 The NatSemi design uses a 'next descriptor' pointer that the driver forms
178 IIIb/c. Transmit/Receive Structure
180 This driver uses a zero-copy receive and transmit scheme.
181 The driver allocates full frame size skbuffs for the Rx ring buffers at
182 open() time and passes the skb->data field to the chip as receive data
183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184 a fresh skbuff is allocated and the frame is copied to the new skbuff.
185 When the incoming frame is larger, the skbuff is passed directly up the
186 protocol stack. Buffers consumed this way are replaced by newly allocated
187 skbuffs in a later phase of receives.
189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190 using a full-sized skbuff for small frames vs. the copying costs of larger
191 frames. New boards are typically used in generously configured machines
192 and the underfilled buffers have negligible impact compared to the benefit of
193 a single allocation size, so the default value of zero results in never
194 copying packets. When copying is done, the cost is usually mitigated by using
195 a combined copy/checksum routine. Copying also preloads the cache, which is
196 most useful with small frames.
198 A subtle aspect of the operation is that unaligned buffers are not permitted
199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200 longword aligned for further processing. On copies frames are put into the
201 skbuff at an offset of "+2", 16-byte aligning the IP header.
203 IIId. Synchronization
205 Most operations are synchronized on the np->lock irq spinlock, except the
206 receive and transmit paths which are synchronised using a combination of
207 hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
211 http://www.scyld.com/expert/100mbps.html
212 http://www.scyld.com/expert/NWay.html
213 Datasheet is available from:
214 http://www.national.com/pf/DP/DP83815.html
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
228 #define PHYID_AM79C874 0x0022561b
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
240 /* array of board data directly indexed by pci_tbl[x].driver_data */
244 unsigned int eeprom_size;
245 } natsemi_pci_info[] = {
246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
247 { "NatSemi DP8381[56]", 0, 24 },
250 static const struct pci_device_id natsemi_pci_tbl[] = {
251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
253 { } /* terminate list */
255 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
257 /* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
262 enum register_offsets {
270 IntrHoldoff = 0x1C, /* DP83816 only */
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
305 /* the values for the 'magic' registers above (PGSEL=1) */
306 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307 #define TSTDAT_VAL 0x0
308 #define DSPCFG_VAL 0x5040
309 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
314 /* misc PCI space registers */
315 enum pci_register_offsets {
329 enum ChipConfig_bits {
333 CfgAnegEnable = 0x2000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
345 EE_ChipSelect = 0x08,
352 enum PCIBusCfg_bits {
356 /* Bits in the interrupt status/mask registers. */
357 enum IntrStatus_bits {
361 IntrRxEarly = 0x0008,
363 IntrRxOverrun = 0x0020,
368 IntrTxUnderrun = 0x0400,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
390 #define DEFAULT_INTR 0x00f1cd65
395 TxMxdmaMask = 0x700000,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
422 #define TX_FLTH_VAL ((512/32) << 8)
423 #define TX_DRTH_VAL_START (64/32)
424 #define TX_DRTH_VAL_INC 2
425 #define TX_DRTH_VAL_LIMIT (1472/32)
429 RxMxdmaMask = 0x700000,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
443 #define RX_DRTH_VAL (128/8)
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
476 enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
486 enum StatsCtrl_bits {
493 enum MIntrCtrl_bits {
501 #define PHY_ADDR_NONE 32
502 #define PHY_ADDR_INTERNAL 1
504 /* values we might find in the silicon revision register */
505 #define SRR_DP83815_C 0x0302
506 #define SRR_DP83815_D 0x0403
507 #define SRR_DP83816_A4 0x0504
508 #define SRR_DP83816_A5 0x0505
510 /* The Rx and Tx buffer descriptors. */
511 /* Note that using only 32 bit fields simplifies conversion to big-endian
520 /* Bits in network_desc.status */
521 enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
538 struct netdev_private {
539 /* Descriptor rings first for alignment */
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
549 struct net_device *dev;
550 void __iomem *ioaddr;
551 struct napi_struct napi;
552 /* Media monitoring timer */
553 struct timer_list timer;
554 /* Frequently used values: keep some adjacent for cache effect */
555 struct pci_dev *pci_dev;
556 struct netdev_desc *rx_head_desc;
557 /* Producer/consumer ring indices */
558 unsigned int cur_rx, dirty_rx;
559 unsigned int cur_tx, dirty_tx;
560 /* Based on MTU+slack. */
561 unsigned int rx_buf_sz;
563 /* Interrupt status */
565 /* Do not touch the nic registers */
567 /* Don't pay attention to the reported link state. */
569 /* external phy that is used: only valid if dev->if_port != PORT_TP */
571 int phy_addr_external;
572 unsigned int full_duplex;
576 /* FIFO and PCI burst thresholds */
577 u32 tx_config, rx_config;
578 /* original contents of ClkRun register */
580 /* silicon revision */
582 /* expected DSPCFG value */
584 int dspcfg_workaround;
585 /* parms saved in ethtool format */
586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
587 u8 duplex; /* Duplex, half or full */
588 u8 autoneg; /* Autonegotiation enabled */
589 /* MII transceiver section */
598 static void move_int_phy(struct net_device *dev, int addr);
599 static int eeprom_read(void __iomem *ioaddr, int location);
600 static int mdio_read(struct net_device *dev, int reg);
601 static void mdio_write(struct net_device *dev, int reg, u16 data);
602 static void init_phy_fixup(struct net_device *dev);
603 static int miiport_read(struct net_device *dev, int phy_id, int reg);
604 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
605 static int find_mii(struct net_device *dev);
606 static void natsemi_reset(struct net_device *dev);
607 static void natsemi_reload_eeprom(struct net_device *dev);
608 static void natsemi_stop_rxtx(struct net_device *dev);
609 static int netdev_open(struct net_device *dev);
610 static void do_cable_magic(struct net_device *dev);
611 static void undo_cable_magic(struct net_device *dev);
612 static void check_link(struct net_device *dev);
613 static void netdev_timer(unsigned long data);
614 static void dump_ring(struct net_device *dev);
615 static void ns_tx_timeout(struct net_device *dev);
616 static int alloc_ring(struct net_device *dev);
617 static void refill_rx(struct net_device *dev);
618 static void init_ring(struct net_device *dev);
619 static void drain_tx(struct net_device *dev);
620 static void drain_ring(struct net_device *dev);
621 static void free_ring(struct net_device *dev);
622 static void reinit_ring(struct net_device *dev);
623 static void init_registers(struct net_device *dev);
624 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
625 static irqreturn_t intr_handler(int irq, void *dev_instance);
626 static void netdev_error(struct net_device *dev, int intr_status);
627 static int natsemi_poll(struct napi_struct *napi, int budget);
628 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
629 static void netdev_tx_done(struct net_device *dev);
630 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
631 #ifdef CONFIG_NET_POLL_CONTROLLER
632 static void natsemi_poll_controller(struct net_device *dev);
634 static void __set_rx_mode(struct net_device *dev);
635 static void set_rx_mode(struct net_device *dev);
636 static void __get_stats(struct net_device *dev);
637 static struct net_device_stats *get_stats(struct net_device *dev);
638 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
639 static int netdev_set_wol(struct net_device *dev, u32 newval);
640 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
641 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
642 static int netdev_get_sopass(struct net_device *dev, u8 *data);
643 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
644 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
645 static void enable_wol_mode(struct net_device *dev, int enable_intr);
646 static int netdev_close(struct net_device *dev);
647 static int netdev_get_regs(struct net_device *dev, u8 *buf);
648 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
649 static const struct ethtool_ops ethtool_ops;
651 #define NATSEMI_ATTR(_name) \
652 static ssize_t natsemi_show_##_name(struct device *dev, \
653 struct device_attribute *attr, char *buf); \
654 static ssize_t natsemi_set_##_name(struct device *dev, \
655 struct device_attribute *attr, \
656 const char *buf, size_t count); \
657 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
659 #define NATSEMI_CREATE_FILE(_dev, _name) \
660 device_create_file(&_dev->dev, &dev_attr_##_name)
661 #define NATSEMI_REMOVE_FILE(_dev, _name) \
662 device_remove_file(&_dev->dev, &dev_attr_##_name)
664 NATSEMI_ATTR(dspcfg_workaround);
666 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
667 struct device_attribute *attr,
670 struct netdev_private *np = netdev_priv(to_net_dev(dev));
672 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
675 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
676 struct device_attribute *attr,
677 const char *buf, size_t count)
679 struct netdev_private *np = netdev_priv(to_net_dev(dev));
683 /* Find out the new setting */
684 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
686 else if (!strncmp("off", buf, count - 1) ||
687 !strncmp("0", buf, count - 1))
692 spin_lock_irqsave(&np->lock, flags);
694 np->dspcfg_workaround = new_setting;
696 spin_unlock_irqrestore(&np->lock, flags);
701 static inline void __iomem *ns_ioaddr(struct net_device *dev)
703 struct netdev_private *np = netdev_priv(dev);
708 static inline void natsemi_irq_enable(struct net_device *dev)
710 writel(1, ns_ioaddr(dev) + IntrEnable);
711 readl(ns_ioaddr(dev) + IntrEnable);
714 static inline void natsemi_irq_disable(struct net_device *dev)
716 writel(0, ns_ioaddr(dev) + IntrEnable);
717 readl(ns_ioaddr(dev) + IntrEnable);
720 static void move_int_phy(struct net_device *dev, int addr)
722 struct netdev_private *np = netdev_priv(dev);
723 void __iomem *ioaddr = ns_ioaddr(dev);
727 * The internal phy is visible on the external mii bus. Therefore we must
728 * move it away before we can send commands to an external phy.
729 * There are two addresses we must avoid:
730 * - the address on the external phy that is used for transmission.
731 * - the address that we want to access. User space can access phys
732 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the
733 * phy that is used for transmission.
738 if (target == np->phy_addr_external)
740 writew(target, ioaddr + PhyCtrl);
741 readw(ioaddr + PhyCtrl);
745 static void natsemi_init_media(struct net_device *dev)
747 struct netdev_private *np = netdev_priv(dev);
751 netif_carrier_on(dev);
753 netif_carrier_off(dev);
755 /* get the initial settings from hardware */
756 tmp = mdio_read(dev, MII_BMCR);
757 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
758 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
759 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
760 np->advertising= mdio_read(dev, MII_ADVERTISE);
762 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
763 netif_msg_probe(np)) {
764 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
766 pci_name(np->pci_dev),
767 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
768 "enabled, advertise" : "disabled, force",
770 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
773 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
776 if (netif_msg_probe(np))
778 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
779 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
784 static const struct net_device_ops natsemi_netdev_ops = {
785 .ndo_open = netdev_open,
786 .ndo_stop = netdev_close,
787 .ndo_start_xmit = start_tx,
788 .ndo_get_stats = get_stats,
789 .ndo_set_rx_mode = set_rx_mode,
790 .ndo_change_mtu = natsemi_change_mtu,
791 .ndo_do_ioctl = netdev_ioctl,
792 .ndo_tx_timeout = ns_tx_timeout,
793 .ndo_set_mac_address = eth_mac_addr,
794 .ndo_validate_addr = eth_validate_addr,
795 #ifdef CONFIG_NET_POLL_CONTROLLER
796 .ndo_poll_controller = natsemi_poll_controller,
800 static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
802 struct net_device *dev;
803 struct netdev_private *np;
804 int i, option, irq, chip_idx = ent->driver_data;
805 static int find_cnt = -1;
806 resource_size_t iostart;
807 unsigned long iosize;
808 void __iomem *ioaddr;
809 const int pcibar = 1; /* PCI base address register */
813 /* when built into the kernel, we only print version if device is found */
815 static int printed_version;
816 if (!printed_version++)
820 i = pci_enable_device(pdev);
823 /* natsemi has a non-standard PM control register
824 * in PCI config space. Some boards apparently need
825 * to be brought to D0 in this manner.
827 pci_read_config_dword(pdev, PCIPM, &tmp);
828 if (tmp & PCI_PM_CTRL_STATE_MASK) {
829 /* D0 state, disable PME assertion */
830 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
831 pci_write_config_dword(pdev, PCIPM, newtmp);
835 iostart = pci_resource_start(pdev, pcibar);
836 iosize = pci_resource_len(pdev, pcibar);
839 pci_set_master(pdev);
841 dev = alloc_etherdev(sizeof (struct netdev_private));
844 SET_NETDEV_DEV(dev, &pdev->dev);
846 i = pci_request_regions(pdev, DRV_NAME);
848 goto err_pci_request_regions;
850 ioaddr = ioremap(iostart, iosize);
856 /* Work around the dropped serial bit. */
857 prev_eedata = eeprom_read(ioaddr, 6);
858 for (i = 0; i < 3; i++) {
859 int eedata = eeprom_read(ioaddr, i + 7);
860 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
861 dev->dev_addr[i*2+1] = eedata >> 7;
862 prev_eedata = eedata;
865 np = netdev_priv(dev);
868 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
872 pci_set_drvdata(pdev, dev);
874 spin_lock_init(&np->lock);
875 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
878 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
879 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
883 np->dspcfg_workaround = dspcfg_workaround;
886 * - If configured to ignore the PHY set up for external.
887 * - If the nic was configured to use an external phy and if find_mii
888 * finds a phy: use external port, first phy that replies.
889 * - Otherwise: internal port.
890 * Note that the phy address for the internal phy doesn't matter:
891 * The address would be used to access a phy over the mii bus, but
892 * the internal phy is accessed through mapped registers.
894 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
895 dev->if_port = PORT_MII;
897 dev->if_port = PORT_TP;
898 /* Reset the chip to erase previous misconfiguration. */
899 natsemi_reload_eeprom(dev);
902 if (dev->if_port != PORT_TP) {
903 np->phy_addr_external = find_mii(dev);
904 /* If we're ignoring the PHY it doesn't matter if we can't
906 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
907 dev->if_port = PORT_TP;
908 np->phy_addr_external = PHY_ADDR_INTERNAL;
911 np->phy_addr_external = PHY_ADDR_INTERNAL;
914 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
915 /* The lower four bits are the media type. */
921 "natsemi %s: ignoring user supplied media type %d",
922 pci_name(np->pci_dev), option & 15);
924 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
927 dev->netdev_ops = &natsemi_netdev_ops;
928 dev->watchdog_timeo = TX_TIMEOUT;
930 dev->ethtool_ops = ðtool_ops;
932 /* MTU range: 64 - 2024 */
933 dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
934 dev->max_mtu = NATSEMI_RX_LIMIT - NATSEMI_HEADERS;
939 natsemi_init_media(dev);
941 /* save the silicon revision for later querying */
942 np->srr = readl(ioaddr + SiliconRev);
943 if (netif_msg_hw(np))
944 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
945 pci_name(np->pci_dev), np->srr);
947 i = register_netdev(dev);
949 goto err_register_netdev;
950 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround);
952 goto err_create_file;
954 if (netif_msg_drv(np)) {
955 printk(KERN_INFO "natsemi %s: %s at %#08llx "
957 dev->name, natsemi_pci_info[chip_idx].name,
958 (unsigned long long)iostart, pci_name(np->pci_dev),
960 if (dev->if_port == PORT_TP)
961 printk(", port TP.\n");
962 else if (np->ignore_phy)
963 printk(", port MII, ignoring PHY\n");
965 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
970 unregister_netdev(dev);
976 pci_release_regions(pdev);
978 err_pci_request_regions:
984 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
985 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
987 /* Delay between EEPROM clock transitions.
988 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
989 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
990 made udelay() unreliable.
991 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
994 #define eeprom_delay(ee_addr) readl(ee_addr)
996 #define EE_Write0 (EE_ChipSelect)
997 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
999 /* The EEPROM commands include the alway-set leading bit. */
1001 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1004 static int eeprom_read(void __iomem *addr, int location)
1008 void __iomem *ee_addr = addr + EECtrl;
1009 int read_cmd = location | EE_ReadCmd;
1011 writel(EE_Write0, ee_addr);
1013 /* Shift the read command bits out. */
1014 for (i = 10; i >= 0; i--) {
1015 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1016 writel(dataval, ee_addr);
1017 eeprom_delay(ee_addr);
1018 writel(dataval | EE_ShiftClk, ee_addr);
1019 eeprom_delay(ee_addr);
1021 writel(EE_ChipSelect, ee_addr);
1022 eeprom_delay(ee_addr);
1024 for (i = 0; i < 16; i++) {
1025 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1026 eeprom_delay(ee_addr);
1027 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1028 writel(EE_ChipSelect, ee_addr);
1029 eeprom_delay(ee_addr);
1032 /* Terminate the EEPROM access. */
1033 writel(EE_Write0, ee_addr);
1038 /* MII transceiver control section.
1039 * The 83815 series has an internal transceiver, and we present the
1040 * internal management registers as if they were MII connected.
1041 * External Phy registers are referenced through the MII interface.
1044 /* clock transitions >= 20ns (25MHz)
1045 * One readl should be good to PCI @ 100MHz
1047 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1049 static int mii_getbit (struct net_device *dev)
1052 void __iomem *ioaddr = ns_ioaddr(dev);
1054 writel(MII_ShiftClk, ioaddr + EECtrl);
1055 data = readl(ioaddr + EECtrl);
1056 writel(0, ioaddr + EECtrl);
1058 return (data & MII_Data)? 1 : 0;
1061 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1064 void __iomem *ioaddr = ns_ioaddr(dev);
1066 for (i = (1 << (len-1)); i; i >>= 1)
1068 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1069 writel(mdio_val, ioaddr + EECtrl);
1071 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1074 writel(0, ioaddr + EECtrl);
1078 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1085 mii_send_bits (dev, 0xffffffff, 32);
1086 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1087 /* ST,OP = 0110'b for read operation */
1088 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1089 mii_send_bits (dev, cmd, 14);
1091 if (mii_getbit (dev))
1094 for (i = 0; i < 16; i++) {
1096 retval |= mii_getbit (dev);
1103 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1108 mii_send_bits (dev, 0xffffffff, 32);
1109 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1110 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1111 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1112 mii_send_bits (dev, cmd, 32);
1117 static int mdio_read(struct net_device *dev, int reg)
1119 struct netdev_private *np = netdev_priv(dev);
1120 void __iomem *ioaddr = ns_ioaddr(dev);
1122 /* The 83815 series has two ports:
1123 * - an internal transceiver
1124 * - an external mii bus
1126 if (dev->if_port == PORT_TP)
1127 return readw(ioaddr+BasicControl+(reg<<2));
1129 return miiport_read(dev, np->phy_addr_external, reg);
1132 static void mdio_write(struct net_device *dev, int reg, u16 data)
1134 struct netdev_private *np = netdev_priv(dev);
1135 void __iomem *ioaddr = ns_ioaddr(dev);
1137 /* The 83815 series has an internal transceiver; handle separately */
1138 if (dev->if_port == PORT_TP)
1139 writew(data, ioaddr+BasicControl+(reg<<2));
1141 miiport_write(dev, np->phy_addr_external, reg, data);
1144 static void init_phy_fixup(struct net_device *dev)
1146 struct netdev_private *np = netdev_priv(dev);
1147 void __iomem *ioaddr = ns_ioaddr(dev);
1152 /* restore stuff lost when power was out */
1153 tmp = mdio_read(dev, MII_BMCR);
1154 if (np->autoneg == AUTONEG_ENABLE) {
1155 /* renegotiate if something changed */
1156 if ((tmp & BMCR_ANENABLE) == 0 ||
1157 np->advertising != mdio_read(dev, MII_ADVERTISE))
1159 /* turn on autonegotiation and force negotiation */
1160 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1161 mdio_write(dev, MII_ADVERTISE, np->advertising);
1164 /* turn off auto negotiation, set speed and duplexity */
1165 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1166 if (np->speed == SPEED_100)
1167 tmp |= BMCR_SPEED100;
1168 if (np->duplex == DUPLEX_FULL)
1169 tmp |= BMCR_FULLDPLX;
1171 * Note: there is no good way to inform the link partner
1172 * that our capabilities changed. The user has to unplug
1173 * and replug the network cable after some changes, e.g.
1174 * after switching from 10HD, autoneg off to 100 HD,
1178 mdio_write(dev, MII_BMCR, tmp);
1179 readl(ioaddr + ChipConfig);
1182 /* find out what phy this is */
1183 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1184 + mdio_read(dev, MII_PHYSID2);
1186 /* handle external phys here */
1188 case PHYID_AM79C874:
1189 /* phy specific configuration for fibre/tp operation */
1190 tmp = mdio_read(dev, MII_MCTRL);
1191 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1192 if (dev->if_port == PORT_FIBRE)
1196 mdio_write(dev, MII_MCTRL, tmp);
1201 cfg = readl(ioaddr + ChipConfig);
1202 if (cfg & CfgExtPhy)
1205 /* On page 78 of the spec, they recommend some settings for "optimum
1206 performance" to be done in sequence. These settings optimize some
1207 of the 100Mbit autodetection circuitry. They say we only want to
1208 do this for rev C of the chip, but engineers at NSC (Bradley
1209 Kennedy) recommends always setting them. If you don't, you get
1210 errors on some autonegotiations that make the device unusable.
1212 It seems that the DSP needs a few usec to reinitialize after
1213 the start of the phy. Just retry writing these values until they
1216 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1219 writew(1, ioaddr + PGSEL);
1220 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1221 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1222 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1223 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1224 writew(np->dspcfg, ioaddr + DSPCFG);
1225 writew(SDCFG_VAL, ioaddr + SDCFG);
1226 writew(0, ioaddr + PGSEL);
1227 readl(ioaddr + ChipConfig);
1230 writew(1, ioaddr + PGSEL);
1231 dspcfg = readw(ioaddr + DSPCFG);
1232 writew(0, ioaddr + PGSEL);
1233 if (np->dspcfg == dspcfg)
1237 if (netif_msg_link(np)) {
1238 if (i==NATSEMI_HW_TIMEOUT) {
1240 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1244 "%s: DSPCFG accepted after %d usec.\n",
1249 * Enable PHY Specific event based interrupts. Link state change
1250 * and Auto-Negotiation Completion are among the affected.
1251 * Read the intr status to clear it (needed for wake events).
1253 readw(ioaddr + MIntrStatus);
1254 writew(MICRIntEn, ioaddr + MIntrCtrl);
1257 static int switch_port_external(struct net_device *dev)
1259 struct netdev_private *np = netdev_priv(dev);
1260 void __iomem *ioaddr = ns_ioaddr(dev);
1263 cfg = readl(ioaddr + ChipConfig);
1264 if (cfg & CfgExtPhy)
1267 if (netif_msg_link(np)) {
1268 printk(KERN_INFO "%s: switching to external transceiver.\n",
1272 /* 1) switch back to external phy */
1273 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1274 readl(ioaddr + ChipConfig);
1277 /* 2) reset the external phy: */
1278 /* resetting the external PHY has been known to cause a hub supplying
1279 * power over Ethernet to kill the power. We don't want to kill
1280 * power to this computer, so we avoid resetting the phy.
1283 /* 3) reinit the phy fixup, it got lost during power down. */
1284 move_int_phy(dev, np->phy_addr_external);
1285 init_phy_fixup(dev);
1290 static int switch_port_internal(struct net_device *dev)
1292 struct netdev_private *np = netdev_priv(dev);
1293 void __iomem *ioaddr = ns_ioaddr(dev);
1298 cfg = readl(ioaddr + ChipConfig);
1299 if (!(cfg &CfgExtPhy))
1302 if (netif_msg_link(np)) {
1303 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1306 /* 1) switch back to internal phy: */
1307 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1308 writel(cfg, ioaddr + ChipConfig);
1309 readl(ioaddr + ChipConfig);
1312 /* 2) reset the internal phy: */
1313 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1314 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1315 readl(ioaddr + ChipConfig);
1317 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1318 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1319 if (!(bmcr & BMCR_RESET))
1323 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1325 "%s: phy reset did not complete in %d usec.\n",
1328 /* 3) reinit the phy fixup, it got lost during power down. */
1329 init_phy_fixup(dev);
1334 /* Scan for a PHY on the external mii bus.
1335 * There are two tricky points:
1336 * - Do not scan while the internal phy is enabled. The internal phy will
1337 * crash: e.g. reads from the DSPCFG register will return odd values and
1338 * the nasty random phy reset code will reset the nic every few seconds.
1339 * - The internal phy must be moved around, an external phy could
1340 * have the same address as the internal phy.
1342 static int find_mii(struct net_device *dev)
1344 struct netdev_private *np = netdev_priv(dev);
1349 /* Switch to external phy */
1350 did_switch = switch_port_external(dev);
1352 /* Scan the possible phy addresses:
1354 * PHY address 0 means that the phy is in isolate mode. Not yet
1355 * supported due to lack of test hardware. User space should
1356 * handle it through ethtool.
1358 for (i = 1; i <= 31; i++) {
1359 move_int_phy(dev, i);
1360 tmp = miiport_read(dev, i, MII_BMSR);
1361 if (tmp != 0xffff && tmp != 0x0000) {
1362 /* found something! */
1363 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1364 + mdio_read(dev, MII_PHYSID2);
1365 if (netif_msg_probe(np)) {
1366 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1367 pci_name(np->pci_dev), np->mii, i);
1372 /* And switch back to internal phy: */
1374 switch_port_internal(dev);
1378 /* CFG bits [13:16] [18:23] */
1379 #define CFG_RESET_SAVE 0xfde000
1380 /* WCSR bits [0:4] [9:10] */
1381 #define WCSR_RESET_SAVE 0x61f
1382 /* RFCR bits [20] [22] [27:31] */
1383 #define RFCR_RESET_SAVE 0xf8500000
1385 static void natsemi_reset(struct net_device *dev)
1393 struct netdev_private *np = netdev_priv(dev);
1394 void __iomem *ioaddr = ns_ioaddr(dev);
1397 * Resetting the chip causes some registers to be lost.
1398 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1399 * we save the state that would have been loaded from EEPROM
1400 * on a normal power-up (see the spec EEPROM map). This assumes
1401 * whoever calls this will follow up with init_registers() eventually.
1405 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1407 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1409 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1411 for (i = 0; i < 3; i++) {
1412 writel(i*2, ioaddr + RxFilterAddr);
1413 pmatch[i] = readw(ioaddr + RxFilterData);
1416 for (i = 0; i < 3; i++) {
1417 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1418 sopass[i] = readw(ioaddr + RxFilterData);
1421 /* now whack the chip */
1422 writel(ChipReset, ioaddr + ChipCmd);
1423 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1424 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1428 if (i==NATSEMI_HW_TIMEOUT) {
1429 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1431 } else if (netif_msg_hw(np)) {
1432 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1437 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1438 /* turn on external phy if it was selected */
1439 if (dev->if_port == PORT_TP)
1440 cfg &= ~(CfgExtPhy | CfgPhyDis);
1442 cfg |= (CfgExtPhy | CfgPhyDis);
1443 writel(cfg, ioaddr + ChipConfig);
1445 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1446 writel(wcsr, ioaddr + WOLCmd);
1448 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1449 /* restore PMATCH */
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 writew(pmatch[i], ioaddr + RxFilterData);
1454 for (i = 0; i < 3; i++) {
1455 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1456 writew(sopass[i], ioaddr + RxFilterData);
1459 writel(rfcr, ioaddr + RxFilterAddr);
1462 static void reset_rx(struct net_device *dev)
1465 struct netdev_private *np = netdev_priv(dev);
1466 void __iomem *ioaddr = ns_ioaddr(dev);
1468 np->intr_status &= ~RxResetDone;
1470 writel(RxReset, ioaddr + ChipCmd);
1472 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1473 np->intr_status |= readl(ioaddr + IntrStatus);
1474 if (np->intr_status & RxResetDone)
1478 if (i==NATSEMI_HW_TIMEOUT) {
1479 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1481 } else if (netif_msg_hw(np)) {
1482 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1487 static void natsemi_reload_eeprom(struct net_device *dev)
1489 struct netdev_private *np = netdev_priv(dev);
1490 void __iomem *ioaddr = ns_ioaddr(dev);
1493 writel(EepromReload, ioaddr + PCIBusCfg);
1494 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1496 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1499 if (i==NATSEMI_HW_TIMEOUT) {
1500 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1501 pci_name(np->pci_dev), i*50);
1502 } else if (netif_msg_hw(np)) {
1503 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1504 pci_name(np->pci_dev), i*50);
1508 static void natsemi_stop_rxtx(struct net_device *dev)
1510 void __iomem * ioaddr = ns_ioaddr(dev);
1511 struct netdev_private *np = netdev_priv(dev);
1514 writel(RxOff | TxOff, ioaddr + ChipCmd);
1515 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1516 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1520 if (i==NATSEMI_HW_TIMEOUT) {
1521 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1523 } else if (netif_msg_hw(np)) {
1524 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1529 static int netdev_open(struct net_device *dev)
1531 struct netdev_private *np = netdev_priv(dev);
1532 void __iomem * ioaddr = ns_ioaddr(dev);
1533 const int irq = np->pci_dev->irq;
1536 /* Reset the chip, just in case. */
1539 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
1542 if (netif_msg_ifup(np))
1543 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1545 i = alloc_ring(dev);
1550 napi_enable(&np->napi);
1553 spin_lock_irq(&np->lock);
1554 init_registers(dev);
1555 /* now set the MAC address according to dev->dev_addr */
1556 for (i = 0; i < 3; i++) {
1557 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1559 writel(i*2, ioaddr + RxFilterAddr);
1560 writew(mac, ioaddr + RxFilterData);
1562 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1563 spin_unlock_irq(&np->lock);
1565 netif_start_queue(dev);
1567 if (netif_msg_ifup(np))
1568 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1569 dev->name, (int)readl(ioaddr + ChipCmd));
1571 /* Set the timer to check for link beat. */
1572 init_timer(&np->timer);
1573 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1574 np->timer.data = (unsigned long)dev;
1575 np->timer.function = netdev_timer; /* timer handler */
1576 add_timer(&np->timer);
1581 static void do_cable_magic(struct net_device *dev)
1583 struct netdev_private *np = netdev_priv(dev);
1584 void __iomem *ioaddr = ns_ioaddr(dev);
1586 if (dev->if_port != PORT_TP)
1589 if (np->srr >= SRR_DP83816_A5)
1593 * 100 MBit links with short cables can trip an issue with the chip.
1594 * The problem manifests as lots of CRC errors and/or flickering
1595 * activity LED while idle. This process is based on instructions
1596 * from engineers at National.
1598 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1601 writew(1, ioaddr + PGSEL);
1603 * coefficient visibility should already be enabled via
1606 data = readw(ioaddr + TSTDAT) & 0xff;
1608 * the value must be negative, and within certain values
1609 * (these values all come from National)
1611 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1612 np = netdev_priv(dev);
1614 /* the bug has been triggered - fix the coefficient */
1615 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1616 /* lock the value */
1617 data = readw(ioaddr + DSPCFG);
1618 np->dspcfg = data | DSPCFG_LOCK;
1619 writew(np->dspcfg, ioaddr + DSPCFG);
1621 writew(0, ioaddr + PGSEL);
1625 static void undo_cable_magic(struct net_device *dev)
1628 struct netdev_private *np = netdev_priv(dev);
1629 void __iomem * ioaddr = ns_ioaddr(dev);
1631 if (dev->if_port != PORT_TP)
1634 if (np->srr >= SRR_DP83816_A5)
1637 writew(1, ioaddr + PGSEL);
1638 /* make sure the lock bit is clear */
1639 data = readw(ioaddr + DSPCFG);
1640 np->dspcfg = data & ~DSPCFG_LOCK;
1641 writew(np->dspcfg, ioaddr + DSPCFG);
1642 writew(0, ioaddr + PGSEL);
1645 static void check_link(struct net_device *dev)
1647 struct netdev_private *np = netdev_priv(dev);
1648 void __iomem * ioaddr = ns_ioaddr(dev);
1649 int duplex = np->duplex;
1652 /* If we are ignoring the PHY then don't try reading it. */
1654 goto propagate_state;
1656 /* The link status field is latched: it remains low after a temporary
1657 * link failure until it's read. We need the current link status,
1660 mdio_read(dev, MII_BMSR);
1661 bmsr = mdio_read(dev, MII_BMSR);
1663 if (!(bmsr & BMSR_LSTATUS)) {
1664 if (netif_carrier_ok(dev)) {
1665 if (netif_msg_link(np))
1666 printk(KERN_NOTICE "%s: link down.\n",
1668 netif_carrier_off(dev);
1669 undo_cable_magic(dev);
1673 if (!netif_carrier_ok(dev)) {
1674 if (netif_msg_link(np))
1675 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1676 netif_carrier_on(dev);
1677 do_cable_magic(dev);
1680 duplex = np->full_duplex;
1682 if (bmsr & BMSR_ANEGCOMPLETE) {
1683 int tmp = mii_nway_result(
1684 np->advertising & mdio_read(dev, MII_LPA));
1685 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1687 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1692 /* if duplex is set then bit 28 must be set, too */
1693 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1694 if (netif_msg_link(np))
1696 "%s: Setting %s-duplex based on negotiated "
1697 "link capability.\n", dev->name,
1698 duplex ? "full" : "half");
1700 np->rx_config |= RxAcceptTx;
1701 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1703 np->rx_config &= ~RxAcceptTx;
1704 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1706 writel(np->tx_config, ioaddr + TxConfig);
1707 writel(np->rx_config, ioaddr + RxConfig);
1711 static void init_registers(struct net_device *dev)
1713 struct netdev_private *np = netdev_priv(dev);
1714 void __iomem * ioaddr = ns_ioaddr(dev);
1716 init_phy_fixup(dev);
1718 /* clear any interrupts that are pending, such as wake events */
1719 readl(ioaddr + IntrStatus);
1721 writel(np->ring_dma, ioaddr + RxRingPtr);
1722 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1723 ioaddr + TxRingPtr);
1725 /* Initialize other registers.
1726 * Configure the PCI bus bursts and FIFO thresholds.
1727 * Configure for standard, in-spec Ethernet.
1728 * Start with half-duplex. check_link will update
1729 * to the correct settings.
1732 /* DRTH: 2: start tx if 64 bytes are in the fifo
1733 * FLTH: 0x10: refill with next packet if 512 bytes are free
1734 * MXDMA: 0: up to 256 byte bursts.
1735 * MXDMA must be <= FLTH
1739 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1740 TX_FLTH_VAL | TX_DRTH_VAL_START;
1741 writel(np->tx_config, ioaddr + TxConfig);
1743 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1744 * MXDMA 0: up to 256 byte bursts
1746 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1747 /* if receive ring now has bigger buffers than normal, enable jumbo */
1748 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1749 np->rx_config |= RxAcceptLong;
1751 writel(np->rx_config, ioaddr + RxConfig);
1754 * The PME bit is initialized from the EEPROM contents.
1755 * PCI cards probably have PME disabled, but motherboard
1756 * implementations may have PME set to enable WakeOnLan.
1757 * With PME set the chip will scan incoming packets but
1758 * nothing will be written to memory. */
1759 np->SavedClkRun = readl(ioaddr + ClkRun);
1760 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1761 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1762 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1763 dev->name, readl(ioaddr + WOLCmd));
1769 /* Enable interrupts by setting the interrupt mask. */
1770 writel(DEFAULT_INTR, ioaddr + IntrMask);
1771 natsemi_irq_enable(dev);
1773 writel(RxOn | TxOn, ioaddr + ChipCmd);
1774 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1780 * 1) check for link changes. Usually they are handled by the MII interrupt
1781 * but it doesn't hurt to check twice.
1782 * 2) check for sudden death of the NIC:
1783 * It seems that a reference set for this chip went out with incorrect info,
1784 * and there exist boards that aren't quite right. An unexpected voltage
1785 * drop can cause the PHY to get itself in a weird state (basically reset).
1786 * NOTE: this only seems to affect revC chips. The user can disable
1787 * this check via dspcfg_workaround sysfs option.
1788 * 3) check of death of the RX path due to OOM
1790 static void netdev_timer(unsigned long data)
1792 struct net_device *dev = (struct net_device *)data;
1793 struct netdev_private *np = netdev_priv(dev);
1794 void __iomem * ioaddr = ns_ioaddr(dev);
1795 int next_tick = NATSEMI_TIMER_FREQ;
1796 const int irq = np->pci_dev->irq;
1798 if (netif_msg_timer(np)) {
1799 /* DO NOT read the IntrStatus register,
1800 * a read clears any pending interrupts.
1802 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1806 if (dev->if_port == PORT_TP) {
1809 spin_lock_irq(&np->lock);
1810 /* check for a nasty random phy-reset - use dspcfg as a flag */
1811 writew(1, ioaddr+PGSEL);
1812 dspcfg = readw(ioaddr+DSPCFG);
1813 writew(0, ioaddr+PGSEL);
1814 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1815 if (!netif_queue_stopped(dev)) {
1816 spin_unlock_irq(&np->lock);
1817 if (netif_msg_drv(np))
1818 printk(KERN_NOTICE "%s: possible phy reset: "
1819 "re-initializing\n", dev->name);
1821 spin_lock_irq(&np->lock);
1822 natsemi_stop_rxtx(dev);
1825 init_registers(dev);
1826 spin_unlock_irq(&np->lock);
1831 spin_unlock_irq(&np->lock);
1834 /* init_registers() calls check_link() for the above case */
1836 spin_unlock_irq(&np->lock);
1839 spin_lock_irq(&np->lock);
1841 spin_unlock_irq(&np->lock);
1849 writel(RxOn, ioaddr + ChipCmd);
1856 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1858 mod_timer(&np->timer, jiffies + next_tick);
1861 static void dump_ring(struct net_device *dev)
1863 struct netdev_private *np = netdev_priv(dev);
1865 if (netif_msg_pktdata(np)) {
1867 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1868 for (i = 0; i < TX_RING_SIZE; i++) {
1869 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1870 i, np->tx_ring[i].next_desc,
1871 np->tx_ring[i].cmd_status,
1872 np->tx_ring[i].addr);
1874 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1875 for (i = 0; i < RX_RING_SIZE; i++) {
1876 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1877 i, np->rx_ring[i].next_desc,
1878 np->rx_ring[i].cmd_status,
1879 np->rx_ring[i].addr);
1884 static void ns_tx_timeout(struct net_device *dev)
1886 struct netdev_private *np = netdev_priv(dev);
1887 void __iomem * ioaddr = ns_ioaddr(dev);
1888 const int irq = np->pci_dev->irq;
1891 spin_lock_irq(&np->lock);
1892 if (!np->hands_off) {
1893 if (netif_msg_tx_err(np))
1895 "%s: Transmit timed out, status %#08x,"
1897 dev->name, readl(ioaddr + IntrStatus));
1902 init_registers(dev);
1905 "%s: tx_timeout while in hands_off state?\n",
1908 spin_unlock_irq(&np->lock);
1911 netif_trans_update(dev); /* prevent tx timeout */
1912 dev->stats.tx_errors++;
1913 netif_wake_queue(dev);
1916 static int alloc_ring(struct net_device *dev)
1918 struct netdev_private *np = netdev_priv(dev);
1919 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1920 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1924 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1928 static void refill_rx(struct net_device *dev)
1930 struct netdev_private *np = netdev_priv(dev);
1932 /* Refill the Rx ring buffers. */
1933 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1934 struct sk_buff *skb;
1935 int entry = np->dirty_rx % RX_RING_SIZE;
1936 if (np->rx_skbuff[entry] == NULL) {
1937 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1938 skb = netdev_alloc_skb(dev, buflen);
1939 np->rx_skbuff[entry] = skb;
1941 break; /* Better luck next round. */
1942 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1943 skb->data, buflen, PCI_DMA_FROMDEVICE);
1944 if (pci_dma_mapping_error(np->pci_dev,
1945 np->rx_dma[entry])) {
1946 dev_kfree_skb_any(skb);
1947 np->rx_skbuff[entry] = NULL;
1948 break; /* Better luck next round. */
1950 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1952 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1954 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1955 if (netif_msg_rx_err(np))
1956 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1961 static void set_bufsize(struct net_device *dev)
1963 struct netdev_private *np = netdev_priv(dev);
1964 if (dev->mtu <= ETH_DATA_LEN)
1965 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1967 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1970 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1971 static void init_ring(struct net_device *dev)
1973 struct netdev_private *np = netdev_priv(dev);
1977 np->dirty_tx = np->cur_tx = 0;
1978 for (i = 0; i < TX_RING_SIZE; i++) {
1979 np->tx_skbuff[i] = NULL;
1980 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1981 +sizeof(struct netdev_desc)
1982 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1983 np->tx_ring[i].cmd_status = 0;
1988 np->cur_rx = RX_RING_SIZE;
1992 np->rx_head_desc = &np->rx_ring[0];
1994 /* Please be careful before changing this loop - at least gcc-2.95.1
1995 * miscompiles it otherwise.
1997 /* Initialize all Rx descriptors. */
1998 for (i = 0; i < RX_RING_SIZE; i++) {
1999 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2000 +sizeof(struct netdev_desc)
2001 *((i+1)%RX_RING_SIZE));
2002 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2003 np->rx_skbuff[i] = NULL;
2009 static void drain_tx(struct net_device *dev)
2011 struct netdev_private *np = netdev_priv(dev);
2014 for (i = 0; i < TX_RING_SIZE; i++) {
2015 if (np->tx_skbuff[i]) {
2016 pci_unmap_single(np->pci_dev,
2017 np->tx_dma[i], np->tx_skbuff[i]->len,
2019 dev_kfree_skb(np->tx_skbuff[i]);
2020 dev->stats.tx_dropped++;
2022 np->tx_skbuff[i] = NULL;
2026 static void drain_rx(struct net_device *dev)
2028 struct netdev_private *np = netdev_priv(dev);
2029 unsigned int buflen = np->rx_buf_sz;
2032 /* Free all the skbuffs in the Rx queue. */
2033 for (i = 0; i < RX_RING_SIZE; i++) {
2034 np->rx_ring[i].cmd_status = 0;
2035 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
2036 if (np->rx_skbuff[i]) {
2037 pci_unmap_single(np->pci_dev, np->rx_dma[i],
2038 buflen + NATSEMI_PADDING,
2039 PCI_DMA_FROMDEVICE);
2040 dev_kfree_skb(np->rx_skbuff[i]);
2042 np->rx_skbuff[i] = NULL;
2046 static void drain_ring(struct net_device *dev)
2052 static void free_ring(struct net_device *dev)
2054 struct netdev_private *np = netdev_priv(dev);
2055 pci_free_consistent(np->pci_dev,
2056 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2057 np->rx_ring, np->ring_dma);
2060 static void reinit_rx(struct net_device *dev)
2062 struct netdev_private *np = netdev_priv(dev);
2067 np->cur_rx = RX_RING_SIZE;
2068 np->rx_head_desc = &np->rx_ring[0];
2069 /* Initialize all Rx descriptors. */
2070 for (i = 0; i < RX_RING_SIZE; i++)
2071 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2076 static void reinit_ring(struct net_device *dev)
2078 struct netdev_private *np = netdev_priv(dev);
2083 np->dirty_tx = np->cur_tx = 0;
2084 for (i=0;i<TX_RING_SIZE;i++)
2085 np->tx_ring[i].cmd_status = 0;
2090 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
2092 struct netdev_private *np = netdev_priv(dev);
2093 void __iomem * ioaddr = ns_ioaddr(dev);
2095 unsigned long flags;
2097 /* Note: Ordering is important here, set the field with the
2098 "ownership" bit last, and only then increment cur_tx. */
2100 /* Calculate the next Tx descriptor entry. */
2101 entry = np->cur_tx % TX_RING_SIZE;
2103 np->tx_skbuff[entry] = skb;
2104 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2105 skb->data,skb->len, PCI_DMA_TODEVICE);
2106 if (pci_dma_mapping_error(np->pci_dev, np->tx_dma[entry])) {
2107 np->tx_skbuff[entry] = NULL;
2108 dev_kfree_skb_irq(skb);
2109 dev->stats.tx_dropped++;
2110 return NETDEV_TX_OK;
2113 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2115 spin_lock_irqsave(&np->lock, flags);
2117 if (!np->hands_off) {
2118 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2119 /* StrongARM: Explicitly cache flush np->tx_ring and
2120 * skb->data,skb->len. */
2123 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2124 netdev_tx_done(dev);
2125 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2126 netif_stop_queue(dev);
2128 /* Wake the potentially-idle transmit channel. */
2129 writel(TxOn, ioaddr + ChipCmd);
2131 dev_kfree_skb_irq(skb);
2132 dev->stats.tx_dropped++;
2134 spin_unlock_irqrestore(&np->lock, flags);
2136 if (netif_msg_tx_queued(np)) {
2137 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2138 dev->name, np->cur_tx, entry);
2140 return NETDEV_TX_OK;
2143 static void netdev_tx_done(struct net_device *dev)
2145 struct netdev_private *np = netdev_priv(dev);
2147 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2148 int entry = np->dirty_tx % TX_RING_SIZE;
2149 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2151 if (netif_msg_tx_done(np))
2153 "%s: tx frame #%d finished, status %#08x.\n",
2154 dev->name, np->dirty_tx,
2155 le32_to_cpu(np->tx_ring[entry].cmd_status));
2156 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2157 dev->stats.tx_packets++;
2158 dev->stats.tx_bytes += np->tx_skbuff[entry]->len;
2159 } else { /* Various Tx errors */
2161 le32_to_cpu(np->tx_ring[entry].cmd_status);
2162 if (tx_status & (DescTxAbort|DescTxExcColl))
2163 dev->stats.tx_aborted_errors++;
2164 if (tx_status & DescTxFIFO)
2165 dev->stats.tx_fifo_errors++;
2166 if (tx_status & DescTxCarrier)
2167 dev->stats.tx_carrier_errors++;
2168 if (tx_status & DescTxOOWCol)
2169 dev->stats.tx_window_errors++;
2170 dev->stats.tx_errors++;
2172 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2173 np->tx_skbuff[entry]->len,
2175 /* Free the original skb. */
2176 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2177 np->tx_skbuff[entry] = NULL;
2179 if (netif_queue_stopped(dev) &&
2180 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2181 /* The ring is no longer full, wake queue. */
2182 netif_wake_queue(dev);
2186 /* The interrupt handler doesn't actually handle interrupts itself, it
2187 * schedules a NAPI poll if there is anything to do. */
2188 static irqreturn_t intr_handler(int irq, void *dev_instance)
2190 struct net_device *dev = dev_instance;
2191 struct netdev_private *np = netdev_priv(dev);
2192 void __iomem * ioaddr = ns_ioaddr(dev);
2194 /* Reading IntrStatus automatically acknowledges so don't do
2195 * that while interrupts are disabled, (for example, while a
2196 * poll is scheduled). */
2197 if (np->hands_off || !readl(ioaddr + IntrEnable))
2200 np->intr_status = readl(ioaddr + IntrStatus);
2202 if (!np->intr_status)
2205 if (netif_msg_intr(np))
2207 "%s: Interrupt, status %#08x, mask %#08x.\n",
2208 dev->name, np->intr_status,
2209 readl(ioaddr + IntrMask));
2211 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2213 if (napi_schedule_prep(&np->napi)) {
2214 /* Disable interrupts and register for poll */
2215 natsemi_irq_disable(dev);
2216 __napi_schedule(&np->napi);
2219 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2220 dev->name, np->intr_status,
2221 readl(ioaddr + IntrMask));
2226 /* This is the NAPI poll routine. As well as the standard RX handling
2227 * it also handles all other interrupts that the chip might raise.
2229 static int natsemi_poll(struct napi_struct *napi, int budget)
2231 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2232 struct net_device *dev = np->dev;
2233 void __iomem * ioaddr = ns_ioaddr(dev);
2237 if (netif_msg_intr(np))
2239 "%s: Poll, status %#08x, mask %#08x.\n",
2240 dev->name, np->intr_status,
2241 readl(ioaddr + IntrMask));
2243 /* netdev_rx() may read IntrStatus again if the RX state
2244 * machine falls over so do it first. */
2245 if (np->intr_status &
2246 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2247 IntrRxErr | IntrRxOverrun)) {
2248 netdev_rx(dev, &work_done, budget);
2251 if (np->intr_status &
2252 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2253 spin_lock(&np->lock);
2254 netdev_tx_done(dev);
2255 spin_unlock(&np->lock);
2258 /* Abnormal error summary/uncommon events handlers. */
2259 if (np->intr_status & IntrAbnormalSummary)
2260 netdev_error(dev, np->intr_status);
2262 if (work_done >= budget)
2265 np->intr_status = readl(ioaddr + IntrStatus);
2266 } while (np->intr_status);
2268 napi_complete(napi);
2270 /* Reenable interrupts providing nothing is trying to shut
2272 spin_lock(&np->lock);
2274 natsemi_irq_enable(dev);
2275 spin_unlock(&np->lock);
2280 /* This routine is logically part of the interrupt handler, but separated
2281 for clarity and better register allocation. */
2282 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2284 struct netdev_private *np = netdev_priv(dev);
2285 int entry = np->cur_rx % RX_RING_SIZE;
2286 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2287 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2288 unsigned int buflen = np->rx_buf_sz;
2289 void __iomem * ioaddr = ns_ioaddr(dev);
2291 /* If the driver owns the next entry it's a new packet. Send it up. */
2292 while (desc_status < 0) { /* e.g. & DescOwn */
2294 if (netif_msg_rx_status(np))
2296 " netdev_rx() entry %d status was %#08x.\n",
2297 entry, desc_status);
2301 if (*work_done >= work_to_do)
2306 pkt_len = (desc_status & DescSizeMask) - 4;
2307 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2308 if (desc_status & DescMore) {
2309 unsigned long flags;
2311 if (netif_msg_rx_err(np))
2313 "%s: Oversized(?) Ethernet "
2314 "frame spanned multiple "
2315 "buffers, entry %#08x "
2316 "status %#08x.\n", dev->name,
2317 np->cur_rx, desc_status);
2318 dev->stats.rx_length_errors++;
2320 /* The RX state machine has probably
2321 * locked up beneath us. Follow the
2322 * reset procedure documented in
2325 spin_lock_irqsave(&np->lock, flags);
2328 writel(np->ring_dma, ioaddr + RxRingPtr);
2330 spin_unlock_irqrestore(&np->lock, flags);
2332 /* We'll enable RX on exit from this
2337 /* There was an error. */
2338 dev->stats.rx_errors++;
2339 if (desc_status & (DescRxAbort|DescRxOver))
2340 dev->stats.rx_over_errors++;
2341 if (desc_status & (DescRxLong|DescRxRunt))
2342 dev->stats.rx_length_errors++;
2343 if (desc_status & (DescRxInvalid|DescRxAlign))
2344 dev->stats.rx_frame_errors++;
2345 if (desc_status & DescRxCRC)
2346 dev->stats.rx_crc_errors++;
2348 } else if (pkt_len > np->rx_buf_sz) {
2349 /* if this is the tail of a double buffer
2350 * packet, we've already counted the error
2351 * on the first part. Ignore the second half.
2354 struct sk_buff *skb;
2355 /* Omit CRC size. */
2356 /* Check if the packet is long enough to accept
2357 * without copying to a minimally-sized skbuff. */
2358 if (pkt_len < rx_copybreak &&
2359 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) {
2360 /* 16 byte align the IP header */
2361 skb_reserve(skb, RX_OFFSET);
2362 pci_dma_sync_single_for_cpu(np->pci_dev,
2365 PCI_DMA_FROMDEVICE);
2366 skb_copy_to_linear_data(skb,
2367 np->rx_skbuff[entry]->data, pkt_len);
2368 skb_put(skb, pkt_len);
2369 pci_dma_sync_single_for_device(np->pci_dev,
2372 PCI_DMA_FROMDEVICE);
2374 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2375 buflen + NATSEMI_PADDING,
2376 PCI_DMA_FROMDEVICE);
2377 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2378 np->rx_skbuff[entry] = NULL;
2380 skb->protocol = eth_type_trans(skb, dev);
2381 netif_receive_skb(skb);
2382 dev->stats.rx_packets++;
2383 dev->stats.rx_bytes += pkt_len;
2385 entry = (++np->cur_rx) % RX_RING_SIZE;
2386 np->rx_head_desc = &np->rx_ring[entry];
2387 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2391 /* Restart Rx engine if stopped. */
2393 mod_timer(&np->timer, jiffies + 1);
2395 writel(RxOn, ioaddr + ChipCmd);
2398 static void netdev_error(struct net_device *dev, int intr_status)
2400 struct netdev_private *np = netdev_priv(dev);
2401 void __iomem * ioaddr = ns_ioaddr(dev);
2403 spin_lock(&np->lock);
2404 if (intr_status & LinkChange) {
2405 u16 lpa = mdio_read(dev, MII_LPA);
2406 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2407 netif_msg_link(np)) {
2409 "%s: Autonegotiation advertising"
2410 " %#04x partner %#04x.\n", dev->name,
2411 np->advertising, lpa);
2414 /* read MII int status to clear the flag */
2415 readw(ioaddr + MIntrStatus);
2418 if (intr_status & StatsMax) {
2421 if (intr_status & IntrTxUnderrun) {
2422 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2423 np->tx_config += TX_DRTH_VAL_INC;
2424 if (netif_msg_tx_err(np))
2426 "%s: increased tx threshold, txcfg %#08x.\n",
2427 dev->name, np->tx_config);
2429 if (netif_msg_tx_err(np))
2431 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2432 dev->name, np->tx_config);
2434 writel(np->tx_config, ioaddr + TxConfig);
2436 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2437 int wol_status = readl(ioaddr + WOLCmd);
2438 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2439 dev->name, wol_status);
2441 if (intr_status & RxStatusFIFOOver) {
2442 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2443 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2446 dev->stats.rx_fifo_errors++;
2447 dev->stats.rx_errors++;
2449 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2450 if (intr_status & IntrPCIErr) {
2451 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2452 intr_status & IntrPCIErr);
2453 dev->stats.tx_fifo_errors++;
2454 dev->stats.tx_errors++;
2455 dev->stats.rx_fifo_errors++;
2456 dev->stats.rx_errors++;
2458 spin_unlock(&np->lock);
2461 static void __get_stats(struct net_device *dev)
2463 void __iomem * ioaddr = ns_ioaddr(dev);
2465 /* The chip only need report frame silently dropped. */
2466 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2467 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2470 static struct net_device_stats *get_stats(struct net_device *dev)
2472 struct netdev_private *np = netdev_priv(dev);
2474 /* The chip only need report frame silently dropped. */
2475 spin_lock_irq(&np->lock);
2476 if (netif_running(dev) && !np->hands_off)
2478 spin_unlock_irq(&np->lock);
2483 #ifdef CONFIG_NET_POLL_CONTROLLER
2484 static void natsemi_poll_controller(struct net_device *dev)
2486 struct netdev_private *np = netdev_priv(dev);
2487 const int irq = np->pci_dev->irq;
2490 intr_handler(irq, dev);
2495 #define HASH_TABLE 0x200
2496 static void __set_rx_mode(struct net_device *dev)
2498 void __iomem * ioaddr = ns_ioaddr(dev);
2499 struct netdev_private *np = netdev_priv(dev);
2500 u8 mc_filter[64]; /* Multicast hash filter */
2503 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2504 rx_mode = RxFilterEnable | AcceptBroadcast
2505 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2506 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2507 (dev->flags & IFF_ALLMULTI)) {
2508 rx_mode = RxFilterEnable | AcceptBroadcast
2509 | AcceptAllMulticast | AcceptMyPhys;
2511 struct netdev_hw_addr *ha;
2514 memset(mc_filter, 0, sizeof(mc_filter));
2515 netdev_for_each_mc_addr(ha, dev) {
2516 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
2517 mc_filter[b/8] |= (1 << (b & 0x07));
2519 rx_mode = RxFilterEnable | AcceptBroadcast
2520 | AcceptMulticast | AcceptMyPhys;
2521 for (i = 0; i < 64; i += 2) {
2522 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2523 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2524 ioaddr + RxFilterData);
2527 writel(rx_mode, ioaddr + RxFilterAddr);
2528 np->cur_rx_mode = rx_mode;
2531 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2535 /* synchronized against open : rtnl_lock() held by caller */
2536 if (netif_running(dev)) {
2537 struct netdev_private *np = netdev_priv(dev);
2538 void __iomem * ioaddr = ns_ioaddr(dev);
2539 const int irq = np->pci_dev->irq;
2542 spin_lock(&np->lock);
2544 natsemi_stop_rxtx(dev);
2545 /* drain rx queue */
2547 /* change buffers */
2550 writel(np->ring_dma, ioaddr + RxRingPtr);
2551 /* restart engines */
2552 writel(RxOn | TxOn, ioaddr + ChipCmd);
2553 spin_unlock(&np->lock);
2559 static void set_rx_mode(struct net_device *dev)
2561 struct netdev_private *np = netdev_priv(dev);
2562 spin_lock_irq(&np->lock);
2565 spin_unlock_irq(&np->lock);
2568 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2570 struct netdev_private *np = netdev_priv(dev);
2571 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2572 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2573 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
2576 static int get_regs_len(struct net_device *dev)
2578 return NATSEMI_REGS_SIZE;
2581 static int get_eeprom_len(struct net_device *dev)
2583 struct netdev_private *np = netdev_priv(dev);
2584 return np->eeprom_size;
2587 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2589 struct netdev_private *np = netdev_priv(dev);
2590 spin_lock_irq(&np->lock);
2591 netdev_get_ecmd(dev, ecmd);
2592 spin_unlock_irq(&np->lock);
2596 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2598 struct netdev_private *np = netdev_priv(dev);
2600 spin_lock_irq(&np->lock);
2601 res = netdev_set_ecmd(dev, ecmd);
2602 spin_unlock_irq(&np->lock);
2606 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2608 struct netdev_private *np = netdev_priv(dev);
2609 spin_lock_irq(&np->lock);
2610 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2611 netdev_get_sopass(dev, wol->sopass);
2612 spin_unlock_irq(&np->lock);
2615 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2617 struct netdev_private *np = netdev_priv(dev);
2619 spin_lock_irq(&np->lock);
2620 netdev_set_wol(dev, wol->wolopts);
2621 res = netdev_set_sopass(dev, wol->sopass);
2622 spin_unlock_irq(&np->lock);
2626 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2628 struct netdev_private *np = netdev_priv(dev);
2629 regs->version = NATSEMI_REGS_VER;
2630 spin_lock_irq(&np->lock);
2631 netdev_get_regs(dev, buf);
2632 spin_unlock_irq(&np->lock);
2635 static u32 get_msglevel(struct net_device *dev)
2637 struct netdev_private *np = netdev_priv(dev);
2638 return np->msg_enable;
2641 static void set_msglevel(struct net_device *dev, u32 val)
2643 struct netdev_private *np = netdev_priv(dev);
2644 np->msg_enable = val;
2647 static int nway_reset(struct net_device *dev)
2651 /* if autoneg is off, it's an error */
2652 tmp = mdio_read(dev, MII_BMCR);
2653 if (tmp & BMCR_ANENABLE) {
2654 tmp |= (BMCR_ANRESTART);
2655 mdio_write(dev, MII_BMCR, tmp);
2661 static u32 get_link(struct net_device *dev)
2663 /* LSTATUS is latched low until a read - so read twice */
2664 mdio_read(dev, MII_BMSR);
2665 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2668 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2670 struct netdev_private *np = netdev_priv(dev);
2674 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2678 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2679 spin_lock_irq(&np->lock);
2680 res = netdev_get_eeprom(dev, eebuf);
2681 spin_unlock_irq(&np->lock);
2683 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2688 static const struct ethtool_ops ethtool_ops = {
2689 .get_drvinfo = get_drvinfo,
2690 .get_regs_len = get_regs_len,
2691 .get_eeprom_len = get_eeprom_len,
2692 .get_settings = get_settings,
2693 .set_settings = set_settings,
2696 .get_regs = get_regs,
2697 .get_msglevel = get_msglevel,
2698 .set_msglevel = set_msglevel,
2699 .nway_reset = nway_reset,
2700 .get_link = get_link,
2701 .get_eeprom = get_eeprom,
2704 static int netdev_set_wol(struct net_device *dev, u32 newval)
2706 struct netdev_private *np = netdev_priv(dev);
2707 void __iomem * ioaddr = ns_ioaddr(dev);
2708 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2710 /* translate to bitmasks this chip understands */
2711 if (newval & WAKE_PHY)
2713 if (newval & WAKE_UCAST)
2714 data |= WakeUnicast;
2715 if (newval & WAKE_MCAST)
2716 data |= WakeMulticast;
2717 if (newval & WAKE_BCAST)
2718 data |= WakeBroadcast;
2719 if (newval & WAKE_ARP)
2721 if (newval & WAKE_MAGIC)
2723 if (np->srr >= SRR_DP83815_D) {
2724 if (newval & WAKE_MAGICSECURE) {
2725 data |= WakeMagicSecure;
2729 writel(data, ioaddr + WOLCmd);
2734 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2736 struct netdev_private *np = netdev_priv(dev);
2737 void __iomem * ioaddr = ns_ioaddr(dev);
2738 u32 regval = readl(ioaddr + WOLCmd);
2740 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2741 | WAKE_ARP | WAKE_MAGIC);
2743 if (np->srr >= SRR_DP83815_D) {
2744 /* SOPASS works on revD and higher */
2745 *supported |= WAKE_MAGICSECURE;
2749 /* translate from chip bitmasks */
2750 if (regval & WakePhy)
2752 if (regval & WakeUnicast)
2754 if (regval & WakeMulticast)
2756 if (regval & WakeBroadcast)
2758 if (regval & WakeArp)
2760 if (regval & WakeMagic)
2762 if (regval & WakeMagicSecure) {
2763 /* this can be on in revC, but it's broken */
2764 *cur |= WAKE_MAGICSECURE;
2770 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2772 struct netdev_private *np = netdev_priv(dev);
2773 void __iomem * ioaddr = ns_ioaddr(dev);
2774 u16 *sval = (u16 *)newval;
2777 if (np->srr < SRR_DP83815_D) {
2781 /* enable writing to these registers by disabling the RX filter */
2782 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2783 addr &= ~RxFilterEnable;
2784 writel(addr, ioaddr + RxFilterAddr);
2786 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2787 writel(addr | 0xa, ioaddr + RxFilterAddr);
2788 writew(sval[0], ioaddr + RxFilterData);
2790 writel(addr | 0xc, ioaddr + RxFilterAddr);
2791 writew(sval[1], ioaddr + RxFilterData);
2793 writel(addr | 0xe, ioaddr + RxFilterAddr);
2794 writew(sval[2], ioaddr + RxFilterData);
2796 /* re-enable the RX filter */
2797 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2802 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2804 struct netdev_private *np = netdev_priv(dev);
2805 void __iomem * ioaddr = ns_ioaddr(dev);
2806 u16 *sval = (u16 *)data;
2809 if (np->srr < SRR_DP83815_D) {
2810 sval[0] = sval[1] = sval[2] = 0;
2814 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2815 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2817 writel(addr | 0xa, ioaddr + RxFilterAddr);
2818 sval[0] = readw(ioaddr + RxFilterData);
2820 writel(addr | 0xc, ioaddr + RxFilterAddr);
2821 sval[1] = readw(ioaddr + RxFilterData);
2823 writel(addr | 0xe, ioaddr + RxFilterAddr);
2824 sval[2] = readw(ioaddr + RxFilterData);
2826 writel(addr, ioaddr + RxFilterAddr);
2831 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2833 struct netdev_private *np = netdev_priv(dev);
2836 ecmd->port = dev->if_port;
2837 ethtool_cmd_speed_set(ecmd, np->speed);
2838 ecmd->duplex = np->duplex;
2839 ecmd->autoneg = np->autoneg;
2840 ecmd->advertising = 0;
2841 if (np->advertising & ADVERTISE_10HALF)
2842 ecmd->advertising |= ADVERTISED_10baseT_Half;
2843 if (np->advertising & ADVERTISE_10FULL)
2844 ecmd->advertising |= ADVERTISED_10baseT_Full;
2845 if (np->advertising & ADVERTISE_100HALF)
2846 ecmd->advertising |= ADVERTISED_100baseT_Half;
2847 if (np->advertising & ADVERTISE_100FULL)
2848 ecmd->advertising |= ADVERTISED_100baseT_Full;
2849 ecmd->supported = (SUPPORTED_Autoneg |
2850 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2851 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2852 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2853 ecmd->phy_address = np->phy_addr_external;
2855 * We intentionally report the phy address of the external
2856 * phy, even if the internal phy is used. This is necessary
2857 * to work around a deficiency of the ethtool interface:
2858 * It's only possible to query the settings of the active
2860 * # ethtool -s ethX port mii
2861 * actually sends an ioctl to switch to port mii with the
2862 * settings that are used for the current active port.
2863 * If we would report a different phy address in this
2865 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2866 * would unintentionally change the phy address.
2868 * Fortunately the phy address doesn't matter with the
2872 /* set information based on active port type */
2873 switch (ecmd->port) {
2876 ecmd->advertising |= ADVERTISED_TP;
2877 ecmd->transceiver = XCVR_INTERNAL;
2880 ecmd->advertising |= ADVERTISED_MII;
2881 ecmd->transceiver = XCVR_EXTERNAL;
2884 ecmd->advertising |= ADVERTISED_FIBRE;
2885 ecmd->transceiver = XCVR_EXTERNAL;
2889 /* if autonegotiation is on, try to return the active speed/duplex */
2890 if (ecmd->autoneg == AUTONEG_ENABLE) {
2891 ecmd->advertising |= ADVERTISED_Autoneg;
2892 tmp = mii_nway_result(
2893 np->advertising & mdio_read(dev, MII_LPA));
2894 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2895 ethtool_cmd_speed_set(ecmd, SPEED_100);
2897 ethtool_cmd_speed_set(ecmd, SPEED_10);
2898 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2899 ecmd->duplex = DUPLEX_FULL;
2901 ecmd->duplex = DUPLEX_HALF;
2904 /* ignore maxtxpkt, maxrxpkt for now */
2909 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2911 struct netdev_private *np = netdev_priv(dev);
2913 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2915 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2917 if (ecmd->autoneg == AUTONEG_ENABLE) {
2918 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2919 ADVERTISED_10baseT_Full |
2920 ADVERTISED_100baseT_Half |
2921 ADVERTISED_100baseT_Full)) == 0) {
2924 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2925 u32 speed = ethtool_cmd_speed(ecmd);
2926 if (speed != SPEED_10 && speed != SPEED_100)
2928 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2935 * If we're ignoring the PHY then autoneg and the internal
2936 * transceiver are really not going to work so don't let the
2939 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2940 ecmd->port == PORT_TP))
2944 * maxtxpkt, maxrxpkt: ignored for now.
2947 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2948 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2949 * selects based on ecmd->port.
2951 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2952 * phys that are connected to the mii bus. It's used to apply fibre
2956 /* WHEW! now lets bang some bits */
2958 /* save the parms */
2959 dev->if_port = ecmd->port;
2960 np->autoneg = ecmd->autoneg;
2961 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2962 if (np->autoneg == AUTONEG_ENABLE) {
2963 /* advertise only what has been requested */
2964 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2965 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2966 np->advertising |= ADVERTISE_10HALF;
2967 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2968 np->advertising |= ADVERTISE_10FULL;
2969 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2970 np->advertising |= ADVERTISE_100HALF;
2971 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2972 np->advertising |= ADVERTISE_100FULL;
2974 np->speed = ethtool_cmd_speed(ecmd);
2975 np->duplex = ecmd->duplex;
2976 /* user overriding the initial full duplex parm? */
2977 if (np->duplex == DUPLEX_HALF)
2978 np->full_duplex = 0;
2981 /* get the right phy enabled */
2982 if (ecmd->port == PORT_TP)
2983 switch_port_internal(dev);
2985 switch_port_external(dev);
2987 /* set parms and see how this affected our link status */
2988 init_phy_fixup(dev);
2993 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2998 u32 *rbuf = (u32 *)buf;
2999 void __iomem * ioaddr = ns_ioaddr(dev);
3001 /* read non-mii page 0 of registers */
3002 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
3003 rbuf[i] = readl(ioaddr + i*4);
3006 /* read current mii registers */
3007 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3008 rbuf[i] = mdio_read(dev, i & 0x1f);
3010 /* read only the 'magic' registers from page 1 */
3011 writew(1, ioaddr + PGSEL);
3012 rbuf[i++] = readw(ioaddr + PMDCSR);
3013 rbuf[i++] = readw(ioaddr + TSTDAT);
3014 rbuf[i++] = readw(ioaddr + DSPCFG);
3015 rbuf[i++] = readw(ioaddr + SDCFG);
3016 writew(0, ioaddr + PGSEL);
3018 /* read RFCR indexed registers */
3019 rfcr = readl(ioaddr + RxFilterAddr);
3020 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3021 writel(j*2, ioaddr + RxFilterAddr);
3022 rbuf[i++] = readw(ioaddr + RxFilterData);
3024 writel(rfcr, ioaddr + RxFilterAddr);
3026 /* the interrupt status is clear-on-read - see if we missed any */
3027 if (rbuf[4] & rbuf[5]) {
3029 "%s: shoot, we dropped an interrupt (%#08x)\n",
3030 dev->name, rbuf[4] & rbuf[5]);
3036 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3037 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3038 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3039 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3040 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3041 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3042 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3043 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3045 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3048 u16 *ebuf = (u16 *)buf;
3049 void __iomem * ioaddr = ns_ioaddr(dev);
3050 struct netdev_private *np = netdev_priv(dev);
3052 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3053 for (i = 0; i < np->eeprom_size/2; i++) {
3054 ebuf[i] = eeprom_read(ioaddr, i);
3055 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3056 * reads it back "sanely". So we swap it back here in order to
3057 * present it to userland as it is stored. */
3058 ebuf[i] = SWAP_BITS(ebuf[i]);
3063 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3065 struct mii_ioctl_data *data = if_mii(rq);
3066 struct netdev_private *np = netdev_priv(dev);
3069 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3070 data->phy_id = np->phy_addr_external;
3073 case SIOCGMIIREG: /* Read MII PHY register. */
3074 /* The phy_id is not enough to uniquely identify
3075 * the intended target. Therefore the command is sent to
3076 * the given mii on the current port.
3078 if (dev->if_port == PORT_TP) {
3079 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3080 data->val_out = mdio_read(dev,
3081 data->reg_num & 0x1f);
3085 move_int_phy(dev, data->phy_id & 0x1f);
3086 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3087 data->reg_num & 0x1f);
3091 case SIOCSMIIREG: /* Write MII PHY register. */
3092 if (dev->if_port == PORT_TP) {
3093 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3094 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3095 np->advertising = data->val_in;
3096 mdio_write(dev, data->reg_num & 0x1f,
3100 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3101 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3102 np->advertising = data->val_in;
3104 move_int_phy(dev, data->phy_id & 0x1f);
3105 miiport_write(dev, data->phy_id & 0x1f,
3106 data->reg_num & 0x1f,
3115 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3117 void __iomem * ioaddr = ns_ioaddr(dev);
3118 struct netdev_private *np = netdev_priv(dev);
3120 if (netif_msg_wol(np))
3121 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3124 /* For WOL we must restart the rx process in silent mode.
3125 * Write NULL to the RxRingPtr. Only possible if
3126 * rx process is stopped
3128 writel(0, ioaddr + RxRingPtr);
3130 /* read WoL status to clear */
3131 readl(ioaddr + WOLCmd);
3133 /* PME on, clear status */
3134 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3136 /* and restart the rx process */
3137 writel(RxOn, ioaddr + ChipCmd);
3140 /* enable the WOL interrupt.
3141 * Could be used to send a netlink message.
3143 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3144 natsemi_irq_enable(dev);
3148 static int netdev_close(struct net_device *dev)
3150 void __iomem * ioaddr = ns_ioaddr(dev);
3151 struct netdev_private *np = netdev_priv(dev);
3152 const int irq = np->pci_dev->irq;
3154 if (netif_msg_ifdown(np))
3156 "%s: Shutting down ethercard, status was %#04x.\n",
3157 dev->name, (int)readl(ioaddr + ChipCmd));
3158 if (netif_msg_pktdata(np))
3160 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3161 dev->name, np->cur_tx, np->dirty_tx,
3162 np->cur_rx, np->dirty_rx);
3164 napi_disable(&np->napi);
3167 * FIXME: what if someone tries to close a device
3168 * that is suspended?
3169 * Should we reenable the nic to switch to
3170 * the final WOL settings?
3173 del_timer_sync(&np->timer);
3175 spin_lock_irq(&np->lock);
3176 natsemi_irq_disable(dev);
3178 spin_unlock_irq(&np->lock);
3183 /* Interrupt disabled, interrupt handler released,
3184 * queue stopped, timer deleted, rtnl_lock held
3185 * All async codepaths that access the driver are disabled.
3187 spin_lock_irq(&np->lock);
3189 readl(ioaddr + IntrMask);
3190 readw(ioaddr + MIntrStatus);
3193 writel(StatsFreeze, ioaddr + StatsCtrl);
3195 /* Stop the chip's Tx and Rx processes. */
3196 natsemi_stop_rxtx(dev);
3199 spin_unlock_irq(&np->lock);
3201 /* clear the carrier last - an interrupt could reenable it otherwise */
3202 netif_carrier_off(dev);
3203 netif_stop_queue(dev);
3210 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3212 /* restart the NIC in WOL mode.
3213 * The nic must be stopped for this.
3215 enable_wol_mode(dev, 0);
3217 /* Restore PME enable bit unmolested */
3218 writel(np->SavedClkRun, ioaddr + ClkRun);
3225 static void natsemi_remove1(struct pci_dev *pdev)
3227 struct net_device *dev = pci_get_drvdata(pdev);
3228 void __iomem * ioaddr = ns_ioaddr(dev);
3230 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3231 unregister_netdev (dev);
3232 pci_release_regions (pdev);
3240 * The ns83815 chip doesn't have explicit RxStop bits.
3241 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3242 * of the nic, thus this function must be very careful:
3244 * suspend/resume synchronization:
3246 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3247 * start_tx, ns_tx_timeout
3249 * No function accesses the hardware without checking np->hands_off.
3250 * the check occurs under spin_lock_irq(&np->lock);
3252 * * netdev_ioctl: noncritical access.
3253 * * netdev_open: cannot happen due to the device_detach
3254 * * netdev_close: doesn't hurt.
3255 * * netdev_timer: timer stopped by natsemi_suspend.
3256 * * intr_handler: doesn't acquire the spinlock. suspend calls
3257 * disable_irq() to enforce synchronization.
3258 * * natsemi_poll: checks before reenabling interrupts. suspend
3259 * sets hands_off, disables interrupts and then waits with
3262 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3265 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3267 struct net_device *dev = pci_get_drvdata (pdev);
3268 struct netdev_private *np = netdev_priv(dev);
3269 void __iomem * ioaddr = ns_ioaddr(dev);
3272 if (netif_running (dev)) {
3273 const int irq = np->pci_dev->irq;
3275 del_timer_sync(&np->timer);
3278 spin_lock_irq(&np->lock);
3280 natsemi_irq_disable(dev);
3282 natsemi_stop_rxtx(dev);
3283 netif_stop_queue(dev);
3285 spin_unlock_irq(&np->lock);
3288 napi_disable(&np->napi);
3290 /* Update the error counts. */
3293 /* pci_power_off(pdev, -1); */
3296 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3297 /* Restore PME enable bit */
3299 /* restart the NIC in WOL mode.
3300 * The nic must be stopped for this.
3301 * FIXME: use the WOL interrupt
3303 enable_wol_mode(dev, 0);
3305 /* Restore PME enable bit unmolested */
3306 writel(np->SavedClkRun, ioaddr + ClkRun);
3310 netif_device_detach(dev);
3316 static int natsemi_resume (struct pci_dev *pdev)
3318 struct net_device *dev = pci_get_drvdata (pdev);
3319 struct netdev_private *np = netdev_priv(dev);
3323 if (netif_device_present(dev))
3325 if (netif_running(dev)) {
3326 const int irq = np->pci_dev->irq;
3328 BUG_ON(!np->hands_off);
3329 ret = pci_enable_device(pdev);
3332 "pci_enable_device() failed: %d\n", ret);
3335 /* pci_power_on(pdev); */
3337 napi_enable(&np->napi);
3342 spin_lock_irq(&np->lock);
3344 init_registers(dev);
3345 netif_device_attach(dev);
3346 spin_unlock_irq(&np->lock);
3349 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
3351 netif_device_attach(dev);
3357 #endif /* CONFIG_PM */
3359 static struct pci_driver natsemi_driver = {
3361 .id_table = natsemi_pci_tbl,
3362 .probe = natsemi_probe1,
3363 .remove = natsemi_remove1,
3365 .suspend = natsemi_suspend,
3366 .resume = natsemi_resume,
3370 static int __init natsemi_init_mod (void)
3372 /* when a module, this is printed whether or not devices are found in probe */
3377 return pci_register_driver(&natsemi_driver);
3380 static void __exit natsemi_exit_mod (void)
3382 pci_unregister_driver (&natsemi_driver);
3385 module_init(natsemi_init_mod);
3386 module_exit(natsemi_exit_mod);