2 * Copyright (C) 2016 Netronome Systems, Inc.
4 * This software is dual licensed under the GNU General License Version 2,
5 * June 1991 as shown in the file COPYING in the top-level directory of this
6 * source tree or the BSD 2-Clause License provided below. You have the
7 * option to license this software under the complete terms of either license.
9 * The BSD 2-Clause License:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * 1. Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * 2. Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define __NFP_ASM_H__ 1
41 #define RE_REG_NO_DST 0x020
42 #define RE_REG_IMM 0x020
43 #define RE_REG_IMM_encode(x) \
44 (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
45 #define RE_REG_IMM_MAX 0x07fULL
46 #define RE_REG_XFR 0x080
48 #define UR_REG_XFR 0x180
49 #define UR_REG_NN 0x280
50 #define UR_REG_NO_DST 0x300
51 #define UR_REG_IMM UR_REG_NO_DST
52 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
53 #define UR_REG_IMM_MAX 0x0ffULL
55 #define OP_BR_BASE 0x0d800000020ULL
56 #define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
57 #define OP_BR_MASK 0x0000000001fULL
58 #define OP_BR_EV_PIP 0x00000000300ULL
59 #define OP_BR_CSS 0x0000003c000ULL
60 #define OP_BR_DEFBR 0x00000300000ULL
61 #define OP_BR_ADDR_LO 0x007ffc00000ULL
62 #define OP_BR_ADDR_HI 0x10000000000ULL
64 #define nfp_is_br(_insn) \
65 (((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE)
81 enum br_ctx_signal_state {
85 #define OP_BBYTE_BASE 0x0c800000000ULL
86 #define OP_BB_A_SRC 0x000000000ffULL
87 #define OP_BB_BYTE 0x00000000300ULL
88 #define OP_BB_B_SRC 0x0000003fc00ULL
89 #define OP_BB_I8 0x00000040000ULL
90 #define OP_BB_EQ 0x00000080000ULL
91 #define OP_BB_DEFBR 0x00000300000ULL
92 #define OP_BB_ADDR_LO 0x007ffc00000ULL
93 #define OP_BB_ADDR_HI 0x10000000000ULL
95 #define OP_BALU_BASE 0x0e800000000ULL
96 #define OP_BA_A_SRC 0x000000003ffULL
97 #define OP_BA_B_SRC 0x000000ffc00ULL
98 #define OP_BA_DEFBR 0x00000300000ULL
99 #define OP_BA_ADDR_HI 0x0007fc00000ULL
101 #define OP_IMMED_A_SRC 0x000000003ffULL
102 #define OP_IMMED_B_SRC 0x000000ffc00ULL
103 #define OP_IMMED_IMM 0x0000ff00000ULL
104 #define OP_IMMED_WIDTH 0x00060000000ULL
105 #define OP_IMMED_INV 0x00080000000ULL
106 #define OP_IMMED_SHIFT 0x00600000000ULL
107 #define OP_IMMED_BASE 0x0f000000000ULL
108 #define OP_IMMED_WR_AB 0x20000000000ULL
112 IMMED_WIDTH_BYTE = 1,
113 IMMED_WIDTH_WORD = 2,
122 #define OP_SHF_BASE 0x08000000000ULL
123 #define OP_SHF_A_SRC 0x000000000ffULL
124 #define OP_SHF_SC 0x00000000300ULL
125 #define OP_SHF_B_SRC 0x0000003fc00ULL
126 #define OP_SHF_I8 0x00000040000ULL
127 #define OP_SHF_SW 0x00000080000ULL
128 #define OP_SHF_DST 0x0000ff00000ULL
129 #define OP_SHF_SHIFT 0x001f0000000ULL
130 #define OP_SHF_OP 0x00e00000000ULL
131 #define OP_SHF_DST_AB 0x01000000000ULL
132 #define OP_SHF_WR_AB 0x20000000000ULL
147 #define OP_ALU_A_SRC 0x000000003ffULL
148 #define OP_ALU_B_SRC 0x000000ffc00ULL
149 #define OP_ALU_DST 0x0003ff00000ULL
150 #define OP_ALU_SW 0x00040000000ULL
151 #define OP_ALU_OP 0x00f80000000ULL
152 #define OP_ALU_DST_AB 0x01000000000ULL
153 #define OP_ALU_BASE 0x0a000000000ULL
154 #define OP_ALU_WR_AB 0x20000000000ULL
173 #define OP_LDF_BASE 0x0c000000000ULL
174 #define OP_LDF_A_SRC 0x000000000ffULL
175 #define OP_LDF_SC 0x00000000300ULL
176 #define OP_LDF_B_SRC 0x0000003fc00ULL
177 #define OP_LDF_I8 0x00000040000ULL
178 #define OP_LDF_SW 0x00000080000ULL
179 #define OP_LDF_ZF 0x00000100000ULL
180 #define OP_LDF_BMASK 0x0000f000000ULL
181 #define OP_LDF_SHF 0x001f0000000ULL
182 #define OP_LDF_WR_AB 0x20000000000ULL
184 #define OP_CMD_A_SRC 0x000000000ffULL
185 #define OP_CMD_CTX 0x00000000300ULL
186 #define OP_CMD_B_SRC 0x0000003fc00ULL
187 #define OP_CMD_TOKEN 0x000000c0000ULL
188 #define OP_CMD_XFER 0x00001f00000ULL
189 #define OP_CMD_CNT 0x0000e000000ULL
190 #define OP_CMD_SIG 0x000f0000000ULL
191 #define OP_CMD_TGT_CMD 0x07f00000000ULL
192 #define OP_CMD_MODE 0x1c0000000000ULL
203 CMD_TGT_READ_SWAP_LE,
218 #define OP_LCSR_BASE 0x0fc00000000ULL
219 #define OP_LCSR_A_SRC 0x000000003ffULL
220 #define OP_LCSR_B_SRC 0x000000ffc00ULL
221 #define OP_LCSR_WRITE 0x00000200000ULL
222 #define OP_LCSR_ADDR 0x001ffc00000ULL
230 #define OP_CARB_BASE 0x0e000000000ULL
231 #define OP_CARB_OR 0x00000010000ULL