drivers/net/ethernet/nvidia/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42
  43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45 #define FORCEDETH_VERSION               "0.64"
  46 #define DRV_NAME                        "forcedeth"
  47
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/delay.h>
  55 #include <linux/sched.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/timer.h>
  59 #include <linux/skbuff.h>
  60 #include <linux/mii.h>
  61 #include <linux/random.h>
  62 #include <linux/init.h>
  63 #include <linux/if_vlan.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/slab.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/prefetch.h>
  68 #include  <linux/io.h>
  69
  70 #include <asm/irq.h>
  71 #include <asm/system.h>
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  93 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  94 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  95 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  96 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  97 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  98 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 100 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 101 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 102 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 103 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 104 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 105 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 106 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 107
 108 enum {
 109         NvRegIrqStatus = 0x000,
 110 #define NVREG_IRQSTAT_MIIEVENT  0x040
 111 #define NVREG_IRQSTAT_MASK              0x83ff
 112         NvRegIrqMask = 0x004,
 113 #define NVREG_IRQ_RX_ERROR              0x0001
 114 #define NVREG_IRQ_RX                    0x0002
 115 #define NVREG_IRQ_RX_NOBUF              0x0004
 116 #define NVREG_IRQ_TX_ERR                0x0008
 117 #define NVREG_IRQ_TX_OK                 0x0010
 118 #define NVREG_IRQ_TIMER                 0x0020
 119 #define NVREG_IRQ_LINK                  0x0040
 120 #define NVREG_IRQ_RX_FORCED             0x0080
 121 #define NVREG_IRQ_TX_FORCED             0x0100
 122 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 123 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 124 #define NVREG_IRQMASK_CPU               0x0060
 125 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 126 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 127 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 128
 129         NvRegUnknownSetupReg6 = 0x008,
 130 #define NVREG_UNKSETUP6_VAL             3
 131
 132 /*
 133  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 134  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 135  */
 136         NvRegPollingInterval = 0x00c,
 137 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 138 #define NVREG_POLL_DEFAULT_CPU  13
 139         NvRegMSIMap0 = 0x020,
 140         NvRegMSIMap1 = 0x024,
 141         NvRegMSIIrqMask = 0x030,
 142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 143         NvRegMisc1 = 0x080,
 144 #define NVREG_MISC1_PAUSE_TX    0x01
 145 #define NVREG_MISC1_HD          0x02
 146 #define NVREG_MISC1_FORCE       0x3b0f3c
 147
 148         NvRegMacReset = 0x34,
 149 #define NVREG_MAC_RESET_ASSERT  0x0F3
 150         NvRegTransmitterControl = 0x084,
 151 #define NVREG_XMITCTL_START     0x01
 152 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 153 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 154 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 155 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 156 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 157 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 158 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 159 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 160 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 161 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 162 #define NVREG_XMITCTL_DATA_START        0x00100000
 163 #define NVREG_XMITCTL_DATA_READY        0x00010000
 164 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 165         NvRegTransmitterStatus = 0x088,
 166 #define NVREG_XMITSTAT_BUSY     0x01
 167
 168         NvRegPacketFilterFlags = 0x8c,
 169 #define NVREG_PFF_PAUSE_RX      0x08
 170 #define NVREG_PFF_ALWAYS        0x7F0000
 171 #define NVREG_PFF_PROMISC       0x80
 172 #define NVREG_PFF_MYADDR        0x20
 173 #define NVREG_PFF_LOOPBACK      0x10
 174
 175         NvRegOffloadConfig = 0x90,
 176 #define NVREG_OFFLOAD_HOMEPHY   0x601
 177 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 178         NvRegReceiverControl = 0x094,
 179 #define NVREG_RCVCTL_START      0x01
 180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 181         NvRegReceiverStatus = 0x98,
 182 #define NVREG_RCVSTAT_BUSY      0x01
 183
 184         NvRegSlotTime = 0x9c,
 185 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 186 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 187 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 188 #define NVREG_SLOTTIME_HALF             0x0000ff00
 189 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 190 #define NVREG_SLOTTIME_MASK             0x000000ff
 191
 192         NvRegTxDeferral = 0xA0,
 193 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 194 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 195 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 198 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 199         NvRegRxDeferral = 0xA4,
 200 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 201         NvRegMacAddrA = 0xA8,
 202         NvRegMacAddrB = 0xAC,
 203         NvRegMulticastAddrA = 0xB0,
 204 #define NVREG_MCASTADDRA_FORCE  0x01
 205         NvRegMulticastAddrB = 0xB4,
 206         NvRegMulticastMaskA = 0xB8,
 207 #define NVREG_MCASTMASKA_NONE           0xffffffff
 208         NvRegMulticastMaskB = 0xBC,
 209 #define NVREG_MCASTMASKB_NONE           0xffff
 210
 211         NvRegPhyInterface = 0xC0,
 212 #define PHY_RGMII               0x10000000
 213         NvRegBackOffControl = 0xC4,
 214 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 215 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 216 #define NVREG_BKOFFCTRL_SELECT                  24
 217 #define NVREG_BKOFFCTRL_GEAR                    12
 218
 219         NvRegTxRingPhysAddr = 0x100,
 220         NvRegRxRingPhysAddr = 0x104,
 221         NvRegRingSizes = 0x108,
 222 #define NVREG_RINGSZ_TXSHIFT 0
 223 #define NVREG_RINGSZ_RXSHIFT 16
 224         NvRegTransmitPoll = 0x10c,
 225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 226         NvRegLinkSpeed = 0x110,
 227 #define NVREG_LINKSPEED_FORCE 0x10000
 228 #define NVREG_LINKSPEED_10      1000
 229 #define NVREG_LINKSPEED_100     100
 230 #define NVREG_LINKSPEED_1000    50
 231 #define NVREG_LINKSPEED_MASK    (0xFFF)
 232         NvRegUnknownSetupReg5 = 0x130,
 233 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 234         NvRegTxWatermark = 0x13c,
 235 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 236 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 237 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 238         NvRegTxRxControl = 0x144,
 239 #define NVREG_TXRXCTL_KICK      0x0001
 240 #define NVREG_TXRXCTL_BIT1      0x0002
 241 #define NVREG_TXRXCTL_BIT2      0x0004
 242 #define NVREG_TXRXCTL_IDLE      0x0008
 243 #define NVREG_TXRXCTL_RESET     0x0010
 244 #define NVREG_TXRXCTL_RXCHECK   0x0400
 245 #define NVREG_TXRXCTL_DESC_1    0
 246 #define NVREG_TXRXCTL_DESC_2    0x002100
 247 #define NVREG_TXRXCTL_DESC_3    0xc02200
 248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 249 #define NVREG_TXRXCTL_VLANINS   0x00080
 250         NvRegTxRingPhysAddrHigh = 0x148,
 251         NvRegRxRingPhysAddrHigh = 0x14C,
 252         NvRegTxPauseFrame = 0x170,
 253 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 257         NvRegTxPauseFrameLimit = 0x174,
 258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 259         NvRegMIIStatus = 0x180,
 260 #define NVREG_MIISTAT_ERROR             0x0001
 261 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 262 #define NVREG_MIISTAT_MASK_RW           0x0007
 263 #define NVREG_MIISTAT_MASK_ALL          0x000f
 264         NvRegMIIMask = 0x184,
 265 #define NVREG_MII_LINKCHANGE            0x0008
 266
 267         NvRegAdapterControl = 0x188,
 268 #define NVREG_ADAPTCTL_START    0x02
 269 #define NVREG_ADAPTCTL_LINKUP   0x04
 270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 271 #define NVREG_ADAPTCTL_RUNNING  0x100000
 272 #define NVREG_ADAPTCTL_PHYSHIFT 24
 273         NvRegMIISpeed = 0x18c,
 274 #define NVREG_MIISPEED_BIT8     (1<<8)
 275 #define NVREG_MIIDELAY  5
 276         NvRegMIIControl = 0x190,
 277 #define NVREG_MIICTL_INUSE      0x08000
 278 #define NVREG_MIICTL_WRITE      0x00400
 279 #define NVREG_MIICTL_ADDRSHIFT  5
 280         NvRegMIIData = 0x194,
 281         NvRegTxUnicast = 0x1a0,
 282         NvRegTxMulticast = 0x1a4,
 283         NvRegTxBroadcast = 0x1a8,
 284         NvRegWakeUpFlags = 0x200,
 285 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 288 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 289 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 290 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 291 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 295 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 296
 297         NvRegMgmtUnitGetVersion = 0x204,
 298 #define NVREG_MGMTUNITGETVERSION        0x01
 299         NvRegMgmtUnitVersion = 0x208,
 300 #define NVREG_MGMTUNITVERSION           0x08
 301         NvRegPowerCap = 0x268,
 302 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 303 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 304 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 305         NvRegPowerState = 0x26c,
 306 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 307 #define NVREG_POWERSTATE_VALID          0x0100
 308 #define NVREG_POWERSTATE_MASK           0x0003
 309 #define NVREG_POWERSTATE_D0             0x0000
 310 #define NVREG_POWERSTATE_D1             0x0001
 311 #define NVREG_POWERSTATE_D2             0x0002
 312 #define NVREG_POWERSTATE_D3             0x0003
 313         NvRegMgmtUnitControl = 0x278,
 314 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 315         NvRegTxCnt = 0x280,
 316         NvRegTxZeroReXmt = 0x284,
 317         NvRegTxOneReXmt = 0x288,
 318         NvRegTxManyReXmt = 0x28c,
 319         NvRegTxLateCol = 0x290,
 320         NvRegTxUnderflow = 0x294,
 321         NvRegTxLossCarrier = 0x298,
 322         NvRegTxExcessDef = 0x29c,
 323         NvRegTxRetryErr = 0x2a0,
 324         NvRegRxFrameErr = 0x2a4,
 325         NvRegRxExtraByte = 0x2a8,
 326         NvRegRxLateCol = 0x2ac,
 327         NvRegRxRunt = 0x2b0,
 328         NvRegRxFrameTooLong = 0x2b4,
 329         NvRegRxOverflow = 0x2b8,
 330         NvRegRxFCSErr = 0x2bc,
 331         NvRegRxFrameAlignErr = 0x2c0,
 332         NvRegRxLenErr = 0x2c4,
 333         NvRegRxUnicast = 0x2c8,
 334         NvRegRxMulticast = 0x2cc,
 335         NvRegRxBroadcast = 0x2d0,
 336         NvRegTxDef = 0x2d4,
 337         NvRegTxFrame = 0x2d8,
 338         NvRegRxCnt = 0x2dc,
 339         NvRegTxPause = 0x2e0,
 340         NvRegRxPause = 0x2e4,
 341         NvRegRxDropFrame = 0x2e8,
 342         NvRegVlanControl = 0x300,
 343 #define NVREG_VLANCONTROL_ENABLE        0x2000
 344         NvRegMSIXMap0 = 0x3e0,
 345         NvRegMSIXMap1 = 0x3e4,
 346         NvRegMSIXIrqStatus = 0x3f0,
 347
 348         NvRegPowerState2 = 0x600,
 349 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 350 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 351 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 352 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 353 };
 354
 355 /* Big endian: should work, but is untested */
 356 struct ring_desc {
 357         __le32 buf;
 358         __le32 flaglen;
 359 };
 360
 361 struct ring_desc_ex {
 362         __le32 bufhigh;
 363         __le32 buflow;
 364         __le32 txvlan;
 365         __le32 flaglen;
 366 };
 367
 368 union ring_type {
 369         struct ring_desc *orig;
 370         struct ring_desc_ex *ex;
 371 };
 372
 373 #define FLAG_MASK_V1 0xffff0000
 374 #define FLAG_MASK_V2 0xffffc000
 375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 377
 378 #define NV_TX_LASTPACKET        (1<<16)
 379 #define NV_TX_RETRYERROR        (1<<19)
 380 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 381 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 382 #define NV_TX_DEFERRED          (1<<26)
 383 #define NV_TX_CARRIERLOST       (1<<27)
 384 #define NV_TX_LATECOLLISION     (1<<28)
 385 #define NV_TX_UNDERFLOW         (1<<29)
 386 #define NV_TX_ERROR             (1<<30)
 387 #define NV_TX_VALID             (1<<31)
 388
 389 #define NV_TX2_LASTPACKET       (1<<29)
 390 #define NV_TX2_RETRYERROR       (1<<18)
 391 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 393 #define NV_TX2_DEFERRED         (1<<25)
 394 #define NV_TX2_CARRIERLOST      (1<<26)
 395 #define NV_TX2_LATECOLLISION    (1<<27)
 396 #define NV_TX2_UNDERFLOW        (1<<28)
 397 /* error and valid are the same for both */
 398 #define NV_TX2_ERROR            (1<<30)
 399 #define NV_TX2_VALID            (1<<31)
 400 #define NV_TX2_TSO              (1<<28)
 401 #define NV_TX2_TSO_SHIFT        14
 402 #define NV_TX2_TSO_MAX_SHIFT    14
 403 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 404 #define NV_TX2_CHECKSUM_L3      (1<<27)
 405 #define NV_TX2_CHECKSUM_L4      (1<<26)
 406
 407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 408
 409 #define NV_RX_DESCRIPTORVALID   (1<<16)
 410 #define NV_RX_MISSEDFRAME       (1<<17)
 411 #define NV_RX_SUBSTRACT1        (1<<18)
 412 #define NV_RX_ERROR1            (1<<23)
 413 #define NV_RX_ERROR2            (1<<24)
 414 #define NV_RX_ERROR3            (1<<25)
 415 #define NV_RX_ERROR4            (1<<26)
 416 #define NV_RX_CRCERR            (1<<27)
 417 #define NV_RX_OVERFLOW          (1<<28)
 418 #define NV_RX_FRAMINGERR        (1<<29)
 419 #define NV_RX_ERROR             (1<<30)
 420 #define NV_RX_AVAIL             (1<<31)
 421 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 422
 423 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 424 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 425 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 426 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 427 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 428 #define NV_RX2_SUBSTRACT1       (1<<25)
 429 #define NV_RX2_ERROR1           (1<<18)
 430 #define NV_RX2_ERROR2           (1<<19)
 431 #define NV_RX2_ERROR3           (1<<20)
 432 #define NV_RX2_ERROR4           (1<<21)
 433 #define NV_RX2_CRCERR           (1<<22)
 434 #define NV_RX2_OVERFLOW         (1<<23)
 435 #define NV_RX2_FRAMINGERR       (1<<24)
 436 /* error and avail are the same for both */
 437 #define NV_RX2_ERROR            (1<<30)
 438 #define NV_RX2_AVAIL            (1<<31)
 439 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 440
 441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 442 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 443
 444 /* Miscellaneous hardware related defines: */
 445 #define NV_PCI_REGSZ_VER1       0x270
 446 #define NV_PCI_REGSZ_VER2       0x2d4
 447 #define NV_PCI_REGSZ_VER3       0x604
 448 #define NV_PCI_REGSZ_MAX        0x604
 449
 450 /* various timeout delays: all in usec */
 451 #define NV_TXRX_RESET_DELAY     4
 452 #define NV_TXSTOP_DELAY1        10
 453 #define NV_TXSTOP_DELAY1MAX     500000
 454 #define NV_TXSTOP_DELAY2        100
 455 #define NV_RXSTOP_DELAY1        10
 456 #define NV_RXSTOP_DELAY1MAX     500000
 457 #define NV_RXSTOP_DELAY2        100
 458 #define NV_SETUP5_DELAY         5
 459 #define NV_SETUP5_DELAYMAX      50000
 460 #define NV_POWERUP_DELAY        5
 461 #define NV_POWERUP_DELAYMAX     5000
 462 #define NV_MIIBUSY_DELAY        50
 463 #define NV_MIIPHY_DELAY 10
 464 #define NV_MIIPHY_DELAYMAX      10000
 465 #define NV_MAC_RESET_DELAY      64
 466
 467 #define NV_WAKEUPPATTERNS       5
 468 #define NV_WAKEUPMASKENTRIES    4
 469
 470 /* General driver defaults */
 471 #define NV_WATCHDOG_TIMEO       (5*HZ)
 472
 473 #define RX_RING_DEFAULT         512
 474 #define TX_RING_DEFAULT         256
 475 #define RX_RING_MIN             128
 476 #define TX_RING_MIN             64
 477 #define RING_MAX_DESC_VER_1     1024
 478 #define RING_MAX_DESC_VER_2_3   16384
 479
 480 /* rx/tx mac addr + type + vlan + align + slack*/
 481 #define NV_RX_HEADERS           (64)
 482 /* even more slack. */
 483 #define NV_RX_ALLOC_PAD         (64)
 484
 485 /* maximum mtu size */
 486 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 487 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 488
 489 #define OOM_REFILL      (1+HZ/20)
 490 #define POLL_WAIT       (1+HZ/100)
 491 #define LINK_TIMEOUT    (3*HZ)
 492 #define STATS_INTERVAL  (10*HZ)
 493
 494 /*
 495  * desc_ver values:
 496  * The nic supports three different descriptor types:
 497  * - DESC_VER_1: Original
 498  * - DESC_VER_2: support for jumbo frames.
 499  * - DESC_VER_3: 64-bit format.
 500  */
 501 #define DESC_VER_1      1
 502 #define DESC_VER_2      2
 503 #define DESC_VER_3      3
 504
 505 /* PHY defines */
 506 #define PHY_OUI_MARVELL         0x5043
 507 #define PHY_OUI_CICADA          0x03f1
 508 #define PHY_OUI_VITESSE         0x01c1
 509 #define PHY_OUI_REALTEK         0x0732
 510 #define PHY_OUI_REALTEK2        0x0020
 511 #define PHYID1_OUI_MASK 0x03ff
 512 #define PHYID1_OUI_SHFT 6
 513 #define PHYID2_OUI_MASK 0xfc00
 514 #define PHYID2_OUI_SHFT 10
 515 #define PHYID2_MODEL_MASK               0x03f0
 516 #define PHY_MODEL_REALTEK_8211          0x0110
 517 #define PHY_REV_MASK                    0x0001
 518 #define PHY_REV_REALTEK_8211B           0x0000
 519 #define PHY_REV_REALTEK_8211C           0x0001
 520 #define PHY_MODEL_REALTEK_8201          0x0200
 521 #define PHY_MODEL_MARVELL_E3016         0x0220
 522 #define PHY_MARVELL_E3016_INITMASK      0x0300
 523 #define PHY_CICADA_INIT1        0x0f000
 524 #define PHY_CICADA_INIT2        0x0e00
 525 #define PHY_CICADA_INIT3        0x01000
 526 #define PHY_CICADA_INIT4        0x0200
 527 #define PHY_CICADA_INIT5        0x0004
 528 #define PHY_CICADA_INIT6        0x02000
 529 #define PHY_VITESSE_INIT_REG1   0x1f
 530 #define PHY_VITESSE_INIT_REG2   0x10
 531 #define PHY_VITESSE_INIT_REG3   0x11
 532 #define PHY_VITESSE_INIT_REG4   0x12
 533 #define PHY_VITESSE_INIT_MSK1   0xc
 534 #define PHY_VITESSE_INIT_MSK2   0x0180
 535 #define PHY_VITESSE_INIT1       0x52b5
 536 #define PHY_VITESSE_INIT2       0xaf8a
 537 #define PHY_VITESSE_INIT3       0x8
 538 #define PHY_VITESSE_INIT4       0x8f8a
 539 #define PHY_VITESSE_INIT5       0xaf86
 540 #define PHY_VITESSE_INIT6       0x8f86
 541 #define PHY_VITESSE_INIT7       0xaf82
 542 #define PHY_VITESSE_INIT8       0x0100
 543 #define PHY_VITESSE_INIT9       0x8f82
 544 #define PHY_VITESSE_INIT10      0x0
 545 #define PHY_REALTEK_INIT_REG1   0x1f
 546 #define PHY_REALTEK_INIT_REG2   0x19
 547 #define PHY_REALTEK_INIT_REG3   0x13
 548 #define PHY_REALTEK_INIT_REG4   0x14
 549 #define PHY_REALTEK_INIT_REG5   0x18
 550 #define PHY_REALTEK_INIT_REG6   0x11
 551 #define PHY_REALTEK_INIT_REG7   0x01
 552 #define PHY_REALTEK_INIT1       0x0000
 553 #define PHY_REALTEK_INIT2       0x8e00
 554 #define PHY_REALTEK_INIT3       0x0001
 555 #define PHY_REALTEK_INIT4       0xad17
 556 #define PHY_REALTEK_INIT5       0xfb54
 557 #define PHY_REALTEK_INIT6       0xf5c7
 558 #define PHY_REALTEK_INIT7       0x1000
 559 #define PHY_REALTEK_INIT8       0x0003
 560 #define PHY_REALTEK_INIT9       0x0008
 561 #define PHY_REALTEK_INIT10      0x0005
 562 #define PHY_REALTEK_INIT11      0x0200
 563 #define PHY_REALTEK_INIT_MSK1   0x0003
 564
 565 #define PHY_GIGABIT     0x0100
 566
 567 #define PHY_TIMEOUT     0x1
 568 #define PHY_ERROR       0x2
 569
 570 #define PHY_100 0x1
 571 #define PHY_1000        0x2
 572 #define PHY_HALF        0x100
 573
 574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 576 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 577 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 578 #define NV_PAUSEFRAME_RX_REQ     0x0010
 579 #define NV_PAUSEFRAME_TX_REQ     0x0020
 580 #define NV_PAUSEFRAME_AUTONEG    0x0040
 581
 582 /* MSI/MSI-X defines */
 583 #define NV_MSI_X_MAX_VECTORS  8
 584 #define NV_MSI_X_VECTORS_MASK 0x000f
 585 #define NV_MSI_CAPABLE        0x0010
 586 #define NV_MSI_X_CAPABLE      0x0020
 587 #define NV_MSI_ENABLED        0x0040
 588 #define NV_MSI_X_ENABLED      0x0080
 589
 590 #define NV_MSI_X_VECTOR_ALL   0x0
 591 #define NV_MSI_X_VECTOR_RX    0x0
 592 #define NV_MSI_X_VECTOR_TX    0x1
 593 #define NV_MSI_X_VECTOR_OTHER 0x2
 594
 595 #define NV_MSI_PRIV_OFFSET 0x68
 596 #define NV_MSI_PRIV_VALUE  0xffffffff
 597
 598 #define NV_RESTART_TX         0x1
 599 #define NV_RESTART_RX         0x2
 600
 601 #define NV_TX_LIMIT_COUNT     16
 602
 603 #define NV_DYNAMIC_THRESHOLD        4
 604 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 605
 606 /* statistics */
 607 struct nv_ethtool_str {
 608         char name[ETH_GSTRING_LEN];
 609 };
 610
 611 static const struct nv_ethtool_str nv_estats_str[] = {
 612         { "tx_bytes" },
 613         { "tx_zero_rexmt" },
 614         { "tx_one_rexmt" },
 615         { "tx_many_rexmt" },
 616         { "tx_late_collision" },
 617         { "tx_fifo_errors" },
 618         { "tx_carrier_errors" },
 619         { "tx_excess_deferral" },
 620         { "tx_retry_error" },
 621         { "rx_frame_error" },
 622         { "rx_extra_byte" },
 623         { "rx_late_collision" },
 624         { "rx_runt" },
 625         { "rx_frame_too_long" },
 626         { "rx_over_errors" },
 627         { "rx_crc_errors" },
 628         { "rx_frame_align_error" },
 629         { "rx_length_error" },
 630         { "rx_unicast" },
 631         { "rx_multicast" },
 632         { "rx_broadcast" },
 633         { "rx_packets" },
 634         { "rx_errors_total" },
 635         { "tx_errors_total" },
 636
 637         /* version 2 stats */
 638         { "tx_deferral" },
 639         { "tx_packets" },
 640         { "rx_bytes" },
 641         { "tx_pause" },
 642         { "rx_pause" },
 643         { "rx_drop_frame" },
 644
 645         /* version 3 stats */
 646         { "tx_unicast" },
 647         { "tx_multicast" },
 648         { "tx_broadcast" }
 649 };
 650
 651 struct nv_ethtool_stats {
 652         u64 tx_bytes;
 653         u64 tx_zero_rexmt;
 654         u64 tx_one_rexmt;
 655         u64 tx_many_rexmt;
 656         u64 tx_late_collision;
 657         u64 tx_fifo_errors;
 658         u64 tx_carrier_errors;
 659         u64 tx_excess_deferral;
 660         u64 tx_retry_error;
 661         u64 rx_frame_error;
 662         u64 rx_extra_byte;
 663         u64 rx_late_collision;
 664         u64 rx_runt;
 665         u64 rx_frame_too_long;
 666         u64 rx_over_errors;
 667         u64 rx_crc_errors;
 668         u64 rx_frame_align_error;
 669         u64 rx_length_error;
 670         u64 rx_unicast;
 671         u64 rx_multicast;
 672         u64 rx_broadcast;
 673         u64 rx_packets;
 674         u64 rx_errors_total;
 675         u64 tx_errors_total;
 676
 677         /* version 2 stats */
 678         u64 tx_deferral;
 679         u64 tx_packets;
 680         u64 rx_bytes;
 681         u64 tx_pause;
 682         u64 rx_pause;
 683         u64 rx_drop_frame;
 684
 685         /* version 3 stats */
 686         u64 tx_unicast;
 687         u64 tx_multicast;
 688         u64 tx_broadcast;
 689 };
 690
 691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 694
 695 /* diagnostics */
 696 #define NV_TEST_COUNT_BASE 3
 697 #define NV_TEST_COUNT_EXTENDED 4
 698
 699 static const struct nv_ethtool_str nv_etests_str[] = {
 700         { "link      (online/offline)" },
 701         { "register  (offline)       " },
 702         { "interrupt (offline)       " },
 703         { "loopback  (offline)       " }
 704 };
 705
 706 struct register_test {
 707         __u32 reg;
 708         __u32 mask;
 709 };
 710
 711 static const struct register_test nv_registers_test[] = {
 712         { NvRegUnknownSetupReg6, 0x01 },
 713         { NvRegMisc1, 0x03c },
 714         { NvRegOffloadConfig, 0x03ff },
 715         { NvRegMulticastAddrA, 0xffffffff },
 716         { NvRegTxWatermark, 0x0ff },
 717         { NvRegWakeUpFlags, 0x07777 },
 718         { 0, 0 }
 719 };
 720
 721 struct nv_skb_map {
 722         struct sk_buff *skb;
 723         dma_addr_t dma;
 724         unsigned int dma_len:31;
 725         unsigned int dma_single:1;
 726         struct ring_desc_ex *first_tx_desc;
 727         struct nv_skb_map *next_tx_ctx;
 728 };
 729
 730 /*
 731  * SMP locking:
 732  * All hardware access under netdev_priv(dev)->lock, except the performance
 733  * critical parts:
 734  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 735  *      by the arch code for interrupts.
 736  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 737  *      needs netdev_priv(dev)->lock :-(
 738  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 739  */
 740
 741 /* in dev: base, irq */
 742 struct fe_priv {
 743         spinlock_t lock;
 744
 745         struct net_device *dev;
 746         struct napi_struct napi;
 747
 748         /* General data:
 749          * Locking: spin_lock(&np->lock); */
 750         struct nv_ethtool_stats estats;
 751         int in_shutdown;
 752         u32 linkspeed;
 753         int duplex;
 754         int autoneg;
 755         int fixed_mode;
 756         int phyaddr;
 757         int wolenabled;
 758         unsigned int phy_oui;
 759         unsigned int phy_model;
 760         unsigned int phy_rev;
 761         u16 gigabit;
 762         int intr_test;
 763         int recover_error;
 764         int quiet_count;
 765
 766         /* General data: RO fields */
 767         dma_addr_t ring_addr;
 768         struct pci_dev *pci_dev;
 769         u32 orig_mac[2];
 770         u32 events;
 771         u32 irqmask;
 772         u32 desc_ver;
 773         u32 txrxctl_bits;
 774         u32 vlanctl_bits;
 775         u32 driver_data;
 776         u32 device_id;
 777         u32 register_size;
 778         u32 mac_in_use;
 779         int mgmt_version;
 780         int mgmt_sema;
 781
 782         void __iomem *base;
 783
 784         /* rx specific fields.
 785          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 786          */
 787         union ring_type get_rx, put_rx, first_rx, last_rx;
 788         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 789         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 790         struct nv_skb_map *rx_skb;
 791
 792         union ring_type rx_ring;
 793         unsigned int rx_buf_sz;
 794         unsigned int pkt_limit;
 795         struct timer_list oom_kick;
 796         struct timer_list nic_poll;
 797         struct timer_list stats_poll;
 798         u32 nic_poll_irq;
 799         int rx_ring_size;
 800
 801         /* media detection workaround.
 802          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 803          */
 804         int need_linktimer;
 805         unsigned long link_timeout;
 806         /*
 807          * tx specific fields.
 808          */
 809         union ring_type get_tx, put_tx, first_tx, last_tx;
 810         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 811         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 812         struct nv_skb_map *tx_skb;
 813
 814         union ring_type tx_ring;
 815         u32 tx_flags;
 816         int tx_ring_size;
 817         int tx_limit;
 818         u32 tx_pkts_in_progress;
 819         struct nv_skb_map *tx_change_owner;
 820         struct nv_skb_map *tx_end_flip;
 821         int tx_stop;
 822
 823         /* msi/msi-x fields */
 824         u32 msi_flags;
 825         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 826
 827         /* flow control */
 828         u32 pause_flags;
 829
 830         /* power saved state */
 831         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 832
 833         /* for different msi-x irq type */
 834         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 835         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 836         char name_other[IFNAMSIZ + 6];    /* -other */
 837 };
 838
 839 /*
 840  * Maximum number of loops until we assume that a bit in the irq mask
 841  * is stuck. Overridable with module param.
 842  */
 843 static int max_interrupt_work = 4;
 844
 845 /*
 846  * Optimization can be either throuput mode or cpu mode
 847  *
 848  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 849  * CPU Mode: Interrupts are controlled by a timer.
 850  */
 851 enum {
 852         NV_OPTIMIZATION_MODE_THROUGHPUT,
 853         NV_OPTIMIZATION_MODE_CPU,
 854         NV_OPTIMIZATION_MODE_DYNAMIC
 855 };
 856 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 857
 858 /*
 859  * Poll interval for timer irq
 860  *
 861  * This interval determines how frequent an interrupt is generated.
 862  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 863  * Min = 0, and Max = 65535
 864  */
 865 static int poll_interval = -1;
 866
 867 /*
 868  * MSI interrupts
 869  */
 870 enum {
 871         NV_MSI_INT_DISABLED,
 872         NV_MSI_INT_ENABLED
 873 };
 874 static int msi = NV_MSI_INT_ENABLED;
 875
 876 /*
 877  * MSIX interrupts
 878  */
 879 enum {
 880         NV_MSIX_INT_DISABLED,
 881         NV_MSIX_INT_ENABLED
 882 };
 883 static int msix = NV_MSIX_INT_ENABLED;
 884
 885 /*
 886  * DMA 64bit
 887  */
 888 enum {
 889         NV_DMA_64BIT_DISABLED,
 890         NV_DMA_64BIT_ENABLED
 891 };
 892 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 893
 894 /*
 895  * Crossover Detection
 896  * Realtek 8201 phy + some OEM boards do not work properly.
 897  */
 898 enum {
 899         NV_CROSSOVER_DETECTION_DISABLED,
 900         NV_CROSSOVER_DETECTION_ENABLED
 901 };
 902 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 903
 904 /*
 905  * Power down phy when interface is down (persists through reboot;
 906  * older Linux and other OSes may not power it up again)
 907  */
 908 static int phy_power_down;
 909
 910 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 911 {
 912         return netdev_priv(dev);
 913 }
 914
 915 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 916 {
 917         return ((struct fe_priv *)netdev_priv(dev))->base;
 918 }
 919
 920 static inline void pci_push(u8 __iomem *base)
 921 {
 922         /* force out pending posted writes */
 923         readl(base);
 924 }
 925
 926 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 927 {
 928         return le32_to_cpu(prd->flaglen)
 929                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 930 }
 931
 932 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 933 {
 934         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 935 }
 936
 937 static bool nv_optimized(struct fe_priv *np)
 938 {
 939         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 940                 return false;
 941         return true;
 942 }
 943
 944 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 945                      int delay, int delaymax)
 946 {
 947         u8 __iomem *base = get_hwbase(dev);
 948
 949         pci_push(base);
 950         do {
 951                 udelay(delay);
 952                 delaymax -= delay;
 953                 if (delaymax < 0)
 954                         return 1;
 955         } while ((readl(base + offset) & mask) != target);
 956         return 0;
 957 }
 958
 959 #define NV_SETUP_RX_RING 0x01
 960 #define NV_SETUP_TX_RING 0x02
 961
 962 static inline u32 dma_low(dma_addr_t addr)
 963 {
 964         return addr;
 965 }
 966
 967 static inline u32 dma_high(dma_addr_t addr)
 968 {
 969         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 970 }
 971
 972 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 973 {
 974         struct fe_priv *np = get_nvpriv(dev);
 975         u8 __iomem *base = get_hwbase(dev);
 976
 977         if (!nv_optimized(np)) {
 978                 if (rxtx_flags & NV_SETUP_RX_RING)
 979                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 980                 if (rxtx_flags & NV_SETUP_TX_RING)
 981                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 982         } else {
 983                 if (rxtx_flags & NV_SETUP_RX_RING) {
 984                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 985                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 986                 }
 987                 if (rxtx_flags & NV_SETUP_TX_RING) {
 988                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 989                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 990                 }
 991         }
 992 }
 993
 994 static void free_rings(struct net_device *dev)
 995 {
 996         struct fe_priv *np = get_nvpriv(dev);
 997
 998         if (!nv_optimized(np)) {
 999                 if (np->rx_ring.orig)
1000                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1001                                             np->rx_ring.orig, np->ring_addr);
1002         } else {
1003                 if (np->rx_ring.ex)
1004                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1005                                             np->rx_ring.ex, np->ring_addr);
1006         }
1007         kfree(np->rx_skb);
1008         kfree(np->tx_skb);
1009 }
1010
1011 static int using_multi_irqs(struct net_device *dev)
1012 {
1013         struct fe_priv *np = get_nvpriv(dev);
1014
1015         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1016             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1017              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1018                 return 0;
1019         else
1020                 return 1;
1021 }
1022
1023 static void nv_txrx_gate(struct net_device *dev, bool gate)
1024 {
1025         struct fe_priv *np = get_nvpriv(dev);
1026         u8 __iomem *base = get_hwbase(dev);
1027         u32 powerstate;
1028
1029         if (!np->mac_in_use &&
1030             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1031                 powerstate = readl(base + NvRegPowerState2);
1032                 if (gate)
1033                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1034                 else
1035                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1036                 writel(powerstate, base + NvRegPowerState2);
1037         }
1038 }
1039
1040 static void nv_enable_irq(struct net_device *dev)
1041 {
1042         struct fe_priv *np = get_nvpriv(dev);
1043
1044         if (!using_multi_irqs(dev)) {
1045                 if (np->msi_flags & NV_MSI_X_ENABLED)
1046                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1047                 else
1048                         enable_irq(np->pci_dev->irq);
1049         } else {
1050                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1051                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1052                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1053         }
1054 }
1055
1056 static void nv_disable_irq(struct net_device *dev)
1057 {
1058         struct fe_priv *np = get_nvpriv(dev);
1059
1060         if (!using_multi_irqs(dev)) {
1061                 if (np->msi_flags & NV_MSI_X_ENABLED)
1062                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1063                 else
1064                         disable_irq(np->pci_dev->irq);
1065         } else {
1066                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1067                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1068                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1069         }
1070 }
1071
1072 /* In MSIX mode, a write to irqmask behaves as XOR */
1073 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1074 {
1075         u8 __iomem *base = get_hwbase(dev);
1076
1077         writel(mask, base + NvRegIrqMask);
1078 }
1079
1080 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1081 {
1082         struct fe_priv *np = get_nvpriv(dev);
1083         u8 __iomem *base = get_hwbase(dev);
1084
1085         if (np->msi_flags & NV_MSI_X_ENABLED) {
1086                 writel(mask, base + NvRegIrqMask);
1087         } else {
1088                 if (np->msi_flags & NV_MSI_ENABLED)
1089                         writel(0, base + NvRegMSIIrqMask);
1090                 writel(0, base + NvRegIrqMask);
1091         }
1092 }
1093
1094 static void nv_napi_enable(struct net_device *dev)
1095 {
1096         struct fe_priv *np = get_nvpriv(dev);
1097
1098         napi_enable(&np->napi);
1099 }
1100
1101 static void nv_napi_disable(struct net_device *dev)
1102 {
1103         struct fe_priv *np = get_nvpriv(dev);
1104
1105         napi_disable(&np->napi);
1106 }
1107
1108 #define MII_READ        (-1)
1109 /* mii_rw: read/write a register on the PHY.
1110  *
1111  * Caller must guarantee serialization
1112  */
1113 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1114 {
1115         u8 __iomem *base = get_hwbase(dev);
1116         u32 reg;
1117         int retval;
1118
1119         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1120
1121         reg = readl(base + NvRegMIIControl);
1122         if (reg & NVREG_MIICTL_INUSE) {
1123                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1124                 udelay(NV_MIIBUSY_DELAY);
1125         }
1126
1127         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1128         if (value != MII_READ) {
1129                 writel(value, base + NvRegMIIData);
1130                 reg |= NVREG_MIICTL_WRITE;
1131         }
1132         writel(reg, base + NvRegMIIControl);
1133
1134         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1135                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1136                 retval = -1;
1137         } else if (value != MII_READ) {
1138                 /* it was a write operation - fewer failures are detectable */
1139                 retval = 0;
1140         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1141                 retval = -1;
1142         } else {
1143                 retval = readl(base + NvRegMIIData);
1144         }
1145
1146         return retval;
1147 }
1148
1149 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1150 {
1151         struct fe_priv *np = netdev_priv(dev);
1152         u32 miicontrol;
1153         unsigned int tries = 0;
1154
1155         miicontrol = BMCR_RESET | bmcr_setup;
1156         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1157                 return -1;
1158
1159         /* wait for 500ms */
1160         msleep(500);
1161
1162         /* must wait till reset is deasserted */
1163         while (miicontrol & BMCR_RESET) {
1164                 usleep_range(10000, 20000);
1165                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1166                 /* FIXME: 100 tries seem excessive */
1167                 if (tries++ > 100)
1168                         return -1;
1169         }
1170         return 0;
1171 }
1172
1173 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1174 {
1175         static const struct {
1176                 int reg;
1177                 int init;
1178         } ri[] = {
1179                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1180                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1181                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1182                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1183                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1184                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1185                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1186         };
1187         int i;
1188
1189         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1190                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1191                         return PHY_ERROR;
1192         }
1193
1194         return 0;
1195 }
1196
1197 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1198 {
1199         u32 reg;
1200         u8 __iomem *base = get_hwbase(dev);
1201         u32 powerstate = readl(base + NvRegPowerState2);
1202
1203         /* need to perform hw phy reset */
1204         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1205         writel(powerstate, base + NvRegPowerState2);
1206         msleep(25);
1207
1208         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1209         writel(powerstate, base + NvRegPowerState2);
1210         msleep(25);
1211
1212         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1213         reg |= PHY_REALTEK_INIT9;
1214         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1215                 return PHY_ERROR;
1216         if (mii_rw(dev, np->phyaddr,
1217                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1218                 return PHY_ERROR;
1219         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1220         if (!(reg & PHY_REALTEK_INIT11)) {
1221                 reg |= PHY_REALTEK_INIT11;
1222                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1223                         return PHY_ERROR;
1224         }
1225         if (mii_rw(dev, np->phyaddr,
1226                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1227                 return PHY_ERROR;
1228
1229         return 0;
1230 }
1231
1232 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1233 {
1234         u32 phy_reserved;
1235
1236         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1237                 phy_reserved = mii_rw(dev, np->phyaddr,
1238                                       PHY_REALTEK_INIT_REG6, MII_READ);
1239                 phy_reserved |= PHY_REALTEK_INIT7;
1240                 if (mii_rw(dev, np->phyaddr,
1241                            PHY_REALTEK_INIT_REG6, phy_reserved))
1242                         return PHY_ERROR;
1243         }
1244
1245         return 0;
1246 }
1247
1248 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1249 {
1250         u32 phy_reserved;
1251
1252         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1253                 if (mii_rw(dev, np->phyaddr,
1254                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1255                         return PHY_ERROR;
1256                 phy_reserved = mii_rw(dev, np->phyaddr,
1257                                       PHY_REALTEK_INIT_REG2, MII_READ);
1258                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1259                 phy_reserved |= PHY_REALTEK_INIT3;
1260                 if (mii_rw(dev, np->phyaddr,
1261                            PHY_REALTEK_INIT_REG2, phy_reserved))
1262                         return PHY_ERROR;
1263                 if (mii_rw(dev, np->phyaddr,
1264                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1265                         return PHY_ERROR;
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1272                        u32 phyinterface)
1273 {
1274         u32 phy_reserved;
1275
1276         if (phyinterface & PHY_RGMII) {
1277                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1278                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1279                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1280                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1281                         return PHY_ERROR;
1282                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1283                 phy_reserved |= PHY_CICADA_INIT5;
1284                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1285                         return PHY_ERROR;
1286         }
1287         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1288         phy_reserved |= PHY_CICADA_INIT6;
1289         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1290                 return PHY_ERROR;
1291
1292         return 0;
1293 }
1294
1295 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1296 {
1297         u32 phy_reserved;
1298
1299         if (mii_rw(dev, np->phyaddr,
1300                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1301                 return PHY_ERROR;
1302         if (mii_rw(dev, np->phyaddr,
1303                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1304                 return PHY_ERROR;
1305         phy_reserved = mii_rw(dev, np->phyaddr,
1306                               PHY_VITESSE_INIT_REG4, MII_READ);
1307         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1308                 return PHY_ERROR;
1309         phy_reserved = mii_rw(dev, np->phyaddr,
1310                               PHY_VITESSE_INIT_REG3, MII_READ);
1311         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1312         phy_reserved |= PHY_VITESSE_INIT3;
1313         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1314                 return PHY_ERROR;
1315         if (mii_rw(dev, np->phyaddr,
1316                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1317                 return PHY_ERROR;
1318         if (mii_rw(dev, np->phyaddr,
1319                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1320                 return PHY_ERROR;
1321         phy_reserved = mii_rw(dev, np->phyaddr,
1322                               PHY_VITESSE_INIT_REG4, MII_READ);
1323         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1324         phy_reserved |= PHY_VITESSE_INIT3;
1325         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1326                 return PHY_ERROR;
1327         phy_reserved = mii_rw(dev, np->phyaddr,
1328                               PHY_VITESSE_INIT_REG3, MII_READ);
1329         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1330                 return PHY_ERROR;
1331         if (mii_rw(dev, np->phyaddr,
1332                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1333                 return PHY_ERROR;
1334         if (mii_rw(dev, np->phyaddr,
1335                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1336                 return PHY_ERROR;
1337         phy_reserved = mii_rw(dev, np->phyaddr,
1338                               PHY_VITESSE_INIT_REG4, MII_READ);
1339         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1340                 return PHY_ERROR;
1341         phy_reserved = mii_rw(dev, np->phyaddr,
1342                               PHY_VITESSE_INIT_REG3, MII_READ);
1343         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1344         phy_reserved |= PHY_VITESSE_INIT8;
1345         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1346                 return PHY_ERROR;
1347         if (mii_rw(dev, np->phyaddr,
1348                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1349                 return PHY_ERROR;
1350         if (mii_rw(dev, np->phyaddr,
1351                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1352                 return PHY_ERROR;
1353
1354         return 0;
1355 }
1356
1357 static int phy_init(struct net_device *dev)
1358 {
1359         struct fe_priv *np = get_nvpriv(dev);
1360         u8 __iomem *base = get_hwbase(dev);
1361         u32 phyinterface;
1362         u32 mii_status, mii_control, mii_control_1000, reg;
1363
1364         /* phy errata for E3016 phy */
1365         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1366                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1367                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1368                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1369                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1370                                     pci_name(np->pci_dev));
1371                         return PHY_ERROR;
1372                 }
1373         }
1374         if (np->phy_oui == PHY_OUI_REALTEK) {
1375                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1376                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1377                         if (init_realtek_8211b(dev, np)) {
1378                                 netdev_info(dev, "%s: phy init failed\n",
1379                                             pci_name(np->pci_dev));
1380                                 return PHY_ERROR;
1381                         }
1382                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1383                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1384                         if (init_realtek_8211c(dev, np)) {
1385                                 netdev_info(dev, "%s: phy init failed\n",
1386                                             pci_name(np->pci_dev));
1387                                 return PHY_ERROR;
1388                         }
1389                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1390                         if (init_realtek_8201(dev, np)) {
1391                                 netdev_info(dev, "%s: phy init failed\n",
1392                                             pci_name(np->pci_dev));
1393                                 return PHY_ERROR;
1394                         }
1395                 }
1396         }
1397
1398         /* set advertise register */
1399         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1400         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1401                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1402                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1403         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1404                 netdev_info(dev, "%s: phy write to advertise failed\n",
1405                             pci_name(np->pci_dev));
1406                 return PHY_ERROR;
1407         }
1408
1409         /* get phy interface type */
1410         phyinterface = readl(base + NvRegPhyInterface);
1411
1412         /* see if gigabit phy */
1413         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1414         if (mii_status & PHY_GIGABIT) {
1415                 np->gigabit = PHY_GIGABIT;
1416                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1417                                           MII_CTRL1000, MII_READ);
1418                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1419                 if (phyinterface & PHY_RGMII)
1420                         mii_control_1000 |= ADVERTISE_1000FULL;
1421                 else
1422                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1423
1424                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1425                         netdev_info(dev, "%s: phy init failed\n",
1426                                     pci_name(np->pci_dev));
1427                         return PHY_ERROR;
1428                 }
1429         } else
1430                 np->gigabit = 0;
1431
1432         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1433         mii_control |= BMCR_ANENABLE;
1434
1435         if (np->phy_oui == PHY_OUI_REALTEK &&
1436             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1437             np->phy_rev == PHY_REV_REALTEK_8211C) {
1438                 /* start autoneg since we already performed hw reset above */
1439                 mii_control |= BMCR_ANRESTART;
1440                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1441                         netdev_info(dev, "%s: phy init failed\n",
1442                                     pci_name(np->pci_dev));
1443                         return PHY_ERROR;
1444                 }
1445         } else {
1446                 /* reset the phy
1447                  * (certain phys need bmcr to be setup with reset)
1448                  */
1449                 if (phy_reset(dev, mii_control)) {
1450                         netdev_info(dev, "%s: phy reset failed\n",
1451                                     pci_name(np->pci_dev));
1452                         return PHY_ERROR;
1453                 }
1454         }
1455
1456         /* phy vendor specific configuration */
1457         if ((np->phy_oui == PHY_OUI_CICADA)) {
1458                 if (init_cicada(dev, np, phyinterface)) {
1459                         netdev_info(dev, "%s: phy init failed\n",
1460                                     pci_name(np->pci_dev));
1461                         return PHY_ERROR;
1462                 }
1463         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1464                 if (init_vitesse(dev, np)) {
1465                         netdev_info(dev, "%s: phy init failed\n",
1466                                     pci_name(np->pci_dev));
1467                         return PHY_ERROR;
1468                 }
1469         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1470                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1471                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1472                         /* reset could have cleared these out, set them back */
1473                         if (init_realtek_8211b(dev, np)) {
1474                                 netdev_info(dev, "%s: phy init failed\n",
1475                                             pci_name(np->pci_dev));
1476                                 return PHY_ERROR;
1477                         }
1478                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1479                         if (init_realtek_8201(dev, np) ||
1480                             init_realtek_8201_cross(dev, np)) {
1481                                 netdev_info(dev, "%s: phy init failed\n",
1482                                             pci_name(np->pci_dev));
1483                                 return PHY_ERROR;
1484                         }
1485                 }
1486         }
1487
1488         /* some phys clear out pause advertisement on reset, set it back */
1489         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1490
1491         /* restart auto negotiation, power down phy */
1492         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1493         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1494         if (phy_power_down)
1495                 mii_control |= BMCR_PDOWN;
1496         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1497                 return PHY_ERROR;
1498
1499         return 0;
1500 }
1501
1502 static void nv_start_rx(struct net_device *dev)
1503 {
1504         struct fe_priv *np = netdev_priv(dev);
1505         u8 __iomem *base = get_hwbase(dev);
1506         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1507
1508         /* Already running? Stop it. */
1509         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1510                 rx_ctrl &= ~NVREG_RCVCTL_START;
1511                 writel(rx_ctrl, base + NvRegReceiverControl);
1512                 pci_push(base);
1513         }
1514         writel(np->linkspeed, base + NvRegLinkSpeed);
1515         pci_push(base);
1516         rx_ctrl |= NVREG_RCVCTL_START;
1517         if (np->mac_in_use)
1518                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1519         writel(rx_ctrl, base + NvRegReceiverControl);
1520         pci_push(base);
1521 }
1522
1523 static void nv_stop_rx(struct net_device *dev)
1524 {
1525         struct fe_priv *np = netdev_priv(dev);
1526         u8 __iomem *base = get_hwbase(dev);
1527         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1528
1529         if (!np->mac_in_use)
1530                 rx_ctrl &= ~NVREG_RCVCTL_START;
1531         else
1532                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1533         writel(rx_ctrl, base + NvRegReceiverControl);
1534         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1535                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1536                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1537                             __func__);
1538
1539         udelay(NV_RXSTOP_DELAY2);
1540         if (!np->mac_in_use)
1541                 writel(0, base + NvRegLinkSpeed);
1542 }
1543
1544 static void nv_start_tx(struct net_device *dev)
1545 {
1546         struct fe_priv *np = netdev_priv(dev);
1547         u8 __iomem *base = get_hwbase(dev);
1548         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1549
1550         tx_ctrl |= NVREG_XMITCTL_START;
1551         if (np->mac_in_use)
1552                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1553         writel(tx_ctrl, base + NvRegTransmitterControl);
1554         pci_push(base);
1555 }
1556
1557 static void nv_stop_tx(struct net_device *dev)
1558 {
1559         struct fe_priv *np = netdev_priv(dev);
1560         u8 __iomem *base = get_hwbase(dev);
1561         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1562
1563         if (!np->mac_in_use)
1564                 tx_ctrl &= ~NVREG_XMITCTL_START;
1565         else
1566                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1567         writel(tx_ctrl, base + NvRegTransmitterControl);
1568         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1569                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1570                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1571                             __func__);
1572
1573         udelay(NV_TXSTOP_DELAY2);
1574         if (!np->mac_in_use)
1575                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1576                        base + NvRegTransmitPoll);
1577 }
1578
1579 static void nv_start_rxtx(struct net_device *dev)
1580 {
1581         nv_start_rx(dev);
1582         nv_start_tx(dev);
1583 }
1584
1585 static void nv_stop_rxtx(struct net_device *dev)
1586 {
1587         nv_stop_rx(dev);
1588         nv_stop_tx(dev);
1589 }
1590
1591 static void nv_txrx_reset(struct net_device *dev)
1592 {
1593         struct fe_priv *np = netdev_priv(dev);
1594         u8 __iomem *base = get_hwbase(dev);
1595
1596         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1597         pci_push(base);
1598         udelay(NV_TXRX_RESET_DELAY);
1599         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1600         pci_push(base);
1601 }
1602
1603 static void nv_mac_reset(struct net_device *dev)
1604 {
1605         struct fe_priv *np = netdev_priv(dev);
1606         u8 __iomem *base = get_hwbase(dev);
1607         u32 temp1, temp2, temp3;
1608
1609         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1610         pci_push(base);
1611
1612         /* save registers since they will be cleared on reset */
1613         temp1 = readl(base + NvRegMacAddrA);
1614         temp2 = readl(base + NvRegMacAddrB);
1615         temp3 = readl(base + NvRegTransmitPoll);
1616
1617         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1618         pci_push(base);
1619         udelay(NV_MAC_RESET_DELAY);
1620         writel(0, base + NvRegMacReset);
1621         pci_push(base);
1622         udelay(NV_MAC_RESET_DELAY);
1623
1624         /* restore saved registers */
1625         writel(temp1, base + NvRegMacAddrA);
1626         writel(temp2, base + NvRegMacAddrB);
1627         writel(temp3, base + NvRegTransmitPoll);
1628
1629         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630         pci_push(base);
1631 }
1632
1633 static void nv_get_hw_stats(struct net_device *dev)
1634 {
1635         struct fe_priv *np = netdev_priv(dev);
1636         u8 __iomem *base = get_hwbase(dev);
1637
1638         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1639         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1640         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1641         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1642         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1643         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1644         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1645         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1646         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1647         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1648         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1649         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1650         np->estats.rx_runt += readl(base + NvRegRxRunt);
1651         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1652         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1653         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1654         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1655         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1656         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1657         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1658         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1659         np->estats.rx_packets =
1660                 np->estats.rx_unicast +
1661                 np->estats.rx_multicast +
1662                 np->estats.rx_broadcast;
1663         np->estats.rx_errors_total =
1664                 np->estats.rx_crc_errors +
1665                 np->estats.rx_over_errors +
1666                 np->estats.rx_frame_error +
1667                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1668                 np->estats.rx_late_collision +
1669                 np->estats.rx_runt +
1670                 np->estats.rx_frame_too_long;
1671         np->estats.tx_errors_total =
1672                 np->estats.tx_late_collision +
1673                 np->estats.tx_fifo_errors +
1674                 np->estats.tx_carrier_errors +
1675                 np->estats.tx_excess_deferral +
1676                 np->estats.tx_retry_error;
1677
1678         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1679                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1680                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1681                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1682                 np->estats.tx_pause += readl(base + NvRegTxPause);
1683                 np->estats.rx_pause += readl(base + NvRegRxPause);
1684                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1685         }
1686
1687         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1688                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1689                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1690                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1691         }
1692 }
1693
1694 /*
1695  * nv_get_stats: dev->get_stats function
1696  * Get latest stats value from the nic.
1697  * Called with read_lock(&dev_base_lock) held for read -
1698  * only synchronized against unregister_netdevice.
1699  */
1700 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1701 {
1702         struct fe_priv *np = netdev_priv(dev);
1703
1704         /* If the nic supports hw counters then retrieve latest values */
1705         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1706                 nv_get_hw_stats(dev);
1707
1708                 /* copy to net_device stats */
1709                 dev->stats.tx_bytes = np->estats.tx_bytes;
1710                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1711                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1712                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1713                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1714                 dev->stats.rx_errors = np->estats.rx_errors_total;
1715                 dev->stats.tx_errors = np->estats.tx_errors_total;
1716         }
1717
1718         return &dev->stats;
1719 }
1720
1721 /*
1722  * nv_alloc_rx: fill rx ring entries.
1723  * Return 1 if the allocations for the skbs failed and the
1724  * rx engine is without Available descriptors
1725  */
1726 static int nv_alloc_rx(struct net_device *dev)
1727 {
1728         struct fe_priv *np = netdev_priv(dev);
1729         struct ring_desc *less_rx;
1730
1731         less_rx = np->get_rx.orig;
1732         if (less_rx-- == np->first_rx.orig)
1733                 less_rx = np->last_rx.orig;
1734
1735         while (np->put_rx.orig != less_rx) {
1736                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1737                 if (skb) {
1738                         np->put_rx_ctx->skb = skb;
1739                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1740                                                              skb->data,
1741                                                              skb_tailroom(skb),
1742                                                              PCI_DMA_FROMDEVICE);
1743                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1744                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1745                         wmb();
1746                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1747                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1748                                 np->put_rx.orig = np->first_rx.orig;
1749                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1750                                 np->put_rx_ctx = np->first_rx_ctx;
1751                 } else
1752                         return 1;
1753         }
1754         return 0;
1755 }
1756
1757 static int nv_alloc_rx_optimized(struct net_device *dev)
1758 {
1759         struct fe_priv *np = netdev_priv(dev);
1760         struct ring_desc_ex *less_rx;
1761
1762         less_rx = np->get_rx.ex;
1763         if (less_rx-- == np->first_rx.ex)
1764                 less_rx = np->last_rx.ex;
1765
1766         while (np->put_rx.ex != less_rx) {
1767                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1768                 if (skb) {
1769                         np->put_rx_ctx->skb = skb;
1770                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1771                                                              skb->data,
1772                                                              skb_tailroom(skb),
1773                                                              PCI_DMA_FROMDEVICE);
1774                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1775                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1776                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1777                         wmb();
1778                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1779                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1780                                 np->put_rx.ex = np->first_rx.ex;
1781                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1782                                 np->put_rx_ctx = np->first_rx_ctx;
1783                 } else
1784                         return 1;
1785         }
1786         return 0;
1787 }
1788
1789 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1790 static void nv_do_rx_refill(unsigned long data)
1791 {
1792         struct net_device *dev = (struct net_device *) data;
1793         struct fe_priv *np = netdev_priv(dev);
1794
1795         /* Just reschedule NAPI rx processing */
1796         napi_schedule(&np->napi);
1797 }
1798
1799 static void nv_init_rx(struct net_device *dev)
1800 {
1801         struct fe_priv *np = netdev_priv(dev);
1802         int i;
1803
1804         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1805
1806         if (!nv_optimized(np))
1807                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1808         else
1809                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1810         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1811         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1812
1813         for (i = 0; i < np->rx_ring_size; i++) {
1814                 if (!nv_optimized(np)) {
1815                         np->rx_ring.orig[i].flaglen = 0;
1816                         np->rx_ring.orig[i].buf = 0;
1817                 } else {
1818                         np->rx_ring.ex[i].flaglen = 0;
1819                         np->rx_ring.ex[i].txvlan = 0;
1820                         np->rx_ring.ex[i].bufhigh = 0;
1821                         np->rx_ring.ex[i].buflow = 0;
1822                 }
1823                 np->rx_skb[i].skb = NULL;
1824                 np->rx_skb[i].dma = 0;
1825         }
1826 }
1827
1828 static void nv_init_tx(struct net_device *dev)
1829 {
1830         struct fe_priv *np = netdev_priv(dev);
1831         int i;
1832
1833         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1834
1835         if (!nv_optimized(np))
1836                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1837         else
1838                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1839         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1840         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1841         np->tx_pkts_in_progress = 0;
1842         np->tx_change_owner = NULL;
1843         np->tx_end_flip = NULL;
1844         np->tx_stop = 0;
1845
1846         for (i = 0; i < np->tx_ring_size; i++) {
1847                 if (!nv_optimized(np)) {
1848                         np->tx_ring.orig[i].flaglen = 0;
1849                         np->tx_ring.orig[i].buf = 0;
1850                 } else {
1851                         np->tx_ring.ex[i].flaglen = 0;
1852                         np->tx_ring.ex[i].txvlan = 0;
1853                         np->tx_ring.ex[i].bufhigh = 0;
1854                         np->tx_ring.ex[i].buflow = 0;
1855                 }
1856                 np->tx_skb[i].skb = NULL;
1857                 np->tx_skb[i].dma = 0;
1858                 np->tx_skb[i].dma_len = 0;
1859                 np->tx_skb[i].dma_single = 0;
1860                 np->tx_skb[i].first_tx_desc = NULL;
1861                 np->tx_skb[i].next_tx_ctx = NULL;
1862         }
1863 }
1864
1865 static int nv_init_ring(struct net_device *dev)
1866 {
1867         struct fe_priv *np = netdev_priv(dev);
1868
1869         nv_init_tx(dev);
1870         nv_init_rx(dev);
1871
1872         if (!nv_optimized(np))
1873                 return nv_alloc_rx(dev);
1874         else
1875                 return nv_alloc_rx_optimized(dev);
1876 }
1877
1878 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1879 {
1880         if (tx_skb->dma) {
1881                 if (tx_skb->dma_single)
1882                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1883                                          tx_skb->dma_len,
1884                                          PCI_DMA_TODEVICE);
1885                 else
1886                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1887                                        tx_skb->dma_len,
1888                                        PCI_DMA_TODEVICE);
1889                 tx_skb->dma = 0;
1890         }
1891 }
1892
1893 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1894 {
1895         nv_unmap_txskb(np, tx_skb);
1896         if (tx_skb->skb) {
1897                 dev_kfree_skb_any(tx_skb->skb);
1898                 tx_skb->skb = NULL;
1899                 return 1;
1900         }
1901         return 0;
1902 }
1903
1904 static void nv_drain_tx(struct net_device *dev)
1905 {
1906         struct fe_priv *np = netdev_priv(dev);
1907         unsigned int i;
1908
1909         for (i = 0; i < np->tx_ring_size; i++) {
1910                 if (!nv_optimized(np)) {
1911                         np->tx_ring.orig[i].flaglen = 0;
1912                         np->tx_ring.orig[i].buf = 0;
1913                 } else {
1914                         np->tx_ring.ex[i].flaglen = 0;
1915                         np->tx_ring.ex[i].txvlan = 0;
1916                         np->tx_ring.ex[i].bufhigh = 0;
1917                         np->tx_ring.ex[i].buflow = 0;
1918                 }
1919                 if (nv_release_txskb(np, &np->tx_skb[i]))
1920                         dev->stats.tx_dropped++;
1921                 np->tx_skb[i].dma = 0;
1922                 np->tx_skb[i].dma_len = 0;
1923                 np->tx_skb[i].dma_single = 0;
1924                 np->tx_skb[i].first_tx_desc = NULL;
1925                 np->tx_skb[i].next_tx_ctx = NULL;
1926         }
1927         np->tx_pkts_in_progress = 0;
1928         np->tx_change_owner = NULL;
1929         np->tx_end_flip = NULL;
1930 }
1931
1932 static void nv_drain_rx(struct net_device *dev)
1933 {
1934         struct fe_priv *np = netdev_priv(dev);
1935         int i;
1936
1937         for (i = 0; i < np->rx_ring_size; i++) {
1938                 if (!nv_optimized(np)) {
1939                         np->rx_ring.orig[i].flaglen = 0;
1940                         np->rx_ring.orig[i].buf = 0;
1941                 } else {
1942                         np->rx_ring.ex[i].flaglen = 0;
1943                         np->rx_ring.ex[i].txvlan = 0;
1944                         np->rx_ring.ex[i].bufhigh = 0;
1945                         np->rx_ring.ex[i].buflow = 0;
1946                 }
1947                 wmb();
1948                 if (np->rx_skb[i].skb) {
1949                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1950                                          (skb_end_pointer(np->rx_skb[i].skb) -
1951                                           np->rx_skb[i].skb->data),
1952                                          PCI_DMA_FROMDEVICE);
1953                         dev_kfree_skb(np->rx_skb[i].skb);
1954                         np->rx_skb[i].skb = NULL;
1955                 }
1956         }
1957 }
1958
1959 static void nv_drain_rxtx(struct net_device *dev)
1960 {
1961         nv_drain_tx(dev);
1962         nv_drain_rx(dev);
1963 }
1964
1965 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1966 {
1967         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1968 }
1969
1970 static void nv_legacybackoff_reseed(struct net_device *dev)
1971 {
1972         u8 __iomem *base = get_hwbase(dev);
1973         u32 reg;
1974         u32 low;
1975         int tx_status = 0;
1976
1977         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1978         get_random_bytes(&low, sizeof(low));
1979         reg |= low & NVREG_SLOTTIME_MASK;
1980
1981         /* Need to stop tx before change takes effect.
1982          * Caller has already gained np->lock.
1983          */
1984         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1985         if (tx_status)
1986                 nv_stop_tx(dev);
1987         nv_stop_rx(dev);
1988         writel(reg, base + NvRegSlotTime);
1989         if (tx_status)
1990                 nv_start_tx(dev);
1991         nv_start_rx(dev);
1992 }
1993
1994 /* Gear Backoff Seeds */
1995 #define BACKOFF_SEEDSET_ROWS    8
1996 #define BACKOFF_SEEDSET_LFSRS   15
1997
1998 /* Known Good seed sets */
1999 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2000         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2001         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2002         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2003         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2004         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2005         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2006         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2007         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2008
2009 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2010         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2011         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2012         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2013         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2014         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2015         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2016         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2017         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2018
2019 static void nv_gear_backoff_reseed(struct net_device *dev)
2020 {
2021         u8 __iomem *base = get_hwbase(dev);
2022         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2023         u32 temp, seedset, combinedSeed;
2024         int i;
2025
2026         /* Setup seed for free running LFSR */
2027         /* We are going to read the time stamp counter 3 times
2028            and swizzle bits around to increase randomness */
2029         get_random_bytes(&miniseed1, sizeof(miniseed1));
2030         miniseed1 &= 0x0fff;
2031         if (miniseed1 == 0)
2032                 miniseed1 = 0xabc;
2033
2034         get_random_bytes(&miniseed2, sizeof(miniseed2));
2035         miniseed2 &= 0x0fff;
2036         if (miniseed2 == 0)
2037                 miniseed2 = 0xabc;
2038         miniseed2_reversed =
2039                 ((miniseed2 & 0xF00) >> 8) |
2040                  (miniseed2 & 0x0F0) |
2041                  ((miniseed2 & 0x00F) << 8);
2042
2043         get_random_bytes(&miniseed3, sizeof(miniseed3));
2044         miniseed3 &= 0x0fff;
2045         if (miniseed3 == 0)
2046                 miniseed3 = 0xabc;
2047         miniseed3_reversed =
2048                 ((miniseed3 & 0xF00) >> 8) |
2049                  (miniseed3 & 0x0F0) |
2050                  ((miniseed3 & 0x00F) << 8);
2051
2052         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2053                        (miniseed2 ^ miniseed3_reversed);
2054
2055         /* Seeds can not be zero */
2056         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2057                 combinedSeed |= 0x08;
2058         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2059                 combinedSeed |= 0x8000;
2060
2061         /* No need to disable tx here */
2062         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2063         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2064         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2065         writel(temp, base + NvRegBackOffControl);
2066
2067         /* Setup seeds for all gear LFSRs. */
2068         get_random_bytes(&seedset, sizeof(seedset));
2069         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2070         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2071                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2072                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2073                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2074                 writel(temp, base + NvRegBackOffControl);
2075         }
2076 }
2077
2078 /*
2079  * nv_start_xmit: dev->hard_start_xmit function
2080  * Called with netif_tx_lock held.
2081  */
2082 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2083 {
2084         struct fe_priv *np = netdev_priv(dev);
2085         u32 tx_flags = 0;
2086         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2087         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2088         unsigned int i;
2089         u32 offset = 0;
2090         u32 bcnt;
2091         u32 size = skb_headlen(skb);
2092         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2093         u32 empty_slots;
2094         struct ring_desc *put_tx;
2095         struct ring_desc *start_tx;
2096         struct ring_desc *prev_tx;
2097         struct nv_skb_map *prev_tx_ctx;
2098         unsigned long flags;
2099
2100         /* add fragments to entries count */
2101         for (i = 0; i < fragments; i++) {
2102                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2103                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2104         }
2105
2106         spin_lock_irqsave(&np->lock, flags);
2107         empty_slots = nv_get_empty_tx_slots(np);
2108         if (unlikely(empty_slots <= entries)) {
2109                 netif_stop_queue(dev);
2110                 np->tx_stop = 1;
2111                 spin_unlock_irqrestore(&np->lock, flags);
2112                 return NETDEV_TX_BUSY;
2113         }
2114         spin_unlock_irqrestore(&np->lock, flags);
2115
2116         start_tx = put_tx = np->put_tx.orig;
2117
2118         /* setup the header buffer */
2119         do {
2120                 prev_tx = put_tx;
2121                 prev_tx_ctx = np->put_tx_ctx;
2122                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2123                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2124                                                 PCI_DMA_TODEVICE);
2125                 np->put_tx_ctx->dma_len = bcnt;
2126                 np->put_tx_ctx->dma_single = 1;
2127                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2128                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2129
2130                 tx_flags = np->tx_flags;
2131                 offset += bcnt;
2132                 size -= bcnt;
2133                 if (unlikely(put_tx++ == np->last_tx.orig))
2134                         put_tx = np->first_tx.orig;
2135                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2136                         np->put_tx_ctx = np->first_tx_ctx;
2137         } while (size);
2138
2139         /* setup the fragments */
2140         for (i = 0; i < fragments; i++) {
2141                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2142                 u32 size = frag->size;
2143                 offset = 0;
2144
2145                 do {
2146                         prev_tx = put_tx;
2147                         prev_tx_ctx = np->put_tx_ctx;
2148                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2149                         np->put_tx_ctx->dma = skb_frag_dma_map(
2150                                                         &np->pci_dev->dev,
2151                                                         frag, offset,
2152                                                         bcnt,
2153                                                         DMA_TO_DEVICE);
2154                         np->put_tx_ctx->dma_len = bcnt;
2155                         np->put_tx_ctx->dma_single = 0;
2156                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2157                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2158
2159                         offset += bcnt;
2160                         size -= bcnt;
2161                         if (unlikely(put_tx++ == np->last_tx.orig))
2162                                 put_tx = np->first_tx.orig;
2163                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2164                                 np->put_tx_ctx = np->first_tx_ctx;
2165                 } while (size);
2166         }
2167
2168         /* set last fragment flag  */
2169         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2170
2171         /* save skb in this slot's context area */
2172         prev_tx_ctx->skb = skb;
2173
2174         if (skb_is_gso(skb))
2175                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2176         else
2177                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2178                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2179
2180         spin_lock_irqsave(&np->lock, flags);
2181
2182         /* set tx flags */
2183         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2184         np->put_tx.orig = put_tx;
2185
2186         spin_unlock_irqrestore(&np->lock, flags);
2187
2188         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2189         return NETDEV_TX_OK;
2190 }
2191
2192 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2193                                            struct net_device *dev)
2194 {
2195         struct fe_priv *np = netdev_priv(dev);
2196         u32 tx_flags = 0;
2197         u32 tx_flags_extra;
2198         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2199         unsigned int i;
2200         u32 offset = 0;
2201         u32 bcnt;
2202         u32 size = skb_headlen(skb);
2203         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2204         u32 empty_slots;
2205         struct ring_desc_ex *put_tx;
2206         struct ring_desc_ex *start_tx;
2207         struct ring_desc_ex *prev_tx;
2208         struct nv_skb_map *prev_tx_ctx;
2209         struct nv_skb_map *start_tx_ctx;
2210         unsigned long flags;
2211
2212         /* add fragments to entries count */
2213         for (i = 0; i < fragments; i++) {
2214                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2215                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2216         }
2217
2218         spin_lock_irqsave(&np->lock, flags);
2219         empty_slots = nv_get_empty_tx_slots(np);
2220         if (unlikely(empty_slots <= entries)) {
2221                 netif_stop_queue(dev);
2222                 np->tx_stop = 1;
2223                 spin_unlock_irqrestore(&np->lock, flags);
2224                 return NETDEV_TX_BUSY;
2225         }
2226         spin_unlock_irqrestore(&np->lock, flags);
2227
2228         start_tx = put_tx = np->put_tx.ex;
2229         start_tx_ctx = np->put_tx_ctx;
2230
2231         /* setup the header buffer */
2232         do {
2233                 prev_tx = put_tx;
2234                 prev_tx_ctx = np->put_tx_ctx;
2235                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2236                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2237                                                 PCI_DMA_TODEVICE);
2238                 np->put_tx_ctx->dma_len = bcnt;
2239                 np->put_tx_ctx->dma_single = 1;
2240                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2241                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2242                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2243
2244                 tx_flags = NV_TX2_VALID;
2245                 offset += bcnt;
2246                 size -= bcnt;
2247                 if (unlikely(put_tx++ == np->last_tx.ex))
2248                         put_tx = np->first_tx.ex;
2249                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2250                         np->put_tx_ctx = np->first_tx_ctx;
2251         } while (size);
2252
2253         /* setup the fragments */
2254         for (i = 0; i < fragments; i++) {
2255                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2256                 u32 size = frag->size;
2257                 offset = 0;
2258
2259                 do {
2260                         prev_tx = put_tx;
2261                         prev_tx_ctx = np->put_tx_ctx;
2262                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2263                         np->put_tx_ctx->dma = skb_frag_dma_map(
2264                                                         &np->pci_dev->dev,
2265                                                         frag, offset,
2266                                                         bcnt,
2267                                                         DMA_TO_DEVICE);
2268                         np->put_tx_ctx->dma_len = bcnt;
2269                         np->put_tx_ctx->dma_single = 0;
2270                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2271                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2272                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2273
2274                         offset += bcnt;
2275                         size -= bcnt;
2276                         if (unlikely(put_tx++ == np->last_tx.ex))
2277                                 put_tx = np->first_tx.ex;
2278                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2279                                 np->put_tx_ctx = np->first_tx_ctx;
2280                 } while (size);
2281         }
2282
2283         /* set last fragment flag  */
2284         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2285
2286         /* save skb in this slot's context area */
2287         prev_tx_ctx->skb = skb;
2288
2289         if (skb_is_gso(skb))
2290                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2291         else
2292                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2293                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2294
2295         /* vlan tag */
2296         if (vlan_tx_tag_present(skb))
2297                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2298                                         vlan_tx_tag_get(skb));
2299         else
2300                 start_tx->txvlan = 0;
2301
2302         spin_lock_irqsave(&np->lock, flags);
2303
2304         if (np->tx_limit) {
2305                 /* Limit the number of outstanding tx. Setup all fragments, but
2306                  * do not set the VALID bit on the first descriptor. Save a pointer
2307                  * to that descriptor and also for next skb_map element.
2308                  */
2309
2310                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2311                         if (!np->tx_change_owner)
2312                                 np->tx_change_owner = start_tx_ctx;
2313
2314                         /* remove VALID bit */
2315                         tx_flags &= ~NV_TX2_VALID;
2316                         start_tx_ctx->first_tx_desc = start_tx;
2317                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2318                         np->tx_end_flip = np->put_tx_ctx;
2319                 } else {
2320                         np->tx_pkts_in_progress++;
2321                 }
2322         }
2323
2324         /* set tx flags */
2325         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2326         np->put_tx.ex = put_tx;
2327
2328         spin_unlock_irqrestore(&np->lock, flags);
2329
2330         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2331         return NETDEV_TX_OK;
2332 }
2333
2334 static inline void nv_tx_flip_ownership(struct net_device *dev)
2335 {
2336         struct fe_priv *np = netdev_priv(dev);
2337
2338         np->tx_pkts_in_progress--;
2339         if (np->tx_change_owner) {
2340                 np->tx_change_owner->first_tx_desc->flaglen |=
2341                         cpu_to_le32(NV_TX2_VALID);
2342                 np->tx_pkts_in_progress++;
2343
2344                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2345                 if (np->tx_change_owner == np->tx_end_flip)
2346                         np->tx_change_owner = NULL;
2347
2348                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2349         }
2350 }
2351
2352 /*
2353  * nv_tx_done: check for completed packets, release the skbs.
2354  *
2355  * Caller must own np->lock.
2356  */
2357 static int nv_tx_done(struct net_device *dev, int limit)
2358 {
2359         struct fe_priv *np = netdev_priv(dev);
2360         u32 flags;
2361         int tx_work = 0;
2362         struct ring_desc *orig_get_tx = np->get_tx.orig;
2363
2364         while ((np->get_tx.orig != np->put_tx.orig) &&
2365                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2366                (tx_work < limit)) {
2367
2368                 nv_unmap_txskb(np, np->get_tx_ctx);
2369
2370                 if (np->desc_ver == DESC_VER_1) {
2371                         if (flags & NV_TX_LASTPACKET) {
2372                                 if (flags & NV_TX_ERROR) {
2373                                         if (flags & NV_TX_UNDERFLOW)
2374                                                 dev->stats.tx_fifo_errors++;
2375                                         if (flags & NV_TX_CARRIERLOST)
2376                                                 dev->stats.tx_carrier_errors++;
2377                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2378                                                 nv_legacybackoff_reseed(dev);
2379                                         dev->stats.tx_errors++;
2380                                 } else {
2381                                         dev->stats.tx_packets++;
2382                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2383                                 }
2384                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2385                                 np->get_tx_ctx->skb = NULL;
2386                                 tx_work++;
2387                         }
2388                 } else {
2389                         if (flags & NV_TX2_LASTPACKET) {
2390                                 if (flags & NV_TX2_ERROR) {
2391                                         if (flags & NV_TX2_UNDERFLOW)
2392                                                 dev->stats.tx_fifo_errors++;
2393                                         if (flags & NV_TX2_CARRIERLOST)
2394                                                 dev->stats.tx_carrier_errors++;
2395                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2396                                                 nv_legacybackoff_reseed(dev);
2397                                         dev->stats.tx_errors++;
2398                                 } else {
2399                                         dev->stats.tx_packets++;
2400                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2401                                 }
2402                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2403                                 np->get_tx_ctx->skb = NULL;
2404                                 tx_work++;
2405                         }
2406                 }
2407                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2408                         np->get_tx.orig = np->first_tx.orig;
2409                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2410                         np->get_tx_ctx = np->first_tx_ctx;
2411         }
2412         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2413                 np->tx_stop = 0;
2414                 netif_wake_queue(dev);
2415         }
2416         return tx_work;
2417 }
2418
2419 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2420 {
2421         struct fe_priv *np = netdev_priv(dev);
2422         u32 flags;
2423         int tx_work = 0;
2424         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2425
2426         while ((np->get_tx.ex != np->put_tx.ex) &&
2427                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2428                (tx_work < limit)) {
2429
2430                 nv_unmap_txskb(np, np->get_tx_ctx);
2431
2432                 if (flags & NV_TX2_LASTPACKET) {
2433                         if (!(flags & NV_TX2_ERROR))
2434                                 dev->stats.tx_packets++;
2435                         else {
2436                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2437                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2438                                                 nv_gear_backoff_reseed(dev);
2439                                         else
2440                                                 nv_legacybackoff_reseed(dev);
2441                                 }
2442                         }
2443
2444                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2445                         np->get_tx_ctx->skb = NULL;
2446                         tx_work++;
2447
2448                         if (np->tx_limit)
2449                                 nv_tx_flip_ownership(dev);
2450                 }
2451                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2452                         np->get_tx.ex = np->first_tx.ex;
2453                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2454                         np->get_tx_ctx = np->first_tx_ctx;
2455         }
2456         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2457                 np->tx_stop = 0;
2458                 netif_wake_queue(dev);
2459         }
2460         return tx_work;
2461 }
2462
2463 /*
2464  * nv_tx_timeout: dev->tx_timeout function
2465  * Called with netif_tx_lock held.
2466  */
2467 static void nv_tx_timeout(struct net_device *dev)
2468 {
2469         struct fe_priv *np = netdev_priv(dev);
2470         u8 __iomem *base = get_hwbase(dev);
2471         u32 status;
2472         union ring_type put_tx;
2473         int saved_tx_limit;
2474         int i;
2475
2476         if (np->msi_flags & NV_MSI_X_ENABLED)
2477                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2478         else
2479                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2480
2481         netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2482
2483         netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2484         netdev_info(dev, "Dumping tx registers\n");
2485         for (i = 0; i <= np->register_size; i += 32) {
2486                 netdev_info(dev,
2487                             "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2488                             i,
2489                             readl(base + i + 0), readl(base + i + 4),
2490                             readl(base + i + 8), readl(base + i + 12),
2491                             readl(base + i + 16), readl(base + i + 20),
2492                             readl(base + i + 24), readl(base + i + 28));
2493         }
2494         netdev_info(dev, "Dumping tx ring\n");
2495         for (i = 0; i < np->tx_ring_size; i += 4) {
2496                 if (!nv_optimized(np)) {
2497                         netdev_info(dev,
2498                                     "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2499                                     i,
2500                                     le32_to_cpu(np->tx_ring.orig[i].buf),
2501                                     le32_to_cpu(np->tx_ring.orig[i].flaglen),
2502                                     le32_to_cpu(np->tx_ring.orig[i+1].buf),
2503                                     le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2504                                     le32_to_cpu(np->tx_ring.orig[i+2].buf),
2505                                     le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2506                                     le32_to_cpu(np->tx_ring.orig[i+3].buf),
2507                                     le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2508                 } else {
2509                         netdev_info(dev,
2510                                     "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2511                                     i,
2512                                     le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2513                                     le32_to_cpu(np->tx_ring.ex[i].buflow),
2514                                     le32_to_cpu(np->tx_ring.ex[i].flaglen),
2515                                     le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2516                                     le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2517                                     le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2518                                     le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2519                                     le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2520                                     le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2521                                     le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2522                                     le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2523                                     le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2524                 }
2525         }
2526
2527         spin_lock_irq(&np->lock);
2528
2529         /* 1) stop tx engine */
2530         nv_stop_tx(dev);
2531
2532         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2533         saved_tx_limit = np->tx_limit;
2534         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2535         np->tx_stop = 0;  /* prevent waking tx queue */
2536         if (!nv_optimized(np))
2537                 nv_tx_done(dev, np->tx_ring_size);
2538         else
2539                 nv_tx_done_optimized(dev, np->tx_ring_size);
2540
2541         /* save current HW position */
2542         if (np->tx_change_owner)
2543                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2544         else
2545                 put_tx = np->put_tx;
2546
2547         /* 3) clear all tx state */
2548         nv_drain_tx(dev);
2549         nv_init_tx(dev);
2550
2551         /* 4) restore state to current HW position */
2552         np->get_tx = np->put_tx = put_tx;
2553         np->tx_limit = saved_tx_limit;
2554
2555         /* 5) restart tx engine */
2556         nv_start_tx(dev);
2557         netif_wake_queue(dev);
2558         spin_unlock_irq(&np->lock);
2559 }
2560
2561 /*
2562  * Called when the nic notices a mismatch between the actual data len on the
2563  * wire and the len indicated in the 802 header
2564  */
2565 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2566 {
2567         int hdrlen;     /* length of the 802 header */
2568         int protolen;   /* length as stored in the proto field */
2569
2570         /* 1) calculate len according to header */
2571         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2572                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2573                 hdrlen = VLAN_HLEN;
2574         } else {
2575                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2576                 hdrlen = ETH_HLEN;
2577         }
2578         if (protolen > ETH_DATA_LEN)
2579                 return datalen; /* Value in proto field not a len, no checks possible */
2580
2581         protolen += hdrlen;
2582         /* consistency checks: */
2583         if (datalen > ETH_ZLEN) {
2584                 if (datalen >= protolen) {
2585                         /* more data on wire than in 802 header, trim of
2586                          * additional data.
2587                          */
2588                         return protolen;
2589                 } else {
2590                         /* less data on wire than mentioned in header.
2591                          * Discard the packet.
2592                          */
2593                         return -1;
2594                 }
2595         } else {
2596                 /* short packet. Accept only if 802 values are also short */
2597                 if (protolen > ETH_ZLEN) {
2598                         return -1;
2599                 }
2600                 return datalen;
2601         }
2602 }
2603
2604 static int nv_rx_process(struct net_device *dev, int limit)
2605 {
2606         struct fe_priv *np = netdev_priv(dev);
2607         u32 flags;
2608         int rx_work = 0;
2609         struct sk_buff *skb;
2610         int len;
2611
2612         while ((np->get_rx.orig != np->put_rx.orig) &&
2613               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2614                 (rx_work < limit)) {
2615
2616                 /*
2617                  * the packet is for us - immediately tear down the pci mapping.
2618                  * TODO: check if a prefetch of the first cacheline improves
2619                  * the performance.
2620                  */
2621                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2622                                 np->get_rx_ctx->dma_len,
2623                                 PCI_DMA_FROMDEVICE);
2624                 skb = np->get_rx_ctx->skb;
2625                 np->get_rx_ctx->skb = NULL;
2626
2627                 /* look at what we actually got: */
2628                 if (np->desc_ver == DESC_VER_1) {
2629                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2630                                 len = flags & LEN_MASK_V1;
2631                                 if (unlikely(flags & NV_RX_ERROR)) {
2632                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2633                                                 len = nv_getlen(dev, skb->data, len);
2634                                                 if (len < 0) {
2635                                                         dev->stats.rx_errors++;
2636                                                         dev_kfree_skb(skb);
2637                                                         goto next_pkt;
2638                                                 }
2639                                         }
2640                                         /* framing errors are soft errors */
2641                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2642                                                 if (flags & NV_RX_SUBSTRACT1)
2643                                                         len--;
2644                                         }
2645                                         /* the rest are hard errors */
2646                                         else {
2647                                                 if (flags & NV_RX_MISSEDFRAME)
2648                                                         dev->stats.rx_missed_errors++;
2649                                                 if (flags & NV_RX_CRCERR)
2650                                                         dev->stats.rx_crc_errors++;
2651                                                 if (flags & NV_RX_OVERFLOW)
2652                                                         dev->stats.rx_over_errors++;
2653                                                 dev->stats.rx_errors++;
2654                                                 dev_kfree_skb(skb);
2655                                                 goto next_pkt;
2656                                         }
2657                                 }
2658                         } else {
2659                                 dev_kfree_skb(skb);
2660                                 goto next_pkt;
2661                         }
2662                 } else {
2663                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2664                                 len = flags & LEN_MASK_V2;
2665                                 if (unlikely(flags & NV_RX2_ERROR)) {
2666                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2667                                                 len = nv_getlen(dev, skb->data, len);
2668                                                 if (len < 0) {
2669                                                         dev->stats.rx_errors++;
2670                                                         dev_kfree_skb(skb);
2671                                                         goto next_pkt;
2672                                                 }
2673                                         }
2674                                         /* framing errors are soft errors */
2675                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2676                                                 if (flags & NV_RX2_SUBSTRACT1)
2677                                                         len--;
2678                                         }
2679                                         /* the rest are hard errors */
2680                                         else {
2681                                                 if (flags & NV_RX2_CRCERR)
2682                                                         dev->stats.rx_crc_errors++;
2683                                                 if (flags & NV_RX2_OVERFLOW)
2684                                                         dev->stats.rx_over_errors++;
2685                                                 dev->stats.rx_errors++;
2686                                                 dev_kfree_skb(skb);
2687                                                 goto next_pkt;
2688                                         }
2689                                 }
2690                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2691                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2692                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2693                         } else {
2694                                 dev_kfree_skb(skb);
2695                                 goto next_pkt;
2696                         }
2697                 }
2698                 /* got a valid packet - forward it to the network core */
2699                 skb_put(skb, len);
2700                 skb->protocol = eth_type_trans(skb, dev);
2701                 napi_gro_receive(&np->napi, skb);
2702                 dev->stats.rx_packets++;
2703                 dev->stats.rx_bytes += len;
2704 next_pkt:
2705                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2706                         np->get_rx.orig = np->first_rx.orig;
2707                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2708                         np->get_rx_ctx = np->first_rx_ctx;
2709
2710                 rx_work++;
2711         }
2712
2713         return rx_work;
2714 }
2715
2716 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2717 {
2718         struct fe_priv *np = netdev_priv(dev);
2719         u32 flags;
2720         u32 vlanflags = 0;
2721         int rx_work = 0;
2722         struct sk_buff *skb;
2723         int len;
2724
2725         while ((np->get_rx.ex != np->put_rx.ex) &&
2726               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2727               (rx_work < limit)) {
2728
2729                 /*
2730                  * the packet is for us - immediately tear down the pci mapping.
2731                  * TODO: check if a prefetch of the first cacheline improves
2732                  * the performance.
2733                  */
2734                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2735                                 np->get_rx_ctx->dma_len,
2736                                 PCI_DMA_FROMDEVICE);
2737                 skb = np->get_rx_ctx->skb;
2738                 np->get_rx_ctx->skb = NULL;
2739
2740                 /* look at what we actually got: */
2741                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2742                         len = flags & LEN_MASK_V2;
2743                         if (unlikely(flags & NV_RX2_ERROR)) {
2744                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2745                                         len = nv_getlen(dev, skb->data, len);
2746                                         if (len < 0) {
2747                                                 dev_kfree_skb(skb);
2748                                                 goto next_pkt;
2749                                         }
2750                                 }
2751                                 /* framing errors are soft errors */
2752                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2753                                         if (flags & NV_RX2_SUBSTRACT1)
2754                                                 len--;
2755                                 }
2756                                 /* the rest are hard errors */
2757                                 else {
2758                                         dev_kfree_skb(skb);
2759                                         goto next_pkt;
2760                                 }
2761                         }
2762
2763                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2764                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2765                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2766
2767                         /* got a valid packet - forward it to the network core */
2768                         skb_put(skb, len);
2769                         skb->protocol = eth_type_trans(skb, dev);
2770                         prefetch(skb->data);
2771
2772                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2773
2774                         /*
2775                          * There's need to check for NETIF_F_HW_VLAN_RX here.
2776                          * Even if vlan rx accel is disabled,
2777                          * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2778                          */
2779                         if (dev->features & NETIF_F_HW_VLAN_RX &&
2780                             vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2781                                 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2782
2783                                 __vlan_hwaccel_put_tag(skb, vid);
2784                         }
2785                         napi_gro_receive(&np->napi, skb);
2786
2787                         dev->stats.rx_packets++;
2788                         dev->stats.rx_bytes += len;
2789                 } else {
2790                         dev_kfree_skb(skb);
2791                 }
2792 next_pkt:
2793                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2794                         np->get_rx.ex = np->first_rx.ex;
2795                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2796                         np->get_rx_ctx = np->first_rx_ctx;
2797
2798                 rx_work++;
2799         }
2800
2801         return rx_work;
2802 }
2803
2804 static void set_bufsize(struct net_device *dev)
2805 {
2806         struct fe_priv *np = netdev_priv(dev);
2807
2808         if (dev->mtu <= ETH_DATA_LEN)
2809                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2810         else
2811                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2812 }
2813
2814 /*
2815  * nv_change_mtu: dev->change_mtu function
2816  * Called with dev_base_lock held for read.
2817  */
2818 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2819 {
2820         struct fe_priv *np = netdev_priv(dev);
2821         int old_mtu;
2822
2823         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2824                 return -EINVAL;
2825
2826         old_mtu = dev->mtu;
2827         dev->mtu = new_mtu;
2828
2829         /* return early if the buffer sizes will not change */
2830         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2831                 return 0;
2832         if (old_mtu == new_mtu)
2833                 return 0;
2834
2835         /* synchronized against open : rtnl_lock() held by caller */
2836         if (netif_running(dev)) {
2837                 u8 __iomem *base = get_hwbase(dev);
2838                 /*
2839                  * It seems that the nic preloads valid ring entries into an
2840                  * internal buffer. The procedure for flushing everything is
2841                  * guessed, there is probably a simpler approach.
2842                  * Changing the MTU is a rare event, it shouldn't matter.
2843                  */
2844                 nv_disable_irq(dev);
2845                 nv_napi_disable(dev);
2846                 netif_tx_lock_bh(dev);
2847                 netif_addr_lock(dev);
2848                 spin_lock(&np->lock);
2849                 /* stop engines */
2850                 nv_stop_rxtx(dev);
2851                 nv_txrx_reset(dev);
2852                 /* drain rx queue */
2853                 nv_drain_rxtx(dev);
2854                 /* reinit driver view of the rx queue */
2855                 set_bufsize(dev);
2856                 if (nv_init_ring(dev)) {
2857                         if (!np->in_shutdown)
2858                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2859                 }
2860                 /* reinit nic view of the rx queue */
2861                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2862                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2863                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2864                         base + NvRegRingSizes);
2865                 pci_push(base);
2866                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2867                 pci_push(base);
2868
2869                 /* restart rx engine */
2870                 nv_start_rxtx(dev);
2871                 spin_unlock(&np->lock);
2872                 netif_addr_unlock(dev);
2873                 netif_tx_unlock_bh(dev);
2874                 nv_napi_enable(dev);
2875                 nv_enable_irq(dev);
2876         }
2877         return 0;
2878 }
2879
2880 static void nv_copy_mac_to_hw(struct net_device *dev)
2881 {
2882         u8 __iomem *base = get_hwbase(dev);
2883         u32 mac[2];
2884
2885         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2886                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2887         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2888
2889         writel(mac[0], base + NvRegMacAddrA);
2890         writel(mac[1], base + NvRegMacAddrB);
2891 }
2892
2893 /*
2894  * nv_set_mac_address: dev->set_mac_address function
2895  * Called with rtnl_lock() held.
2896  */
2897 static int nv_set_mac_address(struct net_device *dev, void *addr)
2898 {
2899         struct fe_priv *np = netdev_priv(dev);
2900         struct sockaddr *macaddr = (struct sockaddr *)addr;
2901
2902         if (!is_valid_ether_addr(macaddr->sa_data))
2903                 return -EADDRNOTAVAIL;
2904
2905         /* synchronized against open : rtnl_lock() held by caller */
2906         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2907
2908         if (netif_running(dev)) {
2909                 netif_tx_lock_bh(dev);
2910                 netif_addr_lock(dev);
2911                 spin_lock_irq(&np->lock);
2912
2913                 /* stop rx engine */
2914                 nv_stop_rx(dev);
2915
2916                 /* set mac address */
2917                 nv_copy_mac_to_hw(dev);
2918
2919                 /* restart rx engine */
2920                 nv_start_rx(dev);
2921                 spin_unlock_irq(&np->lock);
2922                 netif_addr_unlock(dev);
2923                 netif_tx_unlock_bh(dev);
2924         } else {
2925                 nv_copy_mac_to_hw(dev);
2926         }
2927         return 0;
2928 }
2929
2930 /*
2931  * nv_set_multicast: dev->set_multicast function
2932  * Called with netif_tx_lock held.
2933  */
2934 static void nv_set_multicast(struct net_device *dev)
2935 {
2936         struct fe_priv *np = netdev_priv(dev);
2937         u8 __iomem *base = get_hwbase(dev);
2938         u32 addr[2];
2939         u32 mask[2];
2940         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2941
2942         memset(addr, 0, sizeof(addr));
2943         memset(mask, 0, sizeof(mask));
2944
2945         if (dev->flags & IFF_PROMISC) {
2946                 pff |= NVREG_PFF_PROMISC;
2947         } else {
2948                 pff |= NVREG_PFF_MYADDR;
2949
2950                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2951                         u32 alwaysOff[2];
2952                         u32 alwaysOn[2];
2953
2954                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2955                         if (dev->flags & IFF_ALLMULTI) {
2956                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2957                         } else {
2958                                 struct netdev_hw_addr *ha;
2959
2960                                 netdev_for_each_mc_addr(ha, dev) {
2961                                         unsigned char *addr = ha->addr;
2962                                         u32 a, b;
2963
2964                                         a = le32_to_cpu(*(__le32 *) addr);
2965                                         b = le16_to_cpu(*(__le16 *) (&addr[4]));
2966                                         alwaysOn[0] &= a;
2967                                         alwaysOff[0] &= ~a;
2968                                         alwaysOn[1] &= b;
2969                                         alwaysOff[1] &= ~b;
2970                                 }
2971                         }
2972                         addr[0] = alwaysOn[0];
2973                         addr[1] = alwaysOn[1];
2974                         mask[0] = alwaysOn[0] | alwaysOff[0];
2975                         mask[1] = alwaysOn[1] | alwaysOff[1];
2976                 } else {
2977                         mask[0] = NVREG_MCASTMASKA_NONE;
2978                         mask[1] = NVREG_MCASTMASKB_NONE;
2979                 }
2980         }
2981         addr[0] |= NVREG_MCASTADDRA_FORCE;
2982         pff |= NVREG_PFF_ALWAYS;
2983         spin_lock_irq(&np->lock);
2984         nv_stop_rx(dev);
2985         writel(addr[0], base + NvRegMulticastAddrA);
2986         writel(addr[1], base + NvRegMulticastAddrB);
2987         writel(mask[0], base + NvRegMulticastMaskA);
2988         writel(mask[1], base + NvRegMulticastMaskB);
2989         writel(pff, base + NvRegPacketFilterFlags);
2990         nv_start_rx(dev);
2991         spin_unlock_irq(&np->lock);
2992 }
2993
2994 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2995 {
2996         struct fe_priv *np = netdev_priv(dev);
2997         u8 __iomem *base = get_hwbase(dev);
2998
2999         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3000
3001         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3002                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3003                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3004                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3005                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3006                 } else {
3007                         writel(pff, base + NvRegPacketFilterFlags);
3008                 }
3009         }
3010         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3011                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3012                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3013                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3014                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3015                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3016                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3017                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3018                                 /* limit the number of tx pause frames to a default of 8 */
3019                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3020                         }
3021                         writel(pause_enable,  base + NvRegTxPauseFrame);
3022                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3023                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3024                 } else {
3025                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3026                         writel(regmisc, base + NvRegMisc1);
3027                 }
3028         }
3029 }
3030
3031 /**
3032  * nv_update_linkspeed: Setup the MAC according to the link partner
3033  * @dev: Network device to be configured
3034  *
3035  * The function queries the PHY and checks if there is a link partner.
3036  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3037  * set to 10 MBit HD.
3038  *
3039  * The function returns 0 if there is no link partner and 1 if there is
3040  * a good link partner.
3041  */
3042 static int nv_update_linkspeed(struct net_device *dev)
3043 {
3044         struct fe_priv *np = netdev_priv(dev);
3045         u8 __iomem *base = get_hwbase(dev);
3046         int adv = 0;
3047         int lpa = 0;
3048         int adv_lpa, adv_pause, lpa_pause;
3049         int newls = np->linkspeed;
3050         int newdup = np->duplex;
3051         int mii_status;
3052         int retval = 0;
3053         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3054         u32 txrxFlags = 0;
3055         u32 phy_exp;
3056
3057         /* BMSR_LSTATUS is latched, read it twice:
3058          * we want the current value.
3059          */
3060         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3061         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3062
3063         if (!(mii_status & BMSR_LSTATUS)) {
3064                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3065                 newdup = 0;
3066                 retval = 0;
3067                 goto set_speed;
3068         }
3069
3070         if (np->autoneg == 0) {
3071                 if (np->fixed_mode & LPA_100FULL) {
3072                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3073                         newdup = 1;
3074                 } else if (np->fixed_mode & LPA_100HALF) {
3075                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3076                         newdup = 0;
3077                 } else if (np->fixed_mode & LPA_10FULL) {
3078                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3079                         newdup = 1;
3080                 } else {
3081                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3082                         newdup = 0;
3083                 }
3084                 retval = 1;
3085                 goto set_speed;
3086         }
3087         /* check auto negotiation is complete */
3088         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3089                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3090                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3091                 newdup = 0;
3092                 retval = 0;
3093                 goto set_speed;
3094         }
3095
3096         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3097         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3098
3099         retval = 1;
3100         if (np->gigabit == PHY_GIGABIT) {
3101                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3102                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3103
3104                 if ((control_1000 & ADVERTISE_1000FULL) &&
3105                         (status_1000 & LPA_1000FULL)) {
3106                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3107                         newdup = 1;
3108                         goto set_speed;
3109                 }
3110         }
3111
3112         /* FIXME: handle parallel detection properly */
3113         adv_lpa = lpa & adv;
3114         if (adv_lpa & LPA_100FULL) {
3115                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3116                 newdup = 1;
3117         } else if (adv_lpa & LPA_100HALF) {
3118                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3119                 newdup = 0;
3120         } else if (adv_lpa & LPA_10FULL) {
3121                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3122                 newdup = 1;
3123         } else if (adv_lpa & LPA_10HALF) {
3124                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3125                 newdup = 0;
3126         } else {
3127                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3128                 newdup = 0;
3129         }
3130
3131 set_speed:
3132         if (np->duplex == newdup && np->linkspeed == newls)
3133                 return retval;
3134
3135         np->duplex = newdup;
3136         np->linkspeed = newls;
3137
3138         /* The transmitter and receiver must be restarted for safe update */
3139         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3140                 txrxFlags |= NV_RESTART_TX;
3141                 nv_stop_tx(dev);
3142         }
3143         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3144                 txrxFlags |= NV_RESTART_RX;
3145                 nv_stop_rx(dev);
3146         }
3147
3148         if (np->gigabit == PHY_GIGABIT) {
3149                 phyreg = readl(base + NvRegSlotTime);
3150                 phyreg &= ~(0x3FF00);
3151                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3152                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3153                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3154                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3155                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3156                 writel(phyreg, base + NvRegSlotTime);
3157         }
3158
3159         phyreg = readl(base + NvRegPhyInterface);
3160         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3161         if (np->duplex == 0)
3162                 phyreg |= PHY_HALF;
3163         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3164                 phyreg |= PHY_100;
3165         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3166                 phyreg |= PHY_1000;
3167         writel(phyreg, base + NvRegPhyInterface);
3168
3169         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3170         if (phyreg & PHY_RGMII) {
3171                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3172                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3173                 } else {
3174                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3175                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3176                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3177                                 else
3178                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3179                         } else {
3180                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3181                         }
3182                 }
3183         } else {
3184                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3185                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3186                 else
3187                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3188         }
3189         writel(txreg, base + NvRegTxDeferral);
3190
3191         if (np->desc_ver == DESC_VER_1) {
3192                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3193         } else {
3194                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3195                         txreg = NVREG_TX_WM_DESC2_3_1000;
3196                 else
3197                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3198         }
3199         writel(txreg, base + NvRegTxWatermark);
3200
3201         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3202                 base + NvRegMisc1);
3203         pci_push(base);
3204         writel(np->linkspeed, base + NvRegLinkSpeed);
3205         pci_push(base);
3206
3207         pause_flags = 0;
3208         /* setup pause frame */
3209         if (np->duplex != 0) {
3210                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3211                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3212                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3213
3214                         switch (adv_pause) {
3215                         case ADVERTISE_PAUSE_CAP:
3216                                 if (lpa_pause & LPA_PAUSE_CAP) {
3217                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3218                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3219                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3220                                 }
3221                                 break;
3222                         case ADVERTISE_PAUSE_ASYM:
3223                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3224                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3225                                 break;
3226                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3227                                 if (lpa_pause & LPA_PAUSE_CAP) {
3228                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3229                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3230                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3231                                 }
3232                                 if (lpa_pause == LPA_PAUSE_ASYM)
3233                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3234                                 break;
3235                         }
3236                 } else {
3237                         pause_flags = np->pause_flags;
3238                 }
3239         }
3240         nv_update_pause(dev, pause_flags);
3241
3242         if (txrxFlags & NV_RESTART_TX)
3243                 nv_start_tx(dev);
3244         if (txrxFlags & NV_RESTART_RX)
3245                 nv_start_rx(dev);
3246
3247         return retval;
3248 }
3249
3250 static void nv_linkchange(struct net_device *dev)
3251 {
3252         if (nv_update_linkspeed(dev)) {
3253                 if (!netif_carrier_ok(dev)) {
3254                         netif_carrier_on(dev);
3255                         netdev_info(dev, "link up\n");
3256                         nv_txrx_gate(dev, false);
3257                         nv_start_rx(dev);
3258                 }
3259         } else {
3260                 if (netif_carrier_ok(dev)) {
3261                         netif_carrier_off(dev);
3262                         netdev_info(dev, "link down\n");
3263                         nv_txrx_gate(dev, true);
3264                         nv_stop_rx(dev);
3265                 }
3266         }
3267 }
3268
3269 static void nv_link_irq(struct net_device *dev)
3270 {
3271         u8 __iomem *base = get_hwbase(dev);
3272         u32 miistat;
3273
3274         miistat = readl(base + NvRegMIIStatus);
3275         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3276
3277         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3278                 nv_linkchange(dev);
3279 }
3280
3281 static void nv_msi_workaround(struct fe_priv *np)
3282 {
3283
3284         /* Need to toggle the msi irq mask within the ethernet device,
3285          * otherwise, future interrupts will not be detected.
3286          */
3287         if (np->msi_flags & NV_MSI_ENABLED) {
3288                 u8 __iomem *base = np->base;
3289
3290                 writel(0, base + NvRegMSIIrqMask);
3291                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3292         }
3293 }
3294
3295 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3296 {
3297         struct fe_priv *np = netdev_priv(dev);
3298
3299         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3300                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3301                         /* transition to poll based interrupts */
3302                         np->quiet_count = 0;
3303                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3304                                 np->irqmask = NVREG_IRQMASK_CPU;
3305                                 return 1;
3306                         }
3307                 } else {
3308                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3309                                 np->quiet_count++;
3310                         } else {
3311                                 /* reached a period of low activity, switch
3312                                    to per tx/rx packet interrupts */
3313                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3314                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3315                                         return 1;
3316                                 }
3317                         }
3318                 }
3319         }
3320         return 0;
3321 }
3322
3323 static irqreturn_t nv_nic_irq(int foo, void *data)
3324 {
3325         struct net_device *dev = (struct net_device *) data;
3326         struct fe_priv *np = netdev_priv(dev);
3327         u8 __iomem *base = get_hwbase(dev);
3328
3329         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3330                 np->events = readl(base + NvRegIrqStatus);
3331                 writel(np->events, base + NvRegIrqStatus);
3332         } else {
3333                 np->events = readl(base + NvRegMSIXIrqStatus);
3334                 writel(np->events, base + NvRegMSIXIrqStatus);
3335         }
3336         if (!(np->events & np->irqmask))
3337                 return IRQ_NONE;
3338
3339         nv_msi_workaround(np);
3340
3341         if (napi_schedule_prep(&np->napi)) {
3342                 /*
3343                  * Disable further irq's (msix not enabled with napi)
3344                  */
3345                 writel(0, base + NvRegIrqMask);
3346                 __napi_schedule(&np->napi);
3347         }
3348
3349         return IRQ_HANDLED;
3350 }
3351
3352 /**
3353  * All _optimized functions are used to help increase performance
3354  * (reduce CPU and increase throughput). They use descripter version 3,
3355  * compiler directives, and reduce memory accesses.
3356  */
3357 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3358 {
3359         struct net_device *dev = (struct net_device *) data;
3360         struct fe_priv *np = netdev_priv(dev);
3361         u8 __iomem *base = get_hwbase(dev);
3362
3363         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3364                 np->events = readl(base + NvRegIrqStatus);
3365                 writel(np->events, base + NvRegIrqStatus);
3366         } else {
3367                 np->events = readl(base + NvRegMSIXIrqStatus);
3368                 writel(np->events, base + NvRegMSIXIrqStatus);
3369         }
3370         if (!(np->events & np->irqmask))
3371                 return IRQ_NONE;
3372
3373         nv_msi_workaround(np);
3374
3375         if (napi_schedule_prep(&np->napi)) {
3376                 /*
3377                  * Disable further irq's (msix not enabled with napi)
3378                  */
3379                 writel(0, base + NvRegIrqMask);
3380                 __napi_schedule(&np->napi);
3381         }
3382
3383         return IRQ_HANDLED;
3384 }
3385
3386 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3387 {
3388         struct net_device *dev = (struct net_device *) data;
3389         struct fe_priv *np = netdev_priv(dev);
3390         u8 __iomem *base = get_hwbase(dev);
3391         u32 events;
3392         int i;
3393         unsigned long flags;
3394
3395         for (i = 0;; i++) {
3396                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3397                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3398                 if (!(events & np->irqmask))
3399                         break;
3400
3401                 spin_lock_irqsave(&np->lock, flags);
3402                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3403                 spin_unlock_irqrestore(&np->lock, flags);
3404
3405                 if (unlikely(i > max_interrupt_work)) {
3406                         spin_lock_irqsave(&np->lock, flags);
3407                         /* disable interrupts on the nic */
3408                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3409                         pci_push(base);
3410
3411                         if (!np->in_shutdown) {
3412                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3413                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3414                         }
3415                         spin_unlock_irqrestore(&np->lock, flags);
3416                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3417                                    __func__, i);
3418                         break;
3419                 }
3420
3421         }
3422
3423         return IRQ_RETVAL(i);
3424 }
3425
3426 static int nv_napi_poll(struct napi_struct *napi, int budget)
3427 {
3428         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3429         struct net_device *dev = np->dev;
3430         u8 __iomem *base = get_hwbase(dev);
3431         unsigned long flags;
3432         int retcode;
3433         int rx_count, tx_work = 0, rx_work = 0;
3434
3435         do {
3436                 if (!nv_optimized(np)) {
3437                         spin_lock_irqsave(&np->lock, flags);
3438                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3439                         spin_unlock_irqrestore(&np->lock, flags);
3440
3441                         rx_count = nv_rx_process(dev, budget - rx_work);
3442                         retcode = nv_alloc_rx(dev);
3443                 } else {
3444                         spin_lock_irqsave(&np->lock, flags);
3445                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3446                         spin_unlock_irqrestore(&np->lock, flags);
3447
3448                         rx_count = nv_rx_process_optimized(dev,
3449                             budget - rx_work);
3450                         retcode = nv_alloc_rx_optimized(dev);
3451                 }
3452         } while (retcode == 0 &&
3453                  rx_count > 0 && (rx_work += rx_count) < budget);
3454
3455         if (retcode) {
3456                 spin_lock_irqsave(&np->lock, flags);
3457                 if (!np->in_shutdown)
3458                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3459                 spin_unlock_irqrestore(&np->lock, flags);
3460         }
3461
3462         nv_change_interrupt_mode(dev, tx_work + rx_work);
3463
3464         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3465                 spin_lock_irqsave(&np->lock, flags);
3466                 nv_link_irq(dev);
3467                 spin_unlock_irqrestore(&np->lock, flags);
3468         }
3469         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3470                 spin_lock_irqsave(&np->lock, flags);
3471                 nv_linkchange(dev);
3472                 spin_unlock_irqrestore(&np->lock, flags);
3473                 np->link_timeout = jiffies + LINK_TIMEOUT;
3474         }
3475         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3476                 spin_lock_irqsave(&np->lock, flags);
3477                 if (!np->in_shutdown) {
3478                         np->nic_poll_irq = np->irqmask;
3479                         np->recover_error = 1;
3480                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3481                 }
3482                 spin_unlock_irqrestore(&np->lock, flags);
3483                 napi_complete(napi);
3484                 return rx_work;
3485         }
3486
3487         if (rx_work < budget) {
3488                 /* re-enable interrupts
3489                    (msix not enabled in napi) */
3490                 napi_complete(napi);
3491
3492                 writel(np->irqmask, base + NvRegIrqMask);
3493         }
3494         return rx_work;
3495 }
3496
3497 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3498 {
3499         struct net_device *dev = (struct net_device *) data;
3500         struct fe_priv *np = netdev_priv(dev);
3501         u8 __iomem *base = get_hwbase(dev);
3502         u32 events;
3503         int i;
3504         unsigned long flags;
3505
3506         for (i = 0;; i++) {
3507                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3508                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3509                 if (!(events & np->irqmask))
3510                         break;
3511
3512                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3513                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3514                                 spin_lock_irqsave(&np->lock, flags);
3515                                 if (!np->in_shutdown)
3516                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3517                                 spin_unlock_irqrestore(&np->lock, flags);
3518                         }
3519                 }
3520
3521                 if (unlikely(i > max_interrupt_work)) {
3522                         spin_lock_irqsave(&np->lock, flags);
3523                         /* disable interrupts on the nic */
3524                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3525                         pci_push(base);
3526
3527                         if (!np->in_shutdown) {
3528                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3529                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3530                         }
3531                         spin_unlock_irqrestore(&np->lock, flags);
3532                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3533                                    __func__, i);
3534                         break;
3535                 }
3536         }
3537
3538         return IRQ_RETVAL(i);
3539 }
3540
3541 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3542 {
3543         struct net_device *dev = (struct net_device *) data;
3544         struct fe_priv *np = netdev_priv(dev);
3545         u8 __iomem *base = get_hwbase(dev);
3546         u32 events;
3547         int i;
3548         unsigned long flags;
3549
3550         for (i = 0;; i++) {
3551                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3552                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3553                 if (!(events & np->irqmask))
3554                         break;
3555
3556                 /* check tx in case we reached max loop limit in tx isr */
3557                 spin_lock_irqsave(&np->lock, flags);
3558                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3559                 spin_unlock_irqrestore(&np->lock, flags);
3560
3561                 if (events & NVREG_IRQ_LINK) {
3562                         spin_lock_irqsave(&np->lock, flags);
3563                         nv_link_irq(dev);
3564                         spin_unlock_irqrestore(&np->lock, flags);
3565                 }
3566                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3567                         spin_lock_irqsave(&np->lock, flags);
3568                         nv_linkchange(dev);
3569                         spin_unlock_irqrestore(&np->lock, flags);
3570                         np->link_timeout = jiffies + LINK_TIMEOUT;
3571                 }
3572                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3573                         spin_lock_irq(&np->lock);
3574                         /* disable interrupts on the nic */
3575                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3576                         pci_push(base);
3577
3578                         if (!np->in_shutdown) {
3579                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3580                                 np->recover_error = 1;
3581                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3582                         }
3583                         spin_unlock_irq(&np->lock);
3584                         break;
3585                 }
3586                 if (unlikely(i > max_interrupt_work)) {
3587                         spin_lock_irqsave(&np->lock, flags);
3588                         /* disable interrupts on the nic */
3589                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3590                         pci_push(base);
3591
3592                         if (!np->in_shutdown) {
3593                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3594                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3595                         }
3596                         spin_unlock_irqrestore(&np->lock, flags);
3597                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3598                                    __func__, i);
3599                         break;
3600                 }
3601
3602         }
3603
3604         return IRQ_RETVAL(i);
3605 }
3606
3607 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3608 {
3609         struct net_device *dev = (struct net_device *) data;
3610         struct fe_priv *np = netdev_priv(dev);
3611         u8 __iomem *base = get_hwbase(dev);
3612         u32 events;
3613
3614         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3615                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3616                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3617         } else {
3618                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3619                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3620         }
3621         pci_push(base);
3622         if (!(events & NVREG_IRQ_TIMER))
3623                 return IRQ_RETVAL(0);
3624
3625         nv_msi_workaround(np);
3626
3627         spin_lock(&np->lock);
3628         np->intr_test = 1;
3629         spin_unlock(&np->lock);
3630
3631         return IRQ_RETVAL(1);
3632 }
3633
3634 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3635 {
3636         u8 __iomem *base = get_hwbase(dev);
3637         int i;
3638         u32 msixmap = 0;
3639
3640         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3641          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3642          * the remaining 8 interrupts.
3643          */
3644         for (i = 0; i < 8; i++) {
3645                 if ((irqmask >> i) & 0x1)
3646                         msixmap |= vector << (i << 2);
3647         }
3648         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3649
3650         msixmap = 0;
3651         for (i = 0; i < 8; i++) {
3652                 if ((irqmask >> (i + 8)) & 0x1)
3653                         msixmap |= vector << (i << 2);
3654         }
3655         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3656 }
3657
3658 static int nv_request_irq(struct net_device *dev, int intr_test)
3659 {
3660         struct fe_priv *np = get_nvpriv(dev);
3661         u8 __iomem *base = get_hwbase(dev);
3662         int ret = 1;
3663         int i;
3664         irqreturn_t (*handler)(int foo, void *data);
3665
3666         if (intr_test) {
3667                 handler = nv_nic_irq_test;
3668         } else {
3669                 if (nv_optimized(np))
3670                         handler = nv_nic_irq_optimized;
3671                 else
3672                         handler = nv_nic_irq;
3673         }
3674
3675         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3676                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3677                         np->msi_x_entry[i].entry = i;
3678                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3679                 if (ret == 0) {
3680                         np->msi_flags |= NV_MSI_X_ENABLED;
3681                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3682                                 /* Request irq for rx handling */
3683                                 sprintf(np->name_rx, "%s-rx", dev->name);
3684                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3685                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3686                                         netdev_info(dev,
3687                                                     "request_irq failed for rx %d\n",
3688                                                     ret);
3689                                         pci_disable_msix(np->pci_dev);
3690                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3691                                         goto out_err;
3692                                 }
3693                                 /* Request irq for tx handling */
3694                                 sprintf(np->name_tx, "%s-tx", dev->name);
3695                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3696                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3697                                         netdev_info(dev,
3698                                                     "request_irq failed for tx %d\n",
3699                                                     ret);
3700                                         pci_disable_msix(np->pci_dev);
3701                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3702                                         goto out_free_rx;
3703                                 }
3704                                 /* Request irq for link and timer handling */
3705                                 sprintf(np->name_other, "%s-other", dev->name);
3706                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3707                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3708                                         netdev_info(dev,
3709                                                     "request_irq failed for link %d\n",
3710                                                     ret);
3711                                         pci_disable_msix(np->pci_dev);
3712                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3713                                         goto out_free_tx;
3714                                 }
3715                                 /* map interrupts to their respective vector */
3716                                 writel(0, base + NvRegMSIXMap0);
3717                                 writel(0, base + NvRegMSIXMap1);
3718                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3719                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3720                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3721                         } else {
3722                                 /* Request irq for all interrupts */
3723                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3724                                         netdev_info(dev,
3725                                                     "request_irq failed %d\n",
3726                                                     ret);
3727                                         pci_disable_msix(np->pci_dev);
3728                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3729                                         goto out_err;
3730                                 }
3731
3732                                 /* map interrupts to vector 0 */
3733                                 writel(0, base + NvRegMSIXMap0);
3734                                 writel(0, base + NvRegMSIXMap1);
3735                         }
3736                 }
3737         }
3738         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3739                 ret = pci_enable_msi(np->pci_dev);
3740                 if (ret == 0) {
3741                         np->msi_flags |= NV_MSI_ENABLED;
3742                         dev->irq = np->pci_dev->irq;
3743                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3744                                 netdev_info(dev, "request_irq failed %d\n",
3745                                             ret);
3746                                 pci_disable_msi(np->pci_dev);
3747                                 np->msi_flags &= ~NV_MSI_ENABLED;
3748                                 dev->irq = np->pci_dev->irq;
3749                                 goto out_err;
3750                         }
3751
3752                         /* map interrupts to vector 0 */
3753                         writel(0, base + NvRegMSIMap0);
3754                         writel(0, base + NvRegMSIMap1);
3755                         /* enable msi vector 0 */
3756                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3757                 }
3758         }
3759         if (ret != 0) {
3760                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3761                         goto out_err;
3762
3763         }
3764
3765         return 0;
3766 out_free_tx:
3767         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3768 out_free_rx:
3769         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3770 out_err:
3771         return 1;
3772 }
3773
3774 static void nv_free_irq(struct net_device *dev)
3775 {
3776         struct fe_priv *np = get_nvpriv(dev);
3777         int i;
3778
3779         if (np->msi_flags & NV_MSI_X_ENABLED) {
3780                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3781                         free_irq(np->msi_x_entry[i].vector, dev);
3782                 pci_disable_msix(np->pci_dev);
3783                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3784         } else {
3785                 free_irq(np->pci_dev->irq, dev);
3786                 if (np->msi_flags & NV_MSI_ENABLED) {
3787                         pci_disable_msi(np->pci_dev);
3788                         np->msi_flags &= ~NV_MSI_ENABLED;
3789                 }
3790         }
3791 }
3792
3793 static void nv_do_nic_poll(unsigned long data)
3794 {
3795         struct net_device *dev = (struct net_device *) data;
3796         struct fe_priv *np = netdev_priv(dev);
3797         u8 __iomem *base = get_hwbase(dev);
3798         u32 mask = 0;
3799
3800         /*
3801          * First disable irq(s) and then
3802          * reenable interrupts on the nic, we have to do this before calling
3803          * nv_nic_irq because that may decide to do otherwise
3804          */
3805
3806         if (!using_multi_irqs(dev)) {
3807                 if (np->msi_flags & NV_MSI_X_ENABLED)
3808                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3809                 else
3810                         disable_irq_lockdep(np->pci_dev->irq);
3811                 mask = np->irqmask;
3812         } else {
3813                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3814                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3815                         mask |= NVREG_IRQ_RX_ALL;
3816                 }
3817                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3818                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3819                         mask |= NVREG_IRQ_TX_ALL;
3820                 }
3821                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3822                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3823                         mask |= NVREG_IRQ_OTHER;
3824                 }
3825         }
3826         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3827
3828         if (np->recover_error) {
3829                 np->recover_error = 0;
3830                 netdev_info(dev, "MAC in recoverable error state\n");
3831                 if (netif_running(dev)) {
3832                         netif_tx_lock_bh(dev);
3833                         netif_addr_lock(dev);
3834                         spin_lock(&np->lock);
3835                         /* stop engines */
3836                         nv_stop_rxtx(dev);
3837                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3838                                 nv_mac_reset(dev);
3839                         nv_txrx_reset(dev);
3840                         /* drain rx queue */
3841                         nv_drain_rxtx(dev);
3842                         /* reinit driver view of the rx queue */
3843                         set_bufsize(dev);
3844                         if (nv_init_ring(dev)) {
3845                                 if (!np->in_shutdown)
3846                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3847                         }
3848                         /* reinit nic view of the rx queue */
3849                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3850                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3851                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3852                                 base + NvRegRingSizes);
3853                         pci_push(base);
3854                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3855                         pci_push(base);
3856                         /* clear interrupts */
3857                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3858                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3859                         else
3860                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3861
3862                         /* restart rx engine */
3863                         nv_start_rxtx(dev);
3864                         spin_unlock(&np->lock);
3865                         netif_addr_unlock(dev);
3866                         netif_tx_unlock_bh(dev);
3867                 }
3868         }
3869
3870         writel(mask, base + NvRegIrqMask);
3871         pci_push(base);
3872
3873         if (!using_multi_irqs(dev)) {
3874                 np->nic_poll_irq = 0;
3875                 if (nv_optimized(np))
3876                         nv_nic_irq_optimized(0, dev);
3877                 else
3878                         nv_nic_irq(0, dev);
3879                 if (np->msi_flags & NV_MSI_X_ENABLED)
3880                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3881                 else
3882                         enable_irq_lockdep(np->pci_dev->irq);
3883         } else {
3884                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3885                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3886                         nv_nic_irq_rx(0, dev);
3887                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3888                 }
3889                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3890                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3891                         nv_nic_irq_tx(0, dev);
3892                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3893                 }
3894                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3895                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3896                         nv_nic_irq_other(0, dev);
3897                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3898                 }
3899         }
3900
3901 }
3902
3903 #ifdef CONFIG_NET_POLL_CONTROLLER
3904 static void nv_poll_controller(struct net_device *dev)
3905 {
3906         nv_do_nic_poll((unsigned long) dev);
3907 }
3908 #endif
3909
3910 static void nv_do_stats_poll(unsigned long data)
3911 {
3912         struct net_device *dev = (struct net_device *) data;
3913         struct fe_priv *np = netdev_priv(dev);
3914
3915         nv_get_hw_stats(dev);
3916
3917         if (!np->in_shutdown)
3918                 mod_timer(&np->stats_poll,
3919                         round_jiffies(jiffies + STATS_INTERVAL));
3920 }
3921
3922 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3923 {
3924         struct fe_priv *np = netdev_priv(dev);
3925         strcpy(info->driver, DRV_NAME);
3926         strcpy(info->version, FORCEDETH_VERSION);
3927         strcpy(info->bus_info, pci_name(np->pci_dev));
3928 }
3929
3930 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3931 {
3932         struct fe_priv *np = netdev_priv(dev);
3933         wolinfo->supported = WAKE_MAGIC;
3934
3935         spin_lock_irq(&np->lock);
3936         if (np->wolenabled)
3937                 wolinfo->wolopts = WAKE_MAGIC;
3938         spin_unlock_irq(&np->lock);
3939 }
3940
3941 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3942 {
3943         struct fe_priv *np = netdev_priv(dev);
3944         u8 __iomem *base = get_hwbase(dev);
3945         u32 flags = 0;
3946
3947         if (wolinfo->wolopts == 0) {
3948                 np->wolenabled = 0;
3949         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3950                 np->wolenabled = 1;
3951                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3952         }
3953         if (netif_running(dev)) {
3954                 spin_lock_irq(&np->lock);
3955                 writel(flags, base + NvRegWakeUpFlags);
3956                 spin_unlock_irq(&np->lock);
3957         }
3958         device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
3959         return 0;
3960 }
3961
3962 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3963 {
3964         struct fe_priv *np = netdev_priv(dev);
3965         u32 speed;
3966         int adv;
3967
3968         spin_lock_irq(&np->lock);
3969         ecmd->port = PORT_MII;
3970         if (!netif_running(dev)) {
3971                 /* We do not track link speed / duplex setting if the
3972                  * interface is disabled. Force a link check */
3973                 if (nv_update_linkspeed(dev)) {
3974                         if (!netif_carrier_ok(dev))
3975                                 netif_carrier_on(dev);
3976                 } else {
3977                         if (netif_carrier_ok(dev))
3978                                 netif_carrier_off(dev);
3979                 }
3980         }
3981
3982         if (netif_carrier_ok(dev)) {
3983                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3984                 case NVREG_LINKSPEED_10:
3985                         speed = SPEED_10;
3986                         break;
3987                 case NVREG_LINKSPEED_100:
3988                         speed = SPEED_100;
3989                         break;
3990                 case NVREG_LINKSPEED_1000:
3991                         speed = SPEED_1000;
3992                         break;
3993                 default:
3994                         speed = -1;
3995                         break;
3996                 }
3997                 ecmd->duplex = DUPLEX_HALF;
3998                 if (np->duplex)
3999                         ecmd->duplex = DUPLEX_FULL;
4000         } else {
4001                 speed = -1;
4002                 ecmd->duplex = -1;
4003         }
4004         ethtool_cmd_speed_set(ecmd, speed);
4005         ecmd->autoneg = np->autoneg;
4006
4007         ecmd->advertising = ADVERTISED_MII;
4008         if (np->autoneg) {
4009                 ecmd->advertising |= ADVERTISED_Autoneg;
4010                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4011                 if (adv & ADVERTISE_10HALF)
4012                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4013                 if (adv & ADVERTISE_10FULL)
4014                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4015                 if (adv & ADVERTISE_100HALF)
4016                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4017                 if (adv & ADVERTISE_100FULL)
4018                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4019                 if (np->gigabit == PHY_GIGABIT) {
4020                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4021                         if (adv & ADVERTISE_1000FULL)
4022                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4023                 }
4024         }
4025         ecmd->supported = (SUPPORTED_Autoneg |
4026                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4027                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4028                 SUPPORTED_MII);
4029         if (np->gigabit == PHY_GIGABIT)
4030                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4031
4032         ecmd->phy_address = np->phyaddr;
4033         ecmd->transceiver = XCVR_EXTERNAL;
4034
4035         /* ignore maxtxpkt, maxrxpkt for now */
4036         spin_unlock_irq(&np->lock);
4037         return 0;
4038 }
4039
4040 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4041 {
4042         struct fe_priv *np = netdev_priv(dev);
4043         u32 speed = ethtool_cmd_speed(ecmd);
4044
4045         if (ecmd->port != PORT_MII)
4046                 return -EINVAL;
4047         if (ecmd->transceiver != XCVR_EXTERNAL)
4048                 return -EINVAL;
4049         if (ecmd->phy_address != np->phyaddr) {
4050                 /* TODO: support switching between multiple phys. Should be
4051                  * trivial, but not enabled due to lack of test hardware. */
4052                 return -EINVAL;
4053         }
4054         if (ecmd->autoneg == AUTONEG_ENABLE) {
4055                 u32 mask;
4056
4057                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4058                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4059                 if (np->gigabit == PHY_GIGABIT)
4060                         mask |= ADVERTISED_1000baseT_Full;
4061
4062                 if ((ecmd->advertising & mask) == 0)
4063                         return -EINVAL;
4064
4065         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4066                 /* Note: autonegotiation disable, speed 1000 intentionally
4067                  * forbidden - no one should need that. */
4068
4069                 if (speed != SPEED_10 && speed != SPEED_100)
4070                         return -EINVAL;
4071                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4072                         return -EINVAL;
4073         } else {
4074                 return -EINVAL;
4075         }
4076
4077         netif_carrier_off(dev);
4078         if (netif_running(dev)) {
4079                 unsigned long flags;
4080
4081                 nv_disable_irq(dev);
4082                 netif_tx_lock_bh(dev);
4083                 netif_addr_lock(dev);
4084                 /* with plain spinlock lockdep complains */
4085                 spin_lock_irqsave(&np->lock, flags);
4086                 /* stop engines */
4087                 /* FIXME:
4088                  * this can take some time, and interrupts are disabled
4089                  * due to spin_lock_irqsave, but let's hope no daemon
4090                  * is going to change the settings very often...
4091                  * Worst case:
4092                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4093                  * + some minor delays, which is up to a second approximately
4094                  */
4095                 nv_stop_rxtx(dev);
4096                 spin_unlock_irqrestore(&np->lock, flags);
4097                 netif_addr_unlock(dev);
4098                 netif_tx_unlock_bh(dev);
4099         }
4100
4101         if (ecmd->autoneg == AUTONEG_ENABLE) {
4102                 int adv, bmcr;
4103
4104                 np->autoneg = 1;
4105
4106                 /* advertise only what has been requested */
4107                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4108                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4109                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4110                         adv |= ADVERTISE_10HALF;
4111                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4112                         adv |= ADVERTISE_10FULL;
4113                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4114                         adv |= ADVERTISE_100HALF;
4115                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4116                         adv |= ADVERTISE_100FULL;
4117                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4118                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4119                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4120                         adv |=  ADVERTISE_PAUSE_ASYM;
4121                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4122
4123                 if (np->gigabit == PHY_GIGABIT) {
4124                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4125                         adv &= ~ADVERTISE_1000FULL;
4126                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4127                                 adv |= ADVERTISE_1000FULL;
4128                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4129                 }
4130
4131                 if (netif_running(dev))
4132                         netdev_info(dev, "link down\n");
4133                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4134                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4135                         bmcr |= BMCR_ANENABLE;
4136                         /* reset the phy in order for settings to stick,
4137                          * and cause autoneg to start */
4138                         if (phy_reset(dev, bmcr)) {
4139                                 netdev_info(dev, "phy reset failed\n");
4140                                 return -EINVAL;
4141                         }
4142                 } else {
4143                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4144                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4145                 }
4146         } else {
4147                 int adv, bmcr;
4148
4149                 np->autoneg = 0;
4150
4151                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4152                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4153                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4154                         adv |= ADVERTISE_10HALF;
4155                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4156                         adv |= ADVERTISE_10FULL;
4157                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4158                         adv |= ADVERTISE_100HALF;
4159                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4160                         adv |= ADVERTISE_100FULL;
4161                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4162                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4163                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4164                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4165                 }
4166                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4167                         adv |=  ADVERTISE_PAUSE_ASYM;
4168                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4169                 }
4170                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4171                 np->fixed_mode = adv;
4172
4173                 if (np->gigabit == PHY_GIGABIT) {
4174                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4175                         adv &= ~ADVERTISE_1000FULL;
4176                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4177                 }
4178
4179                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4180                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4181                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4182                         bmcr |= BMCR_FULLDPLX;
4183                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4184                         bmcr |= BMCR_SPEED100;
4185                 if (np->phy_oui == PHY_OUI_MARVELL) {
4186                         /* reset the phy in order for forced mode settings to stick */
4187                         if (phy_reset(dev, bmcr)) {
4188                                 netdev_info(dev, "phy reset failed\n");
4189                                 return -EINVAL;
4190                         }
4191                 } else {
4192                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4193                         if (netif_running(dev)) {
4194                                 /* Wait a bit and then reconfigure the nic. */
4195                                 udelay(10);
4196                                 nv_linkchange(dev);
4197                         }
4198                 }
4199         }
4200
4201         if (netif_running(dev)) {
4202                 nv_start_rxtx(dev);
4203                 nv_enable_irq(dev);
4204         }
4205
4206         return 0;
4207 }
4208
4209 #define FORCEDETH_REGS_VER      1
4210
4211 static int nv_get_regs_len(struct net_device *dev)
4212 {
4213         struct fe_priv *np = netdev_priv(dev);
4214         return np->register_size;
4215 }
4216
4217 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4218 {
4219         struct fe_priv *np = netdev_priv(dev);
4220         u8 __iomem *base = get_hwbase(dev);
4221         u32 *rbuf = buf;
4222         int i;
4223
4224         regs->version = FORCEDETH_REGS_VER;
4225         spin_lock_irq(&np->lock);
4226         for (i = 0; i <= np->register_size/sizeof(u32); i++)
4227                 rbuf[i] = readl(base + i*sizeof(u32));
4228         spin_unlock_irq(&np->lock);
4229 }
4230
4231 static int nv_nway_reset(struct net_device *dev)
4232 {
4233         struct fe_priv *np = netdev_priv(dev);
4234         int ret;
4235
4236         if (np->autoneg) {
4237                 int bmcr;
4238
4239                 netif_carrier_off(dev);
4240                 if (netif_running(dev)) {
4241                         nv_disable_irq(dev);
4242                         netif_tx_lock_bh(dev);
4243                         netif_addr_lock(dev);
4244                         spin_lock(&np->lock);
4245                         /* stop engines */
4246                         nv_stop_rxtx(dev);
4247                         spin_unlock(&np->lock);
4248                         netif_addr_unlock(dev);
4249                         netif_tx_unlock_bh(dev);
4250                         netdev_info(dev, "link down\n");
4251                 }
4252
4253                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4254                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4255                         bmcr |= BMCR_ANENABLE;
4256                         /* reset the phy in order for settings to stick*/
4257                         if (phy_reset(dev, bmcr)) {
4258                                 netdev_info(dev, "phy reset failed\n");
4259                                 return -EINVAL;
4260                         }
4261                 } else {
4262                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4263                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4264                 }
4265
4266                 if (netif_running(dev)) {
4267                         nv_start_rxtx(dev);
4268                         nv_enable_irq(dev);
4269                 }
4270                 ret = 0;
4271         } else {
4272                 ret = -EINVAL;
4273         }
4274
4275         return ret;
4276 }
4277
4278 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4279 {
4280         struct fe_priv *np = netdev_priv(dev);
4281
4282         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4283         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4284
4285         ring->rx_pending = np->rx_ring_size;
4286         ring->tx_pending = np->tx_ring_size;
4287 }
4288
4289 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4290 {
4291         struct fe_priv *np = netdev_priv(dev);
4292         u8 __iomem *base = get_hwbase(dev);
4293         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4294         dma_addr_t ring_addr;
4295
4296         if (ring->rx_pending < RX_RING_MIN ||
4297             ring->tx_pending < TX_RING_MIN ||
4298             ring->rx_mini_pending != 0 ||
4299             ring->rx_jumbo_pending != 0 ||
4300             (np->desc_ver == DESC_VER_1 &&
4301              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4302               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4303             (np->desc_ver != DESC_VER_1 &&
4304              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4305               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4306                 return -EINVAL;
4307         }
4308
4309         /* allocate new rings */
4310         if (!nv_optimized(np)) {
4311                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4312                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4313                                             &ring_addr);
4314         } else {
4315                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4316                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4317                                             &ring_addr);
4318         }
4319         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4320         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4321         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4322                 /* fall back to old rings */
4323                 if (!nv_optimized(np)) {
4324                         if (rxtx_ring)
4325                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4326                                                     rxtx_ring, ring_addr);
4327                 } else {
4328                         if (rxtx_ring)
4329                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4330                                                     rxtx_ring, ring_addr);
4331                 }
4332
4333                 kfree(rx_skbuff);
4334                 kfree(tx_skbuff);
4335                 goto exit;
4336         }
4337
4338         if (netif_running(dev)) {
4339                 nv_disable_irq(dev);
4340                 nv_napi_disable(dev);
4341                 netif_tx_lock_bh(dev);
4342                 netif_addr_lock(dev);
4343                 spin_lock(&np->lock);
4344                 /* stop engines */
4345                 nv_stop_rxtx(dev);
4346                 nv_txrx_reset(dev);
4347                 /* drain queues */
4348                 nv_drain_rxtx(dev);
4349                 /* delete queues */
4350                 free_rings(dev);
4351         }
4352
4353         /* set new values */
4354         np->rx_ring_size = ring->rx_pending;
4355         np->tx_ring_size = ring->tx_pending;
4356
4357         if (!nv_optimized(np)) {
4358                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4359                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4360         } else {
4361                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4362                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4363         }
4364         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4365         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4366         np->ring_addr = ring_addr;
4367
4368         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4369         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4370
4371         if (netif_running(dev)) {
4372                 /* reinit driver view of the queues */
4373                 set_bufsize(dev);
4374                 if (nv_init_ring(dev)) {
4375                         if (!np->in_shutdown)
4376                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4377                 }
4378
4379                 /* reinit nic view of the queues */
4380                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4381                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4382                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4383                         base + NvRegRingSizes);
4384                 pci_push(base);
4385                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4386                 pci_push(base);
4387
4388                 /* restart engines */
4389                 nv_start_rxtx(dev);
4390                 spin_unlock(&np->lock);
4391                 netif_addr_unlock(dev);
4392                 netif_tx_unlock_bh(dev);
4393                 nv_napi_enable(dev);
4394                 nv_enable_irq(dev);
4395         }
4396         return 0;
4397 exit:
4398         return -ENOMEM;
4399 }
4400
4401 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4402 {
4403         struct fe_priv *np = netdev_priv(dev);
4404
4405         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4406         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4407         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4408 }
4409
4410 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4411 {
4412         struct fe_priv *np = netdev_priv(dev);
4413         int adv, bmcr;
4414
4415         if ((!np->autoneg && np->duplex == 0) ||
4416             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4417                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4418                 return -EINVAL;
4419         }
4420         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4421                 netdev_info(dev, "hardware does not support tx pause frames\n");
4422                 return -EINVAL;
4423         }
4424
4425         netif_carrier_off(dev);
4426         if (netif_running(dev)) {
4427                 nv_disable_irq(dev);
4428                 netif_tx_lock_bh(dev);
4429                 netif_addr_lock(dev);
4430                 spin_lock(&np->lock);
4431                 /* stop engines */
4432                 nv_stop_rxtx(dev);
4433                 spin_unlock(&np->lock);
4434                 netif_addr_unlock(dev);
4435                 netif_tx_unlock_bh(dev);
4436         }
4437
4438         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4439         if (pause->rx_pause)
4440                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4441         if (pause->tx_pause)
4442                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4443
4444         if (np->autoneg && pause->autoneg) {
4445                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4446
4447                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4448                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4449                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4450                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4451                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4452                         adv |=  ADVERTISE_PAUSE_ASYM;
4453                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4454
4455                 if (netif_running(dev))
4456                         netdev_info(dev, "link down\n");
4457                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4458                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4459                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4460         } else {
4461                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4462                 if (pause->rx_pause)
4463                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4464                 if (pause->tx_pause)
4465                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4466
4467                 if (!netif_running(dev))
4468                         nv_update_linkspeed(dev);
4469                 else
4470                         nv_update_pause(dev, np->pause_flags);
4471         }
4472
4473         if (netif_running(dev)) {
4474                 nv_start_rxtx(dev);
4475                 nv_enable_irq(dev);
4476         }
4477         return 0;
4478 }
4479
4480 static u32 nv_fix_features(struct net_device *dev, u32 features)
4481 {
4482         /* vlan is dependent on rx checksum offload */
4483         if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4484                 features |= NETIF_F_RXCSUM;
4485
4486         return features;
4487 }
4488
4489 static void nv_vlan_mode(struct net_device *dev, u32 features)
4490 {
4491         struct fe_priv *np = get_nvpriv(dev);
4492
4493         spin_lock_irq(&np->lock);
4494
4495         if (features & NETIF_F_HW_VLAN_RX)
4496                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4497         else
4498                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4499
4500         if (features & NETIF_F_HW_VLAN_TX)
4501                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4502         else
4503                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4504
4505         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4506
4507         spin_unlock_irq(&np->lock);
4508 }
4509
4510 static int nv_set_features(struct net_device *dev, u32 features)
4511 {
4512         struct fe_priv *np = netdev_priv(dev);
4513         u8 __iomem *base = get_hwbase(dev);
4514         u32 changed = dev->features ^ features;
4515
4516         if (changed & NETIF_F_RXCSUM) {
4517                 spin_lock_irq(&np->lock);
4518
4519                 if (features & NETIF_F_RXCSUM)
4520                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4521                 else
4522                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4523
4524                 if (netif_running(dev))
4525                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4526
4527                 spin_unlock_irq(&np->lock);
4528         }
4529
4530         if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4531                 nv_vlan_mode(dev, features);
4532
4533         return 0;
4534 }
4535
4536 static int nv_get_sset_count(struct net_device *dev, int sset)
4537 {
4538         struct fe_priv *np = netdev_priv(dev);
4539
4540         switch (sset) {
4541         case ETH_SS_TEST:
4542                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4543                         return NV_TEST_COUNT_EXTENDED;
4544                 else
4545                         return NV_TEST_COUNT_BASE;
4546         case ETH_SS_STATS:
4547                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4548                         return NV_DEV_STATISTICS_V3_COUNT;
4549                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4550                         return NV_DEV_STATISTICS_V2_COUNT;
4551                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4552                         return NV_DEV_STATISTICS_V1_COUNT;
4553                 else
4554                         return 0;
4555         default:
4556                 return -EOPNOTSUPP;
4557         }
4558 }
4559
4560 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4561 {
4562         struct fe_priv *np = netdev_priv(dev);
4563
4564         /* update stats */
4565         nv_do_stats_poll((unsigned long)dev);
4566
4567         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4568 }
4569
4570 static int nv_link_test(struct net_device *dev)
4571 {
4572         struct fe_priv *np = netdev_priv(dev);
4573         int mii_status;
4574
4575         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4576         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4577
4578         /* check phy link status */
4579         if (!(mii_status & BMSR_LSTATUS))
4580                 return 0;
4581         else
4582                 return 1;
4583 }
4584
4585 static int nv_register_test(struct net_device *dev)
4586 {
4587         u8 __iomem *base = get_hwbase(dev);
4588         int i = 0;
4589         u32 orig_read, new_read;
4590
4591         do {
4592                 orig_read = readl(base + nv_registers_test[i].reg);
4593
4594                 /* xor with mask to toggle bits */
4595                 orig_read ^= nv_registers_test[i].mask;
4596
4597                 writel(orig_read, base + nv_registers_test[i].reg);
4598
4599                 new_read = readl(base + nv_registers_test[i].reg);
4600
4601                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4602                         return 0;
4603
4604                 /* restore original value */
4605                 orig_read ^= nv_registers_test[i].mask;
4606                 writel(orig_read, base + nv_registers_test[i].reg);
4607
4608         } while (nv_registers_test[++i].reg != 0);
4609
4610         return 1;
4611 }
4612
4613 static int nv_interrupt_test(struct net_device *dev)
4614 {
4615         struct fe_priv *np = netdev_priv(dev);
4616         u8 __iomem *base = get_hwbase(dev);
4617         int ret = 1;
4618         int testcnt;
4619         u32 save_msi_flags, save_poll_interval = 0;
4620
4621         if (netif_running(dev)) {
4622                 /* free current irq */
4623                 nv_free_irq(dev);
4624                 save_poll_interval = readl(base+NvRegPollingInterval);
4625         }
4626
4627         /* flag to test interrupt handler */
4628         np->intr_test = 0;
4629
4630         /* setup test irq */
4631         save_msi_flags = np->msi_flags;
4632         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4633         np->msi_flags |= 0x001; /* setup 1 vector */
4634         if (nv_request_irq(dev, 1))
4635                 return 0;
4636
4637         /* setup timer interrupt */
4638         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4639         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4640
4641         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4642
4643         /* wait for at least one interrupt */
4644         msleep(100);
4645
4646         spin_lock_irq(&np->lock);
4647
4648         /* flag should be set within ISR */
4649         testcnt = np->intr_test;
4650         if (!testcnt)
4651                 ret = 2;
4652
4653         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4654         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4655                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4656         else
4657                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4658
4659         spin_unlock_irq(&np->lock);
4660
4661         nv_free_irq(dev);
4662
4663         np->msi_flags = save_msi_flags;
4664
4665         if (netif_running(dev)) {
4666                 writel(save_poll_interval, base + NvRegPollingInterval);
4667                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4668                 /* restore original irq */
4669                 if (nv_request_irq(dev, 0))
4670                         return 0;
4671         }
4672
4673         return ret;
4674 }
4675
4676 static int nv_loopback_test(struct net_device *dev)
4677 {
4678         struct fe_priv *np = netdev_priv(dev);
4679         u8 __iomem *base = get_hwbase(dev);
4680         struct sk_buff *tx_skb, *rx_skb;
4681         dma_addr_t test_dma_addr;
4682         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4683         u32 flags;
4684         int len, i, pkt_len;
4685         u8 *pkt_data;
4686         u32 filter_flags = 0;
4687         u32 misc1_flags = 0;
4688         int ret = 1;
4689
4690         if (netif_running(dev)) {
4691                 nv_disable_irq(dev);
4692                 filter_flags = readl(base + NvRegPacketFilterFlags);
4693                 misc1_flags = readl(base + NvRegMisc1);
4694         } else {
4695                 nv_txrx_reset(dev);
4696         }
4697
4698         /* reinit driver view of the rx queue */
4699         set_bufsize(dev);
4700         nv_init_ring(dev);
4701
4702         /* setup hardware for loopback */
4703         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4704         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4705
4706         /* reinit nic view of the rx queue */
4707         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4708         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4709         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4710                 base + NvRegRingSizes);
4711         pci_push(base);
4712
4713         /* restart rx engine */
4714         nv_start_rxtx(dev);
4715
4716         /* setup packet for tx */
4717         pkt_len = ETH_DATA_LEN;
4718         tx_skb = dev_alloc_skb(pkt_len);
4719         if (!tx_skb) {
4720                 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4721                 ret = 0;
4722                 goto out;
4723         }
4724         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4725                                        skb_tailroom(tx_skb),
4726                                        PCI_DMA_FROMDEVICE);
4727         pkt_data = skb_put(tx_skb, pkt_len);
4728         for (i = 0; i < pkt_len; i++)
4729                 pkt_data[i] = (u8)(i & 0xff);
4730
4731         if (!nv_optimized(np)) {
4732                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4733                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4734         } else {
4735                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4736                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4737                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4738         }
4739         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4740         pci_push(get_hwbase(dev));
4741
4742         msleep(500);
4743
4744         /* check for rx of the packet */
4745         if (!nv_optimized(np)) {
4746                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4747                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4748
4749         } else {
4750                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4751                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4752         }
4753
4754         if (flags & NV_RX_AVAIL) {
4755                 ret = 0;
4756         } else if (np->desc_ver == DESC_VER_1) {
4757                 if (flags & NV_RX_ERROR)
4758                         ret = 0;
4759         } else {
4760                 if (flags & NV_RX2_ERROR)
4761                         ret = 0;
4762         }
4763
4764         if (ret) {
4765                 if (len != pkt_len) {
4766                         ret = 0;
4767                 } else {
4768                         rx_skb = np->rx_skb[0].skb;
4769                         for (i = 0; i < pkt_len; i++) {
4770                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4771                                         ret = 0;
4772                                         break;
4773                                 }
4774                         }
4775                 }
4776         }
4777
4778         pci_unmap_single(np->pci_dev, test_dma_addr,
4779                        (skb_end_pointer(tx_skb) - tx_skb->data),
4780                        PCI_DMA_TODEVICE);
4781         dev_kfree_skb_any(tx_skb);
4782  out:
4783         /* stop engines */
4784         nv_stop_rxtx(dev);
4785         nv_txrx_reset(dev);
4786         /* drain rx queue */
4787         nv_drain_rxtx(dev);
4788
4789         if (netif_running(dev)) {
4790                 writel(misc1_flags, base + NvRegMisc1);
4791                 writel(filter_flags, base + NvRegPacketFilterFlags);
4792                 nv_enable_irq(dev);
4793         }
4794
4795         return ret;
4796 }
4797
4798 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4799 {
4800         struct fe_priv *np = netdev_priv(dev);
4801         u8 __iomem *base = get_hwbase(dev);
4802         int result;
4803         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4804
4805         if (!nv_link_test(dev)) {
4806                 test->flags |= ETH_TEST_FL_FAILED;
4807                 buffer[0] = 1;
4808         }
4809
4810         if (test->flags & ETH_TEST_FL_OFFLINE) {
4811                 if (netif_running(dev)) {
4812                         netif_stop_queue(dev);
4813                         nv_napi_disable(dev);
4814                         netif_tx_lock_bh(dev);
4815                         netif_addr_lock(dev);
4816                         spin_lock_irq(&np->lock);
4817                         nv_disable_hw_interrupts(dev, np->irqmask);
4818                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4819                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4820                         else
4821                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4822                         /* stop engines */
4823                         nv_stop_rxtx(dev);
4824                         nv_txrx_reset(dev);
4825                         /* drain rx queue */
4826                         nv_drain_rxtx(dev);
4827                         spin_unlock_irq(&np->lock);
4828                         netif_addr_unlock(dev);
4829                         netif_tx_unlock_bh(dev);
4830                 }
4831
4832                 if (!nv_register_test(dev)) {
4833                         test->flags |= ETH_TEST_FL_FAILED;
4834                         buffer[1] = 1;
4835                 }
4836
4837                 result = nv_interrupt_test(dev);
4838                 if (result != 1) {
4839                         test->flags |= ETH_TEST_FL_FAILED;
4840                         buffer[2] = 1;
4841                 }
4842                 if (result == 0) {
4843                         /* bail out */
4844                         return;
4845                 }
4846
4847                 if (!nv_loopback_test(dev)) {
4848                         test->flags |= ETH_TEST_FL_FAILED;
4849                         buffer[3] = 1;
4850                 }
4851
4852                 if (netif_running(dev)) {
4853                         /* reinit driver view of the rx queue */
4854                         set_bufsize(dev);
4855                         if (nv_init_ring(dev)) {
4856                                 if (!np->in_shutdown)
4857                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4858                         }
4859                         /* reinit nic view of the rx queue */
4860                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4861                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4862                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4863                                 base + NvRegRingSizes);
4864                         pci_push(base);
4865                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4866                         pci_push(base);
4867                         /* restart rx engine */
4868                         nv_start_rxtx(dev);
4869                         netif_start_queue(dev);
4870                         nv_napi_enable(dev);
4871                         nv_enable_hw_interrupts(dev, np->irqmask);
4872                 }
4873         }
4874 }
4875
4876 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4877 {
4878         switch (stringset) {
4879         case ETH_SS_STATS:
4880                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4881                 break;
4882         case ETH_SS_TEST:
4883                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4884                 break;
4885         }
4886 }
4887
4888 static const struct ethtool_ops ops = {
4889         .get_drvinfo = nv_get_drvinfo,
4890         .get_link = ethtool_op_get_link,
4891         .get_wol = nv_get_wol,
4892         .set_wol = nv_set_wol,
4893         .get_settings = nv_get_settings,
4894         .set_settings = nv_set_settings,
4895         .get_regs_len = nv_get_regs_len,
4896         .get_regs = nv_get_regs,
4897         .nway_reset = nv_nway_reset,
4898         .get_ringparam = nv_get_ringparam,
4899         .set_ringparam = nv_set_ringparam,
4900         .get_pauseparam = nv_get_pauseparam,
4901         .set_pauseparam = nv_set_pauseparam,
4902         .get_strings = nv_get_strings,
4903         .get_ethtool_stats = nv_get_ethtool_stats,
4904         .get_sset_count = nv_get_sset_count,
4905         .self_test = nv_self_test,
4906 };
4907
4908 /* The mgmt unit and driver use a semaphore to access the phy during init */
4909 static int nv_mgmt_acquire_sema(struct net_device *dev)
4910 {
4911         struct fe_priv *np = netdev_priv(dev);
4912         u8 __iomem *base = get_hwbase(dev);
4913         int i;
4914         u32 tx_ctrl, mgmt_sema;
4915
4916         for (i = 0; i < 10; i++) {
4917                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4918                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4919                         break;
4920                 msleep(500);
4921         }
4922
4923         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4924                 return 0;
4925
4926         for (i = 0; i < 2; i++) {
4927                 tx_ctrl = readl(base + NvRegTransmitterControl);
4928                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4929                 writel(tx_ctrl, base + NvRegTransmitterControl);
4930
4931                 /* verify that semaphore was acquired */
4932                 tx_ctrl = readl(base + NvRegTransmitterControl);
4933                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4934                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4935                         np->mgmt_sema = 1;
4936                         return 1;
4937                 } else
4938                         udelay(50);
4939         }
4940
4941         return 0;
4942 }
4943
4944 static void nv_mgmt_release_sema(struct net_device *dev)
4945 {
4946         struct fe_priv *np = netdev_priv(dev);
4947         u8 __iomem *base = get_hwbase(dev);
4948         u32 tx_ctrl;
4949
4950         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4951                 if (np->mgmt_sema) {
4952                         tx_ctrl = readl(base + NvRegTransmitterControl);
4953                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4954                         writel(tx_ctrl, base + NvRegTransmitterControl);
4955                 }
4956         }
4957 }
4958
4959
4960 static int nv_mgmt_get_version(struct net_device *dev)
4961 {
4962         struct fe_priv *np = netdev_priv(dev);
4963         u8 __iomem *base = get_hwbase(dev);
4964         u32 data_ready = readl(base + NvRegTransmitterControl);
4965         u32 data_ready2 = 0;
4966         unsigned long start;
4967         int ready = 0;
4968
4969         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4970         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
4971         start = jiffies;
4972         while (time_before(jiffies, start + 5*HZ)) {
4973                 data_ready2 = readl(base + NvRegTransmitterControl);
4974                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
4975                         ready = 1;
4976                         break;
4977                 }
4978                 schedule_timeout_uninterruptible(1);
4979         }
4980
4981         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
4982                 return 0;
4983
4984         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
4985
4986         return 1;
4987 }
4988
4989 static int nv_open(struct net_device *dev)
4990 {
4991         struct fe_priv *np = netdev_priv(dev);
4992         u8 __iomem *base = get_hwbase(dev);
4993         int ret = 1;
4994         int oom, i;
4995         u32 low;
4996
4997         /* power up phy */
4998         mii_rw(dev, np->phyaddr, MII_BMCR,
4999                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5000
5001         nv_txrx_gate(dev, false);
5002         /* erase previous misconfiguration */
5003         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5004                 nv_mac_reset(dev);
5005         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5006         writel(0, base + NvRegMulticastAddrB);
5007         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5008         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5009         writel(0, base + NvRegPacketFilterFlags);
5010
5011         writel(0, base + NvRegTransmitterControl);
5012         writel(0, base + NvRegReceiverControl);
5013
5014         writel(0, base + NvRegAdapterControl);
5015
5016         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5017                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5018
5019         /* initialize descriptor rings */
5020         set_bufsize(dev);
5021         oom = nv_init_ring(dev);
5022
5023         writel(0, base + NvRegLinkSpeed);
5024         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5025         nv_txrx_reset(dev);
5026         writel(0, base + NvRegUnknownSetupReg6);
5027
5028         np->in_shutdown = 0;
5029
5030         /* give hw rings */
5031         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5032         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5033                 base + NvRegRingSizes);
5034
5035         writel(np->linkspeed, base + NvRegLinkSpeed);
5036         if (np->desc_ver == DESC_VER_1)
5037                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5038         else
5039                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5040         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5041         writel(np->vlanctl_bits, base + NvRegVlanControl);
5042         pci_push(base);
5043         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5044         if (reg_delay(dev, NvRegUnknownSetupReg5,
5045                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5046                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5047                 netdev_info(dev,
5048                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5049
5050         writel(0, base + NvRegMIIMask);
5051         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5052         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5053
5054         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5055         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5056         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5057         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5058
5059         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5060
5061         get_random_bytes(&low, sizeof(low));
5062         low &= NVREG_SLOTTIME_MASK;
5063         if (np->desc_ver == DESC_VER_1) {
5064                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5065         } else {
5066                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5067                         /* setup legacy backoff */
5068                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5069                 } else {
5070                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5071                         nv_gear_backoff_reseed(dev);
5072                 }
5073         }
5074         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5075         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5076         if (poll_interval == -1) {
5077                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5078                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5079                 else
5080                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5081         } else
5082                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5083         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5084         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5085                         base + NvRegAdapterControl);
5086         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5087         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5088         if (np->wolenabled)
5089                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5090
5091         i = readl(base + NvRegPowerState);
5092         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5093                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5094
5095         pci_push(base);
5096         udelay(10);
5097         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5098
5099         nv_disable_hw_interrupts(dev, np->irqmask);
5100         pci_push(base);
5101         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5102         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5103         pci_push(base);
5104
5105         if (nv_request_irq(dev, 0))
5106                 goto out_drain;
5107
5108         /* ask for interrupts */
5109         nv_enable_hw_interrupts(dev, np->irqmask);
5110
5111         spin_lock_irq(&np->lock);
5112         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5113         writel(0, base + NvRegMulticastAddrB);
5114         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5115         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5116         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5117         /* One manual link speed update: Interrupts are enabled, future link
5118          * speed changes cause interrupts and are handled by nv_link_irq().
5119          */
5120         {
5121                 u32 miistat;
5122                 miistat = readl(base + NvRegMIIStatus);
5123                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5124         }
5125         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5126          * to init hw */
5127         np->linkspeed = 0;
5128         ret = nv_update_linkspeed(dev);
5129         nv_start_rxtx(dev);
5130         netif_start_queue(dev);
5131         nv_napi_enable(dev);
5132
5133         if (ret) {
5134                 netif_carrier_on(dev);
5135         } else {
5136                 netdev_info(dev, "no link during initialization\n");
5137                 netif_carrier_off(dev);
5138         }
5139         if (oom)
5140                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5141
5142         /* start statistics timer */
5143         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5144                 mod_timer(&np->stats_poll,
5145                         round_jiffies(jiffies + STATS_INTERVAL));
5146
5147         spin_unlock_irq(&np->lock);
5148
5149         return 0;
5150 out_drain:
5151         nv_drain_rxtx(dev);
5152         return ret;
5153 }
5154
5155 static int nv_close(struct net_device *dev)
5156 {
5157         struct fe_priv *np = netdev_priv(dev);
5158         u8 __iomem *base;
5159
5160         spin_lock_irq(&np->lock);
5161         np->in_shutdown = 1;
5162         spin_unlock_irq(&np->lock);
5163         nv_napi_disable(dev);
5164         synchronize_irq(np->pci_dev->irq);
5165
5166         del_timer_sync(&np->oom_kick);
5167         del_timer_sync(&np->nic_poll);
5168         del_timer_sync(&np->stats_poll);
5169
5170         netif_stop_queue(dev);
5171         spin_lock_irq(&np->lock);
5172         nv_stop_rxtx(dev);
5173         nv_txrx_reset(dev);
5174
5175         /* disable interrupts on the nic or we will lock up */
5176         base = get_hwbase(dev);
5177         nv_disable_hw_interrupts(dev, np->irqmask);
5178         pci_push(base);
5179
5180         spin_unlock_irq(&np->lock);
5181
5182         nv_free_irq(dev);
5183
5184         nv_drain_rxtx(dev);
5185
5186         if (np->wolenabled || !phy_power_down) {
5187                 nv_txrx_gate(dev, false);
5188                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5189                 nv_start_rx(dev);
5190         } else {
5191                 /* power down phy */
5192                 mii_rw(dev, np->phyaddr, MII_BMCR,
5193                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5194                 nv_txrx_gate(dev, true);
5195         }
5196
5197         /* FIXME: power down nic */
5198
5199         return 0;
5200 }
5201
5202 static const struct net_device_ops nv_netdev_ops = {
5203         .ndo_open               = nv_open,
5204         .ndo_stop               = nv_close,
5205         .ndo_get_stats          = nv_get_stats,
5206         .ndo_start_xmit         = nv_start_xmit,
5207         .ndo_tx_timeout         = nv_tx_timeout,
5208         .ndo_change_mtu         = nv_change_mtu,
5209         .ndo_fix_features       = nv_fix_features,
5210         .ndo_set_features       = nv_set_features,
5211         .ndo_validate_addr      = eth_validate_addr,
5212         .ndo_set_mac_address    = nv_set_mac_address,
5213         .ndo_set_rx_mode        = nv_set_multicast,
5214 #ifdef CONFIG_NET_POLL_CONTROLLER
5215         .ndo_poll_controller    = nv_poll_controller,
5216 #endif
5217 };
5218
5219 static const struct net_device_ops nv_netdev_ops_optimized = {
5220         .ndo_open               = nv_open,
5221         .ndo_stop               = nv_close,
5222         .ndo_get_stats          = nv_get_stats,
5223         .ndo_start_xmit         = nv_start_xmit_optimized,
5224         .ndo_tx_timeout         = nv_tx_timeout,
5225         .ndo_change_mtu         = nv_change_mtu,
5226         .ndo_fix_features       = nv_fix_features,
5227         .ndo_set_features       = nv_set_features,
5228         .ndo_validate_addr      = eth_validate_addr,
5229         .ndo_set_mac_address    = nv_set_mac_address,
5230         .ndo_set_rx_mode        = nv_set_multicast,
5231 #ifdef CONFIG_NET_POLL_CONTROLLER
5232         .ndo_poll_controller    = nv_poll_controller,
5233 #endif
5234 };
5235
5236 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5237 {
5238         struct net_device *dev;
5239         struct fe_priv *np;
5240         unsigned long addr;
5241         u8 __iomem *base;
5242         int err, i;
5243         u32 powerstate, txreg;
5244         u32 phystate_orig = 0, phystate;
5245         int phyinitialized = 0;
5246         static int printed_version;
5247
5248         if (!printed_version++)
5249                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5250                         FORCEDETH_VERSION);
5251
5252         dev = alloc_etherdev(sizeof(struct fe_priv));
5253         err = -ENOMEM;
5254         if (!dev)
5255                 goto out;
5256
5257         np = netdev_priv(dev);
5258         np->dev = dev;
5259         np->pci_dev = pci_dev;
5260         spin_lock_init(&np->lock);
5261         SET_NETDEV_DEV(dev, &pci_dev->dev);
5262
5263         init_timer(&np->oom_kick);
5264         np->oom_kick.data = (unsigned long) dev;
5265         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5266         init_timer(&np->nic_poll);
5267         np->nic_poll.data = (unsigned long) dev;
5268         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5269         init_timer(&np->stats_poll);
5270         np->stats_poll.data = (unsigned long) dev;
5271         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5272
5273         err = pci_enable_device(pci_dev);
5274         if (err)
5275                 goto out_free;
5276
5277         pci_set_master(pci_dev);
5278
5279         err = pci_request_regions(pci_dev, DRV_NAME);
5280         if (err < 0)
5281                 goto out_disable;
5282
5283         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5284                 np->register_size = NV_PCI_REGSZ_VER3;
5285         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5286                 np->register_size = NV_PCI_REGSZ_VER2;
5287         else
5288                 np->register_size = NV_PCI_REGSZ_VER1;
5289
5290         err = -EINVAL;
5291         addr = 0;
5292         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5293                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5294                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5295                         addr = pci_resource_start(pci_dev, i);
5296                         break;
5297                 }
5298         }
5299         if (i == DEVICE_COUNT_RESOURCE) {
5300                 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5301                 goto out_relreg;
5302         }
5303
5304         /* copy of driver data */
5305         np->driver_data = id->driver_data;
5306         /* copy of device id */
5307         np->device_id = id->device;
5308
5309         /* handle different descriptor versions */
5310         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5311                 /* packet format 3: supports 40-bit addressing */
5312                 np->desc_ver = DESC_VER_3;
5313                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5314                 if (dma_64bit) {
5315                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5316                                 dev_info(&pci_dev->dev,
5317                                          "64-bit DMA failed, using 32-bit addressing\n");
5318                         else
5319                                 dev->features |= NETIF_F_HIGHDMA;
5320                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5321                                 dev_info(&pci_dev->dev,
5322                                          "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5323                         }
5324                 }
5325         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5326                 /* packet format 2: supports jumbo frames */
5327                 np->desc_ver = DESC_VER_2;
5328                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5329         } else {
5330                 /* original packet format */
5331                 np->desc_ver = DESC_VER_1;
5332                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5333         }
5334
5335         np->pkt_limit = NV_PKTLIMIT_1;
5336         if (id->driver_data & DEV_HAS_LARGEDESC)
5337                 np->pkt_limit = NV_PKTLIMIT_2;
5338
5339         if (id->driver_data & DEV_HAS_CHECKSUM) {
5340                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5341                 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5342                         NETIF_F_TSO | NETIF_F_RXCSUM;
5343         }
5344
5345         np->vlanctl_bits = 0;
5346         if (id->driver_data & DEV_HAS_VLAN) {
5347                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5348                 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5349         }
5350
5351         dev->features |= dev->hw_features;
5352
5353         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5354         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5355             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5356             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5357                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5358         }
5359
5360         err = -ENOMEM;
5361         np->base = ioremap(addr, np->register_size);
5362         if (!np->base)
5363                 goto out_relreg;
5364         dev->base_addr = (unsigned long)np->base;
5365
5366         dev->irq = pci_dev->irq;
5367
5368         np->rx_ring_size = RX_RING_DEFAULT;
5369         np->tx_ring_size = TX_RING_DEFAULT;
5370
5371         if (!nv_optimized(np)) {
5372                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5373                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5374                                         &np->ring_addr);
5375                 if (!np->rx_ring.orig)
5376                         goto out_unmap;
5377                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5378         } else {
5379                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5380                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5381                                         &np->ring_addr);
5382                 if (!np->rx_ring.ex)
5383                         goto out_unmap;
5384                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5385         }
5386         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5387         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5388         if (!np->rx_skb || !np->tx_skb)
5389                 goto out_freering;
5390
5391         if (!nv_optimized(np))
5392                 dev->netdev_ops = &nv_netdev_ops;
5393         else
5394                 dev->netdev_ops = &nv_netdev_ops_optimized;
5395
5396         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5397         SET_ETHTOOL_OPS(dev, &ops);
5398         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5399
5400         pci_set_drvdata(pci_dev, dev);
5401
5402         /* read the mac address */
5403         base = get_hwbase(dev);
5404         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5405         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5406
5407         /* check the workaround bit for correct mac address order */
5408         txreg = readl(base + NvRegTransmitPoll);
5409         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5410                 /* mac address is already in correct order */
5411                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5412                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5413                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5414                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5415                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5416                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5417         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5418                 /* mac address is already in correct order */
5419                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5420                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5421                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5422                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5423                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5424                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5425                 /*
5426                  * Set orig mac address back to the reversed version.
5427                  * This flag will be cleared during low power transition.
5428                  * Therefore, we should always put back the reversed address.
5429                  */
5430                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5431                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5432                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5433         } else {
5434                 /* need to reverse mac address to correct order */
5435                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5436                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5437                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5438                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5439                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5440                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5441                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5442                 dev_dbg(&pci_dev->dev,
5443                         "%s: set workaround bit for reversed mac addr\n",
5444                         __func__);
5445         }
5446         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5447
5448         if (!is_valid_ether_addr(dev->perm_addr)) {
5449                 /*
5450                  * Bad mac address. At least one bios sets the mac address
5451                  * to 01:23:45:67:89:ab
5452                  */
5453                 dev_err(&pci_dev->dev,
5454                         "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5455                         dev->dev_addr);
5456                 random_ether_addr(dev->dev_addr);
5457                 dev_err(&pci_dev->dev,
5458                         "Using random MAC address: %pM\n", dev->dev_addr);
5459         }
5460
5461         /* set mac address */
5462         nv_copy_mac_to_hw(dev);
5463
5464         /* disable WOL */
5465         writel(0, base + NvRegWakeUpFlags);
5466         np->wolenabled = 0;
5467         device_set_wakeup_enable(&pci_dev->dev, false);
5468
5469         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5470
5471                 /* take phy and nic out of low power mode */
5472                 powerstate = readl(base + NvRegPowerState2);
5473                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5474                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5475                     pci_dev->revision >= 0xA3)
5476                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5477                 writel(powerstate, base + NvRegPowerState2);
5478         }
5479
5480         if (np->desc_ver == DESC_VER_1)
5481                 np->tx_flags = NV_TX_VALID;
5482         else
5483                 np->tx_flags = NV_TX2_VALID;
5484
5485         np->msi_flags = 0;
5486         if ((id->driver_data & DEV_HAS_MSI) && msi)
5487                 np->msi_flags |= NV_MSI_CAPABLE;
5488
5489         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5490                 /* msix has had reported issues when modifying irqmask
5491                    as in the case of napi, therefore, disable for now
5492                 */
5493 #if 0
5494                 np->msi_flags |= NV_MSI_X_CAPABLE;
5495 #endif
5496         }
5497
5498         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5499                 np->irqmask = NVREG_IRQMASK_CPU;
5500                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5501                         np->msi_flags |= 0x0001;
5502         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5503                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5504                 /* start off in throughput mode */
5505                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5506                 /* remove support for msix mode */
5507                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5508         } else {
5509                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5510                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5511                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5512                         np->msi_flags |= 0x0003;
5513         }
5514
5515         if (id->driver_data & DEV_NEED_TIMERIRQ)
5516                 np->irqmask |= NVREG_IRQ_TIMER;
5517         if (id->driver_data & DEV_NEED_LINKTIMER) {
5518                 np->need_linktimer = 1;
5519                 np->link_timeout = jiffies + LINK_TIMEOUT;
5520         } else {
5521                 np->need_linktimer = 0;
5522         }
5523
5524         /* Limit the number of tx's outstanding for hw bug */
5525         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5526                 np->tx_limit = 1;
5527                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5528                     pci_dev->revision >= 0xA2)
5529                         np->tx_limit = 0;
5530         }
5531
5532         /* clear phy state and temporarily halt phy interrupts */
5533         writel(0, base + NvRegMIIMask);
5534         phystate = readl(base + NvRegAdapterControl);
5535         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5536                 phystate_orig = 1;
5537                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5538                 writel(phystate, base + NvRegAdapterControl);
5539         }
5540         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5541
5542         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5543                 /* management unit running on the mac? */
5544                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5545                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5546                     nv_mgmt_acquire_sema(dev) &&
5547                     nv_mgmt_get_version(dev)) {
5548                         np->mac_in_use = 1;
5549                         if (np->mgmt_version > 0)
5550                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5551                         /* management unit setup the phy already? */
5552                         if (np->mac_in_use &&
5553                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5554                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5555                                 /* phy is inited by mgmt unit */
5556                                 phyinitialized = 1;
5557                         } else {
5558                                 /* we need to init the phy */
5559                         }
5560                 }
5561         }
5562
5563         /* find a suitable phy */
5564         for (i = 1; i <= 32; i++) {
5565                 int id1, id2;
5566                 int phyaddr = i & 0x1F;
5567
5568                 spin_lock_irq(&np->lock);
5569                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5570                 spin_unlock_irq(&np->lock);
5571                 if (id1 < 0 || id1 == 0xffff)
5572                         continue;
5573                 spin_lock_irq(&np->lock);
5574                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5575                 spin_unlock_irq(&np->lock);
5576                 if (id2 < 0 || id2 == 0xffff)
5577                         continue;
5578
5579                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5580                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5581                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5582                 np->phyaddr = phyaddr;
5583                 np->phy_oui = id1 | id2;
5584
5585                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5586                 if (np->phy_oui == PHY_OUI_REALTEK2)
5587                         np->phy_oui = PHY_OUI_REALTEK;
5588                 /* Setup phy revision for Realtek */
5589                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5590                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5591
5592                 break;
5593         }
5594         if (i == 33) {
5595                 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5596                 goto out_error;
5597         }
5598
5599         if (!phyinitialized) {
5600                 /* reset it */
5601                 phy_init(dev);
5602         } else {
5603                 /* see if it is a gigabit phy */
5604                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5605                 if (mii_status & PHY_GIGABIT)
5606                         np->gigabit = PHY_GIGABIT;
5607         }
5608
5609         /* set default link speed settings */
5610         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5611         np->duplex = 0;
5612         np->autoneg = 1;
5613
5614         err = register_netdev(dev);
5615         if (err) {
5616                 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5617                 goto out_error;
5618         }
5619
5620         if (id->driver_data & DEV_HAS_VLAN)
5621                 nv_vlan_mode(dev, dev->features);
5622
5623         netif_carrier_off(dev);
5624
5625         dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5626                  dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5627
5628         dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5629                  dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5630                  dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5631                         "csum " : "",
5632                  dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5633                         "vlan " : "",
5634                  id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5635                  id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5636                  id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5637                  np->gigabit == PHY_GIGABIT ? "gbit " : "",
5638                  np->need_linktimer ? "lnktim " : "",
5639                  np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5640                  np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5641                  np->desc_ver);
5642
5643         return 0;
5644
5645 out_error:
5646         if (phystate_orig)
5647                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5648         pci_set_drvdata(pci_dev, NULL);
5649 out_freering:
5650         free_rings(dev);
5651 out_unmap:
5652         iounmap(get_hwbase(dev));
5653 out_relreg:
5654         pci_release_regions(pci_dev);
5655 out_disable:
5656         pci_disable_device(pci_dev);
5657 out_free:
5658         free_netdev(dev);
5659 out:
5660         return err;
5661 }
5662
5663 static void nv_restore_phy(struct net_device *dev)
5664 {
5665         struct fe_priv *np = netdev_priv(dev);
5666         u16 phy_reserved, mii_control;
5667
5668         if (np->phy_oui == PHY_OUI_REALTEK &&
5669             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5670             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5671                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5672                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5673                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5674                 phy_reserved |= PHY_REALTEK_INIT8;
5675                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5676                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5677
5678                 /* restart auto negotiation */
5679                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5680                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5681                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5682         }
5683 }
5684
5685 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5686 {
5687         struct net_device *dev = pci_get_drvdata(pci_dev);
5688         struct fe_priv *np = netdev_priv(dev);
5689         u8 __iomem *base = get_hwbase(dev);
5690
5691         /* special op: write back the misordered MAC address - otherwise
5692          * the next nv_probe would see a wrong address.
5693          */
5694         writel(np->orig_mac[0], base + NvRegMacAddrA);
5695         writel(np->orig_mac[1], base + NvRegMacAddrB);
5696         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5697                base + NvRegTransmitPoll);
5698 }
5699
5700 static void __devexit nv_remove(struct pci_dev *pci_dev)
5701 {
5702         struct net_device *dev = pci_get_drvdata(pci_dev);
5703
5704         unregister_netdev(dev);
5705
5706         nv_restore_mac_addr(pci_dev);
5707
5708         /* restore any phy related changes */
5709         nv_restore_phy(dev);
5710
5711         nv_mgmt_release_sema(dev);
5712
5713         /* free all structures */
5714         free_rings(dev);
5715         iounmap(get_hwbase(dev));
5716         pci_release_regions(pci_dev);
5717         pci_disable_device(pci_dev);
5718         free_netdev(dev);
5719         pci_set_drvdata(pci_dev, NULL);
5720 }
5721
5722 #ifdef CONFIG_PM_SLEEP
5723 static int nv_suspend(struct device *device)
5724 {
5725         struct pci_dev *pdev = to_pci_dev(device);
5726         struct net_device *dev = pci_get_drvdata(pdev);
5727         struct fe_priv *np = netdev_priv(dev);
5728         u8 __iomem *base = get_hwbase(dev);
5729         int i;
5730
5731         if (netif_running(dev)) {
5732                 /* Gross. */
5733                 nv_close(dev);
5734         }
5735         netif_device_detach(dev);
5736
5737         /* save non-pci configuration space */
5738         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5739                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5740
5741         return 0;
5742 }
5743
5744 static int nv_resume(struct device *device)
5745 {
5746         struct pci_dev *pdev = to_pci_dev(device);
5747         struct net_device *dev = pci_get_drvdata(pdev);
5748         struct fe_priv *np = netdev_priv(dev);
5749         u8 __iomem *base = get_hwbase(dev);
5750         int i, rc = 0;
5751
5752         /* restore non-pci configuration space */
5753         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5754                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5755
5756         if (np->driver_data & DEV_NEED_MSI_FIX)
5757                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5758
5759         /* restore phy state, including autoneg */
5760         phy_init(dev);
5761
5762         netif_device_attach(dev);
5763         if (netif_running(dev)) {
5764                 rc = nv_open(dev);
5765                 nv_set_multicast(dev);
5766         }
5767         return rc;
5768 }
5769
5770 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5771 #define NV_PM_OPS (&nv_pm_ops)
5772
5773 #else
5774 #define NV_PM_OPS NULL
5775 #endif /* CONFIG_PM_SLEEP */
5776
5777 #ifdef CONFIG_PM
5778 static void nv_shutdown(struct pci_dev *pdev)
5779 {
5780         struct net_device *dev = pci_get_drvdata(pdev);
5781         struct fe_priv *np = netdev_priv(dev);
5782
5783         if (netif_running(dev))
5784                 nv_close(dev);
5785
5786         /*
5787          * Restore the MAC so a kernel started by kexec won't get confused.
5788          * If we really go for poweroff, we must not restore the MAC,
5789          * otherwise the MAC for WOL will be reversed at least on some boards.
5790          */
5791         if (system_state != SYSTEM_POWER_OFF)
5792                 nv_restore_mac_addr(pdev);
5793
5794         pci_disable_device(pdev);
5795         /*
5796          * Apparently it is not possible to reinitialise from D3 hot,
5797          * only put the device into D3 if we really go for poweroff.
5798          */
5799         if (system_state == SYSTEM_POWER_OFF) {
5800                 pci_wake_from_d3(pdev, np->wolenabled);
5801                 pci_set_power_state(pdev, PCI_D3hot);
5802         }
5803 }
5804 #else
5805 #define nv_shutdown NULL
5806 #endif /* CONFIG_PM */
5807
5808 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5809         {       /* nForce Ethernet Controller */
5810                 PCI_DEVICE(0x10DE, 0x01C3),
5811                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5812         },
5813         {       /* nForce2 Ethernet Controller */
5814                 PCI_DEVICE(0x10DE, 0x0066),
5815                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5816         },
5817         {       /* nForce3 Ethernet Controller */
5818                 PCI_DEVICE(0x10DE, 0x00D6),
5819                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5820         },
5821         {       /* nForce3 Ethernet Controller */
5822                 PCI_DEVICE(0x10DE, 0x0086),
5823                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5824         },
5825         {       /* nForce3 Ethernet Controller */
5826                 PCI_DEVICE(0x10DE, 0x008C),
5827                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5828         },
5829         {       /* nForce3 Ethernet Controller */
5830                 PCI_DEVICE(0x10DE, 0x00E6),
5831                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5832         },
5833         {       /* nForce3 Ethernet Controller */
5834                 PCI_DEVICE(0x10DE, 0x00DF),
5835                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5836         },
5837         {       /* CK804 Ethernet Controller */
5838                 PCI_DEVICE(0x10DE, 0x0056),
5839                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5840         },
5841         {       /* CK804 Ethernet Controller */
5842                 PCI_DEVICE(0x10DE, 0x0057),
5843                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5844         },
5845         {       /* MCP04 Ethernet Controller */
5846                 PCI_DEVICE(0x10DE, 0x0037),
5847                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5848         },
5849         {       /* MCP04 Ethernet Controller */
5850                 PCI_DEVICE(0x10DE, 0x0038),
5851                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5852         },
5853         {       /* MCP51 Ethernet Controller */
5854                 PCI_DEVICE(0x10DE, 0x0268),
5855                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5856         },
5857         {       /* MCP51 Ethernet Controller */
5858                 PCI_DEVICE(0x10DE, 0x0269),
5859                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5860         },
5861         {       /* MCP55 Ethernet Controller */
5862                 PCI_DEVICE(0x10DE, 0x0372),
5863                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5864         },
5865         {       /* MCP55 Ethernet Controller */
5866                 PCI_DEVICE(0x10DE, 0x0373),
5867                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5868         },
5869         {       /* MCP61 Ethernet Controller */
5870                 PCI_DEVICE(0x10DE, 0x03E5),
5871                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5872         },
5873         {       /* MCP61 Ethernet Controller */
5874                 PCI_DEVICE(0x10DE, 0x03E6),
5875                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5876         },
5877         {       /* MCP61 Ethernet Controller */
5878                 PCI_DEVICE(0x10DE, 0x03EE),
5879                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5880         },
5881         {       /* MCP61 Ethernet Controller */
5882                 PCI_DEVICE(0x10DE, 0x03EF),
5883                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5884         },
5885         {       /* MCP65 Ethernet Controller */
5886                 PCI_DEVICE(0x10DE, 0x0450),
5887                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5888         },
5889         {       /* MCP65 Ethernet Controller */
5890                 PCI_DEVICE(0x10DE, 0x0451),
5891                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5892         },
5893         {       /* MCP65 Ethernet Controller */
5894                 PCI_DEVICE(0x10DE, 0x0452),
5895                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5896         },
5897         {       /* MCP65 Ethernet Controller */
5898                 PCI_DEVICE(0x10DE, 0x0453),
5899                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5900         },
5901         {       /* MCP67 Ethernet Controller */
5902                 PCI_DEVICE(0x10DE, 0x054C),
5903                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5904         },
5905         {       /* MCP67 Ethernet Controller */
5906                 PCI_DEVICE(0x10DE, 0x054D),
5907                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5908         },
5909         {       /* MCP67 Ethernet Controller */
5910                 PCI_DEVICE(0x10DE, 0x054E),
5911                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5912         },
5913         {       /* MCP67 Ethernet Controller */
5914                 PCI_DEVICE(0x10DE, 0x054F),
5915                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5916         },
5917         {       /* MCP73 Ethernet Controller */
5918                 PCI_DEVICE(0x10DE, 0x07DC),
5919                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5920         },
5921         {       /* MCP73 Ethernet Controller */
5922                 PCI_DEVICE(0x10DE, 0x07DD),
5923                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5924         },
5925         {       /* MCP73 Ethernet Controller */
5926                 PCI_DEVICE(0x10DE, 0x07DE),
5927                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5928         },
5929         {       /* MCP73 Ethernet Controller */
5930                 PCI_DEVICE(0x10DE, 0x07DF),
5931                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5932         },
5933         {       /* MCP77 Ethernet Controller */
5934                 PCI_DEVICE(0x10DE, 0x0760),
5935                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5936         },
5937         {       /* MCP77 Ethernet Controller */
5938                 PCI_DEVICE(0x10DE, 0x0761),
5939                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5940         },
5941         {       /* MCP77 Ethernet Controller */
5942                 PCI_DEVICE(0x10DE, 0x0762),
5943                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5944         },
5945         {       /* MCP77 Ethernet Controller */
5946                 PCI_DEVICE(0x10DE, 0x0763),
5947                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5948         },
5949         {       /* MCP79 Ethernet Controller */
5950                 PCI_DEVICE(0x10DE, 0x0AB0),
5951                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5952         },
5953         {       /* MCP79 Ethernet Controller */
5954                 PCI_DEVICE(0x10DE, 0x0AB1),
5955                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5956         },
5957         {       /* MCP79 Ethernet Controller */
5958                 PCI_DEVICE(0x10DE, 0x0AB2),
5959                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5960         },
5961         {       /* MCP79 Ethernet Controller */
5962                 PCI_DEVICE(0x10DE, 0x0AB3),
5963                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5964         },
5965         {       /* MCP89 Ethernet Controller */
5966                 PCI_DEVICE(0x10DE, 0x0D7D),
5967                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
5968         },
5969         {0,},
5970 };
5971
5972 static struct pci_driver driver = {
5973         .name           = DRV_NAME,
5974         .id_table       = pci_tbl,
5975         .probe          = nv_probe,
5976         .remove         = __devexit_p(nv_remove),
5977         .shutdown       = nv_shutdown,
5978         .driver.pm      = NV_PM_OPS,
5979 };
5980
5981 static int __init init_nic(void)
5982 {
5983         return pci_register_driver(&driver);
5984 }
5985
5986 static void __exit exit_nic(void)
5987 {
5988         pci_unregister_driver(&driver);
5989 }
5990
5991 module_param(max_interrupt_work, int, 0);
5992 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5993 module_param(optimization_mode, int, 0);
5994 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
5995 module_param(poll_interval, int, 0);
5996 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5997 module_param(msi, int, 0);
5998 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5999 module_param(msix, int, 0);
6000 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6001 module_param(dma_64bit, int, 0);
6002 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6003 module_param(phy_cross, int, 0);
6004 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6005 module_param(phy_power_down, int, 0);
6006 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6007
6008 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6009 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6010 MODULE_LICENSE("GPL");
6011
6012 MODULE_DEVICE_TABLE(pci, pci_tbl);
6013
6014 module_init(init_nic);
6015 module_exit(exit_nic);