drivers/net/ethernet/qlogic/qed/qed_cxt.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/bitops.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/list.h>
  39 #include <linux/log2.h>
  40 #include <linux/pci.h>
  41 #include <linux/slab.h>
  42 #include <linux/string.h>
  43 #include <linux/bitops.h>
  44 #include "qed.h"
  45 #include "qed_cxt.h"
  46 #include "qed_dev_api.h"
  47 #include "qed_hsi.h"
  48 #include "qed_hw.h"
  49 #include "qed_init_ops.h"
  50 #include "qed_reg_addr.h"
  51 #include "qed_sriov.h"
  52
  53 /* Max number of connection types in HW (DQ/CDU etc.) */
  54 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  55 #define NUM_TASK_TYPES          2
  56 #define NUM_TASK_PF_SEGMENTS    4
  57 #define NUM_TASK_VF_SEGMENTS    1
  58
  59 /* QM constants */
  60 #define QM_PQ_ELEMENT_SIZE      4 /* in bytes */
  61
  62 /* Doorbell-Queue constants */
  63 #define DQ_RANGE_SHIFT          4
  64 #define DQ_RANGE_ALIGN          BIT(DQ_RANGE_SHIFT)
  65
  66 /* Searcher constants */
  67 #define SRC_MIN_NUM_ELEMS 256
  68
  69 /* Timers constants */
  70 #define TM_SHIFT        7
  71 #define TM_ALIGN        BIT(TM_SHIFT)
  72 #define TM_ELEM_SIZE    4
  73
  74 #define ILT_DEFAULT_HW_P_SIZE   4
  75
  76 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  77 #define ILT_CFG_REG(cli, reg)   PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
  78
  79 /* ILT entry structure */
  80 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  81 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  82 #define ILT_ENTRY_VALID_MASK            0x1ULL
  83 #define ILT_ENTRY_VALID_SHIFT           52
  84 #define ILT_ENTRY_IN_REGS               2
  85 #define ILT_REG_SIZE_IN_BYTES           4
  86
  87 /* connection context union */
  88 union conn_context {
  89         struct core_conn_context core_ctx;
  90         struct eth_conn_context eth_ctx;
  91         struct iscsi_conn_context iscsi_ctx;
  92         struct fcoe_conn_context fcoe_ctx;
  93         struct roce_conn_context roce_ctx;
  94 };
  95
  96 /* TYPE-0 task context - iSCSI, FCOE */
  97 union type0_task_context {
  98         struct iscsi_task_context iscsi_ctx;
  99         struct fcoe_task_context fcoe_ctx;
 100 };
 101
 102 /* TYPE-1 task context - ROCE */
 103 union type1_task_context {
 104         struct rdma_task_context roce_ctx;
 105 };
 106
 107 struct src_ent {
 108         u8 opaque[56];
 109         u64 next;
 110 };
 111
 112 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
 113 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
 114
 115 #define CONN_CXT_SIZE(p_hwfn) \
 116         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
 117
 118 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
 119
 120 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
 121         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
 122
 123 /* Alignment is inherent to the type1_task_context structure */
 124 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
 125
 126 /* PF per protocl configuration object */
 127 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 128 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 129
 130 struct qed_tid_seg {
 131         u32 count;
 132         u8 type;
 133         bool has_fl_mem;
 134 };
 135
 136 struct qed_conn_type_cfg {
 137         u32 cid_count;
 138         u32 cid_start;
 139         u32 cids_per_vf;
 140         struct qed_tid_seg tid_seg[TASK_SEGMENTS];
 141 };
 142
 143 /* ILT Client configuration, Per connection type (protocol) resources. */
 144 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 145 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 146 #define CDUC_BLK                (0)
 147 #define SRQ_BLK                 (0)
 148 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 149 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
 150
 151 enum ilt_clients {
 152         ILT_CLI_CDUC,
 153         ILT_CLI_CDUT,
 154         ILT_CLI_QM,
 155         ILT_CLI_TM,
 156         ILT_CLI_SRC,
 157         ILT_CLI_TSDM,
 158         ILT_CLI_MAX
 159 };
 160
 161 struct ilt_cfg_pair {
 162         u32 reg;
 163         u32 val;
 164 };
 165
 166 struct qed_ilt_cli_blk {
 167         u32 total_size; /* 0 means not active */
 168         u32 real_size_in_page;
 169         u32 start_line;
 170         u32 dynamic_line_cnt;
 171 };
 172
 173 struct qed_ilt_client_cfg {
 174         bool active;
 175
 176         /* ILT boundaries */
 177         struct ilt_cfg_pair first;
 178         struct ilt_cfg_pair last;
 179         struct ilt_cfg_pair p_size;
 180
 181         /* ILT client blocks for PF */
 182         struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 183         u32 pf_total_lines;
 184
 185         /* ILT client blocks for VFs */
 186         struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 187         u32 vf_total_lines;
 188 };
 189
 190 /* Per Path -
 191  *      ILT shadow table
 192  *      Protocol acquired CID lists
 193  *      PF start line in ILT
 194  */
 195 struct qed_dma_mem {
 196         dma_addr_t p_phys;
 197         void *p_virt;
 198         size_t size;
 199 };
 200
 201 struct qed_cid_acquired_map {
 202         u32             start_cid;
 203         u32             max_count;
 204         unsigned long   *cid_map;
 205 };
 206
 207 struct qed_cxt_mngr {
 208         /* Per protocl configuration */
 209         struct qed_conn_type_cfg        conn_cfg[MAX_CONN_TYPES];
 210
 211         /* computed ILT structure */
 212         struct qed_ilt_client_cfg       clients[ILT_CLI_MAX];
 213
 214         /* Task type sizes */
 215         u32 task_type_size[NUM_TASK_TYPES];
 216
 217         /* total number of VFs for this hwfn -
 218          * ALL VFs are symmetric in terms of HW resources
 219          */
 220         u32                             vf_count;
 221
 222         /* total number of SRQ's for this hwfn */
 223         u32 srq_count;
 224
 225         /* Acquired CIDs */
 226         struct qed_cid_acquired_map     acquired[MAX_CONN_TYPES];
 227
 228         /* ILT  shadow table */
 229         struct qed_dma_mem              *ilt_shadow;
 230         u32                             pf_start_line;
 231
 232         /* Mutex for a dynamic ILT allocation */
 233         struct mutex mutex;
 234
 235         /* SRC T2 */
 236         struct qed_dma_mem *t2;
 237         u32 t2_num_pages;
 238         u64 first_free;
 239         u64 last_free;
 240 };
 241 static bool src_proto(enum protocol_type type)
 242 {
 243         return type == PROTOCOLID_ISCSI ||
 244                type == PROTOCOLID_FCOE ||
 245                type == PROTOCOLID_ROCE;
 246 }
 247
 248 static bool tm_cid_proto(enum protocol_type type)
 249 {
 250         return type == PROTOCOLID_ISCSI ||
 251                type == PROTOCOLID_FCOE ||
 252                type == PROTOCOLID_ROCE;
 253 }
 254
 255 static bool tm_tid_proto(enum protocol_type type)
 256 {
 257         return type == PROTOCOLID_FCOE;
 258 }
 259
 260 /* counts the iids for the CDU/CDUC ILT client configuration */
 261 struct qed_cdu_iids {
 262         u32 pf_cids;
 263         u32 per_vf_cids;
 264 };
 265
 266 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
 267                              struct qed_cdu_iids *iids)
 268 {
 269         u32 type;
 270
 271         for (type = 0; type < MAX_CONN_TYPES; type++) {
 272                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 273                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 274         }
 275 }
 276
 277 /* counts the iids for the Searcher block configuration */
 278 struct qed_src_iids {
 279         u32 pf_cids;
 280         u32 per_vf_cids;
 281 };
 282
 283 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
 284                              struct qed_src_iids *iids)
 285 {
 286         u32 i;
 287
 288         for (i = 0; i < MAX_CONN_TYPES; i++) {
 289                 if (!src_proto(i))
 290                         continue;
 291
 292                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 293                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 294         }
 295 }
 296
 297 /* counts the iids for the Timers block configuration */
 298 struct qed_tm_iids {
 299         u32 pf_cids;
 300         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 301         u32 pf_tids_total;
 302         u32 per_vf_cids;
 303         u32 per_vf_tids;
 304 };
 305
 306 static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr,
 307                             struct qed_tm_iids *iids)
 308 {
 309         u32 i, j;
 310
 311         for (i = 0; i < MAX_CONN_TYPES; i++) {
 312                 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 313
 314                 if (tm_cid_proto(i)) {
 315                         iids->pf_cids += p_cfg->cid_count;
 316                         iids->per_vf_cids += p_cfg->cids_per_vf;
 317                 }
 318
 319                 if (tm_tid_proto(i)) {
 320                         struct qed_tid_seg *segs = p_cfg->tid_seg;
 321
 322                         /* for each segment there is at most one
 323                          * protocol for which count is not 0.
 324                          */
 325                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 326                                 iids->pf_tids[j] += segs[j].count;
 327
 328                         /* The last array elelment is for the VFs. As for PF
 329                          * segments there can be only one protocol for
 330                          * which this value is not 0.
 331                          */
 332                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 333                 }
 334         }
 335
 336         iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
 337         iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
 338         iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
 339
 340         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 341                 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
 342                 iids->pf_tids_total += iids->pf_tids[j];
 343         }
 344 }
 345
 346 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
 347                             struct qed_qm_iids *iids)
 348 {
 349         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 350         struct qed_tid_seg *segs;
 351         u32 vf_cids = 0, type, j;
 352         u32 vf_tids = 0;
 353
 354         for (type = 0; type < MAX_CONN_TYPES; type++) {
 355                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 356                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 357
 358                 segs = p_mngr->conn_cfg[type].tid_seg;
 359                 /* for each segment there is at most one
 360                  * protocol for which count is not 0.
 361                  */
 362                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 363                         iids->tids += segs[j].count;
 364
 365                 /* The last array elelment is for the VFs. As for PF
 366                  * segments there can be only one protocol for
 367                  * which this value is not 0.
 368                  */
 369                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 370         }
 371
 372         iids->vf_cids += vf_cids * p_mngr->vf_count;
 373         iids->tids += vf_tids * p_mngr->vf_count;
 374
 375         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 376                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 377                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 378 }
 379
 380 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
 381                                                 u32 seg)
 382 {
 383         struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 384         u32 i;
 385
 386         /* Find the protocol with tid count > 0 for this segment.
 387          * Note: there can only be one and this is already validated.
 388          */
 389         for (i = 0; i < MAX_CONN_TYPES; i++)
 390                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 391                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 392         return NULL;
 393 }
 394
 395 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
 396 {
 397         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 398
 399         p_mgr->srq_count = num_srqs;
 400 }
 401
 402 static u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
 403 {
 404         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 405
 406         return p_mgr->srq_count;
 407 }
 408
 409 /* set the iids count per protocol */
 410 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
 411                                         enum protocol_type type,
 412                                         u32 cid_count, u32 vf_cid_cnt)
 413 {
 414         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 415         struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 416
 417         p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
 418         p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
 419
 420         if (type == PROTOCOLID_ROCE) {
 421                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 422                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 423                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 424                 u32 align = elems_per_page * DQ_RANGE_ALIGN;
 425
 426                 p_conn->cid_count = roundup(p_conn->cid_count, align);
 427         }
 428 }
 429
 430 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
 431                                 enum protocol_type type, u32 *vf_cid)
 432 {
 433         if (vf_cid)
 434                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 435
 436         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 437 }
 438
 439 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
 440                                 enum protocol_type type)
 441 {
 442         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 443 }
 444
 445 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
 446                                 enum protocol_type type)
 447 {
 448         u32 cnt = 0;
 449         int i;
 450
 451         for (i = 0; i < TASK_SEGMENTS; i++)
 452                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 453
 454         return cnt;
 455 }
 456
 457 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
 458                                         enum protocol_type proto,
 459                                         u8 seg,
 460                                         u8 seg_type, u32 count, bool has_fl)
 461 {
 462         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 463         struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 464
 465         p_seg->count = count;
 466         p_seg->has_fl_mem = has_fl;
 467         p_seg->type = seg_type;
 468 }
 469
 470 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
 471                                  struct qed_ilt_cli_blk *p_blk,
 472                                  u32 start_line, u32 total_size, u32 elem_size)
 473 {
 474         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 475
 476         /* verify thatits called only once for each block */
 477         if (p_blk->total_size)
 478                 return;
 479
 480         p_blk->total_size = total_size;
 481         p_blk->real_size_in_page = 0;
 482         if (elem_size)
 483                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 484         p_blk->start_line = start_line;
 485 }
 486
 487 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
 488                                  struct qed_ilt_client_cfg *p_cli,
 489                                  struct qed_ilt_cli_blk *p_blk,
 490                                  u32 *p_line, enum ilt_clients client_id)
 491 {
 492         if (!p_blk->total_size)
 493                 return;
 494
 495         if (!p_cli->active)
 496                 p_cli->first.val = *p_line;
 497
 498         p_cli->active = true;
 499         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 500         p_cli->last.val = *p_line - 1;
 501
 502         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 503                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 504                    client_id, p_cli->first.val,
 505                    p_cli->last.val, p_blk->total_size,
 506                    p_blk->real_size_in_page, p_blk->start_line);
 507 }
 508
 509 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
 510                                         enum ilt_clients ilt_client)
 511 {
 512         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 513         struct qed_ilt_client_cfg *p_cli;
 514         u32 lines_to_skip = 0;
 515         u32 cxts_per_p;
 516
 517         if (ilt_client == ILT_CLI_CDUC) {
 518                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 519
 520                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 521                     (u32) CONN_CXT_SIZE(p_hwfn);
 522
 523                 lines_to_skip = cid_count / cxts_per_p;
 524         }
 525
 526         return lines_to_skip;
 527 }
 528
 529 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
 530 {
 531         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 532         u32 curr_line, total, i, task_size, line;
 533         struct qed_ilt_client_cfg *p_cli;
 534         struct qed_ilt_cli_blk *p_blk;
 535         struct qed_cdu_iids cdu_iids;
 536         struct qed_src_iids src_iids;
 537         struct qed_qm_iids qm_iids;
 538         struct qed_tm_iids tm_iids;
 539         struct qed_tid_seg *p_seg;
 540
 541         memset(&qm_iids, 0, sizeof(qm_iids));
 542         memset(&cdu_iids, 0, sizeof(cdu_iids));
 543         memset(&src_iids, 0, sizeof(src_iids));
 544         memset(&tm_iids, 0, sizeof(tm_iids));
 545
 546         p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
 547
 548         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 549                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 550                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 551
 552         /* CDUC */
 553         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 554         curr_line = p_mngr->pf_start_line;
 555
 556         /* CDUC PF */
 557         p_cli->pf_total_lines = 0;
 558
 559         /* get the counters for the CDUC and QM clients  */
 560         qed_cxt_cdu_iids(p_mngr, &cdu_iids);
 561
 562         p_blk = &p_cli->pf_blks[CDUC_BLK];
 563
 564         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 565
 566         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 567                              total, CONN_CXT_SIZE(p_hwfn));
 568
 569         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 570         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 571
 572         p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
 573                                                                ILT_CLI_CDUC);
 574
 575         /* CDUC VF */
 576         p_blk = &p_cli->vf_blks[CDUC_BLK];
 577         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 578
 579         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 580                              total, CONN_CXT_SIZE(p_hwfn));
 581
 582         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 583         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 584
 585         for (i = 1; i < p_mngr->vf_count; i++)
 586                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 587                                      ILT_CLI_CDUC);
 588
 589         /* CDUT PF */
 590         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 591         p_cli->first.val = curr_line;
 592
 593         /* first the 'working' task memory */
 594         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 595                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 596                 if (!p_seg || p_seg->count == 0)
 597                         continue;
 598
 599                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 600                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 601                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 602                                      p_mngr->task_type_size[p_seg->type]);
 603
 604                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 605                                      ILT_CLI_CDUT);
 606         }
 607
 608         /* next the 'init' task memory (forced load memory) */
 609         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 610                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 611                 if (!p_seg || p_seg->count == 0)
 612                         continue;
 613
 614                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 615
 616                 if (!p_seg->has_fl_mem) {
 617                         /* The segment is active (total size pf 'working'
 618                          * memory is > 0) but has no FL (forced-load, Init)
 619                          * memory. Thus:
 620                          *
 621                          * 1.   The total-size in the corrsponding FL block of
 622                          *      the ILT client is set to 0 - No ILT line are
 623                          *      provisioned and no ILT memory allocated.
 624                          *
 625                          * 2.   The start-line of said block is set to the
 626                          *      start line of the matching working memory
 627                          *      block in the ILT client. This is later used to
 628                          *      configure the CDU segment offset registers and
 629                          *      results in an FL command for TIDs of this
 630                          *      segement behaves as regular load commands
 631                          *      (loading TIDs from the working memory).
 632                          */
 633                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 634
 635                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 636                         continue;
 637                 }
 638                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 639
 640                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 641                                      curr_line, total,
 642                                      p_mngr->task_type_size[p_seg->type]);
 643
 644                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 645                                      ILT_CLI_CDUT);
 646         }
 647         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 648
 649         /* CDUT VF */
 650         p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 651         if (p_seg && p_seg->count) {
 652                 /* Stricly speaking we need to iterate over all VF
 653                  * task segment types, but a VF has only 1 segment
 654                  */
 655
 656                 /* 'working' memory */
 657                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 658
 659                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 660                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 661                                      curr_line, total,
 662                                      p_mngr->task_type_size[p_seg->type]);
 663
 664                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 665                                      ILT_CLI_CDUT);
 666
 667                 /* 'init' memory */
 668                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 669                 if (!p_seg->has_fl_mem) {
 670                         /* see comment above */
 671                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 672                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 673                 } else {
 674                         task_size = p_mngr->task_type_size[p_seg->type];
 675                         qed_ilt_cli_blk_fill(p_cli, p_blk,
 676                                              curr_line, total, task_size);
 677                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 678                                              ILT_CLI_CDUT);
 679                 }
 680                 p_cli->vf_total_lines = curr_line -
 681                     p_cli->vf_blks[0].start_line;
 682
 683                 /* Now for the rest of the VFs */
 684                 for (i = 1; i < p_mngr->vf_count; i++) {
 685                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 686                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 687                                              ILT_CLI_CDUT);
 688
 689                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 690                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 691                                              ILT_CLI_CDUT);
 692                 }
 693         }
 694
 695         /* QM */
 696         p_cli = &p_mngr->clients[ILT_CLI_QM];
 697         p_blk = &p_cli->pf_blks[0];
 698
 699         qed_cxt_qm_iids(p_hwfn, &qm_iids);
 700         total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 701                                    qm_iids.vf_cids, qm_iids.tids,
 702                                    p_hwfn->qm_info.num_pqs,
 703                                    p_hwfn->qm_info.num_vf_pqs);
 704
 705         DP_VERBOSE(p_hwfn,
 706                    QED_MSG_ILT,
 707                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 708                    qm_iids.cids,
 709                    qm_iids.vf_cids,
 710                    qm_iids.tids,
 711                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 712
 713         qed_ilt_cli_blk_fill(p_cli, p_blk,
 714                              curr_line, total * 0x1000,
 715                              QM_PQ_ELEMENT_SIZE);
 716
 717         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 718         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 719
 720         /* SRC */
 721         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 722         qed_cxt_src_iids(p_mngr, &src_iids);
 723
 724         /* Both the PF and VFs searcher connections are stored in the per PF
 725          * database. Thus sum the PF searcher cids and all the VFs searcher
 726          * cids.
 727          */
 728         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 729         if (total) {
 730                 u32 local_max = max_t(u32, total,
 731                                       SRC_MIN_NUM_ELEMS);
 732
 733                 total = roundup_pow_of_two(local_max);
 734
 735                 p_blk = &p_cli->pf_blks[0];
 736                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 737                                      total * sizeof(struct src_ent),
 738                                      sizeof(struct src_ent));
 739
 740                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 741                                      ILT_CLI_SRC);
 742                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 743         }
 744
 745         /* TM PF */
 746         p_cli = &p_mngr->clients[ILT_CLI_TM];
 747         qed_cxt_tm_iids(p_mngr, &tm_iids);
 748         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 749         if (total) {
 750                 p_blk = &p_cli->pf_blks[0];
 751                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 752                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 753
 754                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 755                                      ILT_CLI_TM);
 756                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 757         }
 758
 759         /* TM VF */
 760         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 761         if (total) {
 762                 p_blk = &p_cli->vf_blks[0];
 763                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 764                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 765
 766                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 767                                      ILT_CLI_TM);
 768                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 769
 770                 for (i = 1; i < p_mngr->vf_count; i++)
 771                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 772                                              ILT_CLI_TM);
 773         }
 774
 775         /* TSDM (SRQ CONTEXT) */
 776         total = qed_cxt_get_srq_count(p_hwfn);
 777
 778         if (total) {
 779                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 780                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 781                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 782                                      total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 783
 784                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 785                                      ILT_CLI_TSDM);
 786                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 787         }
 788
 789         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 790             RESC_NUM(p_hwfn, QED_ILT)) {
 791                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 792                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 793                 return -EINVAL;
 794         }
 795
 796         return 0;
 797 }
 798
 799 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
 800 {
 801         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 802         u32 i;
 803
 804         if (!p_mngr->t2)
 805                 return;
 806
 807         for (i = 0; i < p_mngr->t2_num_pages; i++)
 808                 if (p_mngr->t2[i].p_virt)
 809                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 810                                           p_mngr->t2[i].size,
 811                                           p_mngr->t2[i].p_virt,
 812                                           p_mngr->t2[i].p_phys);
 813
 814         kfree(p_mngr->t2);
 815         p_mngr->t2 = NULL;
 816 }
 817
 818 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
 819 {
 820         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 821         u32 conn_num, total_size, ent_per_page, psz, i;
 822         struct qed_ilt_client_cfg *p_src;
 823         struct qed_src_iids src_iids;
 824         struct qed_dma_mem *p_t2;
 825         int rc;
 826
 827         memset(&src_iids, 0, sizeof(src_iids));
 828
 829         /* if the SRC ILT client is inactive - there are no connection
 830          * requiring the searcer, leave.
 831          */
 832         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 833         if (!p_src->active)
 834                 return 0;
 835
 836         qed_cxt_src_iids(p_mngr, &src_iids);
 837         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 838         total_size = conn_num * sizeof(struct src_ent);
 839
 840         /* use the same page size as the SRC ILT client */
 841         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 842         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 843
 844         /* allocate t2 */
 845         p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
 846                              GFP_KERNEL);
 847         if (!p_mngr->t2) {
 848                 rc = -ENOMEM;
 849                 goto t2_fail;
 850         }
 851
 852         /* allocate t2 pages */
 853         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 854                 u32 size = min_t(u32, total_size, psz);
 855                 void **p_virt = &p_mngr->t2[i].p_virt;
 856
 857                 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 858                                              size,
 859                                              &p_mngr->t2[i].p_phys, GFP_KERNEL);
 860                 if (!p_mngr->t2[i].p_virt) {
 861                         rc = -ENOMEM;
 862                         goto t2_fail;
 863                 }
 864                 memset(*p_virt, 0, size);
 865                 p_mngr->t2[i].size = size;
 866                 total_size -= size;
 867         }
 868
 869         /* Set the t2 pointers */
 870
 871         /* entries per page - must be a power of two */
 872         ent_per_page = psz / sizeof(struct src_ent);
 873
 874         p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
 875
 876         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 877         p_mngr->last_free = (u64) p_t2->p_phys +
 878             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 879
 880         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 881                 u32 ent_num = min_t(u32,
 882                                     ent_per_page,
 883                                     conn_num);
 884                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 885                 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
 886                 u32 j;
 887
 888                 for (j = 0; j < ent_num - 1; j++) {
 889                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 890                         entries[j].next = cpu_to_be64(val);
 891                 }
 892
 893                 if (i < p_mngr->t2_num_pages - 1)
 894                         val = (u64) p_mngr->t2[i + 1].p_phys;
 895                 else
 896                         val = 0;
 897                 entries[j].next = cpu_to_be64(val);
 898
 899                 conn_num -= ent_num;
 900         }
 901
 902         return 0;
 903
 904 t2_fail:
 905         qed_cxt_src_t2_free(p_hwfn);
 906         return rc;
 907 }
 908
 909 #define for_each_ilt_valid_client(pos, clients) \
 910         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
 911                 if (!clients[pos].active) {     \
 912                         continue;               \
 913                 } else                          \
 914
 915 /* Total number of ILT lines used by this PF */
 916 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
 917 {
 918         u32 size = 0;
 919         u32 i;
 920
 921         for_each_ilt_valid_client(i, ilt_clients)
 922             size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
 923
 924         return size;
 925 }
 926
 927 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
 928 {
 929         struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 930         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 931         u32 ilt_size, i;
 932
 933         ilt_size = qed_cxt_ilt_shadow_size(p_cli);
 934
 935         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 936                 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 937
 938                 if (p_dma->p_virt)
 939                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 940                                           p_dma->size, p_dma->p_virt,
 941                                           p_dma->p_phys);
 942                 p_dma->p_virt = NULL;
 943         }
 944         kfree(p_mngr->ilt_shadow);
 945 }
 946
 947 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
 948                              struct qed_ilt_cli_blk *p_blk,
 949                              enum ilt_clients ilt_client,
 950                              u32 start_line_offset)
 951 {
 952         struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 953         u32 lines, line, sz_left, lines_to_skip = 0;
 954
 955         /* Special handling for RoCE that supports dynamic allocation */
 956         if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) &&
 957             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
 958                 return 0;
 959
 960         lines_to_skip = p_blk->dynamic_line_cnt;
 961
 962         if (!p_blk->total_size)
 963                 return 0;
 964
 965         sz_left = p_blk->total_size;
 966         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 967         line = p_blk->start_line + start_line_offset -
 968             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 969
 970         for (; lines; lines--) {
 971                 dma_addr_t p_phys;
 972                 void *p_virt;
 973                 u32 size;
 974
 975                 size = min_t(u32, sz_left, p_blk->real_size_in_page);
 976                 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 977                                             size, &p_phys, GFP_KERNEL);
 978                 if (!p_virt)
 979                         return -ENOMEM;
 980                 memset(p_virt, 0, size);
 981
 982                 ilt_shadow[line].p_phys = p_phys;
 983                 ilt_shadow[line].p_virt = p_virt;
 984                 ilt_shadow[line].size = size;
 985
 986                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 987                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
 988                             line, (u64)p_phys, p_virt, size);
 989
 990                 sz_left -= size;
 991                 line++;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
 998 {
 999         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1000         struct qed_ilt_client_cfg *clients = p_mngr->clients;
1001         struct qed_ilt_cli_blk *p_blk;
1002         u32 size, i, j, k;
1003         int rc;
1004
1005         size = qed_cxt_ilt_shadow_size(clients);
1006         p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
1007                                      GFP_KERNEL);
1008         if (!p_mngr->ilt_shadow) {
1009                 rc = -ENOMEM;
1010                 goto ilt_shadow_fail;
1011         }
1012
1013         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1014                    "Allocated 0x%x bytes for ilt shadow\n",
1015                    (u32)(size * sizeof(struct qed_dma_mem)));
1016
1017         for_each_ilt_valid_client(i, clients) {
1018                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1019                         p_blk = &clients[i].pf_blks[j];
1020                         rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1021                         if (rc)
1022                                 goto ilt_shadow_fail;
1023                 }
1024                 for (k = 0; k < p_mngr->vf_count; k++) {
1025                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1026                                 u32 lines = clients[i].vf_total_lines * k;
1027
1028                                 p_blk = &clients[i].vf_blks[j];
1029                                 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
1030                                 if (rc)
1031                                         goto ilt_shadow_fail;
1032                         }
1033                 }
1034         }
1035
1036         return 0;
1037
1038 ilt_shadow_fail:
1039         qed_ilt_shadow_free(p_hwfn);
1040         return rc;
1041 }
1042
1043 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
1044 {
1045         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1046         u32 type;
1047
1048         for (type = 0; type < MAX_CONN_TYPES; type++) {
1049                 kfree(p_mngr->acquired[type].cid_map);
1050                 p_mngr->acquired[type].max_count = 0;
1051                 p_mngr->acquired[type].start_cid = 0;
1052         }
1053 }
1054
1055 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1056 {
1057         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1058         u32 start_cid = 0;
1059         u32 type;
1060
1061         for (type = 0; type < MAX_CONN_TYPES; type++) {
1062                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1063                 u32 size;
1064
1065                 if (cid_cnt == 0)
1066                         continue;
1067
1068                 size = DIV_ROUND_UP(cid_cnt,
1069                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1070                        sizeof(unsigned long);
1071                 p_mngr->acquired[type].cid_map = kzalloc(size, GFP_KERNEL);
1072                 if (!p_mngr->acquired[type].cid_map)
1073                         goto cid_map_fail;
1074
1075                 p_mngr->acquired[type].max_count = cid_cnt;
1076                 p_mngr->acquired[type].start_cid = start_cid;
1077
1078                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1079
1080                 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1081                            "Type %08x start: %08x count %08x\n",
1082                            type, p_mngr->acquired[type].start_cid,
1083                            p_mngr->acquired[type].max_count);
1084                 start_cid += cid_cnt;
1085         }
1086
1087         return 0;
1088
1089 cid_map_fail:
1090         qed_cid_map_free(p_hwfn);
1091         return -ENOMEM;
1092 }
1093
1094 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1095 {
1096         struct qed_ilt_client_cfg *clients;
1097         struct qed_cxt_mngr *p_mngr;
1098         u32 i;
1099
1100         p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1101         if (!p_mngr)
1102                 return -ENOMEM;
1103
1104         /* Initialize ILT client registers */
1105         clients = p_mngr->clients;
1106         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1107         clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1108         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1109
1110         clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1111         clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1112         clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1113
1114         clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1115         clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1116         clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1117
1118         clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1119         clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1120         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1121
1122         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1123         clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1124         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1125
1126         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1127         clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1128         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1129         /* default ILT page size for all clients is 64K */
1130         for (i = 0; i < ILT_CLI_MAX; i++)
1131                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1132
1133         /* Initialize task sizes */
1134         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1135         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1136
1137         if (p_hwfn->cdev->p_iov_info)
1138                 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1139         /* Initialize the dynamic ILT allocation mutex */
1140         mutex_init(&p_mngr->mutex);
1141
1142         /* Set the cxt mangr pointer priori to further allocations */
1143         p_hwfn->p_cxt_mngr = p_mngr;
1144
1145         return 0;
1146 }
1147
1148 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1149 {
1150         int rc;
1151
1152         /* Allocate the ILT shadow table */
1153         rc = qed_ilt_shadow_alloc(p_hwfn);
1154         if (rc)
1155                 goto tables_alloc_fail;
1156
1157         /* Allocate the T2  table */
1158         rc = qed_cxt_src_t2_alloc(p_hwfn);
1159         if (rc)
1160                 goto tables_alloc_fail;
1161
1162         /* Allocate and initialize the acquired cids bitmaps */
1163         rc = qed_cid_map_alloc(p_hwfn);
1164         if (rc)
1165                 goto tables_alloc_fail;
1166
1167         return 0;
1168
1169 tables_alloc_fail:
1170         qed_cxt_mngr_free(p_hwfn);
1171         return rc;
1172 }
1173
1174 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1175 {
1176         if (!p_hwfn->p_cxt_mngr)
1177                 return;
1178
1179         qed_cid_map_free(p_hwfn);
1180         qed_cxt_src_t2_free(p_hwfn);
1181         qed_ilt_shadow_free(p_hwfn);
1182         kfree(p_hwfn->p_cxt_mngr);
1183
1184         p_hwfn->p_cxt_mngr = NULL;
1185 }
1186
1187 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1188 {
1189         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1190         int type;
1191
1192         /* Reset acquired cids */
1193         for (type = 0; type < MAX_CONN_TYPES; type++) {
1194                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1195
1196                 if (cid_cnt == 0)
1197                         continue;
1198
1199                 memset(p_mngr->acquired[type].cid_map, 0,
1200                        DIV_ROUND_UP(cid_cnt,
1201                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1202                        sizeof(unsigned long));
1203         }
1204 }
1205
1206 /* CDU Common */
1207 #define CDUC_CXT_SIZE_SHIFT \
1208         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1209
1210 #define CDUC_CXT_SIZE_MASK \
1211         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1212
1213 #define CDUC_BLOCK_WASTE_SHIFT \
1214         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1215
1216 #define CDUC_BLOCK_WASTE_MASK \
1217         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1218
1219 #define CDUC_NCIB_SHIFT \
1220         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1221
1222 #define CDUC_NCIB_MASK \
1223         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1224
1225 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1226         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1227
1228 #define CDUT_TYPE0_CXT_SIZE_MASK                \
1229         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1230          CDUT_TYPE0_CXT_SIZE_SHIFT)
1231
1232 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1233         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1234
1235 #define CDUT_TYPE0_BLOCK_WASTE_MASK                    \
1236         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1237          CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1238
1239 #define CDUT_TYPE0_NCIB_SHIFT \
1240         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1241
1242 #define CDUT_TYPE0_NCIB_MASK                             \
1243         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1244          CDUT_TYPE0_NCIB_SHIFT)
1245
1246 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1247         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1248
1249 #define CDUT_TYPE1_CXT_SIZE_MASK                \
1250         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1251          CDUT_TYPE1_CXT_SIZE_SHIFT)
1252
1253 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1254         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1255
1256 #define CDUT_TYPE1_BLOCK_WASTE_MASK                    \
1257         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1258          CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1259
1260 #define CDUT_TYPE1_NCIB_SHIFT \
1261         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1262
1263 #define CDUT_TYPE1_NCIB_MASK                             \
1264         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1265          CDUT_TYPE1_NCIB_SHIFT)
1266
1267 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1268 {
1269         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1270
1271         /* CDUC - connection configuration */
1272         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1273         cxt_size = CONN_CXT_SIZE(p_hwfn);
1274         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1275         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1276
1277         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1278         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1279         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1280         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1281
1282         /* CDUT - type-0 tasks configuration */
1283         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1284         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1285         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1286         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1287
1288         /* cxt size and block-waste are multipes of 8 */
1289         cdu_params = 0;
1290         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1291         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1292         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1293         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1294
1295         /* CDUT - type-1 tasks configuration */
1296         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1297         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1298         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1299
1300         /* cxt size and block-waste are multipes of 8 */
1301         cdu_params = 0;
1302         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1303         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1304         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1305         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1306 }
1307
1308 /* CDU PF */
1309 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1310 #define CDU_SEG_REG_TYPE_MASK           0x1
1311 #define CDU_SEG_REG_OFFSET_SHIFT        0
1312 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1313
1314 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1315 {
1316         struct qed_ilt_client_cfg *p_cli;
1317         struct qed_tid_seg *p_seg;
1318         u32 cdu_seg_params, offset;
1319         int i;
1320
1321         static const u32 rt_type_offset_arr[] = {
1322                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1323                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1324                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1325                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1326         };
1327
1328         static const u32 rt_type_offset_fl_arr[] = {
1329                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1330                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1331                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1332                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1333         };
1334
1335         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1336
1337         /* There are initializations only for CDUT during pf Phase */
1338         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1339                 /* Segment 0 */
1340                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1341                 if (!p_seg)
1342                         continue;
1343
1344                 /* Note: start_line is already adjusted for the CDU
1345                  * segment register granularity, so we just need to
1346                  * divide. Adjustment is implicit as we assume ILT
1347                  * Page size is larger than 32K!
1348                  */
1349                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1350                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1351                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1352
1353                 cdu_seg_params = 0;
1354                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1355                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1356                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1357
1358                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1359                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1360                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1361
1362                 cdu_seg_params = 0;
1363                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1364                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1365                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1366         }
1367 }
1368
1369 void qed_qm_init_pf(struct qed_hwfn *p_hwfn)
1370 {
1371         struct qed_qm_pf_rt_init_params params;
1372         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1373         struct qed_qm_iids iids;
1374
1375         memset(&iids, 0, sizeof(iids));
1376         qed_cxt_qm_iids(p_hwfn, &iids);
1377
1378         memset(&params, 0, sizeof(params));
1379         params.port_id = p_hwfn->port_id;
1380         params.pf_id = p_hwfn->rel_pf_id;
1381         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1382         params.is_first_pf = p_hwfn->first_on_engine;
1383         params.num_pf_cids = iids.cids;
1384         params.num_vf_cids = iids.vf_cids;
1385         params.start_pq = qm_info->start_pq;
1386         params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1387         params.num_vf_pqs = qm_info->num_vf_pqs;
1388         params.start_vport = qm_info->start_vport;
1389         params.num_vports = qm_info->num_vports;
1390         params.pf_wfq = qm_info->pf_wfq;
1391         params.pf_rl = qm_info->pf_rl;
1392         params.pq_params = qm_info->qm_pq_params;
1393         params.vport_params = qm_info->qm_vport_params;
1394
1395         qed_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, &params);
1396 }
1397
1398 /* CM PF */
1399 void qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1400 {
1401         /* XCM pure-LB queue */
1402         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1403                      qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1404 }
1405
1406 /* DQ PF */
1407 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1408 {
1409         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1410         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1411
1412         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1413         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1414
1415         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1416         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1417
1418         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1419         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1420
1421         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1422         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1423
1424         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1425         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1426
1427         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1428         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1429
1430         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1431         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1432
1433         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1434         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1435
1436         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1437         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1438
1439         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1440         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1441
1442         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1443         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1444
1445         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1446         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1447
1448         /* Connection types 6 & 7 are not in use, yet they must be configured
1449          * as the highest possible connection. Not configuring them means the
1450          * defaults will be  used, and with a large number of cids a bug may
1451          * occur, if the defaults will be smaller than dq_pf_max_cid /
1452          * dq_vf_max_cid.
1453          */
1454         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1455         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1456
1457         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1458         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1459 }
1460
1461 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1462 {
1463         struct qed_ilt_client_cfg *ilt_clients;
1464         int i;
1465
1466         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1467         for_each_ilt_valid_client(i, ilt_clients) {
1468                 STORE_RT_REG(p_hwfn,
1469                              ilt_clients[i].first.reg,
1470                              ilt_clients[i].first.val);
1471                 STORE_RT_REG(p_hwfn,
1472                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1473                 STORE_RT_REG(p_hwfn,
1474                              ilt_clients[i].p_size.reg,
1475                              ilt_clients[i].p_size.val);
1476         }
1477 }
1478
1479 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1480 {
1481         struct qed_ilt_client_cfg *p_cli;
1482         u32 blk_factor;
1483
1484         /* For simplicty  we set the 'block' to be an ILT page */
1485         if (p_hwfn->cdev->p_iov_info) {
1486                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1487
1488                 STORE_RT_REG(p_hwfn,
1489                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1490                              p_iov->first_vf_in_pf);
1491                 STORE_RT_REG(p_hwfn,
1492                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1493                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1494         }
1495
1496         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1497         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1498         if (p_cli->active) {
1499                 STORE_RT_REG(p_hwfn,
1500                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1501                              blk_factor);
1502                 STORE_RT_REG(p_hwfn,
1503                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1504                              p_cli->pf_total_lines);
1505                 STORE_RT_REG(p_hwfn,
1506                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1507                              p_cli->vf_total_lines);
1508         }
1509
1510         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1511         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1512         if (p_cli->active) {
1513                 STORE_RT_REG(p_hwfn,
1514                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1515                              blk_factor);
1516                 STORE_RT_REG(p_hwfn,
1517                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1518                              p_cli->pf_total_lines);
1519                 STORE_RT_REG(p_hwfn,
1520                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1521                              p_cli->vf_total_lines);
1522         }
1523
1524         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1525         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1526         if (p_cli->active) {
1527                 STORE_RT_REG(p_hwfn,
1528                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1529                 STORE_RT_REG(p_hwfn,
1530                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1531                              p_cli->pf_total_lines);
1532                 STORE_RT_REG(p_hwfn,
1533                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1534                              p_cli->vf_total_lines);
1535         }
1536 }
1537
1538 /* ILT (PSWRQ2) PF */
1539 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1540 {
1541         struct qed_ilt_client_cfg *clients;
1542         struct qed_cxt_mngr *p_mngr;
1543         struct qed_dma_mem *p_shdw;
1544         u32 line, rt_offst, i;
1545
1546         qed_ilt_bounds_init(p_hwfn);
1547         qed_ilt_vf_bounds_init(p_hwfn);
1548
1549         p_mngr = p_hwfn->p_cxt_mngr;
1550         p_shdw = p_mngr->ilt_shadow;
1551         clients = p_hwfn->p_cxt_mngr->clients;
1552
1553         for_each_ilt_valid_client(i, clients) {
1554                 /** Client's 1st val and RT array are absolute, ILT shadows'
1555                  *  lines are relative.
1556                  */
1557                 line = clients[i].first.val - p_mngr->pf_start_line;
1558                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1559                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1560
1561                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1562                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1563                         u64 ilt_hw_entry = 0;
1564
1565                         /** p_virt could be NULL incase of dynamic
1566                          *  allocation
1567                          */
1568                         if (p_shdw[line].p_virt) {
1569                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1570                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1571                                           (p_shdw[line].p_phys >> 12));
1572
1573                                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1574                                            "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1575                                            rt_offst, line, i,
1576                                            (u64)(p_shdw[line].p_phys >> 12));
1577                         }
1578
1579                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1580                 }
1581         }
1582 }
1583
1584 /* SRC (Searcher) PF */
1585 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1586 {
1587         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1588         u32 rounded_conn_num, conn_num, conn_max;
1589         struct qed_src_iids src_iids;
1590
1591         memset(&src_iids, 0, sizeof(src_iids));
1592         qed_cxt_src_iids(p_mngr, &src_iids);
1593         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1594         if (!conn_num)
1595                 return;
1596
1597         conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1598         rounded_conn_num = roundup_pow_of_two(conn_max);
1599
1600         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1601         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1602                      ilog2(rounded_conn_num));
1603
1604         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1605                          p_hwfn->p_cxt_mngr->first_free);
1606         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1607                          p_hwfn->p_cxt_mngr->last_free);
1608 }
1609
1610 /* Timers PF */
1611 #define TM_CFG_NUM_IDS_SHIFT            0
1612 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1613 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1614 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1615 #define TM_CFG_PARENT_PF_SHIFT          25
1616 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1617
1618 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1619 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1620
1621 #define TM_CFG_TID_OFFSET_SHIFT         30
1622 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1623 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1624 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1625
1626 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1627 {
1628         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1629         u32 active_seg_mask = 0, tm_offset, rt_reg;
1630         struct qed_tm_iids tm_iids;
1631         u64 cfg_word;
1632         u8 i;
1633
1634         memset(&tm_iids, 0, sizeof(tm_iids));
1635         qed_cxt_tm_iids(p_mngr, &tm_iids);
1636
1637         /* @@@TBD No pre-scan for now */
1638
1639         /* Note: We assume consecutive VFs for a PF */
1640         for (i = 0; i < p_mngr->vf_count; i++) {
1641                 cfg_word = 0;
1642                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1643                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1644                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1645                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1646                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1647                     (sizeof(cfg_word) / sizeof(u32)) *
1648                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1649                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1650         }
1651
1652         cfg_word = 0;
1653         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1654         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1655         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1656         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);       /* scan all   */
1657
1658         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1659             (sizeof(cfg_word) / sizeof(u32)) *
1660             (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1661         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1662
1663         /* enale scan */
1664         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1665                      tm_iids.pf_cids ? 0x1 : 0x0);
1666
1667         /* @@@TBD how to enable the scan for the VFs */
1668
1669         tm_offset = tm_iids.per_vf_cids;
1670
1671         /* Note: We assume consecutive VFs for a PF */
1672         for (i = 0; i < p_mngr->vf_count; i++) {
1673                 cfg_word = 0;
1674                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1675                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1676                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1677                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1678                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1679
1680                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1681                     (sizeof(cfg_word) / sizeof(u32)) *
1682                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1683
1684                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1685         }
1686
1687         tm_offset = tm_iids.pf_cids;
1688         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1689                 cfg_word = 0;
1690                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1691                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1692                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1693                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1694                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1695
1696                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1697                     (sizeof(cfg_word) / sizeof(u32)) *
1698                     (NUM_OF_VFS(p_hwfn->cdev) +
1699                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1700
1701                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1702                 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1703
1704                 tm_offset += tm_iids.pf_tids[i];
1705         }
1706
1707         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE)
1708                 active_seg_mask = 0;
1709
1710         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1711
1712         /* @@@TBD how to enable the scan for the VFs */
1713 }
1714
1715 static void qed_prs_init_common(struct qed_hwfn *p_hwfn)
1716 {
1717         if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) &&
1718             p_hwfn->pf_params.fcoe_pf_params.is_target)
1719                 STORE_RT_REG(p_hwfn,
1720                              PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
1721 }
1722
1723 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn)
1724 {
1725         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1726         struct qed_conn_type_cfg *p_fcoe;
1727         struct qed_tid_seg *p_tid;
1728
1729         p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1730
1731         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1732         if (!p_fcoe->cid_count)
1733                 return;
1734
1735         p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG];
1736         if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
1737                 STORE_RT_REG_AGG(p_hwfn,
1738                                  PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
1739                                  p_tid->count);
1740         } else {
1741                 STORE_RT_REG_AGG(p_hwfn,
1742                                  PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1743                                  p_tid->count);
1744         }
1745 }
1746
1747 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1748 {
1749         qed_cdu_init_common(p_hwfn);
1750         qed_prs_init_common(p_hwfn);
1751 }
1752
1753 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
1754 {
1755         qed_qm_init_pf(p_hwfn);
1756         qed_cm_init_pf(p_hwfn);
1757         qed_dq_init_pf(p_hwfn);
1758         qed_cdu_init_pf(p_hwfn);
1759         qed_ilt_init_pf(p_hwfn);
1760         qed_src_init_pf(p_hwfn);
1761         qed_tm_init_pf(p_hwfn);
1762         qed_prs_init_pf(p_hwfn);
1763 }
1764
1765 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1766                         enum protocol_type type, u32 *p_cid)
1767 {
1768         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1769         u32 rel_cid;
1770
1771         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1772                 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1773                 return -EINVAL;
1774         }
1775
1776         rel_cid = find_first_zero_bit(p_mngr->acquired[type].cid_map,
1777                                       p_mngr->acquired[type].max_count);
1778
1779         if (rel_cid >= p_mngr->acquired[type].max_count) {
1780                 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1781                 return -EINVAL;
1782         }
1783
1784         __set_bit(rel_cid, p_mngr->acquired[type].cid_map);
1785
1786         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1787
1788         return 0;
1789 }
1790
1791 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1792                                       u32 cid, enum protocol_type *p_type)
1793 {
1794         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1795         struct qed_cid_acquired_map *p_map;
1796         enum protocol_type p;
1797         u32 rel_cid;
1798
1799         /* Iterate over protocols and find matching cid range */
1800         for (p = 0; p < MAX_CONN_TYPES; p++) {
1801                 p_map = &p_mngr->acquired[p];
1802
1803                 if (!p_map->cid_map)
1804                         continue;
1805                 if (cid >= p_map->start_cid &&
1806                     cid < p_map->start_cid + p_map->max_count)
1807                         break;
1808         }
1809         *p_type = p;
1810
1811         if (p == MAX_CONN_TYPES) {
1812                 DP_NOTICE(p_hwfn, "Invalid CID %d", cid);
1813                 return false;
1814         }
1815
1816         rel_cid = cid - p_map->start_cid;
1817         if (!test_bit(rel_cid, p_map->cid_map)) {
1818                 DP_NOTICE(p_hwfn, "CID %d not acquired", cid);
1819                 return false;
1820         }
1821         return true;
1822 }
1823
1824 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
1825 {
1826         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1827         enum protocol_type type;
1828         bool b_acquired;
1829         u32 rel_cid;
1830
1831         /* Test acquired and find matching per-protocol map */
1832         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, &type);
1833
1834         if (!b_acquired)
1835                 return;
1836
1837         rel_cid = cid - p_mngr->acquired[type].start_cid;
1838         __clear_bit(rel_cid, p_mngr->acquired[type].cid_map);
1839 }
1840
1841 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
1842 {
1843         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1844         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1845         enum protocol_type type;
1846         bool b_acquired;
1847
1848         /* Test acquired and find matching per-protocol map */
1849         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1850
1851         if (!b_acquired)
1852                 return -EINVAL;
1853
1854         /* set the protocl type */
1855         p_info->type = type;
1856
1857         /* compute context virtual pointer */
1858         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1859
1860         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1861         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1862         line = p_info->iid / cxts_per_p;
1863
1864         /* Make sure context is allocated (dynamic allocation) */
1865         if (!p_mngr->ilt_shadow[line].p_virt)
1866                 return -EINVAL;
1867
1868         p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
1869                         p_info->iid % cxts_per_p * conn_cxt_size;
1870
1871         DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
1872                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1873                    p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
1874
1875         return 0;
1876 }
1877
1878 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
1879                                    struct qed_rdma_pf_params *p_params)
1880 {
1881         u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs;
1882         enum protocol_type proto;
1883
1884         num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs);
1885         num_tasks = num_mrs;    /* each mr uses a single task id */
1886         num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
1887
1888         switch (p_hwfn->hw_info.personality) {
1889         case QED_PCI_ETH_ROCE:
1890                 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
1891                 num_cons = num_qps * 2; /* each QP requires two connections */
1892                 proto = PROTOCOLID_ROCE;
1893                 break;
1894         default:
1895                 return;
1896         }
1897
1898         if (num_cons && num_tasks) {
1899                 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
1900
1901                 /* Deliberatly passing ROCE for tasks id. This is because
1902                  * iWARP / RoCE share the task id.
1903                  */
1904                 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
1905                                             QED_CXT_ROCE_TID_SEG, 1,
1906                                             num_tasks, false);
1907                 qed_cxt_set_srq_count(p_hwfn, num_srqs);
1908         } else {
1909                 DP_INFO(p_hwfn->cdev,
1910                         "RDMA personality used without setting params!\n");
1911         }
1912 }
1913
1914 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
1915 {
1916         /* Set the number of required CORE connections */
1917         u32 core_cids = 1; /* SPQ */
1918
1919         if (p_hwfn->using_ll2)
1920                 core_cids += 4;
1921         qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1922
1923         switch (p_hwfn->hw_info.personality) {
1924         case QED_PCI_ETH_ROCE:
1925         {
1926                 qed_rdma_set_pf_params(p_hwfn,
1927                                        &p_hwfn->
1928                                        pf_params.rdma_pf_params);
1929                 /* no need for break since RoCE coexist with Ethernet */
1930         }
1931         case QED_PCI_ETH:
1932         {
1933                 struct qed_eth_pf_params *p_params =
1934                     &p_hwfn->pf_params.eth_pf_params;
1935
1936                 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1937                                             p_params->num_cons, 1);
1938                 break;
1939         }
1940         case QED_PCI_FCOE:
1941         {
1942                 struct qed_fcoe_pf_params *p_params;
1943
1944                 p_params = &p_hwfn->pf_params.fcoe_pf_params;
1945
1946                 if (p_params->num_cons && p_params->num_tasks) {
1947                         qed_cxt_set_proto_cid_count(p_hwfn,
1948                                                     PROTOCOLID_FCOE,
1949                                                     p_params->num_cons,
1950                                                     0);
1951
1952                         qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
1953                                                     QED_CXT_FCOE_TID_SEG, 0,
1954                                                     p_params->num_tasks, true);
1955                 } else {
1956                         DP_INFO(p_hwfn->cdev,
1957                                 "Fcoe personality used without setting params!\n");
1958                 }
1959                 break;
1960         }
1961         case QED_PCI_ISCSI:
1962         {
1963                 struct qed_iscsi_pf_params *p_params;
1964
1965                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
1966
1967                 if (p_params->num_cons && p_params->num_tasks) {
1968                         qed_cxt_set_proto_cid_count(p_hwfn,
1969                                                     PROTOCOLID_ISCSI,
1970                                                     p_params->num_cons,
1971                                                     0);
1972
1973                         qed_cxt_set_proto_tid_count(p_hwfn,
1974                                                     PROTOCOLID_ISCSI,
1975                                                     QED_CXT_ISCSI_TID_SEG,
1976                                                     0,
1977                                                     p_params->num_tasks,
1978                                                     true);
1979                 } else {
1980                         DP_INFO(p_hwfn->cdev,
1981                                 "Iscsi personality used without setting params!\n");
1982                 }
1983                 break;
1984         }
1985         default:
1986                 return -EINVAL;
1987         }
1988
1989         return 0;
1990 }
1991
1992 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
1993                              struct qed_tid_mem *p_info)
1994 {
1995         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1996         u32 proto, seg, total_lines, i, shadow_line;
1997         struct qed_ilt_client_cfg *p_cli;
1998         struct qed_ilt_cli_blk *p_fl_seg;
1999         struct qed_tid_seg *p_seg_info;
2000
2001         /* Verify the personality */
2002         switch (p_hwfn->hw_info.personality) {
2003         case QED_PCI_FCOE:
2004                 proto = PROTOCOLID_FCOE;
2005                 seg = QED_CXT_FCOE_TID_SEG;
2006                 break;
2007         case QED_PCI_ISCSI:
2008                 proto = PROTOCOLID_ISCSI;
2009                 seg = QED_CXT_ISCSI_TID_SEG;
2010                 break;
2011         default:
2012                 return -EINVAL;
2013         }
2014
2015         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2016         if (!p_cli->active)
2017                 return -EINVAL;
2018
2019         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2020         if (!p_seg_info->has_fl_mem)
2021                 return -EINVAL;
2022
2023         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2024         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2025                                    p_fl_seg->real_size_in_page);
2026
2027         for (i = 0; i < total_lines; i++) {
2028                 shadow_line = i + p_fl_seg->start_line -
2029                     p_hwfn->p_cxt_mngr->pf_start_line;
2030                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2031         }
2032         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2033             p_fl_seg->real_size_in_page;
2034         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2035         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2036             p_info->tid_size;
2037
2038         return 0;
2039 }
2040
2041 /* This function is very RoCE oriented, if another protocol in the future
2042  * will want this feature we'll need to modify the function to be more generic
2043  */
2044 int
2045 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
2046                           enum qed_cxt_elem_type elem_type, u32 iid)
2047 {
2048         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2049         struct qed_ilt_client_cfg *p_cli;
2050         struct qed_ilt_cli_blk *p_blk;
2051         struct qed_ptt *p_ptt;
2052         dma_addr_t p_phys;
2053         u64 ilt_hw_entry;
2054         void *p_virt;
2055         int rc = 0;
2056
2057         switch (elem_type) {
2058         case QED_ELEM_CXT:
2059                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2060                 elem_size = CONN_CXT_SIZE(p_hwfn);
2061                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2062                 break;
2063         case QED_ELEM_SRQ:
2064                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2065                 elem_size = SRQ_CXT_SIZE;
2066                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2067                 break;
2068         case QED_ELEM_TASK:
2069                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2070                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2071                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2072                 break;
2073         default:
2074                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2075                 return -EINVAL;
2076         }
2077
2078         /* Calculate line in ilt */
2079         hw_p_size = p_cli->p_size.val;
2080         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2081         line = p_blk->start_line + (iid / elems_per_p);
2082         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2083
2084         /* If line is already allocated, do nothing, otherwise allocate it and
2085          * write it to the PSWRQ2 registers.
2086          * This section can be run in parallel from different contexts and thus
2087          * a mutex protection is needed.
2088          */
2089
2090         mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
2091
2092         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2093                 goto out0;
2094
2095         p_ptt = qed_ptt_acquire(p_hwfn);
2096         if (!p_ptt) {
2097                 DP_NOTICE(p_hwfn,
2098                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2099                 rc = -EBUSY;
2100                 goto out0;
2101         }
2102
2103         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2104                                     p_blk->real_size_in_page,
2105                                     &p_phys, GFP_KERNEL);
2106         if (!p_virt) {
2107                 rc = -ENOMEM;
2108                 goto out1;
2109         }
2110         memset(p_virt, 0, p_blk->real_size_in_page);
2111
2112         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2113          * to compensate for a HW bug, but it is configured even if DIF is not
2114          * enabled. This is harmless and allows us to avoid a dedicated API. We
2115          * configure the field for all of the contexts on the newly allocated
2116          * page.
2117          */
2118         if (elem_type == QED_ELEM_TASK) {
2119                 u32 elem_i;
2120                 u8 *elem_start = (u8 *)p_virt;
2121                 union type1_task_context *elem;
2122
2123                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2124                         elem = (union type1_task_context *)elem_start;
2125                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2126                                   TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
2127                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2128                 }
2129         }
2130
2131         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2132         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2133         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2134             p_blk->real_size_in_page;
2135
2136         /* compute absolute offset */
2137         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2138             (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2139
2140         ilt_hw_entry = 0;
2141         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2142         SET_FIELD(ilt_hw_entry,
2143                   ILT_ENTRY_PHY_ADDR,
2144                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2145
2146         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2147         qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2148                           reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2149
2150         if (elem_type == QED_ELEM_CXT) {
2151                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2152                     elems_per_p;
2153
2154                 /* Update the relevant register in the parser */
2155                 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2156                        last_cid_allocated - 1);
2157
2158                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2159                         /* Enable RoCE search */
2160                         qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2161                         p_hwfn->b_rdma_enabled_in_prs = true;
2162                 }
2163         }
2164
2165 out1:
2166         qed_ptt_release(p_hwfn, p_ptt);
2167 out0:
2168         mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2169
2170         return rc;
2171 }
2172
2173 /* This function is very RoCE oriented, if another protocol in the future
2174  * will want this feature we'll need to modify the function to be more generic
2175  */
2176 static int
2177 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2178                        enum qed_cxt_elem_type elem_type,
2179                        u32 start_iid, u32 count)
2180 {
2181         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2182         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2183         struct qed_ilt_client_cfg *p_cli;
2184         struct qed_ilt_cli_blk *p_blk;
2185         u32 end_iid = start_iid + count;
2186         struct qed_ptt *p_ptt;
2187         u64 ilt_hw_entry = 0;
2188         u32 i;
2189
2190         switch (elem_type) {
2191         case QED_ELEM_CXT:
2192                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2193                 elem_size = CONN_CXT_SIZE(p_hwfn);
2194                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2195                 break;
2196         case QED_ELEM_SRQ:
2197                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2198                 elem_size = SRQ_CXT_SIZE;
2199                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2200                 break;
2201         case QED_ELEM_TASK:
2202                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2203                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2204                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2205                 break;
2206         default:
2207                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2208                 return -EINVAL;
2209         }
2210
2211         /* Calculate line in ilt */
2212         hw_p_size = p_cli->p_size.val;
2213         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2214         start_line = p_blk->start_line + (start_iid / elems_per_p);
2215         end_line = p_blk->start_line + (end_iid / elems_per_p);
2216         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2217                 end_line--;
2218
2219         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2220         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2221
2222         p_ptt = qed_ptt_acquire(p_hwfn);
2223         if (!p_ptt) {
2224                 DP_NOTICE(p_hwfn,
2225                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2226                 return -EBUSY;
2227         }
2228
2229         for (i = shadow_start_line; i < shadow_end_line; i++) {
2230                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2231                         continue;
2232
2233                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2234                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2235                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2236                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2237
2238                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2239                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2240                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2241
2242                 /* compute absolute offset */
2243                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2244                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2245                      ILT_ENTRY_IN_REGS);
2246
2247                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2248                  * wide-bus.
2249                  */
2250                 qed_dmae_host2grc(p_hwfn, p_ptt,
2251                                   (u64) (uintptr_t) &ilt_hw_entry,
2252                                   reg_offset,
2253                                   sizeof(ilt_hw_entry) / sizeof(u32),
2254                                   0);
2255         }
2256
2257         qed_ptt_release(p_hwfn, p_ptt);
2258
2259         return 0;
2260 }
2261
2262 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2263 {
2264         int rc;
2265         u32 cid;
2266
2267         /* Free Connection CXT */
2268         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2269                                     qed_cxt_get_proto_cid_start(p_hwfn,
2270                                                                 proto),
2271                                     qed_cxt_get_proto_cid_count(p_hwfn,
2272                                                                 proto, &cid));
2273
2274         if (rc)
2275                 return rc;
2276
2277         /* Free Task CXT */
2278         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2279                                     qed_cxt_get_proto_tid_count(p_hwfn, proto));
2280         if (rc)
2281                 return rc;
2282
2283         /* Free TSDM CXT */
2284         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2285                                     qed_cxt_get_srq_count(p_hwfn));
2286
2287         return rc;
2288 }
2289
2290 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2291                          u32 tid, u8 ctx_type, void **pp_task_ctx)
2292 {
2293         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2294         struct qed_ilt_client_cfg *p_cli;
2295         struct qed_tid_seg *p_seg_info;
2296         struct qed_ilt_cli_blk *p_seg;
2297         u32 num_tids_per_block;
2298         u32 tid_size, ilt_idx;
2299         u32 total_lines;
2300         u32 proto, seg;
2301
2302         /* Verify the personality */
2303         switch (p_hwfn->hw_info.personality) {
2304         case QED_PCI_FCOE:
2305                 proto = PROTOCOLID_FCOE;
2306                 seg = QED_CXT_FCOE_TID_SEG;
2307                 break;
2308         case QED_PCI_ISCSI:
2309                 proto = PROTOCOLID_ISCSI;
2310                 seg = QED_CXT_ISCSI_TID_SEG;
2311                 break;
2312         default:
2313                 return -EINVAL;
2314         }
2315
2316         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2317         if (!p_cli->active)
2318                 return -EINVAL;
2319
2320         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2321
2322         if (ctx_type == QED_CTX_WORKING_MEM) {
2323                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2324         } else if (ctx_type == QED_CTX_FL_MEM) {
2325                 if (!p_seg_info->has_fl_mem)
2326                         return -EINVAL;
2327                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2328         } else {
2329                 return -EINVAL;
2330         }
2331         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2332         tid_size = p_mngr->task_type_size[p_seg_info->type];
2333         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2334
2335         if (total_lines < tid / num_tids_per_block)
2336                 return -EINVAL;
2337
2338         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2339                   p_mngr->pf_start_line;
2340         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2341                        (tid % num_tids_per_block) * tid_size;
2342
2343         return 0;
2344 }