drivers/net/ethernet/qlogic/qed/qed_cxt.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/bitops.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/list.h>
  39 #include <linux/log2.h>
  40 #include <linux/pci.h>
  41 #include <linux/slab.h>
  42 #include <linux/string.h>
  43 #include <linux/bitops.h>
  44 #include "qed.h"
  45 #include "qed_cxt.h"
  46 #include "qed_dev_api.h"
  47 #include "qed_hsi.h"
  48 #include "qed_hw.h"
  49 #include "qed_init_ops.h"
  50 #include "qed_reg_addr.h"
  51 #include "qed_sriov.h"
  52
  53 /* Max number of connection types in HW (DQ/CDU etc.) */
  54 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  55 #define NUM_TASK_TYPES          2
  56 #define NUM_TASK_PF_SEGMENTS    4
  57 #define NUM_TASK_VF_SEGMENTS    1
  58
  59 /* QM constants */
  60 #define QM_PQ_ELEMENT_SIZE      4 /* in bytes */
  61
  62 /* Doorbell-Queue constants */
  63 #define DQ_RANGE_SHIFT          4
  64 #define DQ_RANGE_ALIGN          BIT(DQ_RANGE_SHIFT)
  65
  66 /* Searcher constants */
  67 #define SRC_MIN_NUM_ELEMS 256
  68
  69 /* Timers constants */
  70 #define TM_SHIFT        7
  71 #define TM_ALIGN        BIT(TM_SHIFT)
  72 #define TM_ELEM_SIZE    4
  73
  74 #define ILT_DEFAULT_HW_P_SIZE   4
  75
  76 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  77 #define ILT_CFG_REG(cli, reg)   PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
  78
  79 /* ILT entry structure */
  80 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  81 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  82 #define ILT_ENTRY_VALID_MASK            0x1ULL
  83 #define ILT_ENTRY_VALID_SHIFT           52
  84 #define ILT_ENTRY_IN_REGS               2
  85 #define ILT_REG_SIZE_IN_BYTES           4
  86
  87 /* connection context union */
  88 union conn_context {
  89         struct core_conn_context core_ctx;
  90         struct eth_conn_context eth_ctx;
  91         struct iscsi_conn_context iscsi_ctx;
  92         struct fcoe_conn_context fcoe_ctx;
  93         struct roce_conn_context roce_ctx;
  94 };
  95
  96 /* TYPE-0 task context - iSCSI, FCOE */
  97 union type0_task_context {
  98         struct iscsi_task_context iscsi_ctx;
  99         struct fcoe_task_context fcoe_ctx;
 100 };
 101
 102 /* TYPE-1 task context - ROCE */
 103 union type1_task_context {
 104         struct rdma_task_context roce_ctx;
 105 };
 106
 107 struct src_ent {
 108         u8 opaque[56];
 109         u64 next;
 110 };
 111
 112 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
 113 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
 114
 115 #define CONN_CXT_SIZE(p_hwfn) \
 116         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
 117
 118 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
 119
 120 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
 121         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
 122
 123 /* Alignment is inherent to the type1_task_context structure */
 124 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
 125
 126 /* PF per protocl configuration object */
 127 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 128 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 129
 130 struct qed_tid_seg {
 131         u32 count;
 132         u8 type;
 133         bool has_fl_mem;
 134 };
 135
 136 struct qed_conn_type_cfg {
 137         u32 cid_count;
 138         u32 cids_per_vf;
 139         struct qed_tid_seg tid_seg[TASK_SEGMENTS];
 140 };
 141
 142 /* ILT Client configuration, Per connection type (protocol) resources. */
 143 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 144 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 145 #define CDUC_BLK                (0)
 146 #define SRQ_BLK                 (0)
 147 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 148 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
 149
 150 enum ilt_clients {
 151         ILT_CLI_CDUC,
 152         ILT_CLI_CDUT,
 153         ILT_CLI_QM,
 154         ILT_CLI_TM,
 155         ILT_CLI_SRC,
 156         ILT_CLI_TSDM,
 157         ILT_CLI_MAX
 158 };
 159
 160 struct ilt_cfg_pair {
 161         u32 reg;
 162         u32 val;
 163 };
 164
 165 struct qed_ilt_cli_blk {
 166         u32 total_size; /* 0 means not active */
 167         u32 real_size_in_page;
 168         u32 start_line;
 169         u32 dynamic_line_cnt;
 170 };
 171
 172 struct qed_ilt_client_cfg {
 173         bool active;
 174
 175         /* ILT boundaries */
 176         struct ilt_cfg_pair first;
 177         struct ilt_cfg_pair last;
 178         struct ilt_cfg_pair p_size;
 179
 180         /* ILT client blocks for PF */
 181         struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 182         u32 pf_total_lines;
 183
 184         /* ILT client blocks for VFs */
 185         struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 186         u32 vf_total_lines;
 187 };
 188
 189 /* Per Path -
 190  *      ILT shadow table
 191  *      Protocol acquired CID lists
 192  *      PF start line in ILT
 193  */
 194 struct qed_dma_mem {
 195         dma_addr_t p_phys;
 196         void *p_virt;
 197         size_t size;
 198 };
 199
 200 struct qed_cid_acquired_map {
 201         u32             start_cid;
 202         u32             max_count;
 203         unsigned long   *cid_map;
 204 };
 205
 206 struct qed_cxt_mngr {
 207         /* Per protocl configuration */
 208         struct qed_conn_type_cfg        conn_cfg[MAX_CONN_TYPES];
 209
 210         /* computed ILT structure */
 211         struct qed_ilt_client_cfg       clients[ILT_CLI_MAX];
 212
 213         /* Task type sizes */
 214         u32 task_type_size[NUM_TASK_TYPES];
 215
 216         /* total number of VFs for this hwfn -
 217          * ALL VFs are symmetric in terms of HW resources
 218          */
 219         u32                             vf_count;
 220
 221         /* Acquired CIDs */
 222         struct qed_cid_acquired_map     acquired[MAX_CONN_TYPES];
 223
 224         struct qed_cid_acquired_map
 225         acquired_vf[MAX_CONN_TYPES][MAX_NUM_VFS];
 226
 227         /* ILT  shadow table */
 228         struct qed_dma_mem              *ilt_shadow;
 229         u32                             pf_start_line;
 230
 231         /* Mutex for a dynamic ILT allocation */
 232         struct mutex mutex;
 233
 234         /* SRC T2 */
 235         struct qed_dma_mem *t2;
 236         u32 t2_num_pages;
 237         u64 first_free;
 238         u64 last_free;
 239
 240         /* total number of SRQ's for this hwfn */
 241         u32 srq_count;
 242
 243         /* Maximal number of L2 steering filters */
 244         u32 arfs_count;
 245 };
 246 static bool src_proto(enum protocol_type type)
 247 {
 248         return type == PROTOCOLID_ISCSI ||
 249                type == PROTOCOLID_FCOE;
 250 }
 251
 252 static bool tm_cid_proto(enum protocol_type type)
 253 {
 254         return type == PROTOCOLID_ISCSI ||
 255                type == PROTOCOLID_FCOE ||
 256                type == PROTOCOLID_ROCE;
 257 }
 258
 259 static bool tm_tid_proto(enum protocol_type type)
 260 {
 261         return type == PROTOCOLID_FCOE;
 262 }
 263
 264 /* counts the iids for the CDU/CDUC ILT client configuration */
 265 struct qed_cdu_iids {
 266         u32 pf_cids;
 267         u32 per_vf_cids;
 268 };
 269
 270 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
 271                              struct qed_cdu_iids *iids)
 272 {
 273         u32 type;
 274
 275         for (type = 0; type < MAX_CONN_TYPES; type++) {
 276                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 277                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 278         }
 279 }
 280
 281 /* counts the iids for the Searcher block configuration */
 282 struct qed_src_iids {
 283         u32 pf_cids;
 284         u32 per_vf_cids;
 285 };
 286
 287 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
 288                              struct qed_src_iids *iids)
 289 {
 290         u32 i;
 291
 292         for (i = 0; i < MAX_CONN_TYPES; i++) {
 293                 if (!src_proto(i))
 294                         continue;
 295
 296                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 297                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 298         }
 299
 300         /* Add L2 filtering filters in addition */
 301         iids->pf_cids += p_mngr->arfs_count;
 302 }
 303
 304 /* counts the iids for the Timers block configuration */
 305 struct qed_tm_iids {
 306         u32 pf_cids;
 307         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 308         u32 pf_tids_total;
 309         u32 per_vf_cids;
 310         u32 per_vf_tids;
 311 };
 312
 313 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn,
 314                             struct qed_cxt_mngr *p_mngr,
 315                             struct qed_tm_iids *iids)
 316 {
 317         bool tm_vf_required = false;
 318         bool tm_required = false;
 319         int i, j;
 320
 321         /* Timers is a special case -> we don't count how many cids require
 322          * timers but what's the max cid that will be used by the timer block.
 323          * therefore we traverse in reverse order, and once we hit a protocol
 324          * that requires the timers memory, we'll sum all the protocols up
 325          * to that one.
 326          */
 327         for (i = MAX_CONN_TYPES - 1; i >= 0; i--) {
 328                 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 329
 330                 if (tm_cid_proto(i) || tm_required) {
 331                         if (p_cfg->cid_count)
 332                                 tm_required = true;
 333
 334                         iids->pf_cids += p_cfg->cid_count;
 335                 }
 336
 337                 if (tm_cid_proto(i) || tm_vf_required) {
 338                         if (p_cfg->cids_per_vf)
 339                                 tm_vf_required = true;
 340
 341                         iids->per_vf_cids += p_cfg->cids_per_vf;
 342                 }
 343
 344                 if (tm_tid_proto(i)) {
 345                         struct qed_tid_seg *segs = p_cfg->tid_seg;
 346
 347                         /* for each segment there is at most one
 348                          * protocol for which count is not 0.
 349                          */
 350                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 351                                 iids->pf_tids[j] += segs[j].count;
 352
 353                         /* The last array elelment is for the VFs. As for PF
 354                          * segments there can be only one protocol for
 355                          * which this value is not 0.
 356                          */
 357                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 358                 }
 359         }
 360
 361         iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
 362         iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
 363         iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
 364
 365         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 366                 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
 367                 iids->pf_tids_total += iids->pf_tids[j];
 368         }
 369 }
 370
 371 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
 372                             struct qed_qm_iids *iids)
 373 {
 374         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 375         struct qed_tid_seg *segs;
 376         u32 vf_cids = 0, type, j;
 377         u32 vf_tids = 0;
 378
 379         for (type = 0; type < MAX_CONN_TYPES; type++) {
 380                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 381                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 382
 383                 segs = p_mngr->conn_cfg[type].tid_seg;
 384                 /* for each segment there is at most one
 385                  * protocol for which count is not 0.
 386                  */
 387                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 388                         iids->tids += segs[j].count;
 389
 390                 /* The last array elelment is for the VFs. As for PF
 391                  * segments there can be only one protocol for
 392                  * which this value is not 0.
 393                  */
 394                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 395         }
 396
 397         iids->vf_cids += vf_cids * p_mngr->vf_count;
 398         iids->tids += vf_tids * p_mngr->vf_count;
 399
 400         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 401                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 402                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 403 }
 404
 405 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
 406                                                 u32 seg)
 407 {
 408         struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 409         u32 i;
 410
 411         /* Find the protocol with tid count > 0 for this segment.
 412          * Note: there can only be one and this is already validated.
 413          */
 414         for (i = 0; i < MAX_CONN_TYPES; i++)
 415                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 416                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 417         return NULL;
 418 }
 419
 420 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
 421 {
 422         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 423
 424         p_mgr->srq_count = num_srqs;
 425 }
 426
 427 static u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
 428 {
 429         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 430
 431         return p_mgr->srq_count;
 432 }
 433
 434 /* set the iids count per protocol */
 435 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
 436                                         enum protocol_type type,
 437                                         u32 cid_count, u32 vf_cid_cnt)
 438 {
 439         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 440         struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 441
 442         p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
 443         p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
 444
 445         if (type == PROTOCOLID_ROCE) {
 446                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 447                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 448                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 449                 u32 align = elems_per_page * DQ_RANGE_ALIGN;
 450
 451                 p_conn->cid_count = roundup(p_conn->cid_count, align);
 452         }
 453 }
 454
 455 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
 456                                 enum protocol_type type, u32 *vf_cid)
 457 {
 458         if (vf_cid)
 459                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 460
 461         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 462 }
 463
 464 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
 465                                 enum protocol_type type)
 466 {
 467         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 468 }
 469
 470 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
 471                                 enum protocol_type type)
 472 {
 473         u32 cnt = 0;
 474         int i;
 475
 476         for (i = 0; i < TASK_SEGMENTS; i++)
 477                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 478
 479         return cnt;
 480 }
 481
 482 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
 483                                         enum protocol_type proto,
 484                                         u8 seg,
 485                                         u8 seg_type, u32 count, bool has_fl)
 486 {
 487         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 488         struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 489
 490         p_seg->count = count;
 491         p_seg->has_fl_mem = has_fl;
 492         p_seg->type = seg_type;
 493 }
 494
 495 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
 496                                  struct qed_ilt_cli_blk *p_blk,
 497                                  u32 start_line, u32 total_size, u32 elem_size)
 498 {
 499         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 500
 501         /* verify thatits called only once for each block */
 502         if (p_blk->total_size)
 503                 return;
 504
 505         p_blk->total_size = total_size;
 506         p_blk->real_size_in_page = 0;
 507         if (elem_size)
 508                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 509         p_blk->start_line = start_line;
 510 }
 511
 512 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
 513                                  struct qed_ilt_client_cfg *p_cli,
 514                                  struct qed_ilt_cli_blk *p_blk,
 515                                  u32 *p_line, enum ilt_clients client_id)
 516 {
 517         if (!p_blk->total_size)
 518                 return;
 519
 520         if (!p_cli->active)
 521                 p_cli->first.val = *p_line;
 522
 523         p_cli->active = true;
 524         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 525         p_cli->last.val = *p_line - 1;
 526
 527         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 528                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 529                    client_id, p_cli->first.val,
 530                    p_cli->last.val, p_blk->total_size,
 531                    p_blk->real_size_in_page, p_blk->start_line);
 532 }
 533
 534 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
 535                                         enum ilt_clients ilt_client)
 536 {
 537         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 538         struct qed_ilt_client_cfg *p_cli;
 539         u32 lines_to_skip = 0;
 540         u32 cxts_per_p;
 541
 542         if (ilt_client == ILT_CLI_CDUC) {
 543                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 544
 545                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 546                     (u32) CONN_CXT_SIZE(p_hwfn);
 547
 548                 lines_to_skip = cid_count / cxts_per_p;
 549         }
 550
 551         return lines_to_skip;
 552 }
 553
 554 static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg
 555                                                   *p_cli)
 556 {
 557         p_cli->active = false;
 558         p_cli->first.val = 0;
 559         p_cli->last.val = 0;
 560         return p_cli;
 561 }
 562
 563 static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk)
 564 {
 565         p_blk->total_size = 0;
 566         return p_blk;
 567 }
 568
 569 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count)
 570 {
 571         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 572         u32 curr_line, total, i, task_size, line;
 573         struct qed_ilt_client_cfg *p_cli;
 574         struct qed_ilt_cli_blk *p_blk;
 575         struct qed_cdu_iids cdu_iids;
 576         struct qed_src_iids src_iids;
 577         struct qed_qm_iids qm_iids;
 578         struct qed_tm_iids tm_iids;
 579         struct qed_tid_seg *p_seg;
 580
 581         memset(&qm_iids, 0, sizeof(qm_iids));
 582         memset(&cdu_iids, 0, sizeof(cdu_iids));
 583         memset(&src_iids, 0, sizeof(src_iids));
 584         memset(&tm_iids, 0, sizeof(tm_iids));
 585
 586         p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
 587
 588         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 589                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 590                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 591
 592         /* CDUC */
 593         p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]);
 594
 595         curr_line = p_mngr->pf_start_line;
 596
 597         /* CDUC PF */
 598         p_cli->pf_total_lines = 0;
 599
 600         /* get the counters for the CDUC and QM clients  */
 601         qed_cxt_cdu_iids(p_mngr, &cdu_iids);
 602
 603         p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]);
 604
 605         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 606
 607         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 608                              total, CONN_CXT_SIZE(p_hwfn));
 609
 610         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 611         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 612
 613         p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
 614                                                                ILT_CLI_CDUC);
 615
 616         /* CDUC VF */
 617         p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]);
 618         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 619
 620         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 621                              total, CONN_CXT_SIZE(p_hwfn));
 622
 623         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 624         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 625
 626         for (i = 1; i < p_mngr->vf_count; i++)
 627                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 628                                      ILT_CLI_CDUC);
 629
 630         /* CDUT PF */
 631         p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]);
 632         p_cli->first.val = curr_line;
 633
 634         /* first the 'working' task memory */
 635         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 636                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 637                 if (!p_seg || p_seg->count == 0)
 638                         continue;
 639
 640                 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]);
 641                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 642                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 643                                      p_mngr->task_type_size[p_seg->type]);
 644
 645                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 646                                      ILT_CLI_CDUT);
 647         }
 648
 649         /* next the 'init' task memory (forced load memory) */
 650         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 651                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 652                 if (!p_seg || p_seg->count == 0)
 653                         continue;
 654
 655                 p_blk =
 656                     qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]);
 657
 658                 if (!p_seg->has_fl_mem) {
 659                         /* The segment is active (total size pf 'working'
 660                          * memory is > 0) but has no FL (forced-load, Init)
 661                          * memory. Thus:
 662                          *
 663                          * 1.   The total-size in the corrsponding FL block of
 664                          *      the ILT client is set to 0 - No ILT line are
 665                          *      provisioned and no ILT memory allocated.
 666                          *
 667                          * 2.   The start-line of said block is set to the
 668                          *      start line of the matching working memory
 669                          *      block in the ILT client. This is later used to
 670                          *      configure the CDU segment offset registers and
 671                          *      results in an FL command for TIDs of this
 672                          *      segement behaves as regular load commands
 673                          *      (loading TIDs from the working memory).
 674                          */
 675                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 676
 677                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 678                         continue;
 679                 }
 680                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 681
 682                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 683                                      curr_line, total,
 684                                      p_mngr->task_type_size[p_seg->type]);
 685
 686                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 687                                      ILT_CLI_CDUT);
 688         }
 689         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 690
 691         /* CDUT VF */
 692         p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 693         if (p_seg && p_seg->count) {
 694                 /* Stricly speaking we need to iterate over all VF
 695                  * task segment types, but a VF has only 1 segment
 696                  */
 697
 698                 /* 'working' memory */
 699                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 700
 701                 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]);
 702                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 703                                      curr_line, total,
 704                                      p_mngr->task_type_size[p_seg->type]);
 705
 706                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 707                                      ILT_CLI_CDUT);
 708
 709                 /* 'init' memory */
 710                 p_blk =
 711                     qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]);
 712                 if (!p_seg->has_fl_mem) {
 713                         /* see comment above */
 714                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 715                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 716                 } else {
 717                         task_size = p_mngr->task_type_size[p_seg->type];
 718                         qed_ilt_cli_blk_fill(p_cli, p_blk,
 719                                              curr_line, total, task_size);
 720                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 721                                              ILT_CLI_CDUT);
 722                 }
 723                 p_cli->vf_total_lines = curr_line -
 724                     p_cli->vf_blks[0].start_line;
 725
 726                 /* Now for the rest of the VFs */
 727                 for (i = 1; i < p_mngr->vf_count; i++) {
 728                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 729                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 730                                              ILT_CLI_CDUT);
 731
 732                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 733                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 734                                              ILT_CLI_CDUT);
 735                 }
 736         }
 737
 738         /* QM */
 739         p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]);
 740         p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
 741
 742         qed_cxt_qm_iids(p_hwfn, &qm_iids);
 743         total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 744                                    qm_iids.vf_cids, qm_iids.tids,
 745                                    p_hwfn->qm_info.num_pqs,
 746                                    p_hwfn->qm_info.num_vf_pqs);
 747
 748         DP_VERBOSE(p_hwfn,
 749                    QED_MSG_ILT,
 750                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 751                    qm_iids.cids,
 752                    qm_iids.vf_cids,
 753                    qm_iids.tids,
 754                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 755
 756         qed_ilt_cli_blk_fill(p_cli, p_blk,
 757                              curr_line, total * 0x1000,
 758                              QM_PQ_ELEMENT_SIZE);
 759
 760         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 761         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 762
 763         /* SRC */
 764         p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]);
 765         qed_cxt_src_iids(p_mngr, &src_iids);
 766
 767         /* Both the PF and VFs searcher connections are stored in the per PF
 768          * database. Thus sum the PF searcher cids and all the VFs searcher
 769          * cids.
 770          */
 771         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 772         if (total) {
 773                 u32 local_max = max_t(u32, total,
 774                                       SRC_MIN_NUM_ELEMS);
 775
 776                 total = roundup_pow_of_two(local_max);
 777
 778                 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
 779                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 780                                      total * sizeof(struct src_ent),
 781                                      sizeof(struct src_ent));
 782
 783                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 784                                      ILT_CLI_SRC);
 785                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 786         }
 787
 788         /* TM PF */
 789         p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]);
 790         qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
 791         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 792         if (total) {
 793                 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
 794                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 795                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 796
 797                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 798                                      ILT_CLI_TM);
 799                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 800         }
 801
 802         /* TM VF */
 803         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 804         if (total) {
 805                 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]);
 806                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 807                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 808
 809                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 810                                      ILT_CLI_TM);
 811
 812                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 813                 for (i = 1; i < p_mngr->vf_count; i++)
 814                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 815                                              ILT_CLI_TM);
 816         }
 817
 818         /* TSDM (SRQ CONTEXT) */
 819         total = qed_cxt_get_srq_count(p_hwfn);
 820
 821         if (total) {
 822                 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]);
 823                 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]);
 824                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 825                                      total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 826
 827                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 828                                      ILT_CLI_TSDM);
 829                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 830         }
 831
 832         *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line;
 833
 834         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 835             RESC_NUM(p_hwfn, QED_ILT))
 836                 return -EINVAL;
 837
 838         return 0;
 839 }
 840
 841 u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines)
 842 {
 843         struct qed_ilt_client_cfg *p_cli;
 844         u32 excess_lines, available_lines;
 845         struct qed_cxt_mngr *p_mngr;
 846         u32 ilt_page_size, elem_size;
 847         struct qed_tid_seg *p_seg;
 848         int i;
 849
 850         available_lines = RESC_NUM(p_hwfn, QED_ILT);
 851         excess_lines = used_lines - available_lines;
 852
 853         if (!excess_lines)
 854                 return 0;
 855
 856         if (!QED_IS_RDMA_PERSONALITY(p_hwfn))
 857                 return 0;
 858
 859         p_mngr = p_hwfn->p_cxt_mngr;
 860         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 861         ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 862
 863         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 864                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 865                 if (!p_seg || p_seg->count == 0)
 866                         continue;
 867
 868                 elem_size = p_mngr->task_type_size[p_seg->type];
 869                 if (!elem_size)
 870                         continue;
 871
 872                 return (ilt_page_size / elem_size) * excess_lines;
 873         }
 874
 875         DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n");
 876         return 0;
 877 }
 878
 879 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
 880 {
 881         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 882         u32 i;
 883
 884         if (!p_mngr->t2)
 885                 return;
 886
 887         for (i = 0; i < p_mngr->t2_num_pages; i++)
 888                 if (p_mngr->t2[i].p_virt)
 889                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 890                                           p_mngr->t2[i].size,
 891                                           p_mngr->t2[i].p_virt,
 892                                           p_mngr->t2[i].p_phys);
 893
 894         kfree(p_mngr->t2);
 895         p_mngr->t2 = NULL;
 896 }
 897
 898 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
 899 {
 900         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 901         u32 conn_num, total_size, ent_per_page, psz, i;
 902         struct qed_ilt_client_cfg *p_src;
 903         struct qed_src_iids src_iids;
 904         struct qed_dma_mem *p_t2;
 905         int rc;
 906
 907         memset(&src_iids, 0, sizeof(src_iids));
 908
 909         /* if the SRC ILT client is inactive - there are no connection
 910          * requiring the searcer, leave.
 911          */
 912         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 913         if (!p_src->active)
 914                 return 0;
 915
 916         qed_cxt_src_iids(p_mngr, &src_iids);
 917         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 918         total_size = conn_num * sizeof(struct src_ent);
 919
 920         /* use the same page size as the SRC ILT client */
 921         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 922         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 923
 924         /* allocate t2 */
 925         p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
 926                              GFP_KERNEL);
 927         if (!p_mngr->t2) {
 928                 rc = -ENOMEM;
 929                 goto t2_fail;
 930         }
 931
 932         /* allocate t2 pages */
 933         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 934                 u32 size = min_t(u32, total_size, psz);
 935                 void **p_virt = &p_mngr->t2[i].p_virt;
 936
 937                 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 938                                              size,
 939                                              &p_mngr->t2[i].p_phys, GFP_KERNEL);
 940                 if (!p_mngr->t2[i].p_virt) {
 941                         rc = -ENOMEM;
 942                         goto t2_fail;
 943                 }
 944                 memset(*p_virt, 0, size);
 945                 p_mngr->t2[i].size = size;
 946                 total_size -= size;
 947         }
 948
 949         /* Set the t2 pointers */
 950
 951         /* entries per page - must be a power of two */
 952         ent_per_page = psz / sizeof(struct src_ent);
 953
 954         p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
 955
 956         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 957         p_mngr->last_free = (u64) p_t2->p_phys +
 958             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 959
 960         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 961                 u32 ent_num = min_t(u32,
 962                                     ent_per_page,
 963                                     conn_num);
 964                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 965                 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
 966                 u32 j;
 967
 968                 for (j = 0; j < ent_num - 1; j++) {
 969                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 970                         entries[j].next = cpu_to_be64(val);
 971                 }
 972
 973                 if (i < p_mngr->t2_num_pages - 1)
 974                         val = (u64) p_mngr->t2[i + 1].p_phys;
 975                 else
 976                         val = 0;
 977                 entries[j].next = cpu_to_be64(val);
 978
 979                 conn_num -= ent_num;
 980         }
 981
 982         return 0;
 983
 984 t2_fail:
 985         qed_cxt_src_t2_free(p_hwfn);
 986         return rc;
 987 }
 988
 989 #define for_each_ilt_valid_client(pos, clients) \
 990         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
 991                 if (!clients[pos].active) {     \
 992                         continue;               \
 993                 } else                          \
 994
 995 /* Total number of ILT lines used by this PF */
 996 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
 997 {
 998         u32 size = 0;
 999         u32 i;
1000
1001         for_each_ilt_valid_client(i, ilt_clients)
1002             size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
1003
1004         return size;
1005 }
1006
1007 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
1008 {
1009         struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
1010         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1011         u32 ilt_size, i;
1012
1013         ilt_size = qed_cxt_ilt_shadow_size(p_cli);
1014
1015         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
1016                 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
1017
1018                 if (p_dma->p_virt)
1019                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1020                                           p_dma->size, p_dma->p_virt,
1021                                           p_dma->p_phys);
1022                 p_dma->p_virt = NULL;
1023         }
1024         kfree(p_mngr->ilt_shadow);
1025 }
1026
1027 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
1028                              struct qed_ilt_cli_blk *p_blk,
1029                              enum ilt_clients ilt_client,
1030                              u32 start_line_offset)
1031 {
1032         struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
1033         u32 lines, line, sz_left, lines_to_skip = 0;
1034
1035         /* Special handling for RoCE that supports dynamic allocation */
1036         if (QED_IS_RDMA_PERSONALITY(p_hwfn) &&
1037             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
1038                 return 0;
1039
1040         lines_to_skip = p_blk->dynamic_line_cnt;
1041
1042         if (!p_blk->total_size)
1043                 return 0;
1044
1045         sz_left = p_blk->total_size;
1046         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
1047         line = p_blk->start_line + start_line_offset -
1048             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
1049
1050         for (; lines; lines--) {
1051                 dma_addr_t p_phys;
1052                 void *p_virt;
1053                 u32 size;
1054
1055                 size = min_t(u32, sz_left, p_blk->real_size_in_page);
1056                 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1057                                             size, &p_phys, GFP_KERNEL);
1058                 if (!p_virt)
1059                         return -ENOMEM;
1060                 memset(p_virt, 0, size);
1061
1062                 ilt_shadow[line].p_phys = p_phys;
1063                 ilt_shadow[line].p_virt = p_virt;
1064                 ilt_shadow[line].size = size;
1065
1066                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1067                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
1068                             line, (u64)p_phys, p_virt, size);
1069
1070                 sz_left -= size;
1071                 line++;
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
1078 {
1079         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1080         struct qed_ilt_client_cfg *clients = p_mngr->clients;
1081         struct qed_ilt_cli_blk *p_blk;
1082         u32 size, i, j, k;
1083         int rc;
1084
1085         size = qed_cxt_ilt_shadow_size(clients);
1086         p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
1087                                      GFP_KERNEL);
1088         if (!p_mngr->ilt_shadow) {
1089                 rc = -ENOMEM;
1090                 goto ilt_shadow_fail;
1091         }
1092
1093         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1094                    "Allocated 0x%x bytes for ilt shadow\n",
1095                    (u32)(size * sizeof(struct qed_dma_mem)));
1096
1097         for_each_ilt_valid_client(i, clients) {
1098                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1099                         p_blk = &clients[i].pf_blks[j];
1100                         rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1101                         if (rc)
1102                                 goto ilt_shadow_fail;
1103                 }
1104                 for (k = 0; k < p_mngr->vf_count; k++) {
1105                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1106                                 u32 lines = clients[i].vf_total_lines * k;
1107
1108                                 p_blk = &clients[i].vf_blks[j];
1109                                 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
1110                                 if (rc)
1111                                         goto ilt_shadow_fail;
1112                         }
1113                 }
1114         }
1115
1116         return 0;
1117
1118 ilt_shadow_fail:
1119         qed_ilt_shadow_free(p_hwfn);
1120         return rc;
1121 }
1122
1123 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
1124 {
1125         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1126         u32 type, vf;
1127
1128         for (type = 0; type < MAX_CONN_TYPES; type++) {
1129                 kfree(p_mngr->acquired[type].cid_map);
1130                 p_mngr->acquired[type].max_count = 0;
1131                 p_mngr->acquired[type].start_cid = 0;
1132
1133                 for (vf = 0; vf < MAX_NUM_VFS; vf++) {
1134                         kfree(p_mngr->acquired_vf[type][vf].cid_map);
1135                         p_mngr->acquired_vf[type][vf].max_count = 0;
1136                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1137                 }
1138         }
1139 }
1140
1141 static int
1142 qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn,
1143                          u32 type,
1144                          u32 cid_start,
1145                          u32 cid_count, struct qed_cid_acquired_map *p_map)
1146 {
1147         u32 size;
1148
1149         if (!cid_count)
1150                 return 0;
1151
1152         size = DIV_ROUND_UP(cid_count,
1153                             sizeof(unsigned long) * BITS_PER_BYTE) *
1154                sizeof(unsigned long);
1155         p_map->cid_map = kzalloc(size, GFP_KERNEL);
1156         if (!p_map->cid_map)
1157                 return -ENOMEM;
1158
1159         p_map->max_count = cid_count;
1160         p_map->start_cid = cid_start;
1161
1162         DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1163                    "Type %08x start: %08x count %08x\n",
1164                    type, p_map->start_cid, p_map->max_count);
1165
1166         return 0;
1167 }
1168
1169 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1170 {
1171         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1172         u32 start_cid = 0, vf_start_cid = 0;
1173         u32 type, vf;
1174
1175         for (type = 0; type < MAX_CONN_TYPES; type++) {
1176                 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1177                 struct qed_cid_acquired_map *p_map;
1178
1179                 /* Handle PF maps */
1180                 p_map = &p_mngr->acquired[type];
1181                 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid,
1182                                              p_cfg->cid_count, p_map))
1183                         goto cid_map_fail;
1184
1185                 /* Handle VF maps */
1186                 for (vf = 0; vf < MAX_NUM_VFS; vf++) {
1187                         p_map = &p_mngr->acquired_vf[type][vf];
1188                         if (qed_cid_map_alloc_single(p_hwfn, type,
1189                                                      vf_start_cid,
1190                                                      p_cfg->cids_per_vf, p_map))
1191                                 goto cid_map_fail;
1192                 }
1193
1194                 start_cid += p_cfg->cid_count;
1195                 vf_start_cid += p_cfg->cids_per_vf;
1196         }
1197
1198         return 0;
1199
1200 cid_map_fail:
1201         qed_cid_map_free(p_hwfn);
1202         return -ENOMEM;
1203 }
1204
1205 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1206 {
1207         struct qed_ilt_client_cfg *clients;
1208         struct qed_cxt_mngr *p_mngr;
1209         u32 i;
1210
1211         p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1212         if (!p_mngr)
1213                 return -ENOMEM;
1214
1215         /* Initialize ILT client registers */
1216         clients = p_mngr->clients;
1217         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1218         clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1219         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1220
1221         clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1222         clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1223         clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1224
1225         clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1226         clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1227         clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1228
1229         clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1230         clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1231         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1232
1233         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1234         clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1235         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1236
1237         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1238         clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1239         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1240         /* default ILT page size for all clients is 64K */
1241         for (i = 0; i < ILT_CLI_MAX; i++)
1242                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1243
1244         /* Initialize task sizes */
1245         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1246         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1247
1248         if (p_hwfn->cdev->p_iov_info)
1249                 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1250         /* Initialize the dynamic ILT allocation mutex */
1251         mutex_init(&p_mngr->mutex);
1252
1253         /* Set the cxt mangr pointer priori to further allocations */
1254         p_hwfn->p_cxt_mngr = p_mngr;
1255
1256         return 0;
1257 }
1258
1259 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1260 {
1261         int rc;
1262
1263         /* Allocate the ILT shadow table */
1264         rc = qed_ilt_shadow_alloc(p_hwfn);
1265         if (rc)
1266                 goto tables_alloc_fail;
1267
1268         /* Allocate the T2  table */
1269         rc = qed_cxt_src_t2_alloc(p_hwfn);
1270         if (rc)
1271                 goto tables_alloc_fail;
1272
1273         /* Allocate and initialize the acquired cids bitmaps */
1274         rc = qed_cid_map_alloc(p_hwfn);
1275         if (rc)
1276                 goto tables_alloc_fail;
1277
1278         return 0;
1279
1280 tables_alloc_fail:
1281         qed_cxt_mngr_free(p_hwfn);
1282         return rc;
1283 }
1284
1285 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1286 {
1287         if (!p_hwfn->p_cxt_mngr)
1288                 return;
1289
1290         qed_cid_map_free(p_hwfn);
1291         qed_cxt_src_t2_free(p_hwfn);
1292         qed_ilt_shadow_free(p_hwfn);
1293         kfree(p_hwfn->p_cxt_mngr);
1294
1295         p_hwfn->p_cxt_mngr = NULL;
1296 }
1297
1298 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1299 {
1300         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1301         struct qed_cid_acquired_map *p_map;
1302         struct qed_conn_type_cfg *p_cfg;
1303         int type;
1304         u32 len;
1305
1306         /* Reset acquired cids */
1307         for (type = 0; type < MAX_CONN_TYPES; type++) {
1308                 u32 vf;
1309
1310                 p_cfg = &p_mngr->conn_cfg[type];
1311                 if (p_cfg->cid_count) {
1312                         p_map = &p_mngr->acquired[type];
1313                         len = DIV_ROUND_UP(p_map->max_count,
1314                                            sizeof(unsigned long) *
1315                                            BITS_PER_BYTE) *
1316                               sizeof(unsigned long);
1317                         memset(p_map->cid_map, 0, len);
1318                 }
1319
1320                 if (!p_cfg->cids_per_vf)
1321                         continue;
1322
1323                 for (vf = 0; vf < MAX_NUM_VFS; vf++) {
1324                         p_map = &p_mngr->acquired_vf[type][vf];
1325                         len = DIV_ROUND_UP(p_map->max_count,
1326                                            sizeof(unsigned long) *
1327                                            BITS_PER_BYTE) *
1328                               sizeof(unsigned long);
1329                         memset(p_map->cid_map, 0, len);
1330                 }
1331         }
1332 }
1333
1334 /* CDU Common */
1335 #define CDUC_CXT_SIZE_SHIFT \
1336         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1337
1338 #define CDUC_CXT_SIZE_MASK \
1339         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1340
1341 #define CDUC_BLOCK_WASTE_SHIFT \
1342         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1343
1344 #define CDUC_BLOCK_WASTE_MASK \
1345         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1346
1347 #define CDUC_NCIB_SHIFT \
1348         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1349
1350 #define CDUC_NCIB_MASK \
1351         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1352
1353 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1354         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1355
1356 #define CDUT_TYPE0_CXT_SIZE_MASK                \
1357         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1358          CDUT_TYPE0_CXT_SIZE_SHIFT)
1359
1360 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1361         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1362
1363 #define CDUT_TYPE0_BLOCK_WASTE_MASK                    \
1364         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1365          CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1366
1367 #define CDUT_TYPE0_NCIB_SHIFT \
1368         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1369
1370 #define CDUT_TYPE0_NCIB_MASK                             \
1371         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1372          CDUT_TYPE0_NCIB_SHIFT)
1373
1374 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1375         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1376
1377 #define CDUT_TYPE1_CXT_SIZE_MASK                \
1378         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1379          CDUT_TYPE1_CXT_SIZE_SHIFT)
1380
1381 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1382         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1383
1384 #define CDUT_TYPE1_BLOCK_WASTE_MASK                    \
1385         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1386          CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1387
1388 #define CDUT_TYPE1_NCIB_SHIFT \
1389         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1390
1391 #define CDUT_TYPE1_NCIB_MASK                             \
1392         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1393          CDUT_TYPE1_NCIB_SHIFT)
1394
1395 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1396 {
1397         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1398
1399         /* CDUC - connection configuration */
1400         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1401         cxt_size = CONN_CXT_SIZE(p_hwfn);
1402         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1403         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1404
1405         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1406         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1407         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1408         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1409
1410         /* CDUT - type-0 tasks configuration */
1411         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1412         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1413         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1414         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1415
1416         /* cxt size and block-waste are multipes of 8 */
1417         cdu_params = 0;
1418         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1419         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1420         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1421         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1422
1423         /* CDUT - type-1 tasks configuration */
1424         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1425         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1426         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1427
1428         /* cxt size and block-waste are multipes of 8 */
1429         cdu_params = 0;
1430         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1431         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1432         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1433         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1434 }
1435
1436 /* CDU PF */
1437 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1438 #define CDU_SEG_REG_TYPE_MASK           0x1
1439 #define CDU_SEG_REG_OFFSET_SHIFT        0
1440 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1441
1442 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1443 {
1444         struct qed_ilt_client_cfg *p_cli;
1445         struct qed_tid_seg *p_seg;
1446         u32 cdu_seg_params, offset;
1447         int i;
1448
1449         static const u32 rt_type_offset_arr[] = {
1450                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1451                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1452                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1453                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1454         };
1455
1456         static const u32 rt_type_offset_fl_arr[] = {
1457                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1458                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1459                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1460                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1461         };
1462
1463         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1464
1465         /* There are initializations only for CDUT during pf Phase */
1466         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1467                 /* Segment 0 */
1468                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1469                 if (!p_seg)
1470                         continue;
1471
1472                 /* Note: start_line is already adjusted for the CDU
1473                  * segment register granularity, so we just need to
1474                  * divide. Adjustment is implicit as we assume ILT
1475                  * Page size is larger than 32K!
1476                  */
1477                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1478                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1479                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1480
1481                 cdu_seg_params = 0;
1482                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1483                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1484                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1485
1486                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1487                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1488                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1489
1490                 cdu_seg_params = 0;
1491                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1492                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1493                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1494         }
1495 }
1496
1497 void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1498 {
1499         struct qed_qm_pf_rt_init_params params;
1500         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1501         struct qed_qm_iids iids;
1502
1503         memset(&iids, 0, sizeof(iids));
1504         qed_cxt_qm_iids(p_hwfn, &iids);
1505
1506         memset(&params, 0, sizeof(params));
1507         params.port_id = p_hwfn->port_id;
1508         params.pf_id = p_hwfn->rel_pf_id;
1509         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1510         params.is_first_pf = p_hwfn->first_on_engine;
1511         params.num_pf_cids = iids.cids;
1512         params.num_vf_cids = iids.vf_cids;
1513         params.num_tids = iids.tids;
1514         params.start_pq = qm_info->start_pq;
1515         params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1516         params.num_vf_pqs = qm_info->num_vf_pqs;
1517         params.start_vport = qm_info->start_vport;
1518         params.num_vports = qm_info->num_vports;
1519         params.pf_wfq = qm_info->pf_wfq;
1520         params.pf_rl = qm_info->pf_rl;
1521         params.pq_params = qm_info->qm_pq_params;
1522         params.vport_params = qm_info->qm_vport_params;
1523
1524         qed_qm_pf_rt_init(p_hwfn, p_ptt, &params);
1525 }
1526
1527 /* CM PF */
1528 void qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1529 {
1530         /* XCM pure-LB queue */
1531         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1532                      qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1533 }
1534
1535 /* DQ PF */
1536 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1537 {
1538         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1539         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1540
1541         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1542         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1543
1544         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1545         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1546
1547         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1548         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1549
1550         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1551         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1552
1553         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1554         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1555
1556         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1557         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1558
1559         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1560         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1561
1562         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1563         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1564
1565         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1566         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1567
1568         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1569         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1570
1571         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1572         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1573
1574         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1575         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1576
1577         /* Connection types 6 & 7 are not in use, yet they must be configured
1578          * as the highest possible connection. Not configuring them means the
1579          * defaults will be  used, and with a large number of cids a bug may
1580          * occur, if the defaults will be smaller than dq_pf_max_cid /
1581          * dq_vf_max_cid.
1582          */
1583         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1584         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1585
1586         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1587         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1588 }
1589
1590 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1591 {
1592         struct qed_ilt_client_cfg *ilt_clients;
1593         int i;
1594
1595         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1596         for_each_ilt_valid_client(i, ilt_clients) {
1597                 STORE_RT_REG(p_hwfn,
1598                              ilt_clients[i].first.reg,
1599                              ilt_clients[i].first.val);
1600                 STORE_RT_REG(p_hwfn,
1601                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1602                 STORE_RT_REG(p_hwfn,
1603                              ilt_clients[i].p_size.reg,
1604                              ilt_clients[i].p_size.val);
1605         }
1606 }
1607
1608 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1609 {
1610         struct qed_ilt_client_cfg *p_cli;
1611         u32 blk_factor;
1612
1613         /* For simplicty  we set the 'block' to be an ILT page */
1614         if (p_hwfn->cdev->p_iov_info) {
1615                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1616
1617                 STORE_RT_REG(p_hwfn,
1618                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1619                              p_iov->first_vf_in_pf);
1620                 STORE_RT_REG(p_hwfn,
1621                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1622                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1623         }
1624
1625         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1626         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1627         if (p_cli->active) {
1628                 STORE_RT_REG(p_hwfn,
1629                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1630                              blk_factor);
1631                 STORE_RT_REG(p_hwfn,
1632                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1633                              p_cli->pf_total_lines);
1634                 STORE_RT_REG(p_hwfn,
1635                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1636                              p_cli->vf_total_lines);
1637         }
1638
1639         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1640         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1641         if (p_cli->active) {
1642                 STORE_RT_REG(p_hwfn,
1643                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1644                              blk_factor);
1645                 STORE_RT_REG(p_hwfn,
1646                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1647                              p_cli->pf_total_lines);
1648                 STORE_RT_REG(p_hwfn,
1649                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1650                              p_cli->vf_total_lines);
1651         }
1652
1653         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1654         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1655         if (p_cli->active) {
1656                 STORE_RT_REG(p_hwfn,
1657                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1658                 STORE_RT_REG(p_hwfn,
1659                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1660                              p_cli->pf_total_lines);
1661                 STORE_RT_REG(p_hwfn,
1662                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1663                              p_cli->vf_total_lines);
1664         }
1665 }
1666
1667 /* ILT (PSWRQ2) PF */
1668 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1669 {
1670         struct qed_ilt_client_cfg *clients;
1671         struct qed_cxt_mngr *p_mngr;
1672         struct qed_dma_mem *p_shdw;
1673         u32 line, rt_offst, i;
1674
1675         qed_ilt_bounds_init(p_hwfn);
1676         qed_ilt_vf_bounds_init(p_hwfn);
1677
1678         p_mngr = p_hwfn->p_cxt_mngr;
1679         p_shdw = p_mngr->ilt_shadow;
1680         clients = p_hwfn->p_cxt_mngr->clients;
1681
1682         for_each_ilt_valid_client(i, clients) {
1683                 /** Client's 1st val and RT array are absolute, ILT shadows'
1684                  *  lines are relative.
1685                  */
1686                 line = clients[i].first.val - p_mngr->pf_start_line;
1687                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1688                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1689
1690                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1691                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1692                         u64 ilt_hw_entry = 0;
1693
1694                         /** p_virt could be NULL incase of dynamic
1695                          *  allocation
1696                          */
1697                         if (p_shdw[line].p_virt) {
1698                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1699                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1700                                           (p_shdw[line].p_phys >> 12));
1701
1702                                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1703                                            "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1704                                            rt_offst, line, i,
1705                                            (u64)(p_shdw[line].p_phys >> 12));
1706                         }
1707
1708                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1709                 }
1710         }
1711 }
1712
1713 /* SRC (Searcher) PF */
1714 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1715 {
1716         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1717         u32 rounded_conn_num, conn_num, conn_max;
1718         struct qed_src_iids src_iids;
1719
1720         memset(&src_iids, 0, sizeof(src_iids));
1721         qed_cxt_src_iids(p_mngr, &src_iids);
1722         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1723         if (!conn_num)
1724                 return;
1725
1726         conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1727         rounded_conn_num = roundup_pow_of_two(conn_max);
1728
1729         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1730         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1731                      ilog2(rounded_conn_num));
1732
1733         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1734                          p_hwfn->p_cxt_mngr->first_free);
1735         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1736                          p_hwfn->p_cxt_mngr->last_free);
1737 }
1738
1739 /* Timers PF */
1740 #define TM_CFG_NUM_IDS_SHIFT            0
1741 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1742 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1743 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1744 #define TM_CFG_PARENT_PF_SHIFT          25
1745 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1746
1747 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1748 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1749
1750 #define TM_CFG_TID_OFFSET_SHIFT         30
1751 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1752 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1753 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1754
1755 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1756 {
1757         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1758         u32 active_seg_mask = 0, tm_offset, rt_reg;
1759         struct qed_tm_iids tm_iids;
1760         u64 cfg_word;
1761         u8 i;
1762
1763         memset(&tm_iids, 0, sizeof(tm_iids));
1764         qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
1765
1766         /* @@@TBD No pre-scan for now */
1767
1768         /* Note: We assume consecutive VFs for a PF */
1769         for (i = 0; i < p_mngr->vf_count; i++) {
1770                 cfg_word = 0;
1771                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1772                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1773                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1774                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1775                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1776                     (sizeof(cfg_word) / sizeof(u32)) *
1777                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1778                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1779         }
1780
1781         cfg_word = 0;
1782         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1783         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1784         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1785         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);       /* scan all   */
1786
1787         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1788             (sizeof(cfg_word) / sizeof(u32)) *
1789             (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1790         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1791
1792         /* enale scan */
1793         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1794                      tm_iids.pf_cids ? 0x1 : 0x0);
1795
1796         /* @@@TBD how to enable the scan for the VFs */
1797
1798         tm_offset = tm_iids.per_vf_cids;
1799
1800         /* Note: We assume consecutive VFs for a PF */
1801         for (i = 0; i < p_mngr->vf_count; i++) {
1802                 cfg_word = 0;
1803                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1804                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1805                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1806                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1807                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1808
1809                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1810                     (sizeof(cfg_word) / sizeof(u32)) *
1811                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1812
1813                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1814         }
1815
1816         tm_offset = tm_iids.pf_cids;
1817         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1818                 cfg_word = 0;
1819                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1820                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1821                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1822                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1823                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1824
1825                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1826                     (sizeof(cfg_word) / sizeof(u32)) *
1827                     (NUM_OF_VFS(p_hwfn->cdev) +
1828                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1829
1830                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1831                 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1832
1833                 tm_offset += tm_iids.pf_tids[i];
1834         }
1835
1836         if (QED_IS_RDMA_PERSONALITY(p_hwfn))
1837                 active_seg_mask = 0;
1838
1839         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1840
1841         /* @@@TBD how to enable the scan for the VFs */
1842 }
1843
1844 static void qed_prs_init_common(struct qed_hwfn *p_hwfn)
1845 {
1846         if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) &&
1847             p_hwfn->pf_params.fcoe_pf_params.is_target)
1848                 STORE_RT_REG(p_hwfn,
1849                              PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
1850 }
1851
1852 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn)
1853 {
1854         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1855         struct qed_conn_type_cfg *p_fcoe;
1856         struct qed_tid_seg *p_tid;
1857
1858         p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1859
1860         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1861         if (!p_fcoe->cid_count)
1862                 return;
1863
1864         p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG];
1865         if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
1866                 STORE_RT_REG_AGG(p_hwfn,
1867                                  PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
1868                                  p_tid->count);
1869         } else {
1870                 STORE_RT_REG_AGG(p_hwfn,
1871                                  PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1872                                  p_tid->count);
1873         }
1874 }
1875
1876 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1877 {
1878         qed_cdu_init_common(p_hwfn);
1879         qed_prs_init_common(p_hwfn);
1880 }
1881
1882 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1883 {
1884         qed_qm_init_pf(p_hwfn, p_ptt);
1885         qed_cm_init_pf(p_hwfn);
1886         qed_dq_init_pf(p_hwfn);
1887         qed_cdu_init_pf(p_hwfn);
1888         qed_ilt_init_pf(p_hwfn);
1889         qed_src_init_pf(p_hwfn);
1890         qed_tm_init_pf(p_hwfn);
1891         qed_prs_init_pf(p_hwfn);
1892 }
1893
1894 int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1895                          enum protocol_type type, u32 *p_cid, u8 vfid)
1896 {
1897         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1898         struct qed_cid_acquired_map *p_map;
1899         u32 rel_cid;
1900
1901         if (type >= MAX_CONN_TYPES) {
1902                 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1903                 return -EINVAL;
1904         }
1905
1906         if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) {
1907                 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid);
1908                 return -EINVAL;
1909         }
1910
1911         /* Determine the right map to take this CID from */
1912         if (vfid == QED_CXT_PF_CID)
1913                 p_map = &p_mngr->acquired[type];
1914         else
1915                 p_map = &p_mngr->acquired_vf[type][vfid];
1916
1917         if (!p_map->cid_map) {
1918                 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1919                 return -EINVAL;
1920         }
1921
1922         rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count);
1923
1924         if (rel_cid >= p_map->max_count) {
1925                 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1926                 return -EINVAL;
1927         }
1928
1929         __set_bit(rel_cid, p_map->cid_map);
1930
1931         *p_cid = rel_cid + p_map->start_cid;
1932
1933         DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1934                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1935                    *p_cid, rel_cid, vfid, type);
1936
1937         return 0;
1938 }
1939
1940 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1941                         enum protocol_type type, u32 *p_cid)
1942 {
1943         return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID);
1944 }
1945
1946 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1947                                       u32 cid,
1948                                       u8 vfid,
1949                                       enum protocol_type *p_type,
1950                                       struct qed_cid_acquired_map **pp_map)
1951 {
1952         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1953         u32 rel_cid;
1954
1955         /* Iterate over protocols and find matching cid range */
1956         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1957                 if (vfid == QED_CXT_PF_CID)
1958                         *pp_map = &p_mngr->acquired[*p_type];
1959                 else
1960                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1961
1962                 if (!((*pp_map)->cid_map))
1963                         continue;
1964                 if (cid >= (*pp_map)->start_cid &&
1965                     cid < (*pp_map)->start_cid + (*pp_map)->max_count)
1966                         break;
1967         }
1968
1969         if (*p_type == MAX_CONN_TYPES) {
1970                 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid);
1971                 goto fail;
1972         }
1973
1974         rel_cid = cid - (*pp_map)->start_cid;
1975         if (!test_bit(rel_cid, (*pp_map)->cid_map)) {
1976                 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired",
1977                           cid, vfid);
1978                 goto fail;
1979         }
1980
1981         return true;
1982 fail:
1983         *p_type = MAX_CONN_TYPES;
1984         *pp_map = NULL;
1985         return false;
1986 }
1987
1988 void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid)
1989 {
1990         struct qed_cid_acquired_map *p_map = NULL;
1991         enum protocol_type type;
1992         bool b_acquired;
1993         u32 rel_cid;
1994
1995         if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) {
1996                 DP_NOTICE(p_hwfn,
1997                           "Trying to return incorrect CID belonging to VF %02x\n",
1998                           vfid);
1999                 return;
2000         }
2001
2002         /* Test acquired and find matching per-protocol map */
2003         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid,
2004                                                &type, &p_map);
2005
2006         if (!b_acquired)
2007                 return;
2008
2009         rel_cid = cid - p_map->start_cid;
2010         clear_bit(rel_cid, p_map->cid_map);
2011
2012         DP_VERBOSE(p_hwfn, QED_MSG_CXT,
2013                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
2014                    cid, rel_cid, vfid, type);
2015 }
2016
2017 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
2018 {
2019         _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID);
2020 }
2021
2022 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
2023 {
2024         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2025         struct qed_cid_acquired_map *p_map = NULL;
2026         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
2027         enum protocol_type type;
2028         bool b_acquired;
2029
2030         /* Test acquired and find matching per-protocol map */
2031         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid,
2032                                                QED_CXT_PF_CID, &type, &p_map);
2033
2034         if (!b_acquired)
2035                 return -EINVAL;
2036
2037         /* set the protocl type */
2038         p_info->type = type;
2039
2040         /* compute context virtual pointer */
2041         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
2042
2043         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
2044         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
2045         line = p_info->iid / cxts_per_p;
2046
2047         /* Make sure context is allocated (dynamic allocation) */
2048         if (!p_mngr->ilt_shadow[line].p_virt)
2049                 return -EINVAL;
2050
2051         p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
2052                         p_info->iid % cxts_per_p * conn_cxt_size;
2053
2054         DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
2055                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
2056                    p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
2057
2058         return 0;
2059 }
2060
2061 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
2062                                    struct qed_rdma_pf_params *p_params,
2063                                    u32 num_tasks)
2064 {
2065         u32 num_cons, num_qps, num_srqs;
2066         enum protocol_type proto;
2067
2068         num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
2069
2070         switch (p_hwfn->hw_info.personality) {
2071         case QED_PCI_ETH_ROCE:
2072                 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
2073                 num_cons = num_qps * 2; /* each QP requires two connections */
2074                 proto = PROTOCOLID_ROCE;
2075                 break;
2076         default:
2077                 return;
2078         }
2079
2080         if (num_cons && num_tasks) {
2081                 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
2082
2083                 /* Deliberatly passing ROCE for tasks id. This is because
2084                  * iWARP / RoCE share the task id.
2085                  */
2086                 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
2087                                             QED_CXT_ROCE_TID_SEG, 1,
2088                                             num_tasks, false);
2089                 qed_cxt_set_srq_count(p_hwfn, num_srqs);
2090         } else {
2091                 DP_INFO(p_hwfn->cdev,
2092                         "RDMA personality used without setting params!\n");
2093         }
2094 }
2095
2096 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks)
2097 {
2098         /* Set the number of required CORE connections */
2099         u32 core_cids = 1; /* SPQ */
2100
2101         if (p_hwfn->using_ll2)
2102                 core_cids += 4;
2103         qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
2104
2105         switch (p_hwfn->hw_info.personality) {
2106         case QED_PCI_ETH_ROCE:
2107         {
2108                         qed_rdma_set_pf_params(p_hwfn,
2109                                                &p_hwfn->
2110                                                pf_params.rdma_pf_params,
2111                                                rdma_tasks);
2112                 /* no need for break since RoCE coexist with Ethernet */
2113         }
2114         case QED_PCI_ETH:
2115         {
2116                 struct qed_eth_pf_params *p_params =
2117                     &p_hwfn->pf_params.eth_pf_params;
2118
2119                         if (!p_params->num_vf_cons)
2120                                 p_params->num_vf_cons =
2121                                     ETH_PF_PARAMS_VF_CONS_DEFAULT;
2122                         qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2123                                                     p_params->num_cons,
2124                                                     p_params->num_vf_cons);
2125                 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2126                 break;
2127         }
2128         case QED_PCI_FCOE:
2129         {
2130                 struct qed_fcoe_pf_params *p_params;
2131
2132                 p_params = &p_hwfn->pf_params.fcoe_pf_params;
2133
2134                 if (p_params->num_cons && p_params->num_tasks) {
2135                         qed_cxt_set_proto_cid_count(p_hwfn,
2136                                                     PROTOCOLID_FCOE,
2137                                                     p_params->num_cons,
2138                                                     0);
2139
2140                         qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
2141                                                     QED_CXT_FCOE_TID_SEG, 0,
2142                                                     p_params->num_tasks, true);
2143                 } else {
2144                         DP_INFO(p_hwfn->cdev,
2145                                 "Fcoe personality used without setting params!\n");
2146                 }
2147                 break;
2148         }
2149         case QED_PCI_ISCSI:
2150         {
2151                 struct qed_iscsi_pf_params *p_params;
2152
2153                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
2154
2155                 if (p_params->num_cons && p_params->num_tasks) {
2156                         qed_cxt_set_proto_cid_count(p_hwfn,
2157                                                     PROTOCOLID_ISCSI,
2158                                                     p_params->num_cons,
2159                                                     0);
2160
2161                         qed_cxt_set_proto_tid_count(p_hwfn,
2162                                                     PROTOCOLID_ISCSI,
2163                                                     QED_CXT_ISCSI_TID_SEG,
2164                                                     0,
2165                                                     p_params->num_tasks,
2166                                                     true);
2167                 } else {
2168                         DP_INFO(p_hwfn->cdev,
2169                                 "Iscsi personality used without setting params!\n");
2170                 }
2171                 break;
2172         }
2173         default:
2174                 return -EINVAL;
2175         }
2176
2177         return 0;
2178 }
2179
2180 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
2181                              struct qed_tid_mem *p_info)
2182 {
2183         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2184         u32 proto, seg, total_lines, i, shadow_line;
2185         struct qed_ilt_client_cfg *p_cli;
2186         struct qed_ilt_cli_blk *p_fl_seg;
2187         struct qed_tid_seg *p_seg_info;
2188
2189         /* Verify the personality */
2190         switch (p_hwfn->hw_info.personality) {
2191         case QED_PCI_FCOE:
2192                 proto = PROTOCOLID_FCOE;
2193                 seg = QED_CXT_FCOE_TID_SEG;
2194                 break;
2195         case QED_PCI_ISCSI:
2196                 proto = PROTOCOLID_ISCSI;
2197                 seg = QED_CXT_ISCSI_TID_SEG;
2198                 break;
2199         default:
2200                 return -EINVAL;
2201         }
2202
2203         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2204         if (!p_cli->active)
2205                 return -EINVAL;
2206
2207         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2208         if (!p_seg_info->has_fl_mem)
2209                 return -EINVAL;
2210
2211         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2212         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2213                                    p_fl_seg->real_size_in_page);
2214
2215         for (i = 0; i < total_lines; i++) {
2216                 shadow_line = i + p_fl_seg->start_line -
2217                     p_hwfn->p_cxt_mngr->pf_start_line;
2218                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2219         }
2220         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2221             p_fl_seg->real_size_in_page;
2222         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2223         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2224             p_info->tid_size;
2225
2226         return 0;
2227 }
2228
2229 /* This function is very RoCE oriented, if another protocol in the future
2230  * will want this feature we'll need to modify the function to be more generic
2231  */
2232 int
2233 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
2234                           enum qed_cxt_elem_type elem_type, u32 iid)
2235 {
2236         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2237         struct qed_ilt_client_cfg *p_cli;
2238         struct qed_ilt_cli_blk *p_blk;
2239         struct qed_ptt *p_ptt;
2240         dma_addr_t p_phys;
2241         u64 ilt_hw_entry;
2242         void *p_virt;
2243         int rc = 0;
2244
2245         switch (elem_type) {
2246         case QED_ELEM_CXT:
2247                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2248                 elem_size = CONN_CXT_SIZE(p_hwfn);
2249                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2250                 break;
2251         case QED_ELEM_SRQ:
2252                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2253                 elem_size = SRQ_CXT_SIZE;
2254                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2255                 break;
2256         case QED_ELEM_TASK:
2257                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2258                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2259                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2260                 break;
2261         default:
2262                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2263                 return -EINVAL;
2264         }
2265
2266         /* Calculate line in ilt */
2267         hw_p_size = p_cli->p_size.val;
2268         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2269         line = p_blk->start_line + (iid / elems_per_p);
2270         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2271
2272         /* If line is already allocated, do nothing, otherwise allocate it and
2273          * write it to the PSWRQ2 registers.
2274          * This section can be run in parallel from different contexts and thus
2275          * a mutex protection is needed.
2276          */
2277
2278         mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
2279
2280         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2281                 goto out0;
2282
2283         p_ptt = qed_ptt_acquire(p_hwfn);
2284         if (!p_ptt) {
2285                 DP_NOTICE(p_hwfn,
2286                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2287                 rc = -EBUSY;
2288                 goto out0;
2289         }
2290
2291         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2292                                     p_blk->real_size_in_page,
2293                                     &p_phys, GFP_KERNEL);
2294         if (!p_virt) {
2295                 rc = -ENOMEM;
2296                 goto out1;
2297         }
2298         memset(p_virt, 0, p_blk->real_size_in_page);
2299
2300         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2301          * to compensate for a HW bug, but it is configured even if DIF is not
2302          * enabled. This is harmless and allows us to avoid a dedicated API. We
2303          * configure the field for all of the contexts on the newly allocated
2304          * page.
2305          */
2306         if (elem_type == QED_ELEM_TASK) {
2307                 u32 elem_i;
2308                 u8 *elem_start = (u8 *)p_virt;
2309                 union type1_task_context *elem;
2310
2311                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2312                         elem = (union type1_task_context *)elem_start;
2313                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2314                                   TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
2315                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2316                 }
2317         }
2318
2319         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2320         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2321         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2322             p_blk->real_size_in_page;
2323
2324         /* compute absolute offset */
2325         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2326             (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2327
2328         ilt_hw_entry = 0;
2329         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2330         SET_FIELD(ilt_hw_entry,
2331                   ILT_ENTRY_PHY_ADDR,
2332                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2333
2334         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2335         qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2336                           reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2337
2338         if (elem_type == QED_ELEM_CXT) {
2339                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2340                     elems_per_p;
2341
2342                 /* Update the relevant register in the parser */
2343                 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2344                        last_cid_allocated - 1);
2345
2346                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2347                         /* Enable RDMA search */
2348                         qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2349                         p_hwfn->b_rdma_enabled_in_prs = true;
2350                 }
2351         }
2352
2353 out1:
2354         qed_ptt_release(p_hwfn, p_ptt);
2355 out0:
2356         mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2357
2358         return rc;
2359 }
2360
2361 /* This function is very RoCE oriented, if another protocol in the future
2362  * will want this feature we'll need to modify the function to be more generic
2363  */
2364 static int
2365 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2366                        enum qed_cxt_elem_type elem_type,
2367                        u32 start_iid, u32 count)
2368 {
2369         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2370         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2371         struct qed_ilt_client_cfg *p_cli;
2372         struct qed_ilt_cli_blk *p_blk;
2373         u32 end_iid = start_iid + count;
2374         struct qed_ptt *p_ptt;
2375         u64 ilt_hw_entry = 0;
2376         u32 i;
2377
2378         switch (elem_type) {
2379         case QED_ELEM_CXT:
2380                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2381                 elem_size = CONN_CXT_SIZE(p_hwfn);
2382                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2383                 break;
2384         case QED_ELEM_SRQ:
2385                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2386                 elem_size = SRQ_CXT_SIZE;
2387                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2388                 break;
2389         case QED_ELEM_TASK:
2390                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2391                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2392                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2393                 break;
2394         default:
2395                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2396                 return -EINVAL;
2397         }
2398
2399         /* Calculate line in ilt */
2400         hw_p_size = p_cli->p_size.val;
2401         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2402         start_line = p_blk->start_line + (start_iid / elems_per_p);
2403         end_line = p_blk->start_line + (end_iid / elems_per_p);
2404         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2405                 end_line--;
2406
2407         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2408         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2409
2410         p_ptt = qed_ptt_acquire(p_hwfn);
2411         if (!p_ptt) {
2412                 DP_NOTICE(p_hwfn,
2413                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2414                 return -EBUSY;
2415         }
2416
2417         for (i = shadow_start_line; i < shadow_end_line; i++) {
2418                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2419                         continue;
2420
2421                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2422                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2423                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2424                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2425
2426                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2427                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2428                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2429
2430                 /* compute absolute offset */
2431                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2432                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2433                      ILT_ENTRY_IN_REGS);
2434
2435                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2436                  * wide-bus.
2437                  */
2438                 qed_dmae_host2grc(p_hwfn, p_ptt,
2439                                   (u64) (uintptr_t) &ilt_hw_entry,
2440                                   reg_offset,
2441                                   sizeof(ilt_hw_entry) / sizeof(u32),
2442                                   0);
2443         }
2444
2445         qed_ptt_release(p_hwfn, p_ptt);
2446
2447         return 0;
2448 }
2449
2450 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2451 {
2452         int rc;
2453         u32 cid;
2454
2455         /* Free Connection CXT */
2456         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2457                                     qed_cxt_get_proto_cid_start(p_hwfn,
2458                                                                 proto),
2459                                     qed_cxt_get_proto_cid_count(p_hwfn,
2460                                                                 proto, &cid));
2461
2462         if (rc)
2463                 return rc;
2464
2465         /* Free Task CXT */
2466         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2467                                     qed_cxt_get_proto_tid_count(p_hwfn, proto));
2468         if (rc)
2469                 return rc;
2470
2471         /* Free TSDM CXT */
2472         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2473                                     qed_cxt_get_srq_count(p_hwfn));
2474
2475         return rc;
2476 }
2477
2478 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2479                          u32 tid, u8 ctx_type, void **pp_task_ctx)
2480 {
2481         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2482         struct qed_ilt_client_cfg *p_cli;
2483         struct qed_tid_seg *p_seg_info;
2484         struct qed_ilt_cli_blk *p_seg;
2485         u32 num_tids_per_block;
2486         u32 tid_size, ilt_idx;
2487         u32 total_lines;
2488         u32 proto, seg;
2489
2490         /* Verify the personality */
2491         switch (p_hwfn->hw_info.personality) {
2492         case QED_PCI_FCOE:
2493                 proto = PROTOCOLID_FCOE;
2494                 seg = QED_CXT_FCOE_TID_SEG;
2495                 break;
2496         case QED_PCI_ISCSI:
2497                 proto = PROTOCOLID_ISCSI;
2498                 seg = QED_CXT_ISCSI_TID_SEG;
2499                 break;
2500         default:
2501                 return -EINVAL;
2502         }
2503
2504         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2505         if (!p_cli->active)
2506                 return -EINVAL;
2507
2508         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2509
2510         if (ctx_type == QED_CTX_WORKING_MEM) {
2511                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2512         } else if (ctx_type == QED_CTX_FL_MEM) {
2513                 if (!p_seg_info->has_fl_mem)
2514                         return -EINVAL;
2515                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2516         } else {
2517                 return -EINVAL;
2518         }
2519         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2520         tid_size = p_mngr->task_type_size[p_seg_info->type];
2521         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2522
2523         if (total_lines < tid / num_tids_per_block)
2524                 return -EINVAL;
2525
2526         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2527                   p_mngr->pf_start_line;
2528         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2529                        (tid % num_tids_per_block) * tid_size;
2530
2531         return 0;
2532 }