1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <linux/bitops.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/errno.h>
37 #include <linux/kernel.h>
38 #include <linux/list.h>
39 #include <linux/log2.h>
40 #include <linux/pci.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/bitops.h>
46 #include "qed_dev_api.h"
49 #include "qed_init_ops.h"
50 #include "qed_reg_addr.h"
51 #include "qed_sriov.h"
53 /* Max number of connection types in HW (DQ/CDU etc.) */
54 #define MAX_CONN_TYPES PROTOCOLID_COMMON
55 #define NUM_TASK_TYPES 2
56 #define NUM_TASK_PF_SEGMENTS 4
57 #define NUM_TASK_VF_SEGMENTS 1
60 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */
62 /* Doorbell-Queue constants */
63 #define DQ_RANGE_SHIFT 4
64 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT)
66 /* Searcher constants */
67 #define SRC_MIN_NUM_ELEMS 256
69 /* Timers constants */
71 #define TM_ALIGN BIT(TM_SHIFT)
72 #define TM_ELEM_SIZE 4
74 /* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. */
75 #define ILT_DEFAULT_HW_P_SIZE (IS_ENABLED(CONFIG_QED_RDMA) ? 4 : 3)
77 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
78 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
80 /* ILT entry structure */
81 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
82 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
83 #define ILT_ENTRY_VALID_MASK 0x1ULL
84 #define ILT_ENTRY_VALID_SHIFT 52
85 #define ILT_ENTRY_IN_REGS 2
86 #define ILT_REG_SIZE_IN_BYTES 4
88 /* connection context union */
90 struct core_conn_context core_ctx;
91 struct eth_conn_context eth_ctx;
92 struct iscsi_conn_context iscsi_ctx;
93 struct fcoe_conn_context fcoe_ctx;
94 struct roce_conn_context roce_ctx;
97 /* TYPE-0 task context - iSCSI, FCOE */
98 union type0_task_context {
99 struct iscsi_task_context iscsi_ctx;
100 struct fcoe_task_context fcoe_ctx;
103 /* TYPE-1 task context - ROCE */
104 union type1_task_context {
105 struct rdma_task_context roce_ctx;
113 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
114 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
116 #define CONN_CXT_SIZE(p_hwfn) \
117 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
119 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
121 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
122 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
124 /* Alignment is inherent to the type1_task_context structure */
125 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
127 /* PF per protocl configuration object */
128 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
129 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
137 struct qed_conn_type_cfg {
141 struct qed_tid_seg tid_seg[TASK_SEGMENTS];
144 /* ILT Client configuration, Per connection type (protocol) resources. */
145 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
146 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
149 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
150 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
162 struct ilt_cfg_pair {
167 struct qed_ilt_cli_blk {
168 u32 total_size; /* 0 means not active */
169 u32 real_size_in_page;
171 u32 dynamic_line_cnt;
174 struct qed_ilt_client_cfg {
178 struct ilt_cfg_pair first;
179 struct ilt_cfg_pair last;
180 struct ilt_cfg_pair p_size;
182 /* ILT client blocks for PF */
183 struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
186 /* ILT client blocks for VFs */
187 struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
193 * Protocol acquired CID lists
194 * PF start line in ILT
202 struct qed_cid_acquired_map {
205 unsigned long *cid_map;
208 struct qed_cxt_mngr {
209 /* Per protocl configuration */
210 struct qed_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
212 /* computed ILT structure */
213 struct qed_ilt_client_cfg clients[ILT_CLI_MAX];
215 /* Task type sizes */
216 u32 task_type_size[NUM_TASK_TYPES];
218 /* total number of VFs for this hwfn -
219 * ALL VFs are symmetric in terms of HW resources
223 /* total number of SRQ's for this hwfn */
227 struct qed_cid_acquired_map acquired[MAX_CONN_TYPES];
229 /* ILT shadow table */
230 struct qed_dma_mem *ilt_shadow;
233 /* Mutex for a dynamic ILT allocation */
237 struct qed_dma_mem *t2;
242 static bool src_proto(enum protocol_type type)
244 return type == PROTOCOLID_ISCSI ||
245 type == PROTOCOLID_FCOE ||
246 type == PROTOCOLID_ROCE;
249 static bool tm_cid_proto(enum protocol_type type)
251 return type == PROTOCOLID_ISCSI ||
252 type == PROTOCOLID_FCOE ||
253 type == PROTOCOLID_ROCE;
256 static bool tm_tid_proto(enum protocol_type type)
258 return type == PROTOCOLID_FCOE;
261 /* counts the iids for the CDU/CDUC ILT client configuration */
262 struct qed_cdu_iids {
267 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
268 struct qed_cdu_iids *iids)
272 for (type = 0; type < MAX_CONN_TYPES; type++) {
273 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
274 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
278 /* counts the iids for the Searcher block configuration */
279 struct qed_src_iids {
284 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
285 struct qed_src_iids *iids)
289 for (i = 0; i < MAX_CONN_TYPES; i++) {
293 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
294 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
298 /* counts the iids for the Timers block configuration */
301 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
307 static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr,
308 struct qed_tm_iids *iids)
312 for (i = 0; i < MAX_CONN_TYPES; i++) {
313 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
315 if (tm_cid_proto(i)) {
316 iids->pf_cids += p_cfg->cid_count;
317 iids->per_vf_cids += p_cfg->cids_per_vf;
320 if (tm_tid_proto(i)) {
321 struct qed_tid_seg *segs = p_cfg->tid_seg;
323 /* for each segment there is at most one
324 * protocol for which count is not 0.
326 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
327 iids->pf_tids[j] += segs[j].count;
329 /* The last array elelment is for the VFs. As for PF
330 * segments there can be only one protocol for
331 * which this value is not 0.
333 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
337 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
338 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
339 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
341 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
342 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
343 iids->pf_tids_total += iids->pf_tids[j];
347 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
348 struct qed_qm_iids *iids)
350 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
351 struct qed_tid_seg *segs;
352 u32 vf_cids = 0, type, j;
355 for (type = 0; type < MAX_CONN_TYPES; type++) {
356 iids->cids += p_mngr->conn_cfg[type].cid_count;
357 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
359 segs = p_mngr->conn_cfg[type].tid_seg;
360 /* for each segment there is at most one
361 * protocol for which count is not 0.
363 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
364 iids->tids += segs[j].count;
366 /* The last array elelment is for the VFs. As for PF
367 * segments there can be only one protocol for
368 * which this value is not 0.
370 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
373 iids->vf_cids += vf_cids * p_mngr->vf_count;
374 iids->tids += vf_tids * p_mngr->vf_count;
376 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
377 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
378 iids->cids, iids->vf_cids, iids->tids, vf_tids);
381 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
384 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
387 /* Find the protocol with tid count > 0 for this segment.
388 * Note: there can only be one and this is already validated.
390 for (i = 0; i < MAX_CONN_TYPES; i++)
391 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
392 return &p_cfg->conn_cfg[i].tid_seg[seg];
396 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
398 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
400 p_mgr->srq_count = num_srqs;
403 static u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
405 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
407 return p_mgr->srq_count;
410 /* set the iids count per protocol */
411 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
412 enum protocol_type type,
413 u32 cid_count, u32 vf_cid_cnt)
415 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
416 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
418 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
419 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
421 if (type == PROTOCOLID_ROCE) {
422 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
423 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
424 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
425 u32 align = elems_per_page * DQ_RANGE_ALIGN;
427 p_conn->cid_count = roundup(p_conn->cid_count, align);
431 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
432 enum protocol_type type, u32 *vf_cid)
435 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
437 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
440 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
441 enum protocol_type type)
443 return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
446 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
447 enum protocol_type type)
452 for (i = 0; i < TASK_SEGMENTS; i++)
453 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
458 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
459 enum protocol_type proto,
461 u8 seg_type, u32 count, bool has_fl)
463 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
464 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
466 p_seg->count = count;
467 p_seg->has_fl_mem = has_fl;
468 p_seg->type = seg_type;
471 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
472 struct qed_ilt_cli_blk *p_blk,
473 u32 start_line, u32 total_size, u32 elem_size)
475 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
477 /* verify thatits called only once for each block */
478 if (p_blk->total_size)
481 p_blk->total_size = total_size;
482 p_blk->real_size_in_page = 0;
484 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
485 p_blk->start_line = start_line;
488 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
489 struct qed_ilt_client_cfg *p_cli,
490 struct qed_ilt_cli_blk *p_blk,
491 u32 *p_line, enum ilt_clients client_id)
493 if (!p_blk->total_size)
497 p_cli->first.val = *p_line;
499 p_cli->active = true;
500 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
501 p_cli->last.val = *p_line - 1;
503 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
504 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
505 client_id, p_cli->first.val,
506 p_cli->last.val, p_blk->total_size,
507 p_blk->real_size_in_page, p_blk->start_line);
510 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
511 enum ilt_clients ilt_client)
513 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
514 struct qed_ilt_client_cfg *p_cli;
515 u32 lines_to_skip = 0;
518 if (ilt_client == ILT_CLI_CDUC) {
519 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
521 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
522 (u32) CONN_CXT_SIZE(p_hwfn);
524 lines_to_skip = cid_count / cxts_per_p;
527 return lines_to_skip;
530 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
532 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
533 u32 curr_line, total, i, task_size, line;
534 struct qed_ilt_client_cfg *p_cli;
535 struct qed_ilt_cli_blk *p_blk;
536 struct qed_cdu_iids cdu_iids;
537 struct qed_src_iids src_iids;
538 struct qed_qm_iids qm_iids;
539 struct qed_tm_iids tm_iids;
540 struct qed_tid_seg *p_seg;
542 memset(&qm_iids, 0, sizeof(qm_iids));
543 memset(&cdu_iids, 0, sizeof(cdu_iids));
544 memset(&src_iids, 0, sizeof(src_iids));
545 memset(&tm_iids, 0, sizeof(tm_iids));
547 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
549 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
550 "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
551 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
554 p_cli = &p_mngr->clients[ILT_CLI_CDUC];
555 curr_line = p_mngr->pf_start_line;
558 p_cli->pf_total_lines = 0;
560 /* get the counters for the CDUC and QM clients */
561 qed_cxt_cdu_iids(p_mngr, &cdu_iids);
563 p_blk = &p_cli->pf_blks[CDUC_BLK];
565 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
567 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
568 total, CONN_CXT_SIZE(p_hwfn));
570 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
571 p_cli->pf_total_lines = curr_line - p_blk->start_line;
573 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
577 p_blk = &p_cli->vf_blks[CDUC_BLK];
578 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
580 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
581 total, CONN_CXT_SIZE(p_hwfn));
583 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
584 p_cli->vf_total_lines = curr_line - p_blk->start_line;
586 for (i = 1; i < p_mngr->vf_count; i++)
587 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
591 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
592 p_cli->first.val = curr_line;
594 /* first the 'working' task memory */
595 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
596 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
597 if (!p_seg || p_seg->count == 0)
600 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
601 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
602 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
603 p_mngr->task_type_size[p_seg->type]);
605 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
609 /* next the 'init' task memory (forced load memory) */
610 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
611 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
612 if (!p_seg || p_seg->count == 0)
615 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
617 if (!p_seg->has_fl_mem) {
618 /* The segment is active (total size pf 'working'
619 * memory is > 0) but has no FL (forced-load, Init)
622 * 1. The total-size in the corrsponding FL block of
623 * the ILT client is set to 0 - No ILT line are
624 * provisioned and no ILT memory allocated.
626 * 2. The start-line of said block is set to the
627 * start line of the matching working memory
628 * block in the ILT client. This is later used to
629 * configure the CDU segment offset registers and
630 * results in an FL command for TIDs of this
631 * segement behaves as regular load commands
632 * (loading TIDs from the working memory).
634 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
636 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
639 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
641 qed_ilt_cli_blk_fill(p_cli, p_blk,
643 p_mngr->task_type_size[p_seg->type]);
645 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
648 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
651 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
652 if (p_seg && p_seg->count) {
653 /* Stricly speaking we need to iterate over all VF
654 * task segment types, but a VF has only 1 segment
657 /* 'working' memory */
658 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
660 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
661 qed_ilt_cli_blk_fill(p_cli, p_blk,
663 p_mngr->task_type_size[p_seg->type]);
665 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
669 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
670 if (!p_seg->has_fl_mem) {
671 /* see comment above */
672 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
673 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
675 task_size = p_mngr->task_type_size[p_seg->type];
676 qed_ilt_cli_blk_fill(p_cli, p_blk,
677 curr_line, total, task_size);
678 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
681 p_cli->vf_total_lines = curr_line -
682 p_cli->vf_blks[0].start_line;
684 /* Now for the rest of the VFs */
685 for (i = 1; i < p_mngr->vf_count; i++) {
686 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
687 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
690 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
691 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
697 p_cli = &p_mngr->clients[ILT_CLI_QM];
698 p_blk = &p_cli->pf_blks[0];
700 qed_cxt_qm_iids(p_hwfn, &qm_iids);
701 total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
702 qm_iids.vf_cids, qm_iids.tids,
703 p_hwfn->qm_info.num_pqs,
704 p_hwfn->qm_info.num_vf_pqs);
708 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
712 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
714 qed_ilt_cli_blk_fill(p_cli, p_blk,
715 curr_line, total * 0x1000,
718 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
719 p_cli->pf_total_lines = curr_line - p_blk->start_line;
722 p_cli = &p_mngr->clients[ILT_CLI_SRC];
723 qed_cxt_src_iids(p_mngr, &src_iids);
725 /* Both the PF and VFs searcher connections are stored in the per PF
726 * database. Thus sum the PF searcher cids and all the VFs searcher
729 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
731 u32 local_max = max_t(u32, total,
734 total = roundup_pow_of_two(local_max);
736 p_blk = &p_cli->pf_blks[0];
737 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
738 total * sizeof(struct src_ent),
739 sizeof(struct src_ent));
741 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
743 p_cli->pf_total_lines = curr_line - p_blk->start_line;
747 p_cli = &p_mngr->clients[ILT_CLI_TM];
748 qed_cxt_tm_iids(p_mngr, &tm_iids);
749 total = tm_iids.pf_cids + tm_iids.pf_tids_total;
751 p_blk = &p_cli->pf_blks[0];
752 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
753 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
755 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
757 p_cli->pf_total_lines = curr_line - p_blk->start_line;
761 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
763 p_blk = &p_cli->vf_blks[0];
764 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
765 total * TM_ELEM_SIZE, TM_ELEM_SIZE);
767 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
769 p_cli->pf_total_lines = curr_line - p_blk->start_line;
771 for (i = 1; i < p_mngr->vf_count; i++)
772 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
776 /* TSDM (SRQ CONTEXT) */
777 total = qed_cxt_get_srq_count(p_hwfn);
780 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
781 p_blk = &p_cli->pf_blks[SRQ_BLK];
782 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
783 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
785 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
787 p_cli->pf_total_lines = curr_line - p_blk->start_line;
790 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
791 RESC_NUM(p_hwfn, QED_ILT)) {
792 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
793 curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
800 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
802 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
808 for (i = 0; i < p_mngr->t2_num_pages; i++)
809 if (p_mngr->t2[i].p_virt)
810 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
812 p_mngr->t2[i].p_virt,
813 p_mngr->t2[i].p_phys);
819 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
821 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
822 u32 conn_num, total_size, ent_per_page, psz, i;
823 struct qed_ilt_client_cfg *p_src;
824 struct qed_src_iids src_iids;
825 struct qed_dma_mem *p_t2;
828 memset(&src_iids, 0, sizeof(src_iids));
830 /* if the SRC ILT client is inactive - there are no connection
831 * requiring the searcer, leave.
833 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
837 qed_cxt_src_iids(p_mngr, &src_iids);
838 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
839 total_size = conn_num * sizeof(struct src_ent);
841 /* use the same page size as the SRC ILT client */
842 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
843 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
846 p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
853 /* allocate t2 pages */
854 for (i = 0; i < p_mngr->t2_num_pages; i++) {
855 u32 size = min_t(u32, total_size, psz);
856 void **p_virt = &p_mngr->t2[i].p_virt;
858 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
860 &p_mngr->t2[i].p_phys, GFP_KERNEL);
861 if (!p_mngr->t2[i].p_virt) {
865 memset(*p_virt, 0, size);
866 p_mngr->t2[i].size = size;
870 /* Set the t2 pointers */
872 /* entries per page - must be a power of two */
873 ent_per_page = psz / sizeof(struct src_ent);
875 p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
877 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
878 p_mngr->last_free = (u64) p_t2->p_phys +
879 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
881 for (i = 0; i < p_mngr->t2_num_pages; i++) {
882 u32 ent_num = min_t(u32,
885 struct src_ent *entries = p_mngr->t2[i].p_virt;
886 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
889 for (j = 0; j < ent_num - 1; j++) {
890 val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
891 entries[j].next = cpu_to_be64(val);
894 if (i < p_mngr->t2_num_pages - 1)
895 val = (u64) p_mngr->t2[i + 1].p_phys;
898 entries[j].next = cpu_to_be64(val);
906 qed_cxt_src_t2_free(p_hwfn);
910 #define for_each_ilt_valid_client(pos, clients) \
911 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
912 if (!clients[pos].active) { \
916 /* Total number of ILT lines used by this PF */
917 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
922 for_each_ilt_valid_client(i, ilt_clients)
923 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
928 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
930 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
931 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
934 ilt_size = qed_cxt_ilt_shadow_size(p_cli);
936 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
937 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
940 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
941 p_dma->size, p_dma->p_virt,
943 p_dma->p_virt = NULL;
945 kfree(p_mngr->ilt_shadow);
948 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
949 struct qed_ilt_cli_blk *p_blk,
950 enum ilt_clients ilt_client,
951 u32 start_line_offset)
953 struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
954 u32 lines, line, sz_left, lines_to_skip = 0;
956 /* Special handling for RoCE that supports dynamic allocation */
957 if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) &&
958 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
961 lines_to_skip = p_blk->dynamic_line_cnt;
963 if (!p_blk->total_size)
966 sz_left = p_blk->total_size;
967 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
968 line = p_blk->start_line + start_line_offset -
969 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
971 for (; lines; lines--) {
976 size = min_t(u32, sz_left, p_blk->real_size_in_page);
977 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
978 size, &p_phys, GFP_KERNEL);
981 memset(p_virt, 0, size);
983 ilt_shadow[line].p_phys = p_phys;
984 ilt_shadow[line].p_virt = p_virt;
985 ilt_shadow[line].size = size;
987 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
988 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
989 line, (u64)p_phys, p_virt, size);
998 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
1000 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1001 struct qed_ilt_client_cfg *clients = p_mngr->clients;
1002 struct qed_ilt_cli_blk *p_blk;
1006 size = qed_cxt_ilt_shadow_size(clients);
1007 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
1009 if (!p_mngr->ilt_shadow) {
1011 goto ilt_shadow_fail;
1014 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1015 "Allocated 0x%x bytes for ilt shadow\n",
1016 (u32)(size * sizeof(struct qed_dma_mem)));
1018 for_each_ilt_valid_client(i, clients) {
1019 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1020 p_blk = &clients[i].pf_blks[j];
1021 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1023 goto ilt_shadow_fail;
1025 for (k = 0; k < p_mngr->vf_count; k++) {
1026 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1027 u32 lines = clients[i].vf_total_lines * k;
1029 p_blk = &clients[i].vf_blks[j];
1030 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
1032 goto ilt_shadow_fail;
1040 qed_ilt_shadow_free(p_hwfn);
1044 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
1046 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1049 for (type = 0; type < MAX_CONN_TYPES; type++) {
1050 kfree(p_mngr->acquired[type].cid_map);
1051 p_mngr->acquired[type].max_count = 0;
1052 p_mngr->acquired[type].start_cid = 0;
1056 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1058 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1062 for (type = 0; type < MAX_CONN_TYPES; type++) {
1063 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1069 size = DIV_ROUND_UP(cid_cnt,
1070 sizeof(unsigned long) * BITS_PER_BYTE) *
1071 sizeof(unsigned long);
1072 p_mngr->acquired[type].cid_map = kzalloc(size, GFP_KERNEL);
1073 if (!p_mngr->acquired[type].cid_map)
1076 p_mngr->acquired[type].max_count = cid_cnt;
1077 p_mngr->acquired[type].start_cid = start_cid;
1079 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1081 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1082 "Type %08x start: %08x count %08x\n",
1083 type, p_mngr->acquired[type].start_cid,
1084 p_mngr->acquired[type].max_count);
1085 start_cid += cid_cnt;
1091 qed_cid_map_free(p_hwfn);
1095 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1097 struct qed_ilt_client_cfg *clients;
1098 struct qed_cxt_mngr *p_mngr;
1101 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1105 /* Initialize ILT client registers */
1106 clients = p_mngr->clients;
1107 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1108 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1109 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1111 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1112 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1113 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1115 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1116 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1117 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1119 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1120 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1121 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1123 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1124 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1125 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1127 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1128 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1129 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1130 /* default ILT page size for all clients is 32K */
1131 for (i = 0; i < ILT_CLI_MAX; i++)
1132 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1134 /* Initialize task sizes */
1135 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1136 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1138 if (p_hwfn->cdev->p_iov_info)
1139 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1140 /* Initialize the dynamic ILT allocation mutex */
1141 mutex_init(&p_mngr->mutex);
1143 /* Set the cxt mangr pointer priori to further allocations */
1144 p_hwfn->p_cxt_mngr = p_mngr;
1149 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1153 /* Allocate the ILT shadow table */
1154 rc = qed_ilt_shadow_alloc(p_hwfn);
1156 goto tables_alloc_fail;
1158 /* Allocate the T2 table */
1159 rc = qed_cxt_src_t2_alloc(p_hwfn);
1161 goto tables_alloc_fail;
1163 /* Allocate and initialize the acquired cids bitmaps */
1164 rc = qed_cid_map_alloc(p_hwfn);
1166 goto tables_alloc_fail;
1171 qed_cxt_mngr_free(p_hwfn);
1175 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1177 if (!p_hwfn->p_cxt_mngr)
1180 qed_cid_map_free(p_hwfn);
1181 qed_cxt_src_t2_free(p_hwfn);
1182 qed_ilt_shadow_free(p_hwfn);
1183 kfree(p_hwfn->p_cxt_mngr);
1185 p_hwfn->p_cxt_mngr = NULL;
1188 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1190 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1193 /* Reset acquired cids */
1194 for (type = 0; type < MAX_CONN_TYPES; type++) {
1195 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1200 memset(p_mngr->acquired[type].cid_map, 0,
1201 DIV_ROUND_UP(cid_cnt,
1202 sizeof(unsigned long) * BITS_PER_BYTE) *
1203 sizeof(unsigned long));
1208 #define CDUC_CXT_SIZE_SHIFT \
1209 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1211 #define CDUC_CXT_SIZE_MASK \
1212 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1214 #define CDUC_BLOCK_WASTE_SHIFT \
1215 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1217 #define CDUC_BLOCK_WASTE_MASK \
1218 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1220 #define CDUC_NCIB_SHIFT \
1221 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1223 #define CDUC_NCIB_MASK \
1224 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1226 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1227 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1229 #define CDUT_TYPE0_CXT_SIZE_MASK \
1230 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1231 CDUT_TYPE0_CXT_SIZE_SHIFT)
1233 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1234 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1236 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1237 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1238 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1240 #define CDUT_TYPE0_NCIB_SHIFT \
1241 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1243 #define CDUT_TYPE0_NCIB_MASK \
1244 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1245 CDUT_TYPE0_NCIB_SHIFT)
1247 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1248 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1250 #define CDUT_TYPE1_CXT_SIZE_MASK \
1251 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1252 CDUT_TYPE1_CXT_SIZE_SHIFT)
1254 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1255 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1257 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1258 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1259 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1261 #define CDUT_TYPE1_NCIB_SHIFT \
1262 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1264 #define CDUT_TYPE1_NCIB_MASK \
1265 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1266 CDUT_TYPE1_NCIB_SHIFT)
1268 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1270 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1272 /* CDUC - connection configuration */
1273 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1274 cxt_size = CONN_CXT_SIZE(p_hwfn);
1275 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1276 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1278 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1279 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1280 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1281 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1283 /* CDUT - type-0 tasks configuration */
1284 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1285 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1286 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1287 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1289 /* cxt size and block-waste are multipes of 8 */
1291 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1292 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1293 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1294 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1296 /* CDUT - type-1 tasks configuration */
1297 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1298 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1299 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1301 /* cxt size and block-waste are multipes of 8 */
1303 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1304 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1305 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1306 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1310 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1311 #define CDU_SEG_REG_TYPE_MASK 0x1
1312 #define CDU_SEG_REG_OFFSET_SHIFT 0
1313 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1315 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1317 struct qed_ilt_client_cfg *p_cli;
1318 struct qed_tid_seg *p_seg;
1319 u32 cdu_seg_params, offset;
1322 static const u32 rt_type_offset_arr[] = {
1323 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1324 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1325 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1326 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1329 static const u32 rt_type_offset_fl_arr[] = {
1330 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1331 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1332 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1333 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1336 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1338 /* There are initializations only for CDUT during pf Phase */
1339 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1341 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1345 /* Note: start_line is already adjusted for the CDU
1346 * segment register granularity, so we just need to
1347 * divide. Adjustment is implicit as we assume ILT
1348 * Page size is larger than 32K!
1350 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1351 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1352 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1355 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1356 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1357 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1359 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1360 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1361 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1364 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1365 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1366 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1370 void qed_qm_init_pf(struct qed_hwfn *p_hwfn)
1372 struct qed_qm_pf_rt_init_params params;
1373 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1374 struct qed_qm_iids iids;
1376 memset(&iids, 0, sizeof(iids));
1377 qed_cxt_qm_iids(p_hwfn, &iids);
1379 memset(¶ms, 0, sizeof(params));
1380 params.port_id = p_hwfn->port_id;
1381 params.pf_id = p_hwfn->rel_pf_id;
1382 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1383 params.is_first_pf = p_hwfn->first_on_engine;
1384 params.num_pf_cids = iids.cids;
1385 params.num_vf_cids = iids.vf_cids;
1386 params.start_pq = qm_info->start_pq;
1387 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1388 params.num_vf_pqs = qm_info->num_vf_pqs;
1389 params.start_vport = qm_info->start_vport;
1390 params.num_vports = qm_info->num_vports;
1391 params.pf_wfq = qm_info->pf_wfq;
1392 params.pf_rl = qm_info->pf_rl;
1393 params.pq_params = qm_info->qm_pq_params;
1394 params.vport_params = qm_info->qm_vport_params;
1396 qed_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, ¶ms);
1400 static int qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1402 union qed_qm_pq_params pq_params;
1405 /* XCM pure-LB queue */
1406 memset(&pq_params, 0, sizeof(pq_params));
1407 pq_params.core.tc = LB_TC;
1408 pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1409 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1415 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1417 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1418 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1420 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1421 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1423 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1424 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1426 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1427 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1429 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1430 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1432 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1433 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1435 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1436 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1438 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1439 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1441 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1442 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1444 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1445 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1447 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1448 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1450 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1451 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1453 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1454 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1456 /* Connection types 6 & 7 are not in use, yet they must be configured
1457 * as the highest possible connection. Not configuring them means the
1458 * defaults will be used, and with a large number of cids a bug may
1459 * occur, if the defaults will be smaller than dq_pf_max_cid /
1462 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1463 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1465 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1466 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1469 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1471 struct qed_ilt_client_cfg *ilt_clients;
1474 ilt_clients = p_hwfn->p_cxt_mngr->clients;
1475 for_each_ilt_valid_client(i, ilt_clients) {
1476 STORE_RT_REG(p_hwfn,
1477 ilt_clients[i].first.reg,
1478 ilt_clients[i].first.val);
1479 STORE_RT_REG(p_hwfn,
1480 ilt_clients[i].last.reg, ilt_clients[i].last.val);
1481 STORE_RT_REG(p_hwfn,
1482 ilt_clients[i].p_size.reg,
1483 ilt_clients[i].p_size.val);
1487 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1489 struct qed_ilt_client_cfg *p_cli;
1492 /* For simplicty we set the 'block' to be an ILT page */
1493 if (p_hwfn->cdev->p_iov_info) {
1494 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1496 STORE_RT_REG(p_hwfn,
1497 PSWRQ2_REG_VF_BASE_RT_OFFSET,
1498 p_iov->first_vf_in_pf);
1499 STORE_RT_REG(p_hwfn,
1500 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1501 p_iov->first_vf_in_pf + p_iov->total_vfs);
1504 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1505 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1506 if (p_cli->active) {
1507 STORE_RT_REG(p_hwfn,
1508 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1510 STORE_RT_REG(p_hwfn,
1511 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1512 p_cli->pf_total_lines);
1513 STORE_RT_REG(p_hwfn,
1514 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1515 p_cli->vf_total_lines);
1518 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1519 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1520 if (p_cli->active) {
1521 STORE_RT_REG(p_hwfn,
1522 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1524 STORE_RT_REG(p_hwfn,
1525 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1526 p_cli->pf_total_lines);
1527 STORE_RT_REG(p_hwfn,
1528 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1529 p_cli->vf_total_lines);
1532 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1533 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1534 if (p_cli->active) {
1535 STORE_RT_REG(p_hwfn,
1536 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1537 STORE_RT_REG(p_hwfn,
1538 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1539 p_cli->pf_total_lines);
1540 STORE_RT_REG(p_hwfn,
1541 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1542 p_cli->vf_total_lines);
1546 /* ILT (PSWRQ2) PF */
1547 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1549 struct qed_ilt_client_cfg *clients;
1550 struct qed_cxt_mngr *p_mngr;
1551 struct qed_dma_mem *p_shdw;
1552 u32 line, rt_offst, i;
1554 qed_ilt_bounds_init(p_hwfn);
1555 qed_ilt_vf_bounds_init(p_hwfn);
1557 p_mngr = p_hwfn->p_cxt_mngr;
1558 p_shdw = p_mngr->ilt_shadow;
1559 clients = p_hwfn->p_cxt_mngr->clients;
1561 for_each_ilt_valid_client(i, clients) {
1562 /** Client's 1st val and RT array are absolute, ILT shadows'
1563 * lines are relative.
1565 line = clients[i].first.val - p_mngr->pf_start_line;
1566 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1567 clients[i].first.val * ILT_ENTRY_IN_REGS;
1569 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1570 line++, rt_offst += ILT_ENTRY_IN_REGS) {
1571 u64 ilt_hw_entry = 0;
1573 /** p_virt could be NULL incase of dynamic
1576 if (p_shdw[line].p_virt) {
1577 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1578 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1579 (p_shdw[line].p_phys >> 12));
1581 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1582 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1584 (u64)(p_shdw[line].p_phys >> 12));
1587 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1592 /* SRC (Searcher) PF */
1593 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1595 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1596 u32 rounded_conn_num, conn_num, conn_max;
1597 struct qed_src_iids src_iids;
1599 memset(&src_iids, 0, sizeof(src_iids));
1600 qed_cxt_src_iids(p_mngr, &src_iids);
1601 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1605 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1606 rounded_conn_num = roundup_pow_of_two(conn_max);
1608 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1609 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1610 ilog2(rounded_conn_num));
1612 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1613 p_hwfn->p_cxt_mngr->first_free);
1614 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1615 p_hwfn->p_cxt_mngr->last_free);
1619 #define TM_CFG_NUM_IDS_SHIFT 0
1620 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1621 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1622 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1623 #define TM_CFG_PARENT_PF_SHIFT 25
1624 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1626 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1627 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1629 #define TM_CFG_TID_OFFSET_SHIFT 30
1630 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1631 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1632 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1634 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1636 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1637 u32 active_seg_mask = 0, tm_offset, rt_reg;
1638 struct qed_tm_iids tm_iids;
1642 memset(&tm_iids, 0, sizeof(tm_iids));
1643 qed_cxt_tm_iids(p_mngr, &tm_iids);
1645 /* @@@TBD No pre-scan for now */
1647 /* Note: We assume consecutive VFs for a PF */
1648 for (i = 0; i < p_mngr->vf_count; i++) {
1650 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1651 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1652 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1653 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1654 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1655 (sizeof(cfg_word) / sizeof(u32)) *
1656 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1657 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1661 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1662 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1663 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */
1664 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1666 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1667 (sizeof(cfg_word) / sizeof(u32)) *
1668 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1669 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1672 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1673 tm_iids.pf_cids ? 0x1 : 0x0);
1675 /* @@@TBD how to enable the scan for the VFs */
1677 tm_offset = tm_iids.per_vf_cids;
1679 /* Note: We assume consecutive VFs for a PF */
1680 for (i = 0; i < p_mngr->vf_count; i++) {
1682 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1683 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1684 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1685 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1686 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1688 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1689 (sizeof(cfg_word) / sizeof(u32)) *
1690 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1692 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1695 tm_offset = tm_iids.pf_cids;
1696 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1698 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1699 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1700 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1701 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1702 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1704 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1705 (sizeof(cfg_word) / sizeof(u32)) *
1706 (NUM_OF_VFS(p_hwfn->cdev) +
1707 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1709 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1710 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1712 tm_offset += tm_iids.pf_tids[i];
1715 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE)
1716 active_seg_mask = 0;
1718 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1720 /* @@@TBD how to enable the scan for the VFs */
1723 static void qed_prs_init_common(struct qed_hwfn *p_hwfn)
1725 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) &&
1726 p_hwfn->pf_params.fcoe_pf_params.is_target)
1727 STORE_RT_REG(p_hwfn,
1728 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
1731 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn)
1733 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1734 struct qed_conn_type_cfg *p_fcoe;
1735 struct qed_tid_seg *p_tid;
1737 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1739 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1740 if (!p_fcoe->cid_count)
1743 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG];
1744 if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
1745 STORE_RT_REG_AGG(p_hwfn,
1746 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
1749 STORE_RT_REG_AGG(p_hwfn,
1750 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1755 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1757 qed_cdu_init_common(p_hwfn);
1758 qed_prs_init_common(p_hwfn);
1761 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
1763 qed_qm_init_pf(p_hwfn);
1764 qed_cm_init_pf(p_hwfn);
1765 qed_dq_init_pf(p_hwfn);
1766 qed_cdu_init_pf(p_hwfn);
1767 qed_ilt_init_pf(p_hwfn);
1768 qed_src_init_pf(p_hwfn);
1769 qed_tm_init_pf(p_hwfn);
1770 qed_prs_init_pf(p_hwfn);
1773 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1774 enum protocol_type type, u32 *p_cid)
1776 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1779 if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1780 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1784 rel_cid = find_first_zero_bit(p_mngr->acquired[type].cid_map,
1785 p_mngr->acquired[type].max_count);
1787 if (rel_cid >= p_mngr->acquired[type].max_count) {
1788 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1792 __set_bit(rel_cid, p_mngr->acquired[type].cid_map);
1794 *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1799 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1800 u32 cid, enum protocol_type *p_type)
1802 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1803 struct qed_cid_acquired_map *p_map;
1804 enum protocol_type p;
1807 /* Iterate over protocols and find matching cid range */
1808 for (p = 0; p < MAX_CONN_TYPES; p++) {
1809 p_map = &p_mngr->acquired[p];
1811 if (!p_map->cid_map)
1813 if (cid >= p_map->start_cid &&
1814 cid < p_map->start_cid + p_map->max_count)
1819 if (p == MAX_CONN_TYPES) {
1820 DP_NOTICE(p_hwfn, "Invalid CID %d", cid);
1824 rel_cid = cid - p_map->start_cid;
1825 if (!test_bit(rel_cid, p_map->cid_map)) {
1826 DP_NOTICE(p_hwfn, "CID %d not acquired", cid);
1832 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
1834 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1835 enum protocol_type type;
1839 /* Test acquired and find matching per-protocol map */
1840 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, &type);
1845 rel_cid = cid - p_mngr->acquired[type].start_cid;
1846 __clear_bit(rel_cid, p_mngr->acquired[type].cid_map);
1849 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
1851 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1852 u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1853 enum protocol_type type;
1856 /* Test acquired and find matching per-protocol map */
1857 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1862 /* set the protocl type */
1863 p_info->type = type;
1865 /* compute context virtual pointer */
1866 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1868 conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1869 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1870 line = p_info->iid / cxts_per_p;
1872 /* Make sure context is allocated (dynamic allocation) */
1873 if (!p_mngr->ilt_shadow[line].p_virt)
1876 p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
1877 p_info->iid % cxts_per_p * conn_cxt_size;
1879 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
1880 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1881 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
1886 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
1887 struct qed_rdma_pf_params *p_params)
1889 u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs;
1890 enum protocol_type proto;
1892 num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs);
1893 num_tasks = num_mrs; /* each mr uses a single task id */
1894 num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
1896 switch (p_hwfn->hw_info.personality) {
1897 case QED_PCI_ETH_ROCE:
1898 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
1899 num_cons = num_qps * 2; /* each QP requires two connections */
1900 proto = PROTOCOLID_ROCE;
1906 if (num_cons && num_tasks) {
1907 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
1909 /* Deliberatly passing ROCE for tasks id. This is because
1910 * iWARP / RoCE share the task id.
1912 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
1913 QED_CXT_ROCE_TID_SEG, 1,
1915 qed_cxt_set_srq_count(p_hwfn, num_srqs);
1917 DP_INFO(p_hwfn->cdev,
1918 "RDMA personality used without setting params!\n");
1922 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
1924 /* Set the number of required CORE connections */
1925 u32 core_cids = 1; /* SPQ */
1927 if (p_hwfn->using_ll2)
1929 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1931 switch (p_hwfn->hw_info.personality) {
1932 case QED_PCI_ETH_ROCE:
1934 qed_rdma_set_pf_params(p_hwfn,
1936 pf_params.rdma_pf_params);
1937 /* no need for break since RoCE coexist with Ethernet */
1941 struct qed_eth_pf_params *p_params =
1942 &p_hwfn->pf_params.eth_pf_params;
1944 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1945 p_params->num_cons, 1);
1950 struct qed_fcoe_pf_params *p_params;
1952 p_params = &p_hwfn->pf_params.fcoe_pf_params;
1954 if (p_params->num_cons && p_params->num_tasks) {
1955 qed_cxt_set_proto_cid_count(p_hwfn,
1960 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
1961 QED_CXT_FCOE_TID_SEG, 0,
1962 p_params->num_tasks, true);
1964 DP_INFO(p_hwfn->cdev,
1965 "Fcoe personality used without setting params!\n");
1971 struct qed_iscsi_pf_params *p_params;
1973 p_params = &p_hwfn->pf_params.iscsi_pf_params;
1975 if (p_params->num_cons && p_params->num_tasks) {
1976 qed_cxt_set_proto_cid_count(p_hwfn,
1981 qed_cxt_set_proto_tid_count(p_hwfn,
1983 QED_CXT_ISCSI_TID_SEG,
1985 p_params->num_tasks,
1988 DP_INFO(p_hwfn->cdev,
1989 "Iscsi personality used without setting params!\n");
2000 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
2001 struct qed_tid_mem *p_info)
2003 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2004 u32 proto, seg, total_lines, i, shadow_line;
2005 struct qed_ilt_client_cfg *p_cli;
2006 struct qed_ilt_cli_blk *p_fl_seg;
2007 struct qed_tid_seg *p_seg_info;
2009 /* Verify the personality */
2010 switch (p_hwfn->hw_info.personality) {
2012 proto = PROTOCOLID_FCOE;
2013 seg = QED_CXT_FCOE_TID_SEG;
2016 proto = PROTOCOLID_ISCSI;
2017 seg = QED_CXT_ISCSI_TID_SEG;
2023 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2027 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2028 if (!p_seg_info->has_fl_mem)
2031 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2032 total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2033 p_fl_seg->real_size_in_page);
2035 for (i = 0; i < total_lines; i++) {
2036 shadow_line = i + p_fl_seg->start_line -
2037 p_hwfn->p_cxt_mngr->pf_start_line;
2038 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2040 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2041 p_fl_seg->real_size_in_page;
2042 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2043 p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2049 /* This function is very RoCE oriented, if another protocol in the future
2050 * will want this feature we'll need to modify the function to be more generic
2053 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
2054 enum qed_cxt_elem_type elem_type, u32 iid)
2056 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2057 struct qed_ilt_client_cfg *p_cli;
2058 struct qed_ilt_cli_blk *p_blk;
2059 struct qed_ptt *p_ptt;
2065 switch (elem_type) {
2067 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2068 elem_size = CONN_CXT_SIZE(p_hwfn);
2069 p_blk = &p_cli->pf_blks[CDUC_BLK];
2072 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2073 elem_size = SRQ_CXT_SIZE;
2074 p_blk = &p_cli->pf_blks[SRQ_BLK];
2077 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2078 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2079 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2082 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2086 /* Calculate line in ilt */
2087 hw_p_size = p_cli->p_size.val;
2088 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2089 line = p_blk->start_line + (iid / elems_per_p);
2090 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2092 /* If line is already allocated, do nothing, otherwise allocate it and
2093 * write it to the PSWRQ2 registers.
2094 * This section can be run in parallel from different contexts and thus
2095 * a mutex protection is needed.
2098 mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
2100 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2103 p_ptt = qed_ptt_acquire(p_hwfn);
2106 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2111 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2112 p_blk->real_size_in_page,
2113 &p_phys, GFP_KERNEL);
2118 memset(p_virt, 0, p_blk->real_size_in_page);
2120 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2121 * to compensate for a HW bug, but it is configured even if DIF is not
2122 * enabled. This is harmless and allows us to avoid a dedicated API. We
2123 * configure the field for all of the contexts on the newly allocated
2126 if (elem_type == QED_ELEM_TASK) {
2128 u8 *elem_start = (u8 *)p_virt;
2129 union type1_task_context *elem;
2131 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2132 elem = (union type1_task_context *)elem_start;
2133 SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2134 TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
2135 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2139 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2140 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2141 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2142 p_blk->real_size_in_page;
2144 /* compute absolute offset */
2145 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2146 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2149 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2150 SET_FIELD(ilt_hw_entry,
2152 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2154 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2155 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2156 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2158 if (elem_type == QED_ELEM_CXT) {
2159 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2162 /* Update the relevant register in the parser */
2163 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2164 last_cid_allocated - 1);
2166 if (!p_hwfn->b_rdma_enabled_in_prs) {
2167 /* Enable RoCE search */
2168 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2169 p_hwfn->b_rdma_enabled_in_prs = true;
2174 qed_ptt_release(p_hwfn, p_ptt);
2176 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2181 /* This function is very RoCE oriented, if another protocol in the future
2182 * will want this feature we'll need to modify the function to be more generic
2185 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2186 enum qed_cxt_elem_type elem_type,
2187 u32 start_iid, u32 count)
2189 u32 start_line, end_line, shadow_start_line, shadow_end_line;
2190 u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2191 struct qed_ilt_client_cfg *p_cli;
2192 struct qed_ilt_cli_blk *p_blk;
2193 u32 end_iid = start_iid + count;
2194 struct qed_ptt *p_ptt;
2195 u64 ilt_hw_entry = 0;
2198 switch (elem_type) {
2200 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2201 elem_size = CONN_CXT_SIZE(p_hwfn);
2202 p_blk = &p_cli->pf_blks[CDUC_BLK];
2205 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2206 elem_size = SRQ_CXT_SIZE;
2207 p_blk = &p_cli->pf_blks[SRQ_BLK];
2210 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2211 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2212 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2215 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2219 /* Calculate line in ilt */
2220 hw_p_size = p_cli->p_size.val;
2221 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2222 start_line = p_blk->start_line + (start_iid / elems_per_p);
2223 end_line = p_blk->start_line + (end_iid / elems_per_p);
2224 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2227 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2228 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2230 p_ptt = qed_ptt_acquire(p_hwfn);
2233 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2237 for (i = shadow_start_line; i < shadow_end_line; i++) {
2238 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2241 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2242 p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2243 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2244 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2246 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2247 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2248 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2250 /* compute absolute offset */
2251 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2252 ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2255 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2258 qed_dmae_host2grc(p_hwfn, p_ptt,
2259 (u64) (uintptr_t) &ilt_hw_entry,
2261 sizeof(ilt_hw_entry) / sizeof(u32),
2265 qed_ptt_release(p_hwfn, p_ptt);
2270 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2275 /* Free Connection CXT */
2276 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2277 qed_cxt_get_proto_cid_start(p_hwfn,
2279 qed_cxt_get_proto_cid_count(p_hwfn,
2286 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2287 qed_cxt_get_proto_tid_count(p_hwfn, proto));
2292 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2293 qed_cxt_get_srq_count(p_hwfn));
2298 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2299 u32 tid, u8 ctx_type, void **pp_task_ctx)
2301 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2302 struct qed_ilt_client_cfg *p_cli;
2303 struct qed_tid_seg *p_seg_info;
2304 struct qed_ilt_cli_blk *p_seg;
2305 u32 num_tids_per_block;
2306 u32 tid_size, ilt_idx;
2310 /* Verify the personality */
2311 switch (p_hwfn->hw_info.personality) {
2313 proto = PROTOCOLID_FCOE;
2314 seg = QED_CXT_FCOE_TID_SEG;
2317 proto = PROTOCOLID_ISCSI;
2318 seg = QED_CXT_ISCSI_TID_SEG;
2324 p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2328 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2330 if (ctx_type == QED_CTX_WORKING_MEM) {
2331 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2332 } else if (ctx_type == QED_CTX_FL_MEM) {
2333 if (!p_seg_info->has_fl_mem)
2335 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2339 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2340 tid_size = p_mngr->task_type_size[p_seg_info->type];
2341 num_tids_per_block = p_seg->real_size_in_page / tid_size;
2343 if (total_lines < tid / num_tids_per_block)
2346 ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2347 p_mngr->pf_start_line;
2348 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2349 (tid % num_tids_per_block) * tid_size;