drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_roce.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 /* API common to all protocols */
  73 enum BAR_ID {
  74         BAR_ID_0,       /* used for GRC */
  75         BAR_ID_1        /* Used for doorbells */
  76 };
  77
  78 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  79                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  80 {
  81         u32 bar_reg = (bar_id == BAR_ID_0 ?
  82                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  83         u32 val;
  84
  85         if (IS_VF(p_hwfn->cdev))
  86                 return 1 << 17;
  87
  88         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  89         if (val)
  90                 return 1 << (val + 15);
  91
  92         /* Old MFW initialized above registered only conditionally */
  93         if (p_hwfn->cdev->num_hwfns > 1) {
  94                 DP_INFO(p_hwfn,
  95                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  96                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  97         } else {
  98                 DP_INFO(p_hwfn,
  99                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 100                         return 512 * 1024;
 101         }
 102 }
 103
 104 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
 105 {
 106         u32 i;
 107
 108         cdev->dp_level = dp_level;
 109         cdev->dp_module = dp_module;
 110         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 111                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 112
 113                 p_hwfn->dp_level = dp_level;
 114                 p_hwfn->dp_module = dp_module;
 115         }
 116 }
 117
 118 void qed_init_struct(struct qed_dev *cdev)
 119 {
 120         u8 i;
 121
 122         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 123                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 124
 125                 p_hwfn->cdev = cdev;
 126                 p_hwfn->my_id = i;
 127                 p_hwfn->b_active = false;
 128
 129                 mutex_init(&p_hwfn->dmae_info.mutex);
 130         }
 131
 132         /* hwfn 0 is always active */
 133         cdev->hwfns[0].b_active = true;
 134
 135         /* set the default cache alignment to 128 */
 136         cdev->cache_shift = 7;
 137 }
 138
 139 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 140 {
 141         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 142
 143         kfree(qm_info->qm_pq_params);
 144         qm_info->qm_pq_params = NULL;
 145         kfree(qm_info->qm_vport_params);
 146         qm_info->qm_vport_params = NULL;
 147         kfree(qm_info->qm_port_params);
 148         qm_info->qm_port_params = NULL;
 149         kfree(qm_info->wfq_data);
 150         qm_info->wfq_data = NULL;
 151 }
 152
 153 void qed_resc_free(struct qed_dev *cdev)
 154 {
 155         int i;
 156
 157         if (IS_VF(cdev))
 158                 return;
 159
 160         kfree(cdev->fw_data);
 161         cdev->fw_data = NULL;
 162
 163         kfree(cdev->reset_stats);
 164         cdev->reset_stats = NULL;
 165
 166         for_each_hwfn(cdev, i) {
 167                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 168
 169                 qed_cxt_mngr_free(p_hwfn);
 170                 qed_qm_info_free(p_hwfn);
 171                 qed_spq_free(p_hwfn);
 172                 qed_eq_free(p_hwfn);
 173                 qed_consq_free(p_hwfn);
 174                 qed_int_free(p_hwfn);
 175 #ifdef CONFIG_QED_LL2
 176                 qed_ll2_free(p_hwfn);
 177 #endif
 178                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 179                         qed_fcoe_free(p_hwfn);
 180
 181                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 182                         qed_iscsi_free(p_hwfn);
 183                         qed_ooo_free(p_hwfn);
 184                 }
 185                 qed_iov_free(p_hwfn);
 186                 qed_dmae_info_free(p_hwfn);
 187                 qed_dcbx_info_free(p_hwfn);
 188         }
 189 }
 190
 191 /******************** QM initialization *******************/
 192 #define ACTIVE_TCS_BMAP 0x9f
 193 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 194
 195 /* determines the physical queue flags for a given PF. */
 196 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 197 {
 198         u32 flags;
 199
 200         /* common flags */
 201         flags = PQ_FLAGS_LB;
 202
 203         /* feature flags */
 204         if (IS_QED_SRIOV(p_hwfn->cdev))
 205                 flags |= PQ_FLAGS_VFS;
 206
 207         /* protocol flags */
 208         switch (p_hwfn->hw_info.personality) {
 209         case QED_PCI_ETH:
 210                 flags |= PQ_FLAGS_MCOS;
 211                 break;
 212         case QED_PCI_FCOE:
 213                 flags |= PQ_FLAGS_OFLD;
 214                 break;
 215         case QED_PCI_ISCSI:
 216                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 217                 break;
 218         case QED_PCI_ETH_ROCE:
 219                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 220                 break;
 221         default:
 222                 DP_ERR(p_hwfn,
 223                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 224                 return 0;
 225         }
 226
 227         return flags;
 228 }
 229
 230 /* Getters for resource amounts necessary for qm initialization */
 231 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 232 {
 233         return p_hwfn->hw_info.num_hw_tc;
 234 }
 235
 236 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 237 {
 238         return IS_QED_SRIOV(p_hwfn->cdev) ?
 239                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 240 }
 241
 242 #define NUM_DEFAULT_RLS 1
 243
 244 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 245 {
 246         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 247
 248         /* num RLs can't exceed resource amount of rls or vports */
 249         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 250                                  RESC_NUM(p_hwfn, QED_VPORT));
 251
 252         /* Make sure after we reserve there's something left */
 253         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 254                 return 0;
 255
 256         /* subtract rls necessary for VFs and one default one for the PF */
 257         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 258
 259         return num_pf_rls;
 260 }
 261
 262 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 263 {
 264         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 265
 266         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 267         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 268                qed_init_qm_get_num_pf_rls(p_hwfn) +
 269                (!!(PQ_FLAGS_VFS & pq_flags)) *
 270                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 271 }
 272
 273 /* calc amount of PQs according to the requested flags */
 274 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 275 {
 276         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 277
 278         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 279                qed_init_qm_get_num_pf_rls(p_hwfn) +
 280                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 281                qed_init_qm_get_num_tcs(p_hwfn) +
 282                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 283                (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
 284                (!!(PQ_FLAGS_LLT & pq_flags)) +
 285                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 286 }
 287
 288 /* initialize the top level QM params */
 289 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 290 {
 291         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 292         bool four_port;
 293
 294         /* pq and vport bases for this PF */
 295         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 296         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 297
 298         /* rate limiting and weighted fair queueing are always enabled */
 299         qm_info->vport_rl_en = 1;
 300         qm_info->vport_wfq_en = 1;
 301
 302         /* TC config is different for AH 4 port */
 303         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 304
 305         /* in AH 4 port we have fewer TCs per port */
 306         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 307                                                      NUM_OF_PHYS_TCS;
 308
 309         /* unless MFW indicated otherwise, ooo_tc == 3 for
 310          * AH 4-port and 4 otherwise.
 311          */
 312         if (!qm_info->ooo_tc)
 313                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 314                                               DCBX_TCP_OOO_TC;
 315 }
 316
 317 /* initialize qm vport params */
 318 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 319 {
 320         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 321         u8 i;
 322
 323         /* all vports participate in weighted fair queueing */
 324         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 325                 qm_info->qm_vport_params[i].vport_wfq = 1;
 326 }
 327
 328 /* initialize qm port params */
 329 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 330 {
 331         /* Initialize qm port parameters */
 332         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 333
 334         /* indicate how ooo and high pri traffic is dealt with */
 335         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 336                           ACTIVE_TCS_BMAP_4PORT_K2 :
 337                           ACTIVE_TCS_BMAP;
 338
 339         for (i = 0; i < num_ports; i++) {
 340                 struct init_qm_port_params *p_qm_port =
 341                     &p_hwfn->qm_info.qm_port_params[i];
 342
 343                 p_qm_port->active = 1;
 344                 p_qm_port->active_phys_tcs = active_phys_tcs;
 345                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 346                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 347         }
 348 }
 349
 350 /* Reset the params which must be reset for qm init. QM init may be called as
 351  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 352  * params may be affected by the init but would simply recalculate to the same
 353  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 354  * affected as these amounts stay the same.
 355  */
 356 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 357 {
 358         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 359
 360         qm_info->num_pqs = 0;
 361         qm_info->num_vports = 0;
 362         qm_info->num_pf_rls = 0;
 363         qm_info->num_vf_pqs = 0;
 364         qm_info->first_vf_pq = 0;
 365         qm_info->first_mcos_pq = 0;
 366         qm_info->first_rl_pq = 0;
 367 }
 368
 369 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 370 {
 371         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 372
 373         qm_info->num_vports++;
 374
 375         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 376                 DP_ERR(p_hwfn,
 377                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 378                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 379 }
 380
 381 /* initialize a single pq and manage qm_info resources accounting.
 382  * The pq_init_flags param determines whether the PQ is rate limited
 383  * (for VF or PF) and whether a new vport is allocated to the pq or not
 384  * (i.e. vport will be shared).
 385  */
 386
 387 /* flags for pq init */
 388 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 389 #define PQ_INIT_PF_RL           (1 << 1)
 390 #define PQ_INIT_VF_RL           (1 << 2)
 391
 392 /* defines for pq init */
 393 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 394 #define PQ_INIT_DEFAULT_TC              0
 395 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 396
 397 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 398                            struct qed_qm_info *qm_info,
 399                            u8 tc, u32 pq_init_flags)
 400 {
 401         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 402
 403         if (pq_idx > max_pq)
 404                 DP_ERR(p_hwfn,
 405                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 406
 407         /* init pq params */
 408         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 409             qm_info->num_vports;
 410         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 411         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 412         qm_info->qm_pq_params[pq_idx].rl_valid =
 413             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 414
 415         /* qm params accounting */
 416         qm_info->num_pqs++;
 417         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 418                 qm_info->num_vports++;
 419
 420         if (pq_init_flags & PQ_INIT_PF_RL)
 421                 qm_info->num_pf_rls++;
 422
 423         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 424                 DP_ERR(p_hwfn,
 425                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 426                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 427
 428         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 429                 DP_ERR(p_hwfn,
 430                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 431                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 432 }
 433
 434 /* get pq index according to PQ_FLAGS */
 435 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 436                                            u32 pq_flags)
 437 {
 438         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 439
 440         /* Can't have multiple flags set here */
 441         if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
 442                 goto err;
 443
 444         switch (pq_flags) {
 445         case PQ_FLAGS_RLS:
 446                 return &qm_info->first_rl_pq;
 447         case PQ_FLAGS_MCOS:
 448                 return &qm_info->first_mcos_pq;
 449         case PQ_FLAGS_LB:
 450                 return &qm_info->pure_lb_pq;
 451         case PQ_FLAGS_OOO:
 452                 return &qm_info->ooo_pq;
 453         case PQ_FLAGS_ACK:
 454                 return &qm_info->pure_ack_pq;
 455         case PQ_FLAGS_OFLD:
 456                 return &qm_info->offload_pq;
 457         case PQ_FLAGS_LLT:
 458                 return &qm_info->low_latency_pq;
 459         case PQ_FLAGS_VFS:
 460                 return &qm_info->first_vf_pq;
 461         default:
 462                 goto err;
 463         }
 464
 465 err:
 466         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 467         return NULL;
 468 }
 469
 470 /* save pq index in qm info */
 471 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 472                                 u32 pq_flags, u16 pq_val)
 473 {
 474         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 475
 476         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 477 }
 478
 479 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 480 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 481 {
 482         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 483
 484         return *base_pq_idx + CM_TX_PQ_BASE;
 485 }
 486
 487 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 488 {
 489         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 490
 491         if (tc > max_tc)
 492                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 493
 494         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 495 }
 496
 497 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 498 {
 499         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 500
 501         if (vf > max_vf)
 502                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 503
 504         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 505 }
 506
 507 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
 508 {
 509         u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
 510
 511         if (rl > max_rl)
 512                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 513
 514         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 515 }
 516
 517 /* Functions for creating specific types of pqs */
 518 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 519 {
 520         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 521
 522         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 523                 return;
 524
 525         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 526         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 527 }
 528
 529 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 530 {
 531         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 532
 533         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 534                 return;
 535
 536         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 537         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 538 }
 539
 540 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 541 {
 542         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 543
 544         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 545                 return;
 546
 547         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 548         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 549 }
 550
 551 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 552 {
 553         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 554
 555         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 556                 return;
 557
 558         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 559         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 560 }
 561
 562 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 563 {
 564         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 565
 566         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 567                 return;
 568
 569         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 570         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 571 }
 572
 573 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 574 {
 575         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 576         u8 tc_idx;
 577
 578         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 579                 return;
 580
 581         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 582         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 583                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 584 }
 585
 586 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 587 {
 588         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 589         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 590
 591         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 592                 return;
 593
 594         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 595         qm_info->num_vf_pqs = num_vfs;
 596         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 597                 qed_init_qm_pq(p_hwfn,
 598                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 599 }
 600
 601 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 602 {
 603         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 604         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 605
 606         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 607                 return;
 608
 609         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 610         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 611                 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
 612 }
 613
 614 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 615 {
 616         /* rate limited pqs, must come first (FW assumption) */
 617         qed_init_qm_rl_pqs(p_hwfn);
 618
 619         /* pqs for multi cos */
 620         qed_init_qm_mcos_pqs(p_hwfn);
 621
 622         /* pure loopback pq */
 623         qed_init_qm_lb_pq(p_hwfn);
 624
 625         /* out of order pq */
 626         qed_init_qm_ooo_pq(p_hwfn);
 627
 628         /* pure ack pq */
 629         qed_init_qm_pure_ack_pq(p_hwfn);
 630
 631         /* pq for offloaded protocol */
 632         qed_init_qm_offload_pq(p_hwfn);
 633
 634         /* low latency pq */
 635         qed_init_qm_low_latency_pq(p_hwfn);
 636
 637         /* done sharing vports */
 638         qed_init_qm_advance_vport(p_hwfn);
 639
 640         /* pqs for vfs */
 641         qed_init_qm_vf_pqs(p_hwfn);
 642 }
 643
 644 /* compare values of getters against resources amounts */
 645 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 646 {
 647         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 648                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 649                 return -EINVAL;
 650         }
 651
 652         if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
 653                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 654                 return -EINVAL;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 661 {
 662         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 663         struct init_qm_vport_params *vport;
 664         struct init_qm_port_params *port;
 665         struct init_qm_pq_params *pq;
 666         int i, tc;
 667
 668         /* top level params */
 669         DP_VERBOSE(p_hwfn,
 670                    NETIF_MSG_HW,
 671                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 672                    qm_info->start_pq,
 673                    qm_info->start_vport,
 674                    qm_info->pure_lb_pq,
 675                    qm_info->offload_pq, qm_info->pure_ack_pq);
 676         DP_VERBOSE(p_hwfn,
 677                    NETIF_MSG_HW,
 678                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 679                    qm_info->ooo_pq,
 680                    qm_info->first_vf_pq,
 681                    qm_info->num_pqs,
 682                    qm_info->num_vf_pqs,
 683                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 684         DP_VERBOSE(p_hwfn,
 685                    NETIF_MSG_HW,
 686                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 687                    qm_info->pf_rl_en,
 688                    qm_info->pf_wfq_en,
 689                    qm_info->vport_rl_en,
 690                    qm_info->vport_wfq_en,
 691                    qm_info->pf_wfq,
 692                    qm_info->pf_rl,
 693                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 694
 695         /* port table */
 696         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 697                 port = &(qm_info->qm_port_params[i]);
 698                 DP_VERBOSE(p_hwfn,
 699                            NETIF_MSG_HW,
 700                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 701                            i,
 702                            port->active,
 703                            port->active_phys_tcs,
 704                            port->num_pbf_cmd_lines,
 705                            port->num_btb_blocks, port->reserved);
 706         }
 707
 708         /* vport table */
 709         for (i = 0; i < qm_info->num_vports; i++) {
 710                 vport = &(qm_info->qm_vport_params[i]);
 711                 DP_VERBOSE(p_hwfn,
 712                            NETIF_MSG_HW,
 713                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 714                            qm_info->start_vport + i,
 715                            vport->vport_rl, vport->vport_wfq);
 716                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 717                         DP_VERBOSE(p_hwfn,
 718                                    NETIF_MSG_HW,
 719                                    "%d ", vport->first_tx_pq_id[tc]);
 720                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 721         }
 722
 723         /* pq table */
 724         for (i = 0; i < qm_info->num_pqs; i++) {
 725                 pq = &(qm_info->qm_pq_params[i]);
 726                 DP_VERBOSE(p_hwfn,
 727                            NETIF_MSG_HW,
 728                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 729                            qm_info->start_pq + i,
 730                            pq->vport_id,
 731                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 732         }
 733 }
 734
 735 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 736 {
 737         /* reset params required for init run */
 738         qed_init_qm_reset_params(p_hwfn);
 739
 740         /* init QM top level params */
 741         qed_init_qm_params(p_hwfn);
 742
 743         /* init QM port params */
 744         qed_init_qm_port_params(p_hwfn);
 745
 746         /* init QM vport params */
 747         qed_init_qm_vport_params(p_hwfn);
 748
 749         /* init QM physical queue params */
 750         qed_init_qm_pq_params(p_hwfn);
 751
 752         /* display all that init */
 753         qed_dp_init_qm_params(p_hwfn);
 754 }
 755
 756 /* This function reconfigures the QM pf on the fly.
 757  * For this purpose we:
 758  * 1. reconfigure the QM database
 759  * 2. set new values to runtime arrat
 760  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 761  * 4. activate init tool in QM_PF stage
 762  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 763  */
 764 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 765 {
 766         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 767         bool b_rc;
 768         int rc;
 769
 770         /* initialize qed's qm data structure */
 771         qed_init_qm_info(p_hwfn);
 772
 773         /* stop PF's qm queues */
 774         spin_lock_bh(&qm_lock);
 775         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 776                                     qm_info->start_pq, qm_info->num_pqs);
 777         spin_unlock_bh(&qm_lock);
 778         if (!b_rc)
 779                 return -EINVAL;
 780
 781         /* clear the QM_PF runtime phase leftovers from previous init */
 782         qed_init_clear_rt_data(p_hwfn);
 783
 784         /* prepare QM portion of runtime array */
 785         qed_qm_init_pf(p_hwfn, p_ptt);
 786
 787         /* activate init tool on runtime array */
 788         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 789                           p_hwfn->hw_info.hw_mode);
 790         if (rc)
 791                 return rc;
 792
 793         /* start PF's qm queues */
 794         spin_lock_bh(&qm_lock);
 795         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 796                                     qm_info->start_pq, qm_info->num_pqs);
 797         spin_unlock_bh(&qm_lock);
 798         if (!b_rc)
 799                 return -EINVAL;
 800
 801         return 0;
 802 }
 803
 804 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 805 {
 806         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 807         int rc;
 808
 809         rc = qed_init_qm_sanity(p_hwfn);
 810         if (rc)
 811                 goto alloc_err;
 812
 813         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 814                                         qed_init_qm_get_num_pqs(p_hwfn),
 815                                         GFP_KERNEL);
 816         if (!qm_info->qm_pq_params)
 817                 goto alloc_err;
 818
 819         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 820                                            qed_init_qm_get_num_vports(p_hwfn),
 821                                            GFP_KERNEL);
 822         if (!qm_info->qm_vport_params)
 823                 goto alloc_err;
 824
 825         qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
 826                                           p_hwfn->cdev->num_ports_in_engine,
 827                                           GFP_KERNEL);
 828         if (!qm_info->qm_port_params)
 829                 goto alloc_err;
 830
 831         qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
 832                                     qed_init_qm_get_num_vports(p_hwfn),
 833                                     GFP_KERNEL);
 834         if (!qm_info->wfq_data)
 835                 goto alloc_err;
 836
 837         return 0;
 838
 839 alloc_err:
 840         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 841         qed_qm_info_free(p_hwfn);
 842         return -ENOMEM;
 843 }
 844
 845 int qed_resc_alloc(struct qed_dev *cdev)
 846 {
 847         u32 rdma_tasks, excess_tasks;
 848         u32 line_count;
 849         int i, rc = 0;
 850
 851         if (IS_VF(cdev))
 852                 return rc;
 853
 854         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 855         if (!cdev->fw_data)
 856                 return -ENOMEM;
 857
 858         for_each_hwfn(cdev, i) {
 859                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 860                 u32 n_eqes, num_cons;
 861
 862                 /* First allocate the context manager structure */
 863                 rc = qed_cxt_mngr_alloc(p_hwfn);
 864                 if (rc)
 865                         goto alloc_err;
 866
 867                 /* Set the HW cid/tid numbers (in the contest manager)
 868                  * Must be done prior to any further computations.
 869                  */
 870                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 871                 if (rc)
 872                         goto alloc_err;
 873
 874                 rc = qed_alloc_qm_data(p_hwfn);
 875                 if (rc)
 876                         goto alloc_err;
 877
 878                 /* init qm info */
 879                 qed_init_qm_info(p_hwfn);
 880
 881                 /* Compute the ILT client partition */
 882                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 883                 if (rc) {
 884                         DP_NOTICE(p_hwfn,
 885                                   "too many ILT lines; re-computing with less lines\n");
 886                         /* In case there are not enough ILT lines we reduce the
 887                          * number of RDMA tasks and re-compute.
 888                          */
 889                         excess_tasks =
 890                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 891                         if (!excess_tasks)
 892                                 goto alloc_err;
 893
 894                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 895                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 896                         if (rc)
 897                                 goto alloc_err;
 898
 899                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 900                         if (rc) {
 901                                 DP_ERR(p_hwfn,
 902                                        "failed ILT compute. Requested too many lines: %u\n",
 903                                        line_count);
 904
 905                                 goto alloc_err;
 906                         }
 907                 }
 908
 909                 /* CID map / ILT shadow table / T2
 910                  * The talbes sizes are determined by the computations above
 911                  */
 912                 rc = qed_cxt_tables_alloc(p_hwfn);
 913                 if (rc)
 914                         goto alloc_err;
 915
 916                 /* SPQ, must follow ILT because initializes SPQ context */
 917                 rc = qed_spq_alloc(p_hwfn);
 918                 if (rc)
 919                         goto alloc_err;
 920
 921                 /* SP status block allocation */
 922                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 923                                                          RESERVED_PTT_DPC);
 924
 925                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 926                 if (rc)
 927                         goto alloc_err;
 928
 929                 rc = qed_iov_alloc(p_hwfn);
 930                 if (rc)
 931                         goto alloc_err;
 932
 933                 /* EQ */
 934                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 935                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 936                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 937                                                                PROTOCOLID_ROCE,
 938                                                                NULL) * 2;
 939                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 940                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 941                         num_cons =
 942                             qed_cxt_get_proto_cid_count(p_hwfn,
 943                                                         PROTOCOLID_ISCSI,
 944                                                         NULL);
 945                         n_eqes += 2 * num_cons;
 946                 }
 947
 948                 if (n_eqes > 0xFFFF) {
 949                         DP_ERR(p_hwfn,
 950                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 951                                n_eqes, 0xFFFF);
 952                         goto alloc_no_mem;
 953                 }
 954
 955                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 956                 if (rc)
 957                         goto alloc_err;
 958
 959                 rc = qed_consq_alloc(p_hwfn);
 960                 if (rc)
 961                         goto alloc_err;
 962
 963 #ifdef CONFIG_QED_LL2
 964                 if (p_hwfn->using_ll2) {
 965                         rc = qed_ll2_alloc(p_hwfn);
 966                         if (rc)
 967                                 goto alloc_err;
 968                 }
 969 #endif
 970
 971                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
 972                         rc = qed_fcoe_alloc(p_hwfn);
 973                         if (rc)
 974                                 goto alloc_err;
 975                 }
 976
 977                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 978                         rc = qed_iscsi_alloc(p_hwfn);
 979                         if (rc)
 980                                 goto alloc_err;
 981                         rc = qed_ooo_alloc(p_hwfn);
 982                         if (rc)
 983                                 goto alloc_err;
 984                 }
 985
 986                 /* DMA info initialization */
 987                 rc = qed_dmae_info_alloc(p_hwfn);
 988                 if (rc)
 989                         goto alloc_err;
 990
 991                 /* DCBX initialization */
 992                 rc = qed_dcbx_info_alloc(p_hwfn);
 993                 if (rc)
 994                         goto alloc_err;
 995         }
 996
 997         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 998         if (!cdev->reset_stats)
 999                 goto alloc_no_mem;
1000
1001         return 0;
1002
1003 alloc_no_mem:
1004         rc = -ENOMEM;
1005 alloc_err:
1006         qed_resc_free(cdev);
1007         return rc;
1008 }
1009
1010 void qed_resc_setup(struct qed_dev *cdev)
1011 {
1012         int i;
1013
1014         if (IS_VF(cdev))
1015                 return;
1016
1017         for_each_hwfn(cdev, i) {
1018                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1019
1020                 qed_cxt_mngr_setup(p_hwfn);
1021                 qed_spq_setup(p_hwfn);
1022                 qed_eq_setup(p_hwfn);
1023                 qed_consq_setup(p_hwfn);
1024
1025                 /* Read shadow of current MFW mailbox */
1026                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1027                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1028                        p_hwfn->mcp_info->mfw_mb_cur,
1029                        p_hwfn->mcp_info->mfw_mb_length);
1030
1031                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1032
1033                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1034 #ifdef CONFIG_QED_LL2
1035                 if (p_hwfn->using_ll2)
1036                         qed_ll2_setup(p_hwfn);
1037 #endif
1038                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1039                         qed_fcoe_setup(p_hwfn);
1040
1041                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1042                         qed_iscsi_setup(p_hwfn);
1043                         qed_ooo_setup(p_hwfn);
1044                 }
1045         }
1046 }
1047
1048 #define FINAL_CLEANUP_POLL_CNT          (100)
1049 #define FINAL_CLEANUP_POLL_TIME         (10)
1050 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1051                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1052 {
1053         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1054         int rc = -EBUSY;
1055
1056         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1057                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1058
1059         if (is_vf)
1060                 id += 0x10;
1061
1062         command |= X_FINAL_CLEANUP_AGG_INT <<
1063                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1064         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1065         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1066         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1067
1068         /* Make sure notification is not set before initiating final cleanup */
1069         if (REG_RD(p_hwfn, addr)) {
1070                 DP_NOTICE(p_hwfn,
1071                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1072                 REG_WR(p_hwfn, addr, 0);
1073         }
1074
1075         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1076                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1077                    id, command);
1078
1079         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1080
1081         /* Poll until completion */
1082         while (!REG_RD(p_hwfn, addr) && count--)
1083                 msleep(FINAL_CLEANUP_POLL_TIME);
1084
1085         if (REG_RD(p_hwfn, addr))
1086                 rc = 0;
1087         else
1088                 DP_NOTICE(p_hwfn,
1089                           "Failed to receive FW final cleanup notification\n");
1090
1091         /* Cleanup afterwards */
1092         REG_WR(p_hwfn, addr, 0);
1093
1094         return rc;
1095 }
1096
1097 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1098 {
1099         int hw_mode = 0;
1100
1101         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1102                 hw_mode |= 1 << MODE_BB;
1103         } else if (QED_IS_AH(p_hwfn->cdev)) {
1104                 hw_mode |= 1 << MODE_K2;
1105         } else {
1106                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1107                           p_hwfn->cdev->type);
1108                 return -EINVAL;
1109         }
1110
1111         switch (p_hwfn->cdev->num_ports_in_engine) {
1112         case 1:
1113                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1114                 break;
1115         case 2:
1116                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1117                 break;
1118         case 4:
1119                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1120                 break;
1121         default:
1122                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1123                           p_hwfn->cdev->num_ports_in_engine);
1124                 return -EINVAL;
1125         }
1126
1127         switch (p_hwfn->cdev->mf_mode) {
1128         case QED_MF_DEFAULT:
1129         case QED_MF_NPAR:
1130                 hw_mode |= 1 << MODE_MF_SI;
1131                 break;
1132         case QED_MF_OVLAN:
1133                 hw_mode |= 1 << MODE_MF_SD;
1134                 break;
1135         default:
1136                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1137                 hw_mode |= 1 << MODE_MF_SI;
1138         }
1139
1140         hw_mode |= 1 << MODE_ASIC;
1141
1142         if (p_hwfn->cdev->num_hwfns > 1)
1143                 hw_mode |= 1 << MODE_100G;
1144
1145         p_hwfn->hw_info.hw_mode = hw_mode;
1146
1147         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1148                    "Configuring function for hw_mode: 0x%08x\n",
1149                    p_hwfn->hw_info.hw_mode);
1150
1151         return 0;
1152 }
1153
1154 /* Init run time data for all PFs on an engine. */
1155 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1156 {
1157         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1158         int i, sb_id;
1159
1160         for_each_hwfn(cdev, i) {
1161                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1162                 struct qed_igu_info *p_igu_info;
1163                 struct qed_igu_block *p_block;
1164                 struct cau_sb_entry sb_entry;
1165
1166                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1167
1168                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
1169                      sb_id++) {
1170                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1171                         if (!p_block->is_pf)
1172                                 continue;
1173
1174                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1175                                               p_block->function_id, 0, 0);
1176                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1177                 }
1178         }
1179 }
1180
1181 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1182                                      struct qed_ptt *p_ptt)
1183 {
1184         u32 val, wr_mbs, cache_line_size;
1185
1186         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1187         switch (val) {
1188         case 0:
1189                 wr_mbs = 128;
1190                 break;
1191         case 1:
1192                 wr_mbs = 256;
1193                 break;
1194         case 2:
1195                 wr_mbs = 512;
1196                 break;
1197         default:
1198                 DP_INFO(p_hwfn,
1199                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1200                         val);
1201                 return;
1202         }
1203
1204         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1205         switch (cache_line_size) {
1206         case 32:
1207                 val = 0;
1208                 break;
1209         case 64:
1210                 val = 1;
1211                 break;
1212         case 128:
1213                 val = 2;
1214                 break;
1215         case 256:
1216                 val = 3;
1217                 break;
1218         default:
1219                 DP_INFO(p_hwfn,
1220                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1221                         cache_line_size);
1222         }
1223
1224         if (L1_CACHE_BYTES > wr_mbs)
1225                 DP_INFO(p_hwfn,
1226                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1227                         L1_CACHE_BYTES, wr_mbs);
1228
1229         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1230 }
1231
1232 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1233                               struct qed_ptt *p_ptt, int hw_mode)
1234 {
1235         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1236         struct qed_qm_common_rt_init_params params;
1237         struct qed_dev *cdev = p_hwfn->cdev;
1238         u8 vf_id, max_num_vfs;
1239         u16 num_pfs, pf_id;
1240         u32 concrete_fid;
1241         int rc = 0;
1242
1243         qed_init_cau_rt_data(cdev);
1244
1245         /* Program GTT windows */
1246         qed_gtt_init(p_hwfn);
1247
1248         if (p_hwfn->mcp_info) {
1249                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1250                         qm_info->pf_rl_en = 1;
1251                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1252                         qm_info->pf_wfq_en = 1;
1253         }
1254
1255         memset(&params, 0, sizeof(params));
1256         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1257         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1258         params.pf_rl_en = qm_info->pf_rl_en;
1259         params.pf_wfq_en = qm_info->pf_wfq_en;
1260         params.vport_rl_en = qm_info->vport_rl_en;
1261         params.vport_wfq_en = qm_info->vport_wfq_en;
1262         params.port_params = qm_info->qm_port_params;
1263
1264         qed_qm_common_rt_init(p_hwfn, &params);
1265
1266         qed_cxt_hw_init_common(p_hwfn);
1267
1268         qed_init_cache_line_size(p_hwfn, p_ptt);
1269
1270         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1271         if (rc)
1272                 return rc;
1273
1274         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1275         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1276
1277         if (QED_IS_BB(p_hwfn->cdev)) {
1278                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1279                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1280                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1281                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1282                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1283                 }
1284                 /* pretend to original PF */
1285                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1286         }
1287
1288         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1289         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1290                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1291                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1292                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1293                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1294                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1295                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1296         }
1297         /* pretend to original PF */
1298         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1299
1300         return rc;
1301 }
1302
1303 static int
1304 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1305                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1306 {
1307         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1308         u32 min_dpis;
1309         u32 n_wids;
1310
1311         /* Calculate DPI size */
1312         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1313         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1314         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1315         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1316         dpi_count = pwm_region_size / dpi_page_size;
1317
1318         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1319         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1320
1321         p_hwfn->dpi_size = dpi_page_size;
1322         p_hwfn->dpi_count = dpi_count;
1323
1324         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1325
1326         if (dpi_count < min_dpis)
1327                 return -EINVAL;
1328
1329         return 0;
1330 }
1331
1332 enum QED_ROCE_EDPM_MODE {
1333         QED_ROCE_EDPM_MODE_ENABLE = 0,
1334         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1335         QED_ROCE_EDPM_MODE_DISABLE = 2,
1336 };
1337
1338 static int
1339 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1340 {
1341         u32 pwm_regsize, norm_regsize;
1342         u32 non_pwm_conn, min_addr_reg1;
1343         u32 db_bar_size, n_cpus = 1;
1344         u32 roce_edpm_mode;
1345         u32 pf_dems_shift;
1346         int rc = 0;
1347         u8 cond;
1348
1349         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1350         if (p_hwfn->cdev->num_hwfns > 1)
1351                 db_bar_size /= 2;
1352
1353         /* Calculate doorbell regions */
1354         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1355                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1356                                                    NULL) +
1357                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1358                                                    NULL);
1359         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1360         min_addr_reg1 = norm_regsize / 4096;
1361         pwm_regsize = db_bar_size - norm_regsize;
1362
1363         /* Check that the normal and PWM sizes are valid */
1364         if (db_bar_size < norm_regsize) {
1365                 DP_ERR(p_hwfn->cdev,
1366                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1367                        db_bar_size, norm_regsize);
1368                 return -EINVAL;
1369         }
1370
1371         if (pwm_regsize < QED_MIN_PWM_REGION) {
1372                 DP_ERR(p_hwfn->cdev,
1373                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1374                        pwm_regsize,
1375                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1376                 return -EINVAL;
1377         }
1378
1379         /* Calculate number of DPIs */
1380         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1381         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1382             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1383                 /* Either EDPM is mandatory, or we are attempting to allocate a
1384                  * WID per CPU.
1385                  */
1386                 n_cpus = num_present_cpus();
1387                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1388         }
1389
1390         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1391                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1392         if (cond || p_hwfn->dcbx_no_edpm) {
1393                 /* Either EDPM is disabled from user configuration, or it is
1394                  * disabled via DCBx, or it is not mandatory and we failed to
1395                  * allocated a WID per CPU.
1396                  */
1397                 n_cpus = 1;
1398                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1399
1400                 if (cond)
1401                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1402         }
1403
1404         p_hwfn->wid_count = (u16) n_cpus;
1405
1406         DP_INFO(p_hwfn,
1407                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1408                 norm_regsize,
1409                 pwm_regsize,
1410                 p_hwfn->dpi_size,
1411                 p_hwfn->dpi_count,
1412                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1413                 "disabled" : "enabled");
1414
1415         if (rc) {
1416                 DP_ERR(p_hwfn,
1417                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1418                        p_hwfn->dpi_count,
1419                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1420                 return -EINVAL;
1421         }
1422
1423         p_hwfn->dpi_start_offset = norm_regsize;
1424
1425         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1426         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1427         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1428         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1429
1430         return 0;
1431 }
1432
1433 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1434                             struct qed_ptt *p_ptt, int hw_mode)
1435 {
1436         return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
1437                             p_hwfn->port_id, hw_mode);
1438 }
1439
1440 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1441                           struct qed_ptt *p_ptt,
1442                           struct qed_tunnel_info *p_tunn,
1443                           int hw_mode,
1444                           bool b_hw_start,
1445                           enum qed_int_mode int_mode,
1446                           bool allow_npar_tx_switch)
1447 {
1448         u8 rel_pf_id = p_hwfn->rel_pf_id;
1449         int rc = 0;
1450
1451         if (p_hwfn->mcp_info) {
1452                 struct qed_mcp_function_info *p_info;
1453
1454                 p_info = &p_hwfn->mcp_info->func_info;
1455                 if (p_info->bandwidth_min)
1456                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1457
1458                 /* Update rate limit once we'll actually have a link */
1459                 p_hwfn->qm_info.pf_rl = 100000;
1460         }
1461
1462         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1463
1464         qed_int_igu_init_rt(p_hwfn);
1465
1466         /* Set VLAN in NIG if needed */
1467         if (hw_mode & BIT(MODE_MF_SD)) {
1468                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1469                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1470                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1471                              p_hwfn->hw_info.ovlan);
1472         }
1473
1474         /* Enable classification by MAC if needed */
1475         if (hw_mode & BIT(MODE_MF_SI)) {
1476                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1477                            "Configuring TAGMAC_CLS_TYPE\n");
1478                 STORE_RT_REG(p_hwfn,
1479                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1480         }
1481
1482         /* Protocl Configuration  */
1483         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1484                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1485         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1486                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1487         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1488
1489         /* Cleanup chip from previous driver if such remains exist */
1490         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1491         if (rc)
1492                 return rc;
1493
1494         /* PF Init sequence */
1495         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1496         if (rc)
1497                 return rc;
1498
1499         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1500         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1501         if (rc)
1502                 return rc;
1503
1504         /* Pure runtime initializations - directly to the HW  */
1505         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1506
1507         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1508         if (rc)
1509                 return rc;
1510
1511         if (b_hw_start) {
1512                 /* enable interrupts */
1513                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1514
1515                 /* send function start command */
1516                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1517                                      p_hwfn->cdev->mf_mode,
1518                                      allow_npar_tx_switch);
1519                 if (rc) {
1520                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1521                         return rc;
1522                 }
1523                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1524                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1525                         qed_wr(p_hwfn, p_ptt,
1526                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1527                                0x100);
1528                 }
1529         }
1530         return rc;
1531 }
1532
1533 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1534                                struct qed_ptt *p_ptt,
1535                                u8 enable)
1536 {
1537         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1538
1539         /* Change PF in PXP */
1540         qed_wr(p_hwfn, p_ptt,
1541                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1542
1543         /* wait until value is set - try for 1 second every 50us */
1544         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1545                 val = qed_rd(p_hwfn, p_ptt,
1546                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1547                 if (val == set_val)
1548                         break;
1549
1550                 usleep_range(50, 60);
1551         }
1552
1553         if (val != set_val) {
1554                 DP_NOTICE(p_hwfn,
1555                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1556                 return -EAGAIN;
1557         }
1558
1559         return 0;
1560 }
1561
1562 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1563                                 struct qed_ptt *p_main_ptt)
1564 {
1565         /* Read shadow of current MFW mailbox */
1566         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1567         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1568                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1569 }
1570
1571 static void
1572 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1573                          struct qed_drv_load_params *p_drv_load)
1574 {
1575         memset(p_load_req, 0, sizeof(*p_load_req));
1576
1577         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1578                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1579         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1580         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1581         p_load_req->override_force_load = p_drv_load->override_force_load;
1582 }
1583
1584 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1585                         struct qed_hw_init_params *p_params)
1586 {
1587         if (p_params->p_tunn) {
1588                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1589                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1590         }
1591
1592         p_hwfn->b_int_enabled = 1;
1593
1594         return 0;
1595 }
1596
1597 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1598 {
1599         struct qed_load_req_params load_req_params;
1600         u32 load_code, param, drv_mb_param;
1601         bool b_default_mtu = true;
1602         struct qed_hwfn *p_hwfn;
1603         int rc = 0, mfw_rc, i;
1604
1605         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1606                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1607                 return -EINVAL;
1608         }
1609
1610         if (IS_PF(cdev)) {
1611                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1612                 if (rc)
1613                         return rc;
1614         }
1615
1616         for_each_hwfn(cdev, i) {
1617                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1618
1619                 /* If management didn't provide a default, set one of our own */
1620                 if (!p_hwfn->hw_info.mtu) {
1621                         p_hwfn->hw_info.mtu = 1500;
1622                         b_default_mtu = false;
1623                 }
1624
1625                 if (IS_VF(cdev)) {
1626                         qed_vf_start(p_hwfn, p_params);
1627                         continue;
1628                 }
1629
1630                 /* Enable DMAE in PXP */
1631                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1632
1633                 rc = qed_calc_hw_mode(p_hwfn);
1634                 if (rc)
1635                         return rc;
1636
1637                 qed_fill_load_req_params(&load_req_params,
1638                                          p_params->p_drv_load_params);
1639                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1640                                       &load_req_params);
1641                 if (rc) {
1642                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1643                         return rc;
1644                 }
1645
1646                 load_code = load_req_params.load_code;
1647                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1648                            "Load request was sent. Load code: 0x%x\n",
1649                            load_code);
1650
1651                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1652
1653                 p_hwfn->first_on_engine = (load_code ==
1654                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1655
1656                 switch (load_code) {
1657                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1658                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1659                                                 p_hwfn->hw_info.hw_mode);
1660                         if (rc)
1661                                 break;
1662                 /* Fall into */
1663                 case FW_MSG_CODE_DRV_LOAD_PORT:
1664                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1665                                               p_hwfn->hw_info.hw_mode);
1666                         if (rc)
1667                                 break;
1668
1669                 /* Fall into */
1670                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1671                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1672                                             p_params->p_tunn,
1673                                             p_hwfn->hw_info.hw_mode,
1674                                             p_params->b_hw_start,
1675                                             p_params->int_mode,
1676                                             p_params->allow_npar_tx_switch);
1677                         break;
1678                 default:
1679                         DP_NOTICE(p_hwfn,
1680                                   "Unexpected load code [0x%08x]", load_code);
1681                         rc = -EINVAL;
1682                         break;
1683                 }
1684
1685                 if (rc)
1686                         DP_NOTICE(p_hwfn,
1687                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1688                                    load_code, rc);
1689
1690                 /* ACK mfw regardless of success or failure of initialization */
1691                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1692                                      DRV_MSG_CODE_LOAD_DONE,
1693                                      0, &load_code, &param);
1694                 if (rc)
1695                         return rc;
1696                 if (mfw_rc) {
1697                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1698                         return mfw_rc;
1699                 }
1700
1701                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1702                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1703                         DP_NOTICE(p_hwfn,
1704                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1705
1706                 /* send DCBX attention request command */
1707                 DP_VERBOSE(p_hwfn,
1708                            QED_MSG_DCB,
1709                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1710                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1711                                      DRV_MSG_CODE_SET_DCBX,
1712                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1713                                      &load_code, &param);
1714                 if (mfw_rc) {
1715                         DP_NOTICE(p_hwfn,
1716                                   "Failed to send DCBX attention request\n");
1717                         return mfw_rc;
1718                 }
1719
1720                 p_hwfn->hw_init_done = true;
1721         }
1722
1723         if (IS_PF(cdev)) {
1724                 p_hwfn = QED_LEADING_HWFN(cdev);
1725                 drv_mb_param = STORM_FW_VERSION;
1726                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1727                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1728                                  drv_mb_param, &load_code, &param);
1729                 if (rc)
1730                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1731
1732                 if (!b_default_mtu) {
1733                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1734                                                    p_hwfn->hw_info.mtu);
1735                         if (rc)
1736                                 DP_INFO(p_hwfn,
1737                                         "Failed to update default mtu\n");
1738                 }
1739
1740                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1741                                                     p_hwfn->p_main_ptt,
1742                                                   QED_OV_DRIVER_STATE_DISABLED);
1743                 if (rc)
1744                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1745
1746                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1747                                                QED_OV_ESWITCH_VEB);
1748                 if (rc)
1749                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1750         }
1751
1752         return 0;
1753 }
1754
1755 #define QED_HW_STOP_RETRY_LIMIT (10)
1756 static void qed_hw_timers_stop(struct qed_dev *cdev,
1757                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1758 {
1759         int i;
1760
1761         /* close timers */
1762         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1763         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1764
1765         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1766                 if ((!qed_rd(p_hwfn, p_ptt,
1767                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1768                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1769                         break;
1770
1771                 /* Dependent on number of connection/tasks, possibly
1772                  * 1ms sleep is required between polls
1773                  */
1774                 usleep_range(1000, 2000);
1775         }
1776
1777         if (i < QED_HW_STOP_RETRY_LIMIT)
1778                 return;
1779
1780         DP_NOTICE(p_hwfn,
1781                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1782                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1783                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1784 }
1785
1786 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1787 {
1788         int j;
1789
1790         for_each_hwfn(cdev, j) {
1791                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1792                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1793
1794                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1795         }
1796 }
1797
1798 int qed_hw_stop(struct qed_dev *cdev)
1799 {
1800         struct qed_hwfn *p_hwfn;
1801         struct qed_ptt *p_ptt;
1802         int rc, rc2 = 0;
1803         int j;
1804
1805         for_each_hwfn(cdev, j) {
1806                 p_hwfn = &cdev->hwfns[j];
1807                 p_ptt = p_hwfn->p_main_ptt;
1808
1809                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1810
1811                 if (IS_VF(cdev)) {
1812                         qed_vf_pf_int_cleanup(p_hwfn);
1813                         rc = qed_vf_pf_reset(p_hwfn);
1814                         if (rc) {
1815                                 DP_NOTICE(p_hwfn,
1816                                           "qed_vf_pf_reset failed. rc = %d.\n",
1817                                           rc);
1818                                 rc2 = -EINVAL;
1819                         }
1820                         continue;
1821                 }
1822
1823                 /* mark the hw as uninitialized... */
1824                 p_hwfn->hw_init_done = false;
1825
1826                 /* Send unload command to MCP */
1827                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1828                 if (rc) {
1829                         DP_NOTICE(p_hwfn,
1830                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1831                                   rc);
1832                         rc2 = -EINVAL;
1833                 }
1834
1835                 qed_slowpath_irq_sync(p_hwfn);
1836
1837                 /* After this point no MFW attentions are expected, e.g. prevent
1838                  * race between pf stop and dcbx pf update.
1839                  */
1840                 rc = qed_sp_pf_stop(p_hwfn);
1841                 if (rc) {
1842                         DP_NOTICE(p_hwfn,
1843                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1844                                   rc);
1845                         rc2 = -EINVAL;
1846                 }
1847
1848                 qed_wr(p_hwfn, p_ptt,
1849                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1850
1851                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1852                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1853                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1854                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1855                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1856
1857                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1858
1859                 /* Disable Attention Generation */
1860                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1861
1862                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1863                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1864
1865                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1866
1867                 /* Need to wait 1ms to guarantee SBs are cleared */
1868                 usleep_range(1000, 2000);
1869
1870                 /* Disable PF in HW blocks */
1871                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1872                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1873
1874                 qed_mcp_unload_done(p_hwfn, p_ptt);
1875                 if (rc) {
1876                         DP_NOTICE(p_hwfn,
1877                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1878                                   rc);
1879                         rc2 = -EINVAL;
1880                 }
1881         }
1882
1883         if (IS_PF(cdev)) {
1884                 p_hwfn = QED_LEADING_HWFN(cdev);
1885                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1886
1887                 /* Disable DMAE in PXP - in CMT, this should only be done for
1888                  * first hw-function, and only after all transactions have
1889                  * stopped for all active hw-functions.
1890                  */
1891                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1892                 if (rc) {
1893                         DP_NOTICE(p_hwfn,
1894                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1895                         rc2 = -EINVAL;
1896                 }
1897         }
1898
1899         return rc2;
1900 }
1901
1902 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1903 {
1904         int j;
1905
1906         for_each_hwfn(cdev, j) {
1907                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1908                 struct qed_ptt *p_ptt;
1909
1910                 if (IS_VF(cdev)) {
1911                         qed_vf_pf_int_cleanup(p_hwfn);
1912                         continue;
1913                 }
1914                 p_ptt = qed_ptt_acquire(p_hwfn);
1915                 if (!p_ptt)
1916                         return -EAGAIN;
1917
1918                 DP_VERBOSE(p_hwfn,
1919                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1920
1921                 qed_wr(p_hwfn, p_ptt,
1922                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1923
1924                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1925                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1926                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1927                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1928                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1929
1930                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1931
1932                 /* Need to wait 1ms to guarantee SBs are cleared */
1933                 usleep_range(1000, 2000);
1934                 qed_ptt_release(p_hwfn, p_ptt);
1935         }
1936
1937         return 0;
1938 }
1939
1940 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1941 {
1942         struct qed_ptt *p_ptt;
1943
1944         if (IS_VF(p_hwfn->cdev))
1945                 return 0;
1946
1947         p_ptt = qed_ptt_acquire(p_hwfn);
1948         if (!p_ptt)
1949                 return -EAGAIN;
1950
1951         /* Re-open incoming traffic */
1952         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1953         qed_ptt_release(p_hwfn, p_ptt);
1954
1955         return 0;
1956 }
1957
1958 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1959 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1960 {
1961         qed_ptt_pool_free(p_hwfn);
1962         kfree(p_hwfn->hw_info.p_igu_info);
1963         p_hwfn->hw_info.p_igu_info = NULL;
1964 }
1965
1966 /* Setup bar access */
1967 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1968 {
1969         /* clear indirect access */
1970         if (QED_IS_AH(p_hwfn->cdev)) {
1971                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1972                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1973                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1974                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1975                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1976                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1977                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1978                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1979         } else {
1980                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1981                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
1982                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1983                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
1984                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1985                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
1986                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1987                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
1988         }
1989
1990         /* Clean Previous errors if such exist */
1991         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1992                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1993
1994         /* enable internal target-read */
1995         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1996                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1997 }
1998
1999 static void get_function_id(struct qed_hwfn *p_hwfn)
2000 {
2001         /* ME Register */
2002         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2003                                                   PXP_PF_ME_OPAQUE_ADDR);
2004
2005         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2006
2007         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2008         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2009                                       PXP_CONCRETE_FID_PFID);
2010         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2011                                     PXP_CONCRETE_FID_PORT);
2012
2013         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2014                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2015                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2016 }
2017
2018 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2019 {
2020         u32 *feat_num = p_hwfn->hw_info.feat_num;
2021         struct qed_sb_cnt_info sb_cnt_info;
2022         u32 non_l2_sbs = 0;
2023
2024         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2025             p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
2026                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2027                  * the status blocks equally between L2 / RoCE but with
2028                  * consideration as to how many l2 queues / cnqs we have.
2029                  */
2030                 feat_num[QED_RDMA_CNQ] =
2031                         min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 2,
2032                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2033
2034                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2035         }
2036
2037         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
2038             p_hwfn->hw_info.personality == QED_PCI_ETH) {
2039                 /* Start by allocating VF queues, then PF's */
2040                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2041                 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2042                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2043                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2044                                                 sb_cnt_info.sb_iov_cnt);
2045                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2046                                                 RESC_NUM(p_hwfn, QED_SB) -
2047                                                 non_l2_sbs,
2048                                                 RESC_NUM(p_hwfn,
2049                                                          QED_L2_QUEUE) -
2050                                                 FEAT_NUM(p_hwfn,
2051                                                          QED_VF_L2_QUE));
2052         }
2053
2054         if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2055                 feat_num[QED_ISCSI_CQ] = min_t(u32, RESC_NUM(p_hwfn, QED_SB),
2056                                                RESC_NUM(p_hwfn,
2057                                                         QED_CMDQS_CQS));
2058         DP_VERBOSE(p_hwfn,
2059                    NETIF_MSG_PROBE,
2060                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d ISCSI_CQ=%d #SBS=%d\n",
2061                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2062                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2063                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2064                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2065                    RESC_NUM(p_hwfn, QED_SB));
2066 }
2067
2068 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2069 {
2070         switch (res_id) {
2071         case QED_L2_QUEUE:
2072                 return "L2_QUEUE";
2073         case QED_VPORT:
2074                 return "VPORT";
2075         case QED_RSS_ENG:
2076                 return "RSS_ENG";
2077         case QED_PQ:
2078                 return "PQ";
2079         case QED_RL:
2080                 return "RL";
2081         case QED_MAC:
2082                 return "MAC";
2083         case QED_VLAN:
2084                 return "VLAN";
2085         case QED_RDMA_CNQ_RAM:
2086                 return "RDMA_CNQ_RAM";
2087         case QED_ILT:
2088                 return "ILT";
2089         case QED_LL2_QUEUE:
2090                 return "LL2_QUEUE";
2091         case QED_CMDQS_CQS:
2092                 return "CMDQS_CQS";
2093         case QED_RDMA_STATS_QUEUE:
2094                 return "RDMA_STATS_QUEUE";
2095         case QED_BDQ:
2096                 return "BDQ";
2097         case QED_SB:
2098                 return "SB";
2099         default:
2100                 return "UNKNOWN_RESOURCE";
2101         }
2102 }
2103
2104 static int
2105 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2106                             struct qed_ptt *p_ptt,
2107                             enum qed_resources res_id,
2108                             u32 resc_max_val, u32 *p_mcp_resp)
2109 {
2110         int rc;
2111
2112         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2113                                       resc_max_val, p_mcp_resp);
2114         if (rc) {
2115                 DP_NOTICE(p_hwfn,
2116                           "MFW response failure for a max value setting of resource %d [%s]\n",
2117                           res_id, qed_hw_get_resc_name(res_id));
2118                 return rc;
2119         }
2120
2121         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2122                 DP_INFO(p_hwfn,
2123                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2124                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2125
2126         return 0;
2127 }
2128
2129 static int
2130 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2131 {
2132         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2133         u32 resc_max_val, mcp_resp;
2134         u8 res_id;
2135         int rc;
2136
2137         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2138                 switch (res_id) {
2139                 case QED_LL2_QUEUE:
2140                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2141                         break;
2142                 case QED_RDMA_CNQ_RAM:
2143                         /* No need for a case for QED_CMDQS_CQS since
2144                          * CNQ/CMDQS are the same resource.
2145                          */
2146                         resc_max_val = NUM_OF_CMDQS_CQS;
2147                         break;
2148                 case QED_RDMA_STATS_QUEUE:
2149                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2150                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2151                         break;
2152                 case QED_BDQ:
2153                         resc_max_val = BDQ_NUM_RESOURCES;
2154                         break;
2155                 default:
2156                         continue;
2157                 }
2158
2159                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2160                                                  resc_max_val, &mcp_resp);
2161                 if (rc)
2162                         return rc;
2163
2164                 /* There's no point to continue to the next resource if the
2165                  * command is not supported by the MFW.
2166                  * We do continue if the command is supported but the resource
2167                  * is unknown to the MFW. Such a resource will be later
2168                  * configured with the default allocation values.
2169                  */
2170                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2171                         return -EINVAL;
2172         }
2173
2174         return 0;
2175 }
2176
2177 static
2178 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2179                          enum qed_resources res_id,
2180                          u32 *p_resc_num, u32 *p_resc_start)
2181 {
2182         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2183         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2184         struct qed_sb_cnt_info sb_cnt_info;
2185
2186         switch (res_id) {
2187         case QED_L2_QUEUE:
2188                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2189                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2190                 break;
2191         case QED_VPORT:
2192                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2193                                MAX_NUM_VPORTS_BB) / num_funcs;
2194                 break;
2195         case QED_RSS_ENG:
2196                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2197                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2198                 break;
2199         case QED_PQ:
2200                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2201                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2202                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2203                 break;
2204         case QED_RL:
2205                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2206                 break;
2207         case QED_MAC:
2208         case QED_VLAN:
2209                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2210                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2211                 break;
2212         case QED_ILT:
2213                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2214                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2215                 break;
2216         case QED_LL2_QUEUE:
2217                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2218                 break;
2219         case QED_RDMA_CNQ_RAM:
2220         case QED_CMDQS_CQS:
2221                 /* CNQ/CMDQS are the same resource */
2222                 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2223                 break;
2224         case QED_RDMA_STATS_QUEUE:
2225                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2226                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2227                 break;
2228         case QED_BDQ:
2229                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2230                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2231                         *p_resc_num = 0;
2232                 else
2233                         *p_resc_num = 1;
2234                 break;
2235         case QED_SB:
2236                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2237                 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2238                 *p_resc_num = sb_cnt_info.sb_cnt;
2239                 break;
2240         default:
2241                 return -EINVAL;
2242         }
2243
2244         switch (res_id) {
2245         case QED_BDQ:
2246                 if (!*p_resc_num)
2247                         *p_resc_start = 0;
2248                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2249                         *p_resc_start = p_hwfn->port_id;
2250                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2251                         *p_resc_start = p_hwfn->port_id;
2252                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2253                         *p_resc_start = p_hwfn->port_id + 2;
2254                 break;
2255         default:
2256                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2257                 break;
2258         }
2259
2260         return 0;
2261 }
2262
2263 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2264                                   enum qed_resources res_id)
2265 {
2266         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2267         u32 mcp_resp, *p_resc_num, *p_resc_start;
2268         int rc;
2269
2270         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2271         p_resc_start = &RESC_START(p_hwfn, res_id);
2272
2273         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2274                                   &dflt_resc_start);
2275         if (rc) {
2276                 DP_ERR(p_hwfn,
2277                        "Failed to get default amount for resource %d [%s]\n",
2278                        res_id, qed_hw_get_resc_name(res_id));
2279                 return rc;
2280         }
2281
2282         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2283                                    &mcp_resp, p_resc_num, p_resc_start);
2284         if (rc) {
2285                 DP_NOTICE(p_hwfn,
2286                           "MFW response failure for an allocation request for resource %d [%s]\n",
2287                           res_id, qed_hw_get_resc_name(res_id));
2288                 return rc;
2289         }
2290
2291         /* Default driver values are applied in the following cases:
2292          * - The resource allocation MB command is not supported by the MFW
2293          * - There is an internal error in the MFW while processing the request
2294          * - The resource ID is unknown to the MFW
2295          */
2296         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2297                 DP_INFO(p_hwfn,
2298                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2299                         res_id,
2300                         qed_hw_get_resc_name(res_id),
2301                         mcp_resp, dflt_resc_num, dflt_resc_start);
2302                 *p_resc_num = dflt_resc_num;
2303                 *p_resc_start = dflt_resc_start;
2304                 goto out;
2305         }
2306
2307         /* Special handling for status blocks; Would be revised in future */
2308         if (res_id == QED_SB) {
2309                 *p_resc_num -= 1;
2310                 *p_resc_start -= p_hwfn->enabled_func_idx;
2311         }
2312 out:
2313         /* PQs have to divide by 8 [that's the HW granularity].
2314          * Reduce number so it would fit.
2315          */
2316         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2317                 DP_INFO(p_hwfn,
2318                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2319                         *p_resc_num,
2320                         (*p_resc_num) & ~0x7,
2321                         *p_resc_start, (*p_resc_start) & ~0x7);
2322                 *p_resc_num &= ~0x7;
2323                 *p_resc_start &= ~0x7;
2324         }
2325
2326         return 0;
2327 }
2328
2329 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2330 {
2331         int rc;
2332         u8 res_id;
2333
2334         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2335                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2336                 if (rc)
2337                         return rc;
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2344 {
2345         struct qed_resc_unlock_params resc_unlock_params;
2346         struct qed_resc_lock_params resc_lock_params;
2347         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2348         u8 res_id;
2349         int rc;
2350
2351         /* Setting the max values of the soft resources and the following
2352          * resources allocation queries should be atomic. Since several PFs can
2353          * run in parallel - a resource lock is needed.
2354          * If either the resource lock or resource set value commands are not
2355          * supported - skip the the max values setting, release the lock if
2356          * needed, and proceed to the queries. Other failures, including a
2357          * failure to acquire the lock, will cause this function to fail.
2358          */
2359         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2360                                        QED_RESC_LOCK_RESC_ALLOC, false);
2361
2362         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2363         if (rc && rc != -EINVAL) {
2364                 return rc;
2365         } else if (rc == -EINVAL) {
2366                 DP_INFO(p_hwfn,
2367                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2368         } else if (!rc && !resc_lock_params.b_granted) {
2369                 DP_NOTICE(p_hwfn,
2370                           "Failed to acquire the resource lock for the resource allocation commands\n");
2371                 return -EBUSY;
2372         } else {
2373                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2374                 if (rc && rc != -EINVAL) {
2375                         DP_NOTICE(p_hwfn,
2376                                   "Failed to set the max values of the soft resources\n");
2377                         goto unlock_and_exit;
2378                 } else if (rc == -EINVAL) {
2379                         DP_INFO(p_hwfn,
2380                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2381                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2382                                                  &resc_unlock_params);
2383                         if (rc)
2384                                 DP_INFO(p_hwfn,
2385                                         "Failed to release the resource lock for the resource allocation commands\n");
2386                 }
2387         }
2388
2389         rc = qed_hw_set_resc_info(p_hwfn);
2390         if (rc)
2391                 goto unlock_and_exit;
2392
2393         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2394                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2395                 if (rc)
2396                         DP_INFO(p_hwfn,
2397                                 "Failed to release the resource lock for the resource allocation commands\n");
2398         }
2399
2400         /* Sanity for ILT */
2401         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2402             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2403                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2404                           RESC_START(p_hwfn, QED_ILT),
2405                           RESC_END(p_hwfn, QED_ILT) - 1);
2406                 return -EINVAL;
2407         }
2408
2409         qed_hw_set_feat(p_hwfn);
2410
2411         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2412                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2413                            qed_hw_get_resc_name(res_id),
2414                            RESC_NUM(p_hwfn, res_id),
2415                            RESC_START(p_hwfn, res_id));
2416
2417         return 0;
2418
2419 unlock_and_exit:
2420         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2421                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2422         return rc;
2423 }
2424
2425 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2426 {
2427         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2428         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2429         struct qed_mcp_link_params *link;
2430
2431         /* Read global nvm_cfg address */
2432         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2433
2434         /* Verify MCP has initialized it */
2435         if (!nvm_cfg_addr) {
2436                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2437                 return -EINVAL;
2438         }
2439
2440         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2441         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2442
2443         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2444                offsetof(struct nvm_cfg1, glob) +
2445                offsetof(struct nvm_cfg1_glob, core_cfg);
2446
2447         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2448
2449         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2450                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2451         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2452                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2453                 break;
2454         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2455                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2456                 break;
2457         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2458                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2459                 break;
2460         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2461                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2462                 break;
2463         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2464                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2465                 break;
2466         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2467                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2468                 break;
2469         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2470                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2471                 break;
2472         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2473                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2474                 break;
2475         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2476                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2477                 break;
2478         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2479                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2480                 break;
2481         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2482                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2483                 break;
2484         default:
2485                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2486                 break;
2487         }
2488
2489         /* Read default link configuration */
2490         link = &p_hwfn->mcp_info->link_input;
2491         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2492                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2493         link_temp = qed_rd(p_hwfn, p_ptt,
2494                            port_cfg_addr +
2495                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2496         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2497         link->speed.advertised_speeds = link_temp;
2498
2499         link_temp = link->speed.advertised_speeds;
2500         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2501
2502         link_temp = qed_rd(p_hwfn, p_ptt,
2503                            port_cfg_addr +
2504                            offsetof(struct nvm_cfg1_port, link_settings));
2505         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2506                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2507         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2508                 link->speed.autoneg = true;
2509                 break;
2510         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2511                 link->speed.forced_speed = 1000;
2512                 break;
2513         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2514                 link->speed.forced_speed = 10000;
2515                 break;
2516         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2517                 link->speed.forced_speed = 25000;
2518                 break;
2519         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2520                 link->speed.forced_speed = 40000;
2521                 break;
2522         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2523                 link->speed.forced_speed = 50000;
2524                 break;
2525         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2526                 link->speed.forced_speed = 100000;
2527                 break;
2528         default:
2529                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2530         }
2531
2532         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2533                 link->speed.autoneg;
2534
2535         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2536         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2537         link->pause.autoneg = !!(link_temp &
2538                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2539         link->pause.forced_rx = !!(link_temp &
2540                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2541         link->pause.forced_tx = !!(link_temp &
2542                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2543         link->loopback_mode = 0;
2544
2545         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2546                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2547                    link->speed.forced_speed, link->speed.advertised_speeds,
2548                    link->speed.autoneg, link->pause.autoneg);
2549
2550         /* Read Multi-function information from shmem */
2551         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2552                offsetof(struct nvm_cfg1, glob) +
2553                offsetof(struct nvm_cfg1_glob, generic_cont0);
2554
2555         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2556
2557         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2558                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
2559
2560         switch (mf_mode) {
2561         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2562                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2563                 break;
2564         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2565                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2566                 break;
2567         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2568                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2569                 break;
2570         }
2571         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2572                 p_hwfn->cdev->mf_mode);
2573
2574         /* Read Multi-function information from shmem */
2575         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2576                 offsetof(struct nvm_cfg1, glob) +
2577                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2578
2579         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2580         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2581                 __set_bit(QED_DEV_CAP_ETH,
2582                           &p_hwfn->hw_info.device_capabilities);
2583         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2584                 __set_bit(QED_DEV_CAP_FCOE,
2585                           &p_hwfn->hw_info.device_capabilities);
2586         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2587                 __set_bit(QED_DEV_CAP_ISCSI,
2588                           &p_hwfn->hw_info.device_capabilities);
2589         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2590                 __set_bit(QED_DEV_CAP_ROCE,
2591                           &p_hwfn->hw_info.device_capabilities);
2592
2593         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2594 }
2595
2596 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2597 {
2598         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2599         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2600         struct qed_dev *cdev = p_hwfn->cdev;
2601
2602         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2603
2604         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2605          * in the other bits are selected.
2606          * Bits 1-15 are for functions 1-15, respectively, and their value is
2607          * '0' only for enabled functions (function 0 always exists and
2608          * enabled).
2609          * In case of CMT, only the "even" functions are enabled, and thus the
2610          * number of functions for both hwfns is learnt from the same bits.
2611          */
2612         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2613
2614         if (reg_function_hide & 0x1) {
2615                 if (QED_IS_BB(cdev)) {
2616                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2617                                 num_funcs = 0;
2618                                 eng_mask = 0xaaaa;
2619                         } else {
2620                                 num_funcs = 1;
2621                                 eng_mask = 0x5554;
2622                         }
2623                 } else {
2624                         num_funcs = 1;
2625                         eng_mask = 0xfffe;
2626                 }
2627
2628                 /* Get the number of the enabled functions on the engine */
2629                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2630                 while (tmp) {
2631                         if (tmp & 0x1)
2632                                 num_funcs++;
2633                         tmp >>= 0x1;
2634                 }
2635
2636                 /* Get the PF index within the enabled functions */
2637                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2638                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2639                 while (tmp) {
2640                         if (tmp & 0x1)
2641                                 enabled_func_idx--;
2642                         tmp >>= 0x1;
2643                 }
2644         }
2645
2646         p_hwfn->num_funcs_on_engine = num_funcs;
2647         p_hwfn->enabled_func_idx = enabled_func_idx;
2648
2649         DP_VERBOSE(p_hwfn,
2650                    NETIF_MSG_PROBE,
2651                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2652                    p_hwfn->rel_pf_id,
2653                    p_hwfn->abs_pf_id,
2654                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2655 }
2656
2657 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2658                                     struct qed_ptt *p_ptt)
2659 {
2660         u32 port_mode;
2661
2662         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2663
2664         if (port_mode < 3) {
2665                 p_hwfn->cdev->num_ports_in_engine = 1;
2666         } else if (port_mode <= 5) {
2667                 p_hwfn->cdev->num_ports_in_engine = 2;
2668         } else {
2669                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2670                           p_hwfn->cdev->num_ports_in_engine);
2671
2672                 /* Default num_ports_in_engine to something */
2673                 p_hwfn->cdev->num_ports_in_engine = 1;
2674         }
2675 }
2676
2677 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2678                                     struct qed_ptt *p_ptt)
2679 {
2680         u32 port;
2681         int i;
2682
2683         p_hwfn->cdev->num_ports_in_engine = 0;
2684
2685         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2686                 port = qed_rd(p_hwfn, p_ptt,
2687                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2688                 if (port & 1)
2689                         p_hwfn->cdev->num_ports_in_engine++;
2690         }
2691
2692         if (!p_hwfn->cdev->num_ports_in_engine) {
2693                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2694
2695                 /* Default num_ports_in_engine to something */
2696                 p_hwfn->cdev->num_ports_in_engine = 1;
2697         }
2698 }
2699
2700 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2701 {
2702         if (QED_IS_BB(p_hwfn->cdev))
2703                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2704         else
2705                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2706 }
2707
2708 static int
2709 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2710                 struct qed_ptt *p_ptt,
2711                 enum qed_pci_personality personality)
2712 {
2713         int rc;
2714
2715         /* Since all information is common, only first hwfns should do this */
2716         if (IS_LEAD_HWFN(p_hwfn)) {
2717                 rc = qed_iov_hw_info(p_hwfn);
2718                 if (rc)
2719                         return rc;
2720         }
2721
2722         qed_hw_info_port_num(p_hwfn, p_ptt);
2723
2724         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2725
2726         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2727         if (rc)
2728                 return rc;
2729
2730         if (qed_mcp_is_init(p_hwfn))
2731                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2732                                 p_hwfn->mcp_info->func_info.mac);
2733         else
2734                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2735
2736         if (qed_mcp_is_init(p_hwfn)) {
2737                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2738                         p_hwfn->hw_info.ovlan =
2739                                 p_hwfn->mcp_info->func_info.ovlan;
2740
2741                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2742         }
2743
2744         if (qed_mcp_is_init(p_hwfn)) {
2745                 enum qed_pci_personality protocol;
2746
2747                 protocol = p_hwfn->mcp_info->func_info.protocol;
2748                 p_hwfn->hw_info.personality = protocol;
2749         }
2750
2751         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2752         p_hwfn->hw_info.num_active_tc = 1;
2753
2754         qed_get_num_funcs(p_hwfn, p_ptt);
2755
2756         if (qed_mcp_is_init(p_hwfn))
2757                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2758
2759         return qed_hw_get_resc(p_hwfn, p_ptt);
2760 }
2761
2762 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2763 {
2764         struct qed_dev *cdev = p_hwfn->cdev;
2765         u16 device_id_mask;
2766         u32 tmp;
2767
2768         /* Read Vendor Id / Device Id */
2769         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2770         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2771
2772         /* Determine type */
2773         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2774         switch (device_id_mask) {
2775         case QED_DEV_ID_MASK_BB:
2776                 cdev->type = QED_DEV_TYPE_BB;
2777                 break;
2778         case QED_DEV_ID_MASK_AH:
2779                 cdev->type = QED_DEV_TYPE_AH;
2780                 break;
2781         default:
2782                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2783                 return -EBUSY;
2784         }
2785
2786         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2787         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2788
2789         MASK_FIELD(CHIP_REV, cdev->chip_rev);
2790
2791         /* Learn number of HW-functions */
2792         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2793
2794         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2795                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2796                 cdev->num_hwfns = 2;
2797         } else {
2798                 cdev->num_hwfns = 1;
2799         }
2800
2801         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2802                                     MISCS_REG_CHIP_TEST_REG) >> 4;
2803         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2804         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2805         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2806
2807         DP_INFO(cdev->hwfns,
2808                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2809                 QED_IS_BB(cdev) ? "BB" : "AH",
2810                 'A' + cdev->chip_rev,
2811                 (int)cdev->chip_metal,
2812                 cdev->chip_num, cdev->chip_rev,
2813                 cdev->chip_bond_id, cdev->chip_metal);
2814
2815         return 0;
2816 }
2817
2818 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2819                                  void __iomem *p_regview,
2820                                  void __iomem *p_doorbells,
2821                                  enum qed_pci_personality personality)
2822 {
2823         int rc = 0;
2824
2825         /* Split PCI bars evenly between hwfns */
2826         p_hwfn->regview = p_regview;
2827         p_hwfn->doorbells = p_doorbells;
2828
2829         if (IS_VF(p_hwfn->cdev))
2830                 return qed_vf_hw_prepare(p_hwfn);
2831
2832         /* Validate that chip access is feasible */
2833         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2834                 DP_ERR(p_hwfn,
2835                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2836                 return -EINVAL;
2837         }
2838
2839         get_function_id(p_hwfn);
2840
2841         /* Allocate PTT pool */
2842         rc = qed_ptt_pool_alloc(p_hwfn);
2843         if (rc)
2844                 goto err0;
2845
2846         /* Allocate the main PTT */
2847         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2848
2849         /* First hwfn learns basic information, e.g., number of hwfns */
2850         if (!p_hwfn->my_id) {
2851                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2852                 if (rc)
2853                         goto err1;
2854         }
2855
2856         qed_hw_hwfn_prepare(p_hwfn);
2857
2858         /* Initialize MCP structure */
2859         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2860         if (rc) {
2861                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2862                 goto err1;
2863         }
2864
2865         /* Read the device configuration information from the HW and SHMEM */
2866         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2867         if (rc) {
2868                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2869                 goto err2;
2870         }
2871
2872         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2873          * is called as it sets the ports number in an engine.
2874          */
2875         if (IS_LEAD_HWFN(p_hwfn)) {
2876                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2877                 if (rc)
2878                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2879         }
2880
2881         /* Allocate the init RT array and initialize the init-ops engine */
2882         rc = qed_init_alloc(p_hwfn);
2883         if (rc)
2884                 goto err2;
2885
2886         return rc;
2887 err2:
2888         if (IS_LEAD_HWFN(p_hwfn))
2889                 qed_iov_free_hw_info(p_hwfn->cdev);
2890         qed_mcp_free(p_hwfn);
2891 err1:
2892         qed_hw_hwfn_free(p_hwfn);
2893 err0:
2894         return rc;
2895 }
2896
2897 int qed_hw_prepare(struct qed_dev *cdev,
2898                    int personality)
2899 {
2900         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2901         int rc;
2902
2903         /* Store the precompiled init data ptrs */
2904         if (IS_PF(cdev))
2905                 qed_init_iro_array(cdev);
2906
2907         /* Initialize the first hwfn - will learn number of hwfns */
2908         rc = qed_hw_prepare_single(p_hwfn,
2909                                    cdev->regview,
2910                                    cdev->doorbells, personality);
2911         if (rc)
2912                 return rc;
2913
2914         personality = p_hwfn->hw_info.personality;
2915
2916         /* Initialize the rest of the hwfns */
2917         if (cdev->num_hwfns > 1) {
2918                 void __iomem *p_regview, *p_doorbell;
2919                 u8 __iomem *addr;
2920
2921                 /* adjust bar offset for second engine */
2922                 addr = cdev->regview +
2923                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2924                                        BAR_ID_0) / 2;
2925                 p_regview = addr;
2926
2927                 addr = cdev->doorbells +
2928                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2929                                        BAR_ID_1) / 2;
2930                 p_doorbell = addr;
2931
2932                 /* prepare second hw function */
2933                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
2934                                            p_doorbell, personality);
2935
2936                 /* in case of error, need to free the previously
2937                  * initiliazed hwfn 0.
2938                  */
2939                 if (rc) {
2940                         if (IS_PF(cdev)) {
2941                                 qed_init_free(p_hwfn);
2942                                 qed_mcp_free(p_hwfn);
2943                                 qed_hw_hwfn_free(p_hwfn);
2944                         }
2945                 }
2946         }
2947
2948         return rc;
2949 }
2950
2951 void qed_hw_remove(struct qed_dev *cdev)
2952 {
2953         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2954         int i;
2955
2956         if (IS_PF(cdev))
2957                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2958                                                QED_OV_DRIVER_STATE_NOT_LOADED);
2959
2960         for_each_hwfn(cdev, i) {
2961                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2962
2963                 if (IS_VF(cdev)) {
2964                         qed_vf_pf_release(p_hwfn);
2965                         continue;
2966                 }
2967
2968                 qed_init_free(p_hwfn);
2969                 qed_hw_hwfn_free(p_hwfn);
2970                 qed_mcp_free(p_hwfn);
2971         }
2972
2973         qed_iov_free_hw_info(cdev);
2974 }
2975
2976 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2977                                     struct qed_chain *p_chain)
2978 {
2979         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2980         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2981         struct qed_chain_next *p_next;
2982         u32 size, i;
2983
2984         if (!p_virt)
2985                 return;
2986
2987         size = p_chain->elem_size * p_chain->usable_per_page;
2988
2989         for (i = 0; i < p_chain->page_cnt; i++) {
2990                 if (!p_virt)
2991                         break;
2992
2993                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2994                 p_virt_next = p_next->next_virt;
2995                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2996
2997                 dma_free_coherent(&cdev->pdev->dev,
2998                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2999
3000                 p_virt = p_virt_next;
3001                 p_phys = p_phys_next;
3002         }
3003 }
3004
3005 static void qed_chain_free_single(struct qed_dev *cdev,
3006                                   struct qed_chain *p_chain)
3007 {
3008         if (!p_chain->p_virt_addr)
3009                 return;
3010
3011         dma_free_coherent(&cdev->pdev->dev,
3012                           QED_CHAIN_PAGE_SIZE,
3013                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3014 }
3015
3016 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3017 {
3018         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3019         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3020         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3021
3022         if (!pp_virt_addr_tbl)
3023                 return;
3024
3025         if (!p_pbl_virt)
3026                 goto out;
3027
3028         for (i = 0; i < page_cnt; i++) {
3029                 if (!pp_virt_addr_tbl[i])
3030                         break;
3031
3032                 dma_free_coherent(&cdev->pdev->dev,
3033                                   QED_CHAIN_PAGE_SIZE,
3034                                   pp_virt_addr_tbl[i],
3035                                   *(dma_addr_t *)p_pbl_virt);
3036
3037                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3038         }
3039
3040         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3041         dma_free_coherent(&cdev->pdev->dev,
3042                           pbl_size,
3043                           p_chain->pbl_sp.p_virt_table,
3044                           p_chain->pbl_sp.p_phys_table);
3045 out:
3046         vfree(p_chain->pbl.pp_virt_addr_tbl);
3047 }
3048
3049 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3050 {
3051         switch (p_chain->mode) {
3052         case QED_CHAIN_MODE_NEXT_PTR:
3053                 qed_chain_free_next_ptr(cdev, p_chain);
3054                 break;
3055         case QED_CHAIN_MODE_SINGLE:
3056                 qed_chain_free_single(cdev, p_chain);
3057                 break;
3058         case QED_CHAIN_MODE_PBL:
3059                 qed_chain_free_pbl(cdev, p_chain);
3060                 break;
3061         }
3062 }
3063
3064 static int
3065 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3066                              enum qed_chain_cnt_type cnt_type,
3067                              size_t elem_size, u32 page_cnt)
3068 {
3069         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3070
3071         /* The actual chain size can be larger than the maximal possible value
3072          * after rounding up the requested elements number to pages, and after
3073          * taking into acount the unusuable elements (next-ptr elements).
3074          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3075          * size/capacity fields are of a u32 type.
3076          */
3077         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3078              chain_size > ((u32)U16_MAX + 1)) ||
3079             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3080                 DP_NOTICE(cdev,
3081                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3082                           chain_size);
3083                 return -EINVAL;
3084         }
3085
3086         return 0;
3087 }
3088
3089 static int
3090 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3091 {
3092         void *p_virt = NULL, *p_virt_prev = NULL;
3093         dma_addr_t p_phys = 0;
3094         u32 i;
3095
3096         for (i = 0; i < p_chain->page_cnt; i++) {
3097                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3098                                             QED_CHAIN_PAGE_SIZE,
3099                                             &p_phys, GFP_KERNEL);
3100                 if (!p_virt)
3101                         return -ENOMEM;
3102
3103                 if (i == 0) {
3104                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3105                         qed_chain_reset(p_chain);
3106                 } else {
3107                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3108                                                      p_virt, p_phys);
3109                 }
3110
3111                 p_virt_prev = p_virt;
3112         }
3113         /* Last page's next element should point to the beginning of the
3114          * chain.
3115          */
3116         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3117                                      p_chain->p_virt_addr,
3118                                      p_chain->p_phys_addr);
3119
3120         return 0;
3121 }
3122
3123 static int
3124 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3125 {
3126         dma_addr_t p_phys = 0;
3127         void *p_virt = NULL;
3128
3129         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3130                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3131         if (!p_virt)
3132                 return -ENOMEM;
3133
3134         qed_chain_init_mem(p_chain, p_virt, p_phys);
3135         qed_chain_reset(p_chain);
3136
3137         return 0;
3138 }
3139
3140 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3141 {
3142         u32 page_cnt = p_chain->page_cnt, size, i;
3143         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3144         void **pp_virt_addr_tbl = NULL;
3145         u8 *p_pbl_virt = NULL;
3146         void *p_virt = NULL;
3147
3148         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3149         pp_virt_addr_tbl = vzalloc(size);
3150         if (!pp_virt_addr_tbl)
3151                 return -ENOMEM;
3152
3153         /* The allocation of the PBL table is done with its full size, since it
3154          * is expected to be successive.
3155          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3156          * failure, since pp_virt_addr_tbl was previously allocated, and it
3157          * should be saved to allow its freeing during the error flow.
3158          */
3159         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3160         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3161                                         size, &p_pbl_phys, GFP_KERNEL);
3162         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3163                                pp_virt_addr_tbl);
3164         if (!p_pbl_virt)
3165                 return -ENOMEM;
3166
3167         for (i = 0; i < page_cnt; i++) {
3168                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3169                                             QED_CHAIN_PAGE_SIZE,
3170                                             &p_phys, GFP_KERNEL);
3171                 if (!p_virt)
3172                         return -ENOMEM;
3173
3174                 if (i == 0) {
3175                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3176                         qed_chain_reset(p_chain);
3177                 }
3178
3179                 /* Fill the PBL table with the physical address of the page */
3180                 *(dma_addr_t *)p_pbl_virt = p_phys;
3181                 /* Keep the virtual address of the page */
3182                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3183
3184                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3185         }
3186
3187         return 0;
3188 }
3189
3190 int qed_chain_alloc(struct qed_dev *cdev,
3191                     enum qed_chain_use_mode intended_use,
3192                     enum qed_chain_mode mode,
3193                     enum qed_chain_cnt_type cnt_type,
3194                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
3195 {
3196         u32 page_cnt;
3197         int rc = 0;
3198
3199         if (mode == QED_CHAIN_MODE_SINGLE)
3200                 page_cnt = 1;
3201         else
3202                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3203
3204         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3205         if (rc) {
3206                 DP_NOTICE(cdev,
3207                           "Cannot allocate a chain with the given arguments:\n");
3208                 DP_NOTICE(cdev,
3209                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3210                           intended_use, mode, cnt_type, num_elems, elem_size);
3211                 return rc;
3212         }
3213
3214         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3215                               mode, cnt_type);
3216
3217         switch (mode) {
3218         case QED_CHAIN_MODE_NEXT_PTR:
3219                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3220                 break;
3221         case QED_CHAIN_MODE_SINGLE:
3222                 rc = qed_chain_alloc_single(cdev, p_chain);
3223                 break;
3224         case QED_CHAIN_MODE_PBL:
3225                 rc = qed_chain_alloc_pbl(cdev, p_chain);
3226                 break;
3227         }
3228         if (rc)
3229                 goto nomem;
3230
3231         return 0;
3232
3233 nomem:
3234         qed_chain_free(cdev, p_chain);
3235         return rc;
3236 }
3237
3238 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3239 {
3240         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3241                 u16 min, max;
3242
3243                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3244                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3245                 DP_NOTICE(p_hwfn,
3246                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3247                           src_id, min, max);
3248
3249                 return -EINVAL;
3250         }
3251
3252         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3253
3254         return 0;
3255 }
3256
3257 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3258 {
3259         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3260                 u8 min, max;
3261
3262                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3263                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3264                 DP_NOTICE(p_hwfn,
3265                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3266                           src_id, min, max);
3267
3268                 return -EINVAL;
3269         }
3270
3271         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3272
3273         return 0;
3274 }
3275
3276 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3277 {
3278         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3279                 u8 min, max;
3280
3281                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3282                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3283                 DP_NOTICE(p_hwfn,
3284                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3285                           src_id, min, max);
3286
3287                 return -EINVAL;
3288         }
3289
3290         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3291
3292         return 0;
3293 }
3294
3295 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3296                                   u8 *p_filter)
3297 {
3298         *p_high = p_filter[1] | (p_filter[0] << 8);
3299         *p_low = p_filter[5] | (p_filter[4] << 8) |
3300                  (p_filter[3] << 16) | (p_filter[2] << 24);
3301 }
3302
3303 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3304                            struct qed_ptt *p_ptt, u8 *p_filter)
3305 {
3306         u32 high = 0, low = 0, en;
3307         int i;
3308
3309         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3310                 return 0;
3311
3312         qed_llh_mac_to_filter(&high, &low, p_filter);
3313
3314         /* Find a free entry and utilize it */
3315         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3316                 en = qed_rd(p_hwfn, p_ptt,
3317                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3318                 if (en)
3319                         continue;
3320                 qed_wr(p_hwfn, p_ptt,
3321                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3322                        2 * i * sizeof(u32), low);
3323                 qed_wr(p_hwfn, p_ptt,
3324                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3325                        (2 * i + 1) * sizeof(u32), high);
3326                 qed_wr(p_hwfn, p_ptt,
3327                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3328                 qed_wr(p_hwfn, p_ptt,
3329                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3330                        i * sizeof(u32), 0);
3331                 qed_wr(p_hwfn, p_ptt,
3332                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3333                 break;
3334         }
3335         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3336                 DP_NOTICE(p_hwfn,
3337                           "Failed to find an empty LLH filter to utilize\n");
3338                 return -EINVAL;
3339         }
3340
3341         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3342                    "mac: %pM is added at %d\n",
3343                    p_filter, i);
3344
3345         return 0;
3346 }
3347
3348 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3349                                struct qed_ptt *p_ptt, u8 *p_filter)
3350 {
3351         u32 high = 0, low = 0;
3352         int i;
3353
3354         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3355                 return;
3356
3357         qed_llh_mac_to_filter(&high, &low, p_filter);
3358
3359         /* Find the entry and clean it */
3360         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3361                 if (qed_rd(p_hwfn, p_ptt,
3362                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3363                            2 * i * sizeof(u32)) != low)
3364                         continue;
3365                 if (qed_rd(p_hwfn, p_ptt,
3366                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3367                            (2 * i + 1) * sizeof(u32)) != high)
3368                         continue;
3369
3370                 qed_wr(p_hwfn, p_ptt,
3371                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3372                 qed_wr(p_hwfn, p_ptt,
3373                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3374                 qed_wr(p_hwfn, p_ptt,
3375                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3376                        (2 * i + 1) * sizeof(u32), 0);
3377
3378                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3379                            "mac: %pM is removed from %d\n",
3380                            p_filter, i);
3381                 break;
3382         }
3383         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3384                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3385 }
3386
3387 int
3388 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3389                             struct qed_ptt *p_ptt,
3390                             u16 source_port_or_eth_type,
3391                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3392 {
3393         u32 high = 0, low = 0, en;
3394         int i;
3395
3396         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3397                 return 0;
3398
3399         switch (type) {
3400         case QED_LLH_FILTER_ETHERTYPE:
3401                 high = source_port_or_eth_type;
3402                 break;
3403         case QED_LLH_FILTER_TCP_SRC_PORT:
3404         case QED_LLH_FILTER_UDP_SRC_PORT:
3405                 low = source_port_or_eth_type << 16;
3406                 break;
3407         case QED_LLH_FILTER_TCP_DEST_PORT:
3408         case QED_LLH_FILTER_UDP_DEST_PORT:
3409                 low = dest_port;
3410                 break;
3411         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3412         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3413                 low = (source_port_or_eth_type << 16) | dest_port;
3414                 break;
3415         default:
3416                 DP_NOTICE(p_hwfn,
3417                           "Non valid LLH protocol filter type %d\n", type);
3418                 return -EINVAL;
3419         }
3420         /* Find a free entry and utilize it */
3421         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3422                 en = qed_rd(p_hwfn, p_ptt,
3423                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3424                 if (en)
3425                         continue;
3426                 qed_wr(p_hwfn, p_ptt,
3427                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3428                        2 * i * sizeof(u32), low);
3429                 qed_wr(p_hwfn, p_ptt,
3430                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3431                        (2 * i + 1) * sizeof(u32), high);
3432                 qed_wr(p_hwfn, p_ptt,
3433                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3434                 qed_wr(p_hwfn, p_ptt,
3435                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3436                        i * sizeof(u32), 1 << type);
3437                 qed_wr(p_hwfn, p_ptt,
3438                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3439                 break;
3440         }
3441         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3442                 DP_NOTICE(p_hwfn,
3443                           "Failed to find an empty LLH filter to utilize\n");
3444                 return -EINVAL;
3445         }
3446         switch (type) {
3447         case QED_LLH_FILTER_ETHERTYPE:
3448                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3449                            "ETH type %x is added at %d\n",
3450                            source_port_or_eth_type, i);
3451                 break;
3452         case QED_LLH_FILTER_TCP_SRC_PORT:
3453                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3454                            "TCP src port %x is added at %d\n",
3455                            source_port_or_eth_type, i);
3456                 break;
3457         case QED_LLH_FILTER_UDP_SRC_PORT:
3458                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3459                            "UDP src port %x is added at %d\n",
3460                            source_port_or_eth_type, i);
3461                 break;
3462         case QED_LLH_FILTER_TCP_DEST_PORT:
3463                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3464                            "TCP dst port %x is added at %d\n", dest_port, i);
3465                 break;
3466         case QED_LLH_FILTER_UDP_DEST_PORT:
3467                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3468                            "UDP dst port %x is added at %d\n", dest_port, i);
3469                 break;
3470         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3471                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3472                            "TCP src/dst ports %x/%x are added at %d\n",
3473                            source_port_or_eth_type, dest_port, i);
3474                 break;
3475         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3476                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3477                            "UDP src/dst ports %x/%x are added at %d\n",
3478                            source_port_or_eth_type, dest_port, i);
3479                 break;
3480         }
3481         return 0;
3482 }
3483
3484 void
3485 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3486                                struct qed_ptt *p_ptt,
3487                                u16 source_port_or_eth_type,
3488                                u16 dest_port,
3489                                enum qed_llh_port_filter_type_t type)
3490 {
3491         u32 high = 0, low = 0;
3492         int i;
3493
3494         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3495                 return;
3496
3497         switch (type) {
3498         case QED_LLH_FILTER_ETHERTYPE:
3499                 high = source_port_or_eth_type;
3500                 break;
3501         case QED_LLH_FILTER_TCP_SRC_PORT:
3502         case QED_LLH_FILTER_UDP_SRC_PORT:
3503                 low = source_port_or_eth_type << 16;
3504                 break;
3505         case QED_LLH_FILTER_TCP_DEST_PORT:
3506         case QED_LLH_FILTER_UDP_DEST_PORT:
3507                 low = dest_port;
3508                 break;
3509         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3510         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3511                 low = (source_port_or_eth_type << 16) | dest_port;
3512                 break;
3513         default:
3514                 DP_NOTICE(p_hwfn,
3515                           "Non valid LLH protocol filter type %d\n", type);
3516                 return;
3517         }
3518
3519         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3520                 if (!qed_rd(p_hwfn, p_ptt,
3521                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3522                         continue;
3523                 if (!qed_rd(p_hwfn, p_ptt,
3524                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3525                         continue;
3526                 if (!(qed_rd(p_hwfn, p_ptt,
3527                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3528                              i * sizeof(u32)) & BIT(type)))
3529                         continue;
3530                 if (qed_rd(p_hwfn, p_ptt,
3531                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3532                            2 * i * sizeof(u32)) != low)
3533                         continue;
3534                 if (qed_rd(p_hwfn, p_ptt,
3535                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3536                            (2 * i + 1) * sizeof(u32)) != high)
3537                         continue;
3538
3539                 qed_wr(p_hwfn, p_ptt,
3540                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3541                 qed_wr(p_hwfn, p_ptt,
3542                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3543                 qed_wr(p_hwfn, p_ptt,
3544                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3545                        i * sizeof(u32), 0);
3546                 qed_wr(p_hwfn, p_ptt,
3547                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3548                 qed_wr(p_hwfn, p_ptt,
3549                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3550                        (2 * i + 1) * sizeof(u32), 0);
3551                 break;
3552         }
3553
3554         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3555                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3556 }
3557
3558 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3559                             u32 hw_addr, void *p_eth_qzone,
3560                             size_t eth_qzone_size, u8 timeset)
3561 {
3562         struct coalescing_timeset *p_coal_timeset;
3563
3564         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3565                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3566                 return -EINVAL;
3567         }
3568
3569         p_coal_timeset = p_eth_qzone;
3570         memset(p_coal_timeset, 0, eth_qzone_size);
3571         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3572         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3573         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3574
3575         return 0;
3576 }
3577
3578 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3579                          u16 coalesce, u16 qid, u16 sb_id)
3580 {
3581         struct ustorm_eth_queue_zone eth_qzone;
3582         u8 timeset, timer_res;
3583         u16 fw_qid = 0;
3584         u32 address;
3585         int rc;
3586
3587         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3588         if (coalesce <= 0x7F) {
3589                 timer_res = 0;
3590         } else if (coalesce <= 0xFF) {
3591                 timer_res = 1;
3592         } else if (coalesce <= 0x1FF) {
3593                 timer_res = 2;
3594         } else {
3595                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3596                 return -EINVAL;
3597         }
3598         timeset = (u8)(coalesce >> timer_res);
3599
3600         rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);
3601         if (rc)
3602                 return rc;
3603
3604         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3605         if (rc)
3606                 goto out;
3607
3608         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3609
3610         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3611                               sizeof(struct ustorm_eth_queue_zone), timeset);
3612         if (rc)
3613                 goto out;
3614
3615         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3616 out:
3617         return rc;
3618 }
3619
3620 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3621                          u16 coalesce, u16 qid, u16 sb_id)
3622 {
3623         struct xstorm_eth_queue_zone eth_qzone;
3624         u8 timeset, timer_res;
3625         u16 fw_qid = 0;
3626         u32 address;
3627         int rc;
3628
3629         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3630         if (coalesce <= 0x7F) {
3631                 timer_res = 0;
3632         } else if (coalesce <= 0xFF) {
3633                 timer_res = 1;
3634         } else if (coalesce <= 0x1FF) {
3635                 timer_res = 2;
3636         } else {
3637                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3638                 return -EINVAL;
3639         }
3640         timeset = (u8)(coalesce >> timer_res);
3641
3642         rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);
3643         if (rc)
3644                 return rc;
3645
3646         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3647         if (rc)
3648                 goto out;
3649
3650         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3651
3652         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3653                               sizeof(struct xstorm_eth_queue_zone), timeset);
3654         if (rc)
3655                 goto out;
3656
3657         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3658 out:
3659         return rc;
3660 }
3661
3662 /* Calculate final WFQ values for all vports and configure them.
3663  * After this configuration each vport will have
3664  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3665  */
3666 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3667                                              struct qed_ptt *p_ptt,
3668                                              u32 min_pf_rate)
3669 {
3670         struct init_qm_vport_params *vport_params;
3671         int i;
3672
3673         vport_params = p_hwfn->qm_info.qm_vport_params;
3674
3675         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3676                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3677
3678                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3679                                                 min_pf_rate;
3680                 qed_init_vport_wfq(p_hwfn, p_ptt,
3681                                    vport_params[i].first_tx_pq_id,
3682                                    vport_params[i].vport_wfq);
3683         }
3684 }
3685
3686 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3687                                        u32 min_pf_rate)
3688
3689 {
3690         int i;
3691
3692         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3693                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3694 }
3695
3696 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3697                                            struct qed_ptt *p_ptt,
3698                                            u32 min_pf_rate)
3699 {
3700         struct init_qm_vport_params *vport_params;
3701         int i;
3702
3703         vport_params = p_hwfn->qm_info.qm_vport_params;
3704
3705         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3706                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3707                 qed_init_vport_wfq(p_hwfn, p_ptt,
3708                                    vport_params[i].first_tx_pq_id,
3709                                    vport_params[i].vport_wfq);
3710         }
3711 }
3712
3713 /* This function performs several validations for WFQ
3714  * configuration and required min rate for a given vport
3715  * 1. req_rate must be greater than one percent of min_pf_rate.
3716  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3717  *    rates to get less than one percent of min_pf_rate.
3718  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3719  */
3720 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3721                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
3722 {
3723         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3724         int non_requested_count = 0, req_count = 0, i, num_vports;
3725
3726         num_vports = p_hwfn->qm_info.num_vports;
3727
3728         /* Accounting for the vports which are configured for WFQ explicitly */
3729         for (i = 0; i < num_vports; i++) {
3730                 u32 tmp_speed;
3731
3732                 if ((i != vport_id) &&
3733                     p_hwfn->qm_info.wfq_data[i].configured) {
3734                         req_count++;
3735                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3736                         total_req_min_rate += tmp_speed;
3737                 }
3738         }
3739
3740         /* Include current vport data as well */
3741         req_count++;
3742         total_req_min_rate += req_rate;
3743         non_requested_count = num_vports - req_count;
3744
3745         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3746                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3747                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3748                            vport_id, req_rate, min_pf_rate);
3749                 return -EINVAL;
3750         }
3751
3752         if (num_vports > QED_WFQ_UNIT) {
3753                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3754                            "Number of vports is greater than %d\n",
3755                            QED_WFQ_UNIT);
3756                 return -EINVAL;
3757         }
3758
3759         if (total_req_min_rate > min_pf_rate) {
3760                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3761                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3762                            total_req_min_rate, min_pf_rate);
3763                 return -EINVAL;
3764         }
3765
3766         total_left_rate = min_pf_rate - total_req_min_rate;
3767
3768         left_rate_per_vp = total_left_rate / non_requested_count;
3769         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
3770                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3771                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3772                            left_rate_per_vp, min_pf_rate);
3773                 return -EINVAL;
3774         }
3775
3776         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3777         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3778
3779         for (i = 0; i < num_vports; i++) {
3780                 if (p_hwfn->qm_info.wfq_data[i].configured)
3781                         continue;
3782
3783                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3784         }
3785
3786         return 0;
3787 }
3788
3789 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3790                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3791 {
3792         struct qed_mcp_link_state *p_link;
3793         int rc = 0;
3794
3795         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3796
3797         if (!p_link->min_pf_rate) {
3798                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3799                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3800                 return rc;
3801         }
3802
3803         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3804
3805         if (!rc)
3806                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3807                                                  p_link->min_pf_rate);
3808         else
3809                 DP_NOTICE(p_hwfn,
3810                           "Validation failed while configuring min rate\n");
3811
3812         return rc;
3813 }
3814
3815 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3816                                                  struct qed_ptt *p_ptt,
3817                                                  u32 min_pf_rate)
3818 {
3819         bool use_wfq = false;
3820         int rc = 0;
3821         u16 i;
3822
3823         /* Validate all pre configured vports for wfq */
3824         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3825                 u32 rate;
3826
3827                 if (!p_hwfn->qm_info.wfq_data[i].configured)
3828                         continue;
3829
3830                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3831                 use_wfq = true;
3832
3833                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3834                 if (rc) {
3835                         DP_NOTICE(p_hwfn,
3836                                   "WFQ validation failed while configuring min rate\n");
3837                         break;
3838                 }
3839         }
3840
3841         if (!rc && use_wfq)
3842                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3843         else
3844                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3845
3846         return rc;
3847 }
3848
3849 /* Main API for qed clients to configure vport min rate.
3850  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3851  * rate - Speed in Mbps needs to be assigned to a given vport.
3852  */
3853 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3854 {
3855         int i, rc = -EINVAL;
3856
3857         /* Currently not supported; Might change in future */
3858         if (cdev->num_hwfns > 1) {
3859                 DP_NOTICE(cdev,
3860                           "WFQ configuration is not supported for this device\n");
3861                 return rc;
3862         }
3863
3864         for_each_hwfn(cdev, i) {
3865                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3866                 struct qed_ptt *p_ptt;
3867
3868                 p_ptt = qed_ptt_acquire(p_hwfn);
3869                 if (!p_ptt)
3870                         return -EBUSY;
3871
3872                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3873
3874                 if (rc) {
3875                         qed_ptt_release(p_hwfn, p_ptt);
3876                         return rc;
3877                 }
3878
3879                 qed_ptt_release(p_hwfn, p_ptt);
3880         }
3881
3882         return rc;
3883 }
3884
3885 /* API to configure WFQ from mcp link change */
3886 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3887                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
3888 {
3889         int i;
3890
3891         if (cdev->num_hwfns > 1) {
3892                 DP_VERBOSE(cdev,
3893                            NETIF_MSG_LINK,
3894                            "WFQ configuration is not supported for this device\n");
3895                 return;
3896         }
3897
3898         for_each_hwfn(cdev, i) {
3899                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3900
3901                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
3902                                                       min_pf_rate);
3903         }
3904 }
3905
3906 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3907                                      struct qed_ptt *p_ptt,
3908                                      struct qed_mcp_link_state *p_link,
3909                                      u8 max_bw)
3910 {
3911         int rc = 0;
3912
3913         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3914
3915         if (!p_link->line_speed && (max_bw != 100))
3916                 return rc;
3917
3918         p_link->speed = (p_link->line_speed * max_bw) / 100;
3919         p_hwfn->qm_info.pf_rl = p_link->speed;
3920
3921         /* Since the limiter also affects Tx-switched traffic, we don't want it
3922          * to limit such traffic in case there's no actual limit.
3923          * In that case, set limit to imaginary high boundary.
3924          */
3925         if (max_bw == 100)
3926                 p_hwfn->qm_info.pf_rl = 100000;
3927
3928         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3929                             p_hwfn->qm_info.pf_rl);
3930
3931         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3932                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3933                    p_link->speed);
3934
3935         return rc;
3936 }
3937
3938 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3939 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3940 {
3941         int i, rc = -EINVAL;
3942
3943         if (max_bw < 1 || max_bw > 100) {
3944                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3945                 return rc;
3946         }
3947
3948         for_each_hwfn(cdev, i) {
3949                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3950                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3951                 struct qed_mcp_link_state *p_link;
3952                 struct qed_ptt *p_ptt;
3953
3954                 p_link = &p_lead->mcp_info->link_output;
3955
3956                 p_ptt = qed_ptt_acquire(p_hwfn);
3957                 if (!p_ptt)
3958                         return -EBUSY;
3959
3960                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3961                                                       p_link, max_bw);
3962
3963                 qed_ptt_release(p_hwfn, p_ptt);
3964
3965                 if (rc)
3966                         break;
3967         }
3968
3969         return rc;
3970 }
3971
3972 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3973                                      struct qed_ptt *p_ptt,
3974                                      struct qed_mcp_link_state *p_link,
3975                                      u8 min_bw)
3976 {
3977         int rc = 0;
3978
3979         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3980         p_hwfn->qm_info.pf_wfq = min_bw;
3981
3982         if (!p_link->line_speed)
3983                 return rc;
3984
3985         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3986
3987         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3988
3989         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3990                    "Configured MIN bandwidth to be %d Mb/sec\n",
3991                    p_link->min_pf_rate);
3992
3993         return rc;
3994 }
3995
3996 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3997 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
3998 {
3999         int i, rc = -EINVAL;
4000
4001         if (min_bw < 1 || min_bw > 100) {
4002                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4003                 return rc;
4004         }
4005
4006         for_each_hwfn(cdev, i) {
4007                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4008                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4009                 struct qed_mcp_link_state *p_link;
4010                 struct qed_ptt *p_ptt;
4011
4012                 p_link = &p_lead->mcp_info->link_output;
4013
4014                 p_ptt = qed_ptt_acquire(p_hwfn);
4015                 if (!p_ptt)
4016                         return -EBUSY;
4017
4018                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4019                                                       p_link, min_bw);
4020                 if (rc) {
4021                         qed_ptt_release(p_hwfn, p_ptt);
4022                         return rc;
4023                 }
4024
4025                 if (p_link->min_pf_rate) {
4026                         u32 min_rate = p_link->min_pf_rate;
4027
4028                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4029                                                                    p_ptt,
4030                                                                    min_rate);
4031                 }
4032
4033                 qed_ptt_release(p_hwfn, p_ptt);
4034         }
4035
4036         return rc;
4037 }
4038
4039 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4040 {
4041         struct qed_mcp_link_state *p_link;
4042
4043         p_link = &p_hwfn->mcp_info->link_output;
4044
4045         if (p_link->min_pf_rate)
4046                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4047                                                p_link->min_pf_rate);
4048
4049         memset(p_hwfn->qm_info.wfq_data, 0,
4050                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4051 }
4052
4053 int qed_device_num_engines(struct qed_dev *cdev)
4054 {
4055         return QED_IS_BB(cdev) ? 2 : 1;
4056 }
4057
4058 static int qed_device_num_ports(struct qed_dev *cdev)
4059 {
4060         /* in CMT always only one port */
4061         if (cdev->num_hwfns > 1)
4062                 return 1;
4063
4064         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4065 }
4066
4067 int qed_device_get_port_id(struct qed_dev *cdev)
4068 {
4069         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4070 }