drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  73                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  74 {
  75         u32 bar_reg = (bar_id == BAR_ID_0 ?
  76                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  77         u32 val;
  78
  79         if (IS_VF(p_hwfn->cdev))
  80                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
  81
  82         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  83         if (val)
  84                 return 1 << (val + 15);
  85
  86         /* Old MFW initialized above registered only conditionally */
  87         if (p_hwfn->cdev->num_hwfns > 1) {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  90                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  91         } else {
  92                 DP_INFO(p_hwfn,
  93                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  94                         return 512 * 1024;
  95         }
  96 }
  97
  98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  99 {
 100         u32 i;
 101
 102         cdev->dp_level = dp_level;
 103         cdev->dp_module = dp_module;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109         }
 110 }
 111
 112 void qed_init_struct(struct qed_dev *cdev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 118
 119                 p_hwfn->cdev = cdev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 mutex_init(&p_hwfn->dmae_info.mutex);
 124         }
 125
 126         /* hwfn 0 is always active */
 127         cdev->hwfns[0].b_active = true;
 128
 129         /* set the default cache alignment to 128 */
 130         cdev->cache_shift = 7;
 131 }
 132
 133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 134 {
 135         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 136
 137         kfree(qm_info->qm_pq_params);
 138         qm_info->qm_pq_params = NULL;
 139         kfree(qm_info->qm_vport_params);
 140         qm_info->qm_vport_params = NULL;
 141         kfree(qm_info->qm_port_params);
 142         qm_info->qm_port_params = NULL;
 143         kfree(qm_info->wfq_data);
 144         qm_info->wfq_data = NULL;
 145 }
 146
 147 void qed_resc_free(struct qed_dev *cdev)
 148 {
 149         int i;
 150
 151         if (IS_VF(cdev)) {
 152                 for_each_hwfn(cdev, i)
 153                         qed_l2_free(&cdev->hwfns[i]);
 154                 return;
 155         }
 156
 157         kfree(cdev->fw_data);
 158         cdev->fw_data = NULL;
 159
 160         kfree(cdev->reset_stats);
 161         cdev->reset_stats = NULL;
 162
 163         for_each_hwfn(cdev, i) {
 164                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 165
 166                 qed_cxt_mngr_free(p_hwfn);
 167                 qed_qm_info_free(p_hwfn);
 168                 qed_spq_free(p_hwfn);
 169                 qed_eq_free(p_hwfn);
 170                 qed_consq_free(p_hwfn);
 171                 qed_int_free(p_hwfn);
 172 #ifdef CONFIG_QED_LL2
 173                 qed_ll2_free(p_hwfn);
 174 #endif
 175                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 176                         qed_fcoe_free(p_hwfn);
 177
 178                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 179                         qed_iscsi_free(p_hwfn);
 180                         qed_ooo_free(p_hwfn);
 181                 }
 182                 qed_iov_free(p_hwfn);
 183                 qed_l2_free(p_hwfn);
 184                 qed_dmae_info_free(p_hwfn);
 185                 qed_dcbx_info_free(p_hwfn);
 186         }
 187 }
 188
 189 /******************** QM initialization *******************/
 190 #define ACTIVE_TCS_BMAP 0x9f
 191 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 192
 193 /* determines the physical queue flags for a given PF. */
 194 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 195 {
 196         u32 flags;
 197
 198         /* common flags */
 199         flags = PQ_FLAGS_LB;
 200
 201         /* feature flags */
 202         if (IS_QED_SRIOV(p_hwfn->cdev))
 203                 flags |= PQ_FLAGS_VFS;
 204
 205         /* protocol flags */
 206         switch (p_hwfn->hw_info.personality) {
 207         case QED_PCI_ETH:
 208                 flags |= PQ_FLAGS_MCOS;
 209                 break;
 210         case QED_PCI_FCOE:
 211                 flags |= PQ_FLAGS_OFLD;
 212                 break;
 213         case QED_PCI_ISCSI:
 214                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 215                 break;
 216         case QED_PCI_ETH_ROCE:
 217                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 218                 break;
 219         default:
 220                 DP_ERR(p_hwfn,
 221                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 222                 return 0;
 223         }
 224
 225         return flags;
 226 }
 227
 228 /* Getters for resource amounts necessary for qm initialization */
 229 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 230 {
 231         return p_hwfn->hw_info.num_hw_tc;
 232 }
 233
 234 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 235 {
 236         return IS_QED_SRIOV(p_hwfn->cdev) ?
 237                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 238 }
 239
 240 #define NUM_DEFAULT_RLS 1
 241
 242 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 243 {
 244         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 245
 246         /* num RLs can't exceed resource amount of rls or vports */
 247         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 248                                  RESC_NUM(p_hwfn, QED_VPORT));
 249
 250         /* Make sure after we reserve there's something left */
 251         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 252                 return 0;
 253
 254         /* subtract rls necessary for VFs and one default one for the PF */
 255         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 256
 257         return num_pf_rls;
 258 }
 259
 260 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 261 {
 262         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 263
 264         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 265         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 266                qed_init_qm_get_num_pf_rls(p_hwfn) +
 267                (!!(PQ_FLAGS_VFS & pq_flags)) *
 268                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 269 }
 270
 271 /* calc amount of PQs according to the requested flags */
 272 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 273 {
 274         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 275
 276         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 277                qed_init_qm_get_num_pf_rls(p_hwfn) +
 278                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 279                qed_init_qm_get_num_tcs(p_hwfn) +
 280                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 281                (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
 282                (!!(PQ_FLAGS_LLT & pq_flags)) +
 283                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 284 }
 285
 286 /* initialize the top level QM params */
 287 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 288 {
 289         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 290         bool four_port;
 291
 292         /* pq and vport bases for this PF */
 293         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 294         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 295
 296         /* rate limiting and weighted fair queueing are always enabled */
 297         qm_info->vport_rl_en = 1;
 298         qm_info->vport_wfq_en = 1;
 299
 300         /* TC config is different for AH 4 port */
 301         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 302
 303         /* in AH 4 port we have fewer TCs per port */
 304         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 305                                                      NUM_OF_PHYS_TCS;
 306
 307         /* unless MFW indicated otherwise, ooo_tc == 3 for
 308          * AH 4-port and 4 otherwise.
 309          */
 310         if (!qm_info->ooo_tc)
 311                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 312                                               DCBX_TCP_OOO_TC;
 313 }
 314
 315 /* initialize qm vport params */
 316 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 317 {
 318         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 319         u8 i;
 320
 321         /* all vports participate in weighted fair queueing */
 322         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 323                 qm_info->qm_vport_params[i].vport_wfq = 1;
 324 }
 325
 326 /* initialize qm port params */
 327 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 328 {
 329         /* Initialize qm port parameters */
 330         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 331
 332         /* indicate how ooo and high pri traffic is dealt with */
 333         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 334                           ACTIVE_TCS_BMAP_4PORT_K2 :
 335                           ACTIVE_TCS_BMAP;
 336
 337         for (i = 0; i < num_ports; i++) {
 338                 struct init_qm_port_params *p_qm_port =
 339                     &p_hwfn->qm_info.qm_port_params[i];
 340
 341                 p_qm_port->active = 1;
 342                 p_qm_port->active_phys_tcs = active_phys_tcs;
 343                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 344                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 345         }
 346 }
 347
 348 /* Reset the params which must be reset for qm init. QM init may be called as
 349  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 350  * params may be affected by the init but would simply recalculate to the same
 351  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 352  * affected as these amounts stay the same.
 353  */
 354 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 355 {
 356         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 357
 358         qm_info->num_pqs = 0;
 359         qm_info->num_vports = 0;
 360         qm_info->num_pf_rls = 0;
 361         qm_info->num_vf_pqs = 0;
 362         qm_info->first_vf_pq = 0;
 363         qm_info->first_mcos_pq = 0;
 364         qm_info->first_rl_pq = 0;
 365 }
 366
 367 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 368 {
 369         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 370
 371         qm_info->num_vports++;
 372
 373         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 374                 DP_ERR(p_hwfn,
 375                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 376                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 377 }
 378
 379 /* initialize a single pq and manage qm_info resources accounting.
 380  * The pq_init_flags param determines whether the PQ is rate limited
 381  * (for VF or PF) and whether a new vport is allocated to the pq or not
 382  * (i.e. vport will be shared).
 383  */
 384
 385 /* flags for pq init */
 386 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 387 #define PQ_INIT_PF_RL           (1 << 1)
 388 #define PQ_INIT_VF_RL           (1 << 2)
 389
 390 /* defines for pq init */
 391 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 392 #define PQ_INIT_DEFAULT_TC              0
 393 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 394
 395 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 396                            struct qed_qm_info *qm_info,
 397                            u8 tc, u32 pq_init_flags)
 398 {
 399         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 400
 401         if (pq_idx > max_pq)
 402                 DP_ERR(p_hwfn,
 403                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 404
 405         /* init pq params */
 406         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 407             qm_info->num_vports;
 408         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 409         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 410         qm_info->qm_pq_params[pq_idx].rl_valid =
 411             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 412
 413         /* qm params accounting */
 414         qm_info->num_pqs++;
 415         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 416                 qm_info->num_vports++;
 417
 418         if (pq_init_flags & PQ_INIT_PF_RL)
 419                 qm_info->num_pf_rls++;
 420
 421         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 422                 DP_ERR(p_hwfn,
 423                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 424                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 425
 426         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 427                 DP_ERR(p_hwfn,
 428                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 429                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 430 }
 431
 432 /* get pq index according to PQ_FLAGS */
 433 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 434                                            u32 pq_flags)
 435 {
 436         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 437
 438         /* Can't have multiple flags set here */
 439         if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
 440                 goto err;
 441
 442         switch (pq_flags) {
 443         case PQ_FLAGS_RLS:
 444                 return &qm_info->first_rl_pq;
 445         case PQ_FLAGS_MCOS:
 446                 return &qm_info->first_mcos_pq;
 447         case PQ_FLAGS_LB:
 448                 return &qm_info->pure_lb_pq;
 449         case PQ_FLAGS_OOO:
 450                 return &qm_info->ooo_pq;
 451         case PQ_FLAGS_ACK:
 452                 return &qm_info->pure_ack_pq;
 453         case PQ_FLAGS_OFLD:
 454                 return &qm_info->offload_pq;
 455         case PQ_FLAGS_LLT:
 456                 return &qm_info->low_latency_pq;
 457         case PQ_FLAGS_VFS:
 458                 return &qm_info->first_vf_pq;
 459         default:
 460                 goto err;
 461         }
 462
 463 err:
 464         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 465         return NULL;
 466 }
 467
 468 /* save pq index in qm info */
 469 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 470                                 u32 pq_flags, u16 pq_val)
 471 {
 472         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 473
 474         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 475 }
 476
 477 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 478 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 479 {
 480         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 481
 482         return *base_pq_idx + CM_TX_PQ_BASE;
 483 }
 484
 485 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 486 {
 487         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 488
 489         if (tc > max_tc)
 490                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 491
 492         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 493 }
 494
 495 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 496 {
 497         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 498
 499         if (vf > max_vf)
 500                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 501
 502         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 503 }
 504
 505 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
 506 {
 507         u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
 508
 509         if (rl > max_rl)
 510                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 511
 512         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 513 }
 514
 515 /* Functions for creating specific types of pqs */
 516 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 517 {
 518         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 519
 520         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 521                 return;
 522
 523         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 524         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 525 }
 526
 527 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 528 {
 529         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 530
 531         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 532                 return;
 533
 534         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 535         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 536 }
 537
 538 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 539 {
 540         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 541
 542         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 543                 return;
 544
 545         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 546         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 547 }
 548
 549 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 550 {
 551         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 552
 553         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 554                 return;
 555
 556         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 557         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 558 }
 559
 560 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 561 {
 562         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 563
 564         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 565                 return;
 566
 567         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 568         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 569 }
 570
 571 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 572 {
 573         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 574         u8 tc_idx;
 575
 576         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 577                 return;
 578
 579         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 580         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 581                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 582 }
 583
 584 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 585 {
 586         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 587         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 588
 589         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 590                 return;
 591
 592         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 593         qm_info->num_vf_pqs = num_vfs;
 594         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 595                 qed_init_qm_pq(p_hwfn,
 596                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 597 }
 598
 599 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 600 {
 601         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 602         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 603
 604         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 605                 return;
 606
 607         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 608         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 609                 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
 610 }
 611
 612 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 613 {
 614         /* rate limited pqs, must come first (FW assumption) */
 615         qed_init_qm_rl_pqs(p_hwfn);
 616
 617         /* pqs for multi cos */
 618         qed_init_qm_mcos_pqs(p_hwfn);
 619
 620         /* pure loopback pq */
 621         qed_init_qm_lb_pq(p_hwfn);
 622
 623         /* out of order pq */
 624         qed_init_qm_ooo_pq(p_hwfn);
 625
 626         /* pure ack pq */
 627         qed_init_qm_pure_ack_pq(p_hwfn);
 628
 629         /* pq for offloaded protocol */
 630         qed_init_qm_offload_pq(p_hwfn);
 631
 632         /* low latency pq */
 633         qed_init_qm_low_latency_pq(p_hwfn);
 634
 635         /* done sharing vports */
 636         qed_init_qm_advance_vport(p_hwfn);
 637
 638         /* pqs for vfs */
 639         qed_init_qm_vf_pqs(p_hwfn);
 640 }
 641
 642 /* compare values of getters against resources amounts */
 643 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 644 {
 645         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 646                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 647                 return -EINVAL;
 648         }
 649
 650         if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
 651                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 652                 return -EINVAL;
 653         }
 654
 655         return 0;
 656 }
 657
 658 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 659 {
 660         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 661         struct init_qm_vport_params *vport;
 662         struct init_qm_port_params *port;
 663         struct init_qm_pq_params *pq;
 664         int i, tc;
 665
 666         /* top level params */
 667         DP_VERBOSE(p_hwfn,
 668                    NETIF_MSG_HW,
 669                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 670                    qm_info->start_pq,
 671                    qm_info->start_vport,
 672                    qm_info->pure_lb_pq,
 673                    qm_info->offload_pq, qm_info->pure_ack_pq);
 674         DP_VERBOSE(p_hwfn,
 675                    NETIF_MSG_HW,
 676                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 677                    qm_info->ooo_pq,
 678                    qm_info->first_vf_pq,
 679                    qm_info->num_pqs,
 680                    qm_info->num_vf_pqs,
 681                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 682         DP_VERBOSE(p_hwfn,
 683                    NETIF_MSG_HW,
 684                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 685                    qm_info->pf_rl_en,
 686                    qm_info->pf_wfq_en,
 687                    qm_info->vport_rl_en,
 688                    qm_info->vport_wfq_en,
 689                    qm_info->pf_wfq,
 690                    qm_info->pf_rl,
 691                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 692
 693         /* port table */
 694         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 695                 port = &(qm_info->qm_port_params[i]);
 696                 DP_VERBOSE(p_hwfn,
 697                            NETIF_MSG_HW,
 698                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 699                            i,
 700                            port->active,
 701                            port->active_phys_tcs,
 702                            port->num_pbf_cmd_lines,
 703                            port->num_btb_blocks, port->reserved);
 704         }
 705
 706         /* vport table */
 707         for (i = 0; i < qm_info->num_vports; i++) {
 708                 vport = &(qm_info->qm_vport_params[i]);
 709                 DP_VERBOSE(p_hwfn,
 710                            NETIF_MSG_HW,
 711                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 712                            qm_info->start_vport + i,
 713                            vport->vport_rl, vport->vport_wfq);
 714                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 715                         DP_VERBOSE(p_hwfn,
 716                                    NETIF_MSG_HW,
 717                                    "%d ", vport->first_tx_pq_id[tc]);
 718                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 719         }
 720
 721         /* pq table */
 722         for (i = 0; i < qm_info->num_pqs; i++) {
 723                 pq = &(qm_info->qm_pq_params[i]);
 724                 DP_VERBOSE(p_hwfn,
 725                            NETIF_MSG_HW,
 726                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 727                            qm_info->start_pq + i,
 728                            pq->vport_id,
 729                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 730         }
 731 }
 732
 733 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 734 {
 735         /* reset params required for init run */
 736         qed_init_qm_reset_params(p_hwfn);
 737
 738         /* init QM top level params */
 739         qed_init_qm_params(p_hwfn);
 740
 741         /* init QM port params */
 742         qed_init_qm_port_params(p_hwfn);
 743
 744         /* init QM vport params */
 745         qed_init_qm_vport_params(p_hwfn);
 746
 747         /* init QM physical queue params */
 748         qed_init_qm_pq_params(p_hwfn);
 749
 750         /* display all that init */
 751         qed_dp_init_qm_params(p_hwfn);
 752 }
 753
 754 /* This function reconfigures the QM pf on the fly.
 755  * For this purpose we:
 756  * 1. reconfigure the QM database
 757  * 2. set new values to runtime arrat
 758  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 759  * 4. activate init tool in QM_PF stage
 760  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 761  */
 762 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 763 {
 764         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 765         bool b_rc;
 766         int rc;
 767
 768         /* initialize qed's qm data structure */
 769         qed_init_qm_info(p_hwfn);
 770
 771         /* stop PF's qm queues */
 772         spin_lock_bh(&qm_lock);
 773         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 774                                     qm_info->start_pq, qm_info->num_pqs);
 775         spin_unlock_bh(&qm_lock);
 776         if (!b_rc)
 777                 return -EINVAL;
 778
 779         /* clear the QM_PF runtime phase leftovers from previous init */
 780         qed_init_clear_rt_data(p_hwfn);
 781
 782         /* prepare QM portion of runtime array */
 783         qed_qm_init_pf(p_hwfn, p_ptt);
 784
 785         /* activate init tool on runtime array */
 786         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 787                           p_hwfn->hw_info.hw_mode);
 788         if (rc)
 789                 return rc;
 790
 791         /* start PF's qm queues */
 792         spin_lock_bh(&qm_lock);
 793         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 794                                     qm_info->start_pq, qm_info->num_pqs);
 795         spin_unlock_bh(&qm_lock);
 796         if (!b_rc)
 797                 return -EINVAL;
 798
 799         return 0;
 800 }
 801
 802 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 803 {
 804         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 805         int rc;
 806
 807         rc = qed_init_qm_sanity(p_hwfn);
 808         if (rc)
 809                 goto alloc_err;
 810
 811         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 812                                         qed_init_qm_get_num_pqs(p_hwfn),
 813                                         GFP_KERNEL);
 814         if (!qm_info->qm_pq_params)
 815                 goto alloc_err;
 816
 817         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 818                                            qed_init_qm_get_num_vports(p_hwfn),
 819                                            GFP_KERNEL);
 820         if (!qm_info->qm_vport_params)
 821                 goto alloc_err;
 822
 823         qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
 824                                           p_hwfn->cdev->num_ports_in_engine,
 825                                           GFP_KERNEL);
 826         if (!qm_info->qm_port_params)
 827                 goto alloc_err;
 828
 829         qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
 830                                     qed_init_qm_get_num_vports(p_hwfn),
 831                                     GFP_KERNEL);
 832         if (!qm_info->wfq_data)
 833                 goto alloc_err;
 834
 835         return 0;
 836
 837 alloc_err:
 838         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 839         qed_qm_info_free(p_hwfn);
 840         return -ENOMEM;
 841 }
 842
 843 int qed_resc_alloc(struct qed_dev *cdev)
 844 {
 845         u32 rdma_tasks, excess_tasks;
 846         u32 line_count;
 847         int i, rc = 0;
 848
 849         if (IS_VF(cdev)) {
 850                 for_each_hwfn(cdev, i) {
 851                         rc = qed_l2_alloc(&cdev->hwfns[i]);
 852                         if (rc)
 853                                 return rc;
 854                 }
 855                 return rc;
 856         }
 857
 858         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 859         if (!cdev->fw_data)
 860                 return -ENOMEM;
 861
 862         for_each_hwfn(cdev, i) {
 863                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 864                 u32 n_eqes, num_cons;
 865
 866                 /* First allocate the context manager structure */
 867                 rc = qed_cxt_mngr_alloc(p_hwfn);
 868                 if (rc)
 869                         goto alloc_err;
 870
 871                 /* Set the HW cid/tid numbers (in the contest manager)
 872                  * Must be done prior to any further computations.
 873                  */
 874                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 875                 if (rc)
 876                         goto alloc_err;
 877
 878                 rc = qed_alloc_qm_data(p_hwfn);
 879                 if (rc)
 880                         goto alloc_err;
 881
 882                 /* init qm info */
 883                 qed_init_qm_info(p_hwfn);
 884
 885                 /* Compute the ILT client partition */
 886                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 887                 if (rc) {
 888                         DP_NOTICE(p_hwfn,
 889                                   "too many ILT lines; re-computing with less lines\n");
 890                         /* In case there are not enough ILT lines we reduce the
 891                          * number of RDMA tasks and re-compute.
 892                          */
 893                         excess_tasks =
 894                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 895                         if (!excess_tasks)
 896                                 goto alloc_err;
 897
 898                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 899                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 900                         if (rc)
 901                                 goto alloc_err;
 902
 903                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 904                         if (rc) {
 905                                 DP_ERR(p_hwfn,
 906                                        "failed ILT compute. Requested too many lines: %u\n",
 907                                        line_count);
 908
 909                                 goto alloc_err;
 910                         }
 911                 }
 912
 913                 /* CID map / ILT shadow table / T2
 914                  * The talbes sizes are determined by the computations above
 915                  */
 916                 rc = qed_cxt_tables_alloc(p_hwfn);
 917                 if (rc)
 918                         goto alloc_err;
 919
 920                 /* SPQ, must follow ILT because initializes SPQ context */
 921                 rc = qed_spq_alloc(p_hwfn);
 922                 if (rc)
 923                         goto alloc_err;
 924
 925                 /* SP status block allocation */
 926                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 927                                                          RESERVED_PTT_DPC);
 928
 929                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 930                 if (rc)
 931                         goto alloc_err;
 932
 933                 rc = qed_iov_alloc(p_hwfn);
 934                 if (rc)
 935                         goto alloc_err;
 936
 937                 /* EQ */
 938                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 939                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
 940                         enum protocol_type rdma_proto;
 941
 942                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
 943                                 rdma_proto = PROTOCOLID_ROCE;
 944                         else
 945                                 rdma_proto = PROTOCOLID_IWARP;
 946
 947                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 948                                                                rdma_proto,
 949                                                                NULL) * 2;
 950                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 951                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 952                         num_cons =
 953                             qed_cxt_get_proto_cid_count(p_hwfn,
 954                                                         PROTOCOLID_ISCSI,
 955                                                         NULL);
 956                         n_eqes += 2 * num_cons;
 957                 }
 958
 959                 if (n_eqes > 0xFFFF) {
 960                         DP_ERR(p_hwfn,
 961                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 962                                n_eqes, 0xFFFF);
 963                         goto alloc_no_mem;
 964                 }
 965
 966                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 967                 if (rc)
 968                         goto alloc_err;
 969
 970                 rc = qed_consq_alloc(p_hwfn);
 971                 if (rc)
 972                         goto alloc_err;
 973
 974                 rc = qed_l2_alloc(p_hwfn);
 975                 if (rc)
 976                         goto alloc_err;
 977
 978 #ifdef CONFIG_QED_LL2
 979                 if (p_hwfn->using_ll2) {
 980                         rc = qed_ll2_alloc(p_hwfn);
 981                         if (rc)
 982                                 goto alloc_err;
 983                 }
 984 #endif
 985
 986                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
 987                         rc = qed_fcoe_alloc(p_hwfn);
 988                         if (rc)
 989                                 goto alloc_err;
 990                 }
 991
 992                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 993                         rc = qed_iscsi_alloc(p_hwfn);
 994                         if (rc)
 995                                 goto alloc_err;
 996                         rc = qed_ooo_alloc(p_hwfn);
 997                         if (rc)
 998                                 goto alloc_err;
 999                 }
1000
1001                 /* DMA info initialization */
1002                 rc = qed_dmae_info_alloc(p_hwfn);
1003                 if (rc)
1004                         goto alloc_err;
1005
1006                 /* DCBX initialization */
1007                 rc = qed_dcbx_info_alloc(p_hwfn);
1008                 if (rc)
1009                         goto alloc_err;
1010         }
1011
1012         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1013         if (!cdev->reset_stats)
1014                 goto alloc_no_mem;
1015
1016         return 0;
1017
1018 alloc_no_mem:
1019         rc = -ENOMEM;
1020 alloc_err:
1021         qed_resc_free(cdev);
1022         return rc;
1023 }
1024
1025 void qed_resc_setup(struct qed_dev *cdev)
1026 {
1027         int i;
1028
1029         if (IS_VF(cdev)) {
1030                 for_each_hwfn(cdev, i)
1031                         qed_l2_setup(&cdev->hwfns[i]);
1032                 return;
1033         }
1034
1035         for_each_hwfn(cdev, i) {
1036                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1037
1038                 qed_cxt_mngr_setup(p_hwfn);
1039                 qed_spq_setup(p_hwfn);
1040                 qed_eq_setup(p_hwfn);
1041                 qed_consq_setup(p_hwfn);
1042
1043                 /* Read shadow of current MFW mailbox */
1044                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1045                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1046                        p_hwfn->mcp_info->mfw_mb_cur,
1047                        p_hwfn->mcp_info->mfw_mb_length);
1048
1049                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1050
1051                 qed_l2_setup(p_hwfn);
1052                 qed_iov_setup(p_hwfn);
1053 #ifdef CONFIG_QED_LL2
1054                 if (p_hwfn->using_ll2)
1055                         qed_ll2_setup(p_hwfn);
1056 #endif
1057                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1058                         qed_fcoe_setup(p_hwfn);
1059
1060                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1061                         qed_iscsi_setup(p_hwfn);
1062                         qed_ooo_setup(p_hwfn);
1063                 }
1064         }
1065 }
1066
1067 #define FINAL_CLEANUP_POLL_CNT          (100)
1068 #define FINAL_CLEANUP_POLL_TIME         (10)
1069 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1070                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1071 {
1072         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1073         int rc = -EBUSY;
1074
1075         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1076                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1077
1078         if (is_vf)
1079                 id += 0x10;
1080
1081         command |= X_FINAL_CLEANUP_AGG_INT <<
1082                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1083         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1084         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1085         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1086
1087         /* Make sure notification is not set before initiating final cleanup */
1088         if (REG_RD(p_hwfn, addr)) {
1089                 DP_NOTICE(p_hwfn,
1090                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1091                 REG_WR(p_hwfn, addr, 0);
1092         }
1093
1094         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1095                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1096                    id, command);
1097
1098         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1099
1100         /* Poll until completion */
1101         while (!REG_RD(p_hwfn, addr) && count--)
1102                 msleep(FINAL_CLEANUP_POLL_TIME);
1103
1104         if (REG_RD(p_hwfn, addr))
1105                 rc = 0;
1106         else
1107                 DP_NOTICE(p_hwfn,
1108                           "Failed to receive FW final cleanup notification\n");
1109
1110         /* Cleanup afterwards */
1111         REG_WR(p_hwfn, addr, 0);
1112
1113         return rc;
1114 }
1115
1116 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1117 {
1118         int hw_mode = 0;
1119
1120         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1121                 hw_mode |= 1 << MODE_BB;
1122         } else if (QED_IS_AH(p_hwfn->cdev)) {
1123                 hw_mode |= 1 << MODE_K2;
1124         } else {
1125                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1126                           p_hwfn->cdev->type);
1127                 return -EINVAL;
1128         }
1129
1130         switch (p_hwfn->cdev->num_ports_in_engine) {
1131         case 1:
1132                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1133                 break;
1134         case 2:
1135                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1136                 break;
1137         case 4:
1138                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1139                 break;
1140         default:
1141                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1142                           p_hwfn->cdev->num_ports_in_engine);
1143                 return -EINVAL;
1144         }
1145
1146         switch (p_hwfn->cdev->mf_mode) {
1147         case QED_MF_DEFAULT:
1148         case QED_MF_NPAR:
1149                 hw_mode |= 1 << MODE_MF_SI;
1150                 break;
1151         case QED_MF_OVLAN:
1152                 hw_mode |= 1 << MODE_MF_SD;
1153                 break;
1154         default:
1155                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1156                 hw_mode |= 1 << MODE_MF_SI;
1157         }
1158
1159         hw_mode |= 1 << MODE_ASIC;
1160
1161         if (p_hwfn->cdev->num_hwfns > 1)
1162                 hw_mode |= 1 << MODE_100G;
1163
1164         p_hwfn->hw_info.hw_mode = hw_mode;
1165
1166         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1167                    "Configuring function for hw_mode: 0x%08x\n",
1168                    p_hwfn->hw_info.hw_mode);
1169
1170         return 0;
1171 }
1172
1173 /* Init run time data for all PFs on an engine. */
1174 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1175 {
1176         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1177         int i, igu_sb_id;
1178
1179         for_each_hwfn(cdev, i) {
1180                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1181                 struct qed_igu_info *p_igu_info;
1182                 struct qed_igu_block *p_block;
1183                 struct cau_sb_entry sb_entry;
1184
1185                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1186
1187                 for (igu_sb_id = 0;
1188                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1189                         p_block = &p_igu_info->entry[igu_sb_id];
1190
1191                         if (!p_block->is_pf)
1192                                 continue;
1193
1194                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1195                                               p_block->function_id, 0, 0);
1196                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1197                                          sb_entry);
1198                 }
1199         }
1200 }
1201
1202 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1203                                      struct qed_ptt *p_ptt)
1204 {
1205         u32 val, wr_mbs, cache_line_size;
1206
1207         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1208         switch (val) {
1209         case 0:
1210                 wr_mbs = 128;
1211                 break;
1212         case 1:
1213                 wr_mbs = 256;
1214                 break;
1215         case 2:
1216                 wr_mbs = 512;
1217                 break;
1218         default:
1219                 DP_INFO(p_hwfn,
1220                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1221                         val);
1222                 return;
1223         }
1224
1225         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1226         switch (cache_line_size) {
1227         case 32:
1228                 val = 0;
1229                 break;
1230         case 64:
1231                 val = 1;
1232                 break;
1233         case 128:
1234                 val = 2;
1235                 break;
1236         case 256:
1237                 val = 3;
1238                 break;
1239         default:
1240                 DP_INFO(p_hwfn,
1241                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1242                         cache_line_size);
1243         }
1244
1245         if (L1_CACHE_BYTES > wr_mbs)
1246                 DP_INFO(p_hwfn,
1247                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1248                         L1_CACHE_BYTES, wr_mbs);
1249
1250         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1251         if (val > 0) {
1252                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1253                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1254         }
1255 }
1256
1257 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1258                               struct qed_ptt *p_ptt, int hw_mode)
1259 {
1260         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1261         struct qed_qm_common_rt_init_params params;
1262         struct qed_dev *cdev = p_hwfn->cdev;
1263         u8 vf_id, max_num_vfs;
1264         u16 num_pfs, pf_id;
1265         u32 concrete_fid;
1266         int rc = 0;
1267
1268         qed_init_cau_rt_data(cdev);
1269
1270         /* Program GTT windows */
1271         qed_gtt_init(p_hwfn);
1272
1273         if (p_hwfn->mcp_info) {
1274                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1275                         qm_info->pf_rl_en = 1;
1276                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1277                         qm_info->pf_wfq_en = 1;
1278         }
1279
1280         memset(&params, 0, sizeof(params));
1281         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1282         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1283         params.pf_rl_en = qm_info->pf_rl_en;
1284         params.pf_wfq_en = qm_info->pf_wfq_en;
1285         params.vport_rl_en = qm_info->vport_rl_en;
1286         params.vport_wfq_en = qm_info->vport_wfq_en;
1287         params.port_params = qm_info->qm_port_params;
1288
1289         qed_qm_common_rt_init(p_hwfn, &params);
1290
1291         qed_cxt_hw_init_common(p_hwfn);
1292
1293         qed_init_cache_line_size(p_hwfn, p_ptt);
1294
1295         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1296         if (rc)
1297                 return rc;
1298
1299         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1300         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1301
1302         if (QED_IS_BB(p_hwfn->cdev)) {
1303                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1304                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1305                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1306                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1307                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1308                 }
1309                 /* pretend to original PF */
1310                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1311         }
1312
1313         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1314         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1315                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1316                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1317                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1318                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1319                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1320                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1321         }
1322         /* pretend to original PF */
1323         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1324
1325         return rc;
1326 }
1327
1328 static int
1329 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1330                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1331 {
1332         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1333         u32 min_dpis;
1334         u32 n_wids;
1335
1336         /* Calculate DPI size */
1337         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1338         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1339         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1340         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1341         dpi_count = pwm_region_size / dpi_page_size;
1342
1343         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1344         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1345
1346         p_hwfn->dpi_size = dpi_page_size;
1347         p_hwfn->dpi_count = dpi_count;
1348
1349         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1350
1351         if (dpi_count < min_dpis)
1352                 return -EINVAL;
1353
1354         return 0;
1355 }
1356
1357 enum QED_ROCE_EDPM_MODE {
1358         QED_ROCE_EDPM_MODE_ENABLE = 0,
1359         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1360         QED_ROCE_EDPM_MODE_DISABLE = 2,
1361 };
1362
1363 static int
1364 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1365 {
1366         u32 pwm_regsize, norm_regsize;
1367         u32 non_pwm_conn, min_addr_reg1;
1368         u32 db_bar_size, n_cpus = 1;
1369         u32 roce_edpm_mode;
1370         u32 pf_dems_shift;
1371         int rc = 0;
1372         u8 cond;
1373
1374         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1375         if (p_hwfn->cdev->num_hwfns > 1)
1376                 db_bar_size /= 2;
1377
1378         /* Calculate doorbell regions */
1379         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1380                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1381                                                    NULL) +
1382                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1383                                                    NULL);
1384         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1385         min_addr_reg1 = norm_regsize / 4096;
1386         pwm_regsize = db_bar_size - norm_regsize;
1387
1388         /* Check that the normal and PWM sizes are valid */
1389         if (db_bar_size < norm_regsize) {
1390                 DP_ERR(p_hwfn->cdev,
1391                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1392                        db_bar_size, norm_regsize);
1393                 return -EINVAL;
1394         }
1395
1396         if (pwm_regsize < QED_MIN_PWM_REGION) {
1397                 DP_ERR(p_hwfn->cdev,
1398                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1399                        pwm_regsize,
1400                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1401                 return -EINVAL;
1402         }
1403
1404         /* Calculate number of DPIs */
1405         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1406         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1407             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1408                 /* Either EDPM is mandatory, or we are attempting to allocate a
1409                  * WID per CPU.
1410                  */
1411                 n_cpus = num_present_cpus();
1412                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1413         }
1414
1415         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1416                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1417         if (cond || p_hwfn->dcbx_no_edpm) {
1418                 /* Either EDPM is disabled from user configuration, or it is
1419                  * disabled via DCBx, or it is not mandatory and we failed to
1420                  * allocated a WID per CPU.
1421                  */
1422                 n_cpus = 1;
1423                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1424
1425                 if (cond)
1426                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1427         }
1428
1429         p_hwfn->wid_count = (u16) n_cpus;
1430
1431         DP_INFO(p_hwfn,
1432                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1433                 norm_regsize,
1434                 pwm_regsize,
1435                 p_hwfn->dpi_size,
1436                 p_hwfn->dpi_count,
1437                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1438                 "disabled" : "enabled");
1439
1440         if (rc) {
1441                 DP_ERR(p_hwfn,
1442                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1443                        p_hwfn->dpi_count,
1444                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1445                 return -EINVAL;
1446         }
1447
1448         p_hwfn->dpi_start_offset = norm_regsize;
1449
1450         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1451         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1452         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1453         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1454
1455         return 0;
1456 }
1457
1458 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1459                             struct qed_ptt *p_ptt, int hw_mode)
1460 {
1461         int rc = 0;
1462
1463         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1464         if (rc)
1465                 return rc;
1466
1467         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1468
1469         return 0;
1470 }
1471
1472 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1473                           struct qed_ptt *p_ptt,
1474                           struct qed_tunnel_info *p_tunn,
1475                           int hw_mode,
1476                           bool b_hw_start,
1477                           enum qed_int_mode int_mode,
1478                           bool allow_npar_tx_switch)
1479 {
1480         u8 rel_pf_id = p_hwfn->rel_pf_id;
1481         int rc = 0;
1482
1483         if (p_hwfn->mcp_info) {
1484                 struct qed_mcp_function_info *p_info;
1485
1486                 p_info = &p_hwfn->mcp_info->func_info;
1487                 if (p_info->bandwidth_min)
1488                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1489
1490                 /* Update rate limit once we'll actually have a link */
1491                 p_hwfn->qm_info.pf_rl = 100000;
1492         }
1493
1494         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1495
1496         qed_int_igu_init_rt(p_hwfn);
1497
1498         /* Set VLAN in NIG if needed */
1499         if (hw_mode & BIT(MODE_MF_SD)) {
1500                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1501                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1502                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1503                              p_hwfn->hw_info.ovlan);
1504         }
1505
1506         /* Enable classification by MAC if needed */
1507         if (hw_mode & BIT(MODE_MF_SI)) {
1508                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1509                            "Configuring TAGMAC_CLS_TYPE\n");
1510                 STORE_RT_REG(p_hwfn,
1511                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1512         }
1513
1514         /* Protocl Configuration  */
1515         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1516                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1517         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1518                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1519         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1520
1521         /* Cleanup chip from previous driver if such remains exist */
1522         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1523         if (rc)
1524                 return rc;
1525
1526         /* PF Init sequence */
1527         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1528         if (rc)
1529                 return rc;
1530
1531         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1532         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1533         if (rc)
1534                 return rc;
1535
1536         /* Pure runtime initializations - directly to the HW  */
1537         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1538
1539         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1540         if (rc)
1541                 return rc;
1542
1543         if (b_hw_start) {
1544                 /* enable interrupts */
1545                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1546
1547                 /* send function start command */
1548                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1549                                      p_hwfn->cdev->mf_mode,
1550                                      allow_npar_tx_switch);
1551                 if (rc) {
1552                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1553                         return rc;
1554                 }
1555                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1556                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1557                         qed_wr(p_hwfn, p_ptt,
1558                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1559                                0x100);
1560                 }
1561         }
1562         return rc;
1563 }
1564
1565 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1566                                struct qed_ptt *p_ptt,
1567                                u8 enable)
1568 {
1569         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1570
1571         /* Change PF in PXP */
1572         qed_wr(p_hwfn, p_ptt,
1573                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1574
1575         /* wait until value is set - try for 1 second every 50us */
1576         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1577                 val = qed_rd(p_hwfn, p_ptt,
1578                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1579                 if (val == set_val)
1580                         break;
1581
1582                 usleep_range(50, 60);
1583         }
1584
1585         if (val != set_val) {
1586                 DP_NOTICE(p_hwfn,
1587                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1588                 return -EAGAIN;
1589         }
1590
1591         return 0;
1592 }
1593
1594 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1595                                 struct qed_ptt *p_main_ptt)
1596 {
1597         /* Read shadow of current MFW mailbox */
1598         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1599         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1600                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1601 }
1602
1603 static void
1604 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1605                          struct qed_drv_load_params *p_drv_load)
1606 {
1607         memset(p_load_req, 0, sizeof(*p_load_req));
1608
1609         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1610                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1611         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1612         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1613         p_load_req->override_force_load = p_drv_load->override_force_load;
1614 }
1615
1616 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1617                         struct qed_hw_init_params *p_params)
1618 {
1619         if (p_params->p_tunn) {
1620                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1621                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1622         }
1623
1624         p_hwfn->b_int_enabled = 1;
1625
1626         return 0;
1627 }
1628
1629 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1630 {
1631         struct qed_load_req_params load_req_params;
1632         u32 load_code, param, drv_mb_param;
1633         bool b_default_mtu = true;
1634         struct qed_hwfn *p_hwfn;
1635         int rc = 0, mfw_rc, i;
1636
1637         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1638                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1639                 return -EINVAL;
1640         }
1641
1642         if (IS_PF(cdev)) {
1643                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1644                 if (rc)
1645                         return rc;
1646         }
1647
1648         for_each_hwfn(cdev, i) {
1649                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1650
1651                 /* If management didn't provide a default, set one of our own */
1652                 if (!p_hwfn->hw_info.mtu) {
1653                         p_hwfn->hw_info.mtu = 1500;
1654                         b_default_mtu = false;
1655                 }
1656
1657                 if (IS_VF(cdev)) {
1658                         qed_vf_start(p_hwfn, p_params);
1659                         continue;
1660                 }
1661
1662                 /* Enable DMAE in PXP */
1663                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1664
1665                 rc = qed_calc_hw_mode(p_hwfn);
1666                 if (rc)
1667                         return rc;
1668
1669                 qed_fill_load_req_params(&load_req_params,
1670                                          p_params->p_drv_load_params);
1671                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1672                                       &load_req_params);
1673                 if (rc) {
1674                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1675                         return rc;
1676                 }
1677
1678                 load_code = load_req_params.load_code;
1679                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1680                            "Load request was sent. Load code: 0x%x\n",
1681                            load_code);
1682
1683                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1684
1685                 p_hwfn->first_on_engine = (load_code ==
1686                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1687
1688                 switch (load_code) {
1689                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1690                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1691                                                 p_hwfn->hw_info.hw_mode);
1692                         if (rc)
1693                                 break;
1694                 /* Fall into */
1695                 case FW_MSG_CODE_DRV_LOAD_PORT:
1696                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1697                                               p_hwfn->hw_info.hw_mode);
1698                         if (rc)
1699                                 break;
1700
1701                 /* Fall into */
1702                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1703                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1704                                             p_params->p_tunn,
1705                                             p_hwfn->hw_info.hw_mode,
1706                                             p_params->b_hw_start,
1707                                             p_params->int_mode,
1708                                             p_params->allow_npar_tx_switch);
1709                         break;
1710                 default:
1711                         DP_NOTICE(p_hwfn,
1712                                   "Unexpected load code [0x%08x]", load_code);
1713                         rc = -EINVAL;
1714                         break;
1715                 }
1716
1717                 if (rc)
1718                         DP_NOTICE(p_hwfn,
1719                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1720                                    load_code, rc);
1721
1722                 /* ACK mfw regardless of success or failure of initialization */
1723                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1724                                      DRV_MSG_CODE_LOAD_DONE,
1725                                      0, &load_code, &param);
1726                 if (rc)
1727                         return rc;
1728                 if (mfw_rc) {
1729                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1730                         return mfw_rc;
1731                 }
1732
1733                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1734                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1735                         DP_NOTICE(p_hwfn,
1736                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1737
1738                 /* send DCBX attention request command */
1739                 DP_VERBOSE(p_hwfn,
1740                            QED_MSG_DCB,
1741                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1742                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1743                                      DRV_MSG_CODE_SET_DCBX,
1744                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1745                                      &load_code, &param);
1746                 if (mfw_rc) {
1747                         DP_NOTICE(p_hwfn,
1748                                   "Failed to send DCBX attention request\n");
1749                         return mfw_rc;
1750                 }
1751
1752                 p_hwfn->hw_init_done = true;
1753         }
1754
1755         if (IS_PF(cdev)) {
1756                 p_hwfn = QED_LEADING_HWFN(cdev);
1757                 drv_mb_param = STORM_FW_VERSION;
1758                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1759                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1760                                  drv_mb_param, &load_code, &param);
1761                 if (rc)
1762                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1763
1764                 if (!b_default_mtu) {
1765                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1766                                                    p_hwfn->hw_info.mtu);
1767                         if (rc)
1768                                 DP_INFO(p_hwfn,
1769                                         "Failed to update default mtu\n");
1770                 }
1771
1772                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1773                                                     p_hwfn->p_main_ptt,
1774                                                   QED_OV_DRIVER_STATE_DISABLED);
1775                 if (rc)
1776                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1777
1778                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1779                                                QED_OV_ESWITCH_VEB);
1780                 if (rc)
1781                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1782         }
1783
1784         return 0;
1785 }
1786
1787 #define QED_HW_STOP_RETRY_LIMIT (10)
1788 static void qed_hw_timers_stop(struct qed_dev *cdev,
1789                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1790 {
1791         int i;
1792
1793         /* close timers */
1794         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1795         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1796
1797         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1798                 if ((!qed_rd(p_hwfn, p_ptt,
1799                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1800                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1801                         break;
1802
1803                 /* Dependent on number of connection/tasks, possibly
1804                  * 1ms sleep is required between polls
1805                  */
1806                 usleep_range(1000, 2000);
1807         }
1808
1809         if (i < QED_HW_STOP_RETRY_LIMIT)
1810                 return;
1811
1812         DP_NOTICE(p_hwfn,
1813                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1814                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1815                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1816 }
1817
1818 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1819 {
1820         int j;
1821
1822         for_each_hwfn(cdev, j) {
1823                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1824                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1825
1826                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1827         }
1828 }
1829
1830 int qed_hw_stop(struct qed_dev *cdev)
1831 {
1832         struct qed_hwfn *p_hwfn;
1833         struct qed_ptt *p_ptt;
1834         int rc, rc2 = 0;
1835         int j;
1836
1837         for_each_hwfn(cdev, j) {
1838                 p_hwfn = &cdev->hwfns[j];
1839                 p_ptt = p_hwfn->p_main_ptt;
1840
1841                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1842
1843                 if (IS_VF(cdev)) {
1844                         qed_vf_pf_int_cleanup(p_hwfn);
1845                         rc = qed_vf_pf_reset(p_hwfn);
1846                         if (rc) {
1847                                 DP_NOTICE(p_hwfn,
1848                                           "qed_vf_pf_reset failed. rc = %d.\n",
1849                                           rc);
1850                                 rc2 = -EINVAL;
1851                         }
1852                         continue;
1853                 }
1854
1855                 /* mark the hw as uninitialized... */
1856                 p_hwfn->hw_init_done = false;
1857
1858                 /* Send unload command to MCP */
1859                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1860                 if (rc) {
1861                         DP_NOTICE(p_hwfn,
1862                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1863                                   rc);
1864                         rc2 = -EINVAL;
1865                 }
1866
1867                 qed_slowpath_irq_sync(p_hwfn);
1868
1869                 /* After this point no MFW attentions are expected, e.g. prevent
1870                  * race between pf stop and dcbx pf update.
1871                  */
1872                 rc = qed_sp_pf_stop(p_hwfn);
1873                 if (rc) {
1874                         DP_NOTICE(p_hwfn,
1875                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1876                                   rc);
1877                         rc2 = -EINVAL;
1878                 }
1879
1880                 qed_wr(p_hwfn, p_ptt,
1881                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1882
1883                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1884                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1885                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1886                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1887                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1888
1889                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1890
1891                 /* Disable Attention Generation */
1892                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1893
1894                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1895                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1896
1897                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1898
1899                 /* Need to wait 1ms to guarantee SBs are cleared */
1900                 usleep_range(1000, 2000);
1901
1902                 /* Disable PF in HW blocks */
1903                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1904                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1905
1906                 qed_mcp_unload_done(p_hwfn, p_ptt);
1907                 if (rc) {
1908                         DP_NOTICE(p_hwfn,
1909                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1910                                   rc);
1911                         rc2 = -EINVAL;
1912                 }
1913         }
1914
1915         if (IS_PF(cdev)) {
1916                 p_hwfn = QED_LEADING_HWFN(cdev);
1917                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1918
1919                 /* Disable DMAE in PXP - in CMT, this should only be done for
1920                  * first hw-function, and only after all transactions have
1921                  * stopped for all active hw-functions.
1922                  */
1923                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1924                 if (rc) {
1925                         DP_NOTICE(p_hwfn,
1926                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1927                         rc2 = -EINVAL;
1928                 }
1929         }
1930
1931         return rc2;
1932 }
1933
1934 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1935 {
1936         int j;
1937
1938         for_each_hwfn(cdev, j) {
1939                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1940                 struct qed_ptt *p_ptt;
1941
1942                 if (IS_VF(cdev)) {
1943                         qed_vf_pf_int_cleanup(p_hwfn);
1944                         continue;
1945                 }
1946                 p_ptt = qed_ptt_acquire(p_hwfn);
1947                 if (!p_ptt)
1948                         return -EAGAIN;
1949
1950                 DP_VERBOSE(p_hwfn,
1951                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1952
1953                 qed_wr(p_hwfn, p_ptt,
1954                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1955
1956                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1957                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1958                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1959                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1960                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1961
1962                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1963
1964                 /* Need to wait 1ms to guarantee SBs are cleared */
1965                 usleep_range(1000, 2000);
1966                 qed_ptt_release(p_hwfn, p_ptt);
1967         }
1968
1969         return 0;
1970 }
1971
1972 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1973 {
1974         struct qed_ptt *p_ptt;
1975
1976         if (IS_VF(p_hwfn->cdev))
1977                 return 0;
1978
1979         p_ptt = qed_ptt_acquire(p_hwfn);
1980         if (!p_ptt)
1981                 return -EAGAIN;
1982
1983         /* If roce info is allocated it means roce is initialized and should
1984          * be enabled in searcher.
1985          */
1986         if (p_hwfn->p_rdma_info &&
1987             p_hwfn->b_rdma_enabled_in_prs)
1988                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
1989
1990         /* Re-open incoming traffic */
1991         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1992         qed_ptt_release(p_hwfn, p_ptt);
1993
1994         return 0;
1995 }
1996
1997 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1998 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1999 {
2000         qed_ptt_pool_free(p_hwfn);
2001         kfree(p_hwfn->hw_info.p_igu_info);
2002         p_hwfn->hw_info.p_igu_info = NULL;
2003 }
2004
2005 /* Setup bar access */
2006 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2007 {
2008         /* clear indirect access */
2009         if (QED_IS_AH(p_hwfn->cdev)) {
2010                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2011                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2012                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2013                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2014                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2015                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2016                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2017                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2018         } else {
2019                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2020                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2021                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2022                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2023                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2024                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2025                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2026                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2027         }
2028
2029         /* Clean Previous errors if such exist */
2030         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2031                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2032
2033         /* enable internal target-read */
2034         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2035                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2036 }
2037
2038 static void get_function_id(struct qed_hwfn *p_hwfn)
2039 {
2040         /* ME Register */
2041         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2042                                                   PXP_PF_ME_OPAQUE_ADDR);
2043
2044         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2045
2046         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2047         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2048                                       PXP_CONCRETE_FID_PFID);
2049         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2050                                     PXP_CONCRETE_FID_PORT);
2051
2052         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2053                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2054                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2055 }
2056
2057 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2058 {
2059         u32 *feat_num = p_hwfn->hw_info.feat_num;
2060         struct qed_sb_cnt_info sb_cnt;
2061         u32 non_l2_sbs = 0;
2062
2063         memset(&sb_cnt, 0, sizeof(sb_cnt));
2064         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2065
2066         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2067             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2068                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2069                  * the status blocks equally between L2 / RoCE but with
2070                  * consideration as to how many l2 queues / cnqs we have.
2071                  */
2072                 feat_num[QED_RDMA_CNQ] =
2073                         min_t(u32, sb_cnt.cnt / 2,
2074                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2075
2076                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2077         }
2078         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2079                 /* Start by allocating VF queues, then PF's */
2080                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2081                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2082                                                 sb_cnt.iov_cnt);
2083                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2084                                                 sb_cnt.cnt - non_l2_sbs,
2085                                                 RESC_NUM(p_hwfn,
2086                                                          QED_L2_QUEUE) -
2087                                                 FEAT_NUM(p_hwfn,
2088                                                          QED_VF_L2_QUE));
2089         }
2090
2091         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2092                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2093                                                RESC_NUM(p_hwfn,
2094                                                         QED_CMDQS_CQS));
2095
2096         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2097                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2098                                                RESC_NUM(p_hwfn,
2099                                                         QED_CMDQS_CQS));
2100         DP_VERBOSE(p_hwfn,
2101                    NETIF_MSG_PROBE,
2102                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2103                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2104                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2105                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2106                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2107                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2108                    (int)sb_cnt.cnt);
2109 }
2110
2111 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2112 {
2113         switch (res_id) {
2114         case QED_L2_QUEUE:
2115                 return "L2_QUEUE";
2116         case QED_VPORT:
2117                 return "VPORT";
2118         case QED_RSS_ENG:
2119                 return "RSS_ENG";
2120         case QED_PQ:
2121                 return "PQ";
2122         case QED_RL:
2123                 return "RL";
2124         case QED_MAC:
2125                 return "MAC";
2126         case QED_VLAN:
2127                 return "VLAN";
2128         case QED_RDMA_CNQ_RAM:
2129                 return "RDMA_CNQ_RAM";
2130         case QED_ILT:
2131                 return "ILT";
2132         case QED_LL2_QUEUE:
2133                 return "LL2_QUEUE";
2134         case QED_CMDQS_CQS:
2135                 return "CMDQS_CQS";
2136         case QED_RDMA_STATS_QUEUE:
2137                 return "RDMA_STATS_QUEUE";
2138         case QED_BDQ:
2139                 return "BDQ";
2140         case QED_SB:
2141                 return "SB";
2142         default:
2143                 return "UNKNOWN_RESOURCE";
2144         }
2145 }
2146
2147 static int
2148 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2149                             struct qed_ptt *p_ptt,
2150                             enum qed_resources res_id,
2151                             u32 resc_max_val, u32 *p_mcp_resp)
2152 {
2153         int rc;
2154
2155         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2156                                       resc_max_val, p_mcp_resp);
2157         if (rc) {
2158                 DP_NOTICE(p_hwfn,
2159                           "MFW response failure for a max value setting of resource %d [%s]\n",
2160                           res_id, qed_hw_get_resc_name(res_id));
2161                 return rc;
2162         }
2163
2164         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2165                 DP_INFO(p_hwfn,
2166                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2167                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2168
2169         return 0;
2170 }
2171
2172 static int
2173 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2174 {
2175         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2176         u32 resc_max_val, mcp_resp;
2177         u8 res_id;
2178         int rc;
2179
2180         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2181                 switch (res_id) {
2182                 case QED_LL2_QUEUE:
2183                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2184                         break;
2185                 case QED_RDMA_CNQ_RAM:
2186                         /* No need for a case for QED_CMDQS_CQS since
2187                          * CNQ/CMDQS are the same resource.
2188                          */
2189                         resc_max_val = NUM_OF_CMDQS_CQS;
2190                         break;
2191                 case QED_RDMA_STATS_QUEUE:
2192                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2193                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2194                         break;
2195                 case QED_BDQ:
2196                         resc_max_val = BDQ_NUM_RESOURCES;
2197                         break;
2198                 default:
2199                         continue;
2200                 }
2201
2202                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2203                                                  resc_max_val, &mcp_resp);
2204                 if (rc)
2205                         return rc;
2206
2207                 /* There's no point to continue to the next resource if the
2208                  * command is not supported by the MFW.
2209                  * We do continue if the command is supported but the resource
2210                  * is unknown to the MFW. Such a resource will be later
2211                  * configured with the default allocation values.
2212                  */
2213                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2214                         return -EINVAL;
2215         }
2216
2217         return 0;
2218 }
2219
2220 static
2221 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2222                          enum qed_resources res_id,
2223                          u32 *p_resc_num, u32 *p_resc_start)
2224 {
2225         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2226         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2227
2228         switch (res_id) {
2229         case QED_L2_QUEUE:
2230                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2231                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2232                 break;
2233         case QED_VPORT:
2234                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2235                                MAX_NUM_VPORTS_BB) / num_funcs;
2236                 break;
2237         case QED_RSS_ENG:
2238                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2239                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2240                 break;
2241         case QED_PQ:
2242                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2243                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2244                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2245                 break;
2246         case QED_RL:
2247                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2248                 break;
2249         case QED_MAC:
2250         case QED_VLAN:
2251                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2252                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2253                 break;
2254         case QED_ILT:
2255                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2256                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2257                 break;
2258         case QED_LL2_QUEUE:
2259                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2260                 break;
2261         case QED_RDMA_CNQ_RAM:
2262         case QED_CMDQS_CQS:
2263                 /* CNQ/CMDQS are the same resource */
2264                 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2265                 break;
2266         case QED_RDMA_STATS_QUEUE:
2267                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2268                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2269                 break;
2270         case QED_BDQ:
2271                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2272                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2273                         *p_resc_num = 0;
2274                 else
2275                         *p_resc_num = 1;
2276                 break;
2277         case QED_SB:
2278                 /* Since we want its value to reflect whether MFW supports
2279                  * the new scheme, have a default of 0.
2280                  */
2281                 *p_resc_num = 0;
2282                 break;
2283         default:
2284                 return -EINVAL;
2285         }
2286
2287         switch (res_id) {
2288         case QED_BDQ:
2289                 if (!*p_resc_num)
2290                         *p_resc_start = 0;
2291                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2292                         *p_resc_start = p_hwfn->port_id;
2293                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2294                         *p_resc_start = p_hwfn->port_id;
2295                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2296                         *p_resc_start = p_hwfn->port_id + 2;
2297                 break;
2298         default:
2299                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2300                 break;
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2307                                   enum qed_resources res_id)
2308 {
2309         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2310         u32 mcp_resp, *p_resc_num, *p_resc_start;
2311         int rc;
2312
2313         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2314         p_resc_start = &RESC_START(p_hwfn, res_id);
2315
2316         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2317                                   &dflt_resc_start);
2318         if (rc) {
2319                 DP_ERR(p_hwfn,
2320                        "Failed to get default amount for resource %d [%s]\n",
2321                        res_id, qed_hw_get_resc_name(res_id));
2322                 return rc;
2323         }
2324
2325         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2326                                    &mcp_resp, p_resc_num, p_resc_start);
2327         if (rc) {
2328                 DP_NOTICE(p_hwfn,
2329                           "MFW response failure for an allocation request for resource %d [%s]\n",
2330                           res_id, qed_hw_get_resc_name(res_id));
2331                 return rc;
2332         }
2333
2334         /* Default driver values are applied in the following cases:
2335          * - The resource allocation MB command is not supported by the MFW
2336          * - There is an internal error in the MFW while processing the request
2337          * - The resource ID is unknown to the MFW
2338          */
2339         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2340                 DP_INFO(p_hwfn,
2341                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2342                         res_id,
2343                         qed_hw_get_resc_name(res_id),
2344                         mcp_resp, dflt_resc_num, dflt_resc_start);
2345                 *p_resc_num = dflt_resc_num;
2346                 *p_resc_start = dflt_resc_start;
2347                 goto out;
2348         }
2349
2350 out:
2351         /* PQs have to divide by 8 [that's the HW granularity].
2352          * Reduce number so it would fit.
2353          */
2354         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2355                 DP_INFO(p_hwfn,
2356                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2357                         *p_resc_num,
2358                         (*p_resc_num) & ~0x7,
2359                         *p_resc_start, (*p_resc_start) & ~0x7);
2360                 *p_resc_num &= ~0x7;
2361                 *p_resc_start &= ~0x7;
2362         }
2363
2364         return 0;
2365 }
2366
2367 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2368 {
2369         int rc;
2370         u8 res_id;
2371
2372         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2373                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2374                 if (rc)
2375                         return rc;
2376         }
2377
2378         return 0;
2379 }
2380
2381 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2382 {
2383         struct qed_resc_unlock_params resc_unlock_params;
2384         struct qed_resc_lock_params resc_lock_params;
2385         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2386         u8 res_id;
2387         int rc;
2388
2389         /* Setting the max values of the soft resources and the following
2390          * resources allocation queries should be atomic. Since several PFs can
2391          * run in parallel - a resource lock is needed.
2392          * If either the resource lock or resource set value commands are not
2393          * supported - skip the the max values setting, release the lock if
2394          * needed, and proceed to the queries. Other failures, including a
2395          * failure to acquire the lock, will cause this function to fail.
2396          */
2397         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2398                                        QED_RESC_LOCK_RESC_ALLOC, false);
2399
2400         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2401         if (rc && rc != -EINVAL) {
2402                 return rc;
2403         } else if (rc == -EINVAL) {
2404                 DP_INFO(p_hwfn,
2405                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2406         } else if (!rc && !resc_lock_params.b_granted) {
2407                 DP_NOTICE(p_hwfn,
2408                           "Failed to acquire the resource lock for the resource allocation commands\n");
2409                 return -EBUSY;
2410         } else {
2411                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2412                 if (rc && rc != -EINVAL) {
2413                         DP_NOTICE(p_hwfn,
2414                                   "Failed to set the max values of the soft resources\n");
2415                         goto unlock_and_exit;
2416                 } else if (rc == -EINVAL) {
2417                         DP_INFO(p_hwfn,
2418                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2419                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2420                                                  &resc_unlock_params);
2421                         if (rc)
2422                                 DP_INFO(p_hwfn,
2423                                         "Failed to release the resource lock for the resource allocation commands\n");
2424                 }
2425         }
2426
2427         rc = qed_hw_set_resc_info(p_hwfn);
2428         if (rc)
2429                 goto unlock_and_exit;
2430
2431         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2432                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2433                 if (rc)
2434                         DP_INFO(p_hwfn,
2435                                 "Failed to release the resource lock for the resource allocation commands\n");
2436         }
2437
2438         /* Sanity for ILT */
2439         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2440             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2441                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2442                           RESC_START(p_hwfn, QED_ILT),
2443                           RESC_END(p_hwfn, QED_ILT) - 1);
2444                 return -EINVAL;
2445         }
2446
2447         /* This will also learn the number of SBs from MFW */
2448         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2449                 return -EINVAL;
2450
2451         qed_hw_set_feat(p_hwfn);
2452
2453         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2454                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2455                            qed_hw_get_resc_name(res_id),
2456                            RESC_NUM(p_hwfn, res_id),
2457                            RESC_START(p_hwfn, res_id));
2458
2459         return 0;
2460
2461 unlock_and_exit:
2462         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2463                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2464         return rc;
2465 }
2466
2467 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2468 {
2469         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2470         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2471         struct qed_mcp_link_params *link;
2472
2473         /* Read global nvm_cfg address */
2474         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2475
2476         /* Verify MCP has initialized it */
2477         if (!nvm_cfg_addr) {
2478                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2479                 return -EINVAL;
2480         }
2481
2482         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2483         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2484
2485         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2486                offsetof(struct nvm_cfg1, glob) +
2487                offsetof(struct nvm_cfg1_glob, core_cfg);
2488
2489         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2490
2491         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2492                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2493         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2494                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2495                 break;
2496         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2497                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2498                 break;
2499         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2500                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2501                 break;
2502         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2503                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2504                 break;
2505         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2506                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2507                 break;
2508         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2509                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2510                 break;
2511         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2512                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2513                 break;
2514         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2515                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2516                 break;
2517         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2518                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2519                 break;
2520         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2521                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2522                 break;
2523         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2524                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2525                 break;
2526         default:
2527                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2528                 break;
2529         }
2530
2531         /* Read default link configuration */
2532         link = &p_hwfn->mcp_info->link_input;
2533         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2534                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2535         link_temp = qed_rd(p_hwfn, p_ptt,
2536                            port_cfg_addr +
2537                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2538         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2539         link->speed.advertised_speeds = link_temp;
2540
2541         link_temp = link->speed.advertised_speeds;
2542         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2543
2544         link_temp = qed_rd(p_hwfn, p_ptt,
2545                            port_cfg_addr +
2546                            offsetof(struct nvm_cfg1_port, link_settings));
2547         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2548                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2549         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2550                 link->speed.autoneg = true;
2551                 break;
2552         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2553                 link->speed.forced_speed = 1000;
2554                 break;
2555         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2556                 link->speed.forced_speed = 10000;
2557                 break;
2558         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2559                 link->speed.forced_speed = 25000;
2560                 break;
2561         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2562                 link->speed.forced_speed = 40000;
2563                 break;
2564         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2565                 link->speed.forced_speed = 50000;
2566                 break;
2567         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2568                 link->speed.forced_speed = 100000;
2569                 break;
2570         default:
2571                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2572         }
2573
2574         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2575                 link->speed.autoneg;
2576
2577         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2578         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2579         link->pause.autoneg = !!(link_temp &
2580                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2581         link->pause.forced_rx = !!(link_temp &
2582                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2583         link->pause.forced_tx = !!(link_temp &
2584                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2585         link->loopback_mode = 0;
2586
2587         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2588                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2589                    link->speed.forced_speed, link->speed.advertised_speeds,
2590                    link->speed.autoneg, link->pause.autoneg);
2591
2592         /* Read Multi-function information from shmem */
2593         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2594                offsetof(struct nvm_cfg1, glob) +
2595                offsetof(struct nvm_cfg1_glob, generic_cont0);
2596
2597         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2598
2599         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2600                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
2601
2602         switch (mf_mode) {
2603         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2604                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2605                 break;
2606         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2607                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2608                 break;
2609         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2610                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2611                 break;
2612         }
2613         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2614                 p_hwfn->cdev->mf_mode);
2615
2616         /* Read Multi-function information from shmem */
2617         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2618                 offsetof(struct nvm_cfg1, glob) +
2619                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2620
2621         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2622         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2623                 __set_bit(QED_DEV_CAP_ETH,
2624                           &p_hwfn->hw_info.device_capabilities);
2625         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2626                 __set_bit(QED_DEV_CAP_FCOE,
2627                           &p_hwfn->hw_info.device_capabilities);
2628         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2629                 __set_bit(QED_DEV_CAP_ISCSI,
2630                           &p_hwfn->hw_info.device_capabilities);
2631         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2632                 __set_bit(QED_DEV_CAP_ROCE,
2633                           &p_hwfn->hw_info.device_capabilities);
2634
2635         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2636 }
2637
2638 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2639 {
2640         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2641         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2642         struct qed_dev *cdev = p_hwfn->cdev;
2643
2644         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2645
2646         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2647          * in the other bits are selected.
2648          * Bits 1-15 are for functions 1-15, respectively, and their value is
2649          * '0' only for enabled functions (function 0 always exists and
2650          * enabled).
2651          * In case of CMT, only the "even" functions are enabled, and thus the
2652          * number of functions for both hwfns is learnt from the same bits.
2653          */
2654         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2655
2656         if (reg_function_hide & 0x1) {
2657                 if (QED_IS_BB(cdev)) {
2658                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2659                                 num_funcs = 0;
2660                                 eng_mask = 0xaaaa;
2661                         } else {
2662                                 num_funcs = 1;
2663                                 eng_mask = 0x5554;
2664                         }
2665                 } else {
2666                         num_funcs = 1;
2667                         eng_mask = 0xfffe;
2668                 }
2669
2670                 /* Get the number of the enabled functions on the engine */
2671                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2672                 while (tmp) {
2673                         if (tmp & 0x1)
2674                                 num_funcs++;
2675                         tmp >>= 0x1;
2676                 }
2677
2678                 /* Get the PF index within the enabled functions */
2679                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2680                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2681                 while (tmp) {
2682                         if (tmp & 0x1)
2683                                 enabled_func_idx--;
2684                         tmp >>= 0x1;
2685                 }
2686         }
2687
2688         p_hwfn->num_funcs_on_engine = num_funcs;
2689         p_hwfn->enabled_func_idx = enabled_func_idx;
2690
2691         DP_VERBOSE(p_hwfn,
2692                    NETIF_MSG_PROBE,
2693                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2694                    p_hwfn->rel_pf_id,
2695                    p_hwfn->abs_pf_id,
2696                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2697 }
2698
2699 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2700                                     struct qed_ptt *p_ptt)
2701 {
2702         u32 port_mode;
2703
2704         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2705
2706         if (port_mode < 3) {
2707                 p_hwfn->cdev->num_ports_in_engine = 1;
2708         } else if (port_mode <= 5) {
2709                 p_hwfn->cdev->num_ports_in_engine = 2;
2710         } else {
2711                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2712                           p_hwfn->cdev->num_ports_in_engine);
2713
2714                 /* Default num_ports_in_engine to something */
2715                 p_hwfn->cdev->num_ports_in_engine = 1;
2716         }
2717 }
2718
2719 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2720                                     struct qed_ptt *p_ptt)
2721 {
2722         u32 port;
2723         int i;
2724
2725         p_hwfn->cdev->num_ports_in_engine = 0;
2726
2727         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2728                 port = qed_rd(p_hwfn, p_ptt,
2729                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2730                 if (port & 1)
2731                         p_hwfn->cdev->num_ports_in_engine++;
2732         }
2733
2734         if (!p_hwfn->cdev->num_ports_in_engine) {
2735                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2736
2737                 /* Default num_ports_in_engine to something */
2738                 p_hwfn->cdev->num_ports_in_engine = 1;
2739         }
2740 }
2741
2742 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2743 {
2744         if (QED_IS_BB(p_hwfn->cdev))
2745                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2746         else
2747                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2748 }
2749
2750 static int
2751 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2752                 struct qed_ptt *p_ptt,
2753                 enum qed_pci_personality personality)
2754 {
2755         int rc;
2756
2757         /* Since all information is common, only first hwfns should do this */
2758         if (IS_LEAD_HWFN(p_hwfn)) {
2759                 rc = qed_iov_hw_info(p_hwfn);
2760                 if (rc)
2761                         return rc;
2762         }
2763
2764         qed_hw_info_port_num(p_hwfn, p_ptt);
2765
2766         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2767
2768         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2769         if (rc)
2770                 return rc;
2771
2772         if (qed_mcp_is_init(p_hwfn))
2773                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2774                                 p_hwfn->mcp_info->func_info.mac);
2775         else
2776                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2777
2778         if (qed_mcp_is_init(p_hwfn)) {
2779                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2780                         p_hwfn->hw_info.ovlan =
2781                                 p_hwfn->mcp_info->func_info.ovlan;
2782
2783                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2784         }
2785
2786         if (qed_mcp_is_init(p_hwfn)) {
2787                 enum qed_pci_personality protocol;
2788
2789                 protocol = p_hwfn->mcp_info->func_info.protocol;
2790                 p_hwfn->hw_info.personality = protocol;
2791         }
2792
2793         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2794         p_hwfn->hw_info.num_active_tc = 1;
2795
2796         qed_get_num_funcs(p_hwfn, p_ptt);
2797
2798         if (qed_mcp_is_init(p_hwfn))
2799                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2800
2801         return qed_hw_get_resc(p_hwfn, p_ptt);
2802 }
2803
2804 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2805 {
2806         struct qed_dev *cdev = p_hwfn->cdev;
2807         u16 device_id_mask;
2808         u32 tmp;
2809
2810         /* Read Vendor Id / Device Id */
2811         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2812         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2813
2814         /* Determine type */
2815         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2816         switch (device_id_mask) {
2817         case QED_DEV_ID_MASK_BB:
2818                 cdev->type = QED_DEV_TYPE_BB;
2819                 break;
2820         case QED_DEV_ID_MASK_AH:
2821                 cdev->type = QED_DEV_TYPE_AH;
2822                 break;
2823         default:
2824                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2825                 return -EBUSY;
2826         }
2827
2828         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2829         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2830
2831         MASK_FIELD(CHIP_REV, cdev->chip_rev);
2832
2833         /* Learn number of HW-functions */
2834         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2835
2836         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2837                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2838                 cdev->num_hwfns = 2;
2839         } else {
2840                 cdev->num_hwfns = 1;
2841         }
2842
2843         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2844                                     MISCS_REG_CHIP_TEST_REG) >> 4;
2845         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2846         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2847         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2848
2849         DP_INFO(cdev->hwfns,
2850                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2851                 QED_IS_BB(cdev) ? "BB" : "AH",
2852                 'A' + cdev->chip_rev,
2853                 (int)cdev->chip_metal,
2854                 cdev->chip_num, cdev->chip_rev,
2855                 cdev->chip_bond_id, cdev->chip_metal);
2856
2857         return 0;
2858 }
2859
2860 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2861                                  void __iomem *p_regview,
2862                                  void __iomem *p_doorbells,
2863                                  enum qed_pci_personality personality)
2864 {
2865         int rc = 0;
2866
2867         /* Split PCI bars evenly between hwfns */
2868         p_hwfn->regview = p_regview;
2869         p_hwfn->doorbells = p_doorbells;
2870
2871         if (IS_VF(p_hwfn->cdev))
2872                 return qed_vf_hw_prepare(p_hwfn);
2873
2874         /* Validate that chip access is feasible */
2875         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2876                 DP_ERR(p_hwfn,
2877                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2878                 return -EINVAL;
2879         }
2880
2881         get_function_id(p_hwfn);
2882
2883         /* Allocate PTT pool */
2884         rc = qed_ptt_pool_alloc(p_hwfn);
2885         if (rc)
2886                 goto err0;
2887
2888         /* Allocate the main PTT */
2889         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2890
2891         /* First hwfn learns basic information, e.g., number of hwfns */
2892         if (!p_hwfn->my_id) {
2893                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2894                 if (rc)
2895                         goto err1;
2896         }
2897
2898         qed_hw_hwfn_prepare(p_hwfn);
2899
2900         /* Initialize MCP structure */
2901         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2902         if (rc) {
2903                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2904                 goto err1;
2905         }
2906
2907         /* Read the device configuration information from the HW and SHMEM */
2908         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2909         if (rc) {
2910                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2911                 goto err2;
2912         }
2913
2914         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2915          * is called as it sets the ports number in an engine.
2916          */
2917         if (IS_LEAD_HWFN(p_hwfn)) {
2918                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2919                 if (rc)
2920                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2921         }
2922
2923         /* Allocate the init RT array and initialize the init-ops engine */
2924         rc = qed_init_alloc(p_hwfn);
2925         if (rc)
2926                 goto err2;
2927
2928         return rc;
2929 err2:
2930         if (IS_LEAD_HWFN(p_hwfn))
2931                 qed_iov_free_hw_info(p_hwfn->cdev);
2932         qed_mcp_free(p_hwfn);
2933 err1:
2934         qed_hw_hwfn_free(p_hwfn);
2935 err0:
2936         return rc;
2937 }
2938
2939 int qed_hw_prepare(struct qed_dev *cdev,
2940                    int personality)
2941 {
2942         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2943         int rc;
2944
2945         /* Store the precompiled init data ptrs */
2946         if (IS_PF(cdev))
2947                 qed_init_iro_array(cdev);
2948
2949         /* Initialize the first hwfn - will learn number of hwfns */
2950         rc = qed_hw_prepare_single(p_hwfn,
2951                                    cdev->regview,
2952                                    cdev->doorbells, personality);
2953         if (rc)
2954                 return rc;
2955
2956         personality = p_hwfn->hw_info.personality;
2957
2958         /* Initialize the rest of the hwfns */
2959         if (cdev->num_hwfns > 1) {
2960                 void __iomem *p_regview, *p_doorbell;
2961                 u8 __iomem *addr;
2962
2963                 /* adjust bar offset for second engine */
2964                 addr = cdev->regview +
2965                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2966                                        BAR_ID_0) / 2;
2967                 p_regview = addr;
2968
2969                 addr = cdev->doorbells +
2970                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2971                                        BAR_ID_1) / 2;
2972                 p_doorbell = addr;
2973
2974                 /* prepare second hw function */
2975                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
2976                                            p_doorbell, personality);
2977
2978                 /* in case of error, need to free the previously
2979                  * initiliazed hwfn 0.
2980                  */
2981                 if (rc) {
2982                         if (IS_PF(cdev)) {
2983                                 qed_init_free(p_hwfn);
2984                                 qed_mcp_free(p_hwfn);
2985                                 qed_hw_hwfn_free(p_hwfn);
2986                         }
2987                 }
2988         }
2989
2990         return rc;
2991 }
2992
2993 void qed_hw_remove(struct qed_dev *cdev)
2994 {
2995         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2996         int i;
2997
2998         if (IS_PF(cdev))
2999                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3000                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3001
3002         for_each_hwfn(cdev, i) {
3003                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3004
3005                 if (IS_VF(cdev)) {
3006                         qed_vf_pf_release(p_hwfn);
3007                         continue;
3008                 }
3009
3010                 qed_init_free(p_hwfn);
3011                 qed_hw_hwfn_free(p_hwfn);
3012                 qed_mcp_free(p_hwfn);
3013         }
3014
3015         qed_iov_free_hw_info(cdev);
3016 }
3017
3018 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3019                                     struct qed_chain *p_chain)
3020 {
3021         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3022         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3023         struct qed_chain_next *p_next;
3024         u32 size, i;
3025
3026         if (!p_virt)
3027                 return;
3028
3029         size = p_chain->elem_size * p_chain->usable_per_page;
3030
3031         for (i = 0; i < p_chain->page_cnt; i++) {
3032                 if (!p_virt)
3033                         break;
3034
3035                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3036                 p_virt_next = p_next->next_virt;
3037                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3038
3039                 dma_free_coherent(&cdev->pdev->dev,
3040                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3041
3042                 p_virt = p_virt_next;
3043                 p_phys = p_phys_next;
3044         }
3045 }
3046
3047 static void qed_chain_free_single(struct qed_dev *cdev,
3048                                   struct qed_chain *p_chain)
3049 {
3050         if (!p_chain->p_virt_addr)
3051                 return;
3052
3053         dma_free_coherent(&cdev->pdev->dev,
3054                           QED_CHAIN_PAGE_SIZE,
3055                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3056 }
3057
3058 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3059 {
3060         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3061         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3062         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3063
3064         if (!pp_virt_addr_tbl)
3065                 return;
3066
3067         if (!p_pbl_virt)
3068                 goto out;
3069
3070         for (i = 0; i < page_cnt; i++) {
3071                 if (!pp_virt_addr_tbl[i])
3072                         break;
3073
3074                 dma_free_coherent(&cdev->pdev->dev,
3075                                   QED_CHAIN_PAGE_SIZE,
3076                                   pp_virt_addr_tbl[i],
3077                                   *(dma_addr_t *)p_pbl_virt);
3078
3079                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3080         }
3081
3082         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3083
3084         if (!p_chain->b_external_pbl)
3085                 dma_free_coherent(&cdev->pdev->dev,
3086                                   pbl_size,
3087                                   p_chain->pbl_sp.p_virt_table,
3088                                   p_chain->pbl_sp.p_phys_table);
3089 out:
3090         vfree(p_chain->pbl.pp_virt_addr_tbl);
3091         p_chain->pbl.pp_virt_addr_tbl = NULL;
3092 }
3093
3094 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3095 {
3096         switch (p_chain->mode) {
3097         case QED_CHAIN_MODE_NEXT_PTR:
3098                 qed_chain_free_next_ptr(cdev, p_chain);
3099                 break;
3100         case QED_CHAIN_MODE_SINGLE:
3101                 qed_chain_free_single(cdev, p_chain);
3102                 break;
3103         case QED_CHAIN_MODE_PBL:
3104                 qed_chain_free_pbl(cdev, p_chain);
3105                 break;
3106         }
3107 }
3108
3109 static int
3110 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3111                              enum qed_chain_cnt_type cnt_type,
3112                              size_t elem_size, u32 page_cnt)
3113 {
3114         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3115
3116         /* The actual chain size can be larger than the maximal possible value
3117          * after rounding up the requested elements number to pages, and after
3118          * taking into acount the unusuable elements (next-ptr elements).
3119          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3120          * size/capacity fields are of a u32 type.
3121          */
3122         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3123              chain_size > ((u32)U16_MAX + 1)) ||
3124             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3125                 DP_NOTICE(cdev,
3126                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3127                           chain_size);
3128                 return -EINVAL;
3129         }
3130
3131         return 0;
3132 }
3133
3134 static int
3135 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3136 {
3137         void *p_virt = NULL, *p_virt_prev = NULL;
3138         dma_addr_t p_phys = 0;
3139         u32 i;
3140
3141         for (i = 0; i < p_chain->page_cnt; i++) {
3142                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3143                                             QED_CHAIN_PAGE_SIZE,
3144                                             &p_phys, GFP_KERNEL);
3145                 if (!p_virt)
3146                         return -ENOMEM;
3147
3148                 if (i == 0) {
3149                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3150                         qed_chain_reset(p_chain);
3151                 } else {
3152                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3153                                                      p_virt, p_phys);
3154                 }
3155
3156                 p_virt_prev = p_virt;
3157         }
3158         /* Last page's next element should point to the beginning of the
3159          * chain.
3160          */
3161         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3162                                      p_chain->p_virt_addr,
3163                                      p_chain->p_phys_addr);
3164
3165         return 0;
3166 }
3167
3168 static int
3169 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3170 {
3171         dma_addr_t p_phys = 0;
3172         void *p_virt = NULL;
3173
3174         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3175                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3176         if (!p_virt)
3177                 return -ENOMEM;
3178
3179         qed_chain_init_mem(p_chain, p_virt, p_phys);
3180         qed_chain_reset(p_chain);
3181
3182         return 0;
3183 }
3184
3185 static int
3186 qed_chain_alloc_pbl(struct qed_dev *cdev,
3187                     struct qed_chain *p_chain,
3188                     struct qed_chain_ext_pbl *ext_pbl)
3189 {
3190         u32 page_cnt = p_chain->page_cnt, size, i;
3191         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3192         void **pp_virt_addr_tbl = NULL;
3193         u8 *p_pbl_virt = NULL;
3194         void *p_virt = NULL;
3195
3196         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3197         pp_virt_addr_tbl = vzalloc(size);
3198         if (!pp_virt_addr_tbl)
3199                 return -ENOMEM;
3200
3201         /* The allocation of the PBL table is done with its full size, since it
3202          * is expected to be successive.
3203          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3204          * failure, since pp_virt_addr_tbl was previously allocated, and it
3205          * should be saved to allow its freeing during the error flow.
3206          */
3207         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3208
3209         if (!ext_pbl) {
3210                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3211                                                 size, &p_pbl_phys, GFP_KERNEL);
3212         } else {
3213                 p_pbl_virt = ext_pbl->p_pbl_virt;
3214                 p_pbl_phys = ext_pbl->p_pbl_phys;
3215                 p_chain->b_external_pbl = true;
3216         }
3217
3218         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3219                                pp_virt_addr_tbl);
3220         if (!p_pbl_virt)
3221                 return -ENOMEM;
3222
3223         for (i = 0; i < page_cnt; i++) {
3224                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3225                                             QED_CHAIN_PAGE_SIZE,
3226                                             &p_phys, GFP_KERNEL);
3227                 if (!p_virt)
3228                         return -ENOMEM;
3229
3230                 if (i == 0) {
3231                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3232                         qed_chain_reset(p_chain);
3233                 }
3234
3235                 /* Fill the PBL table with the physical address of the page */
3236                 *(dma_addr_t *)p_pbl_virt = p_phys;
3237                 /* Keep the virtual address of the page */
3238                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3239
3240                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3241         }
3242
3243         return 0;
3244 }
3245
3246 int qed_chain_alloc(struct qed_dev *cdev,
3247                     enum qed_chain_use_mode intended_use,
3248                     enum qed_chain_mode mode,
3249                     enum qed_chain_cnt_type cnt_type,
3250                     u32 num_elems,
3251                     size_t elem_size,
3252                     struct qed_chain *p_chain,
3253                     struct qed_chain_ext_pbl *ext_pbl)
3254 {
3255         u32 page_cnt;
3256         int rc = 0;
3257
3258         if (mode == QED_CHAIN_MODE_SINGLE)
3259                 page_cnt = 1;
3260         else
3261                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3262
3263         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3264         if (rc) {
3265                 DP_NOTICE(cdev,
3266                           "Cannot allocate a chain with the given arguments:\n");
3267                 DP_NOTICE(cdev,
3268                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3269                           intended_use, mode, cnt_type, num_elems, elem_size);
3270                 return rc;
3271         }
3272
3273         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3274                               mode, cnt_type);
3275
3276         switch (mode) {
3277         case QED_CHAIN_MODE_NEXT_PTR:
3278                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3279                 break;
3280         case QED_CHAIN_MODE_SINGLE:
3281                 rc = qed_chain_alloc_single(cdev, p_chain);
3282                 break;
3283         case QED_CHAIN_MODE_PBL:
3284                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3285                 break;
3286         }
3287         if (rc)
3288                 goto nomem;
3289
3290         return 0;
3291
3292 nomem:
3293         qed_chain_free(cdev, p_chain);
3294         return rc;
3295 }
3296
3297 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3298 {
3299         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3300                 u16 min, max;
3301
3302                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3303                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3304                 DP_NOTICE(p_hwfn,
3305                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3306                           src_id, min, max);
3307
3308                 return -EINVAL;
3309         }
3310
3311         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3312
3313         return 0;
3314 }
3315
3316 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3317 {
3318         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3319                 u8 min, max;
3320
3321                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3322                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3323                 DP_NOTICE(p_hwfn,
3324                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3325                           src_id, min, max);
3326
3327                 return -EINVAL;
3328         }
3329
3330         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3331
3332         return 0;
3333 }
3334
3335 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3336 {
3337         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3338                 u8 min, max;
3339
3340                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3341                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3342                 DP_NOTICE(p_hwfn,
3343                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3344                           src_id, min, max);
3345
3346                 return -EINVAL;
3347         }
3348
3349         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3350
3351         return 0;
3352 }
3353
3354 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3355                                   u8 *p_filter)
3356 {
3357         *p_high = p_filter[1] | (p_filter[0] << 8);
3358         *p_low = p_filter[5] | (p_filter[4] << 8) |
3359                  (p_filter[3] << 16) | (p_filter[2] << 24);
3360 }
3361
3362 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3363                            struct qed_ptt *p_ptt, u8 *p_filter)
3364 {
3365         u32 high = 0, low = 0, en;
3366         int i;
3367
3368         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3369                 return 0;
3370
3371         qed_llh_mac_to_filter(&high, &low, p_filter);
3372
3373         /* Find a free entry and utilize it */
3374         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3375                 en = qed_rd(p_hwfn, p_ptt,
3376                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3377                 if (en)
3378                         continue;
3379                 qed_wr(p_hwfn, p_ptt,
3380                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3381                        2 * i * sizeof(u32), low);
3382                 qed_wr(p_hwfn, p_ptt,
3383                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3384                        (2 * i + 1) * sizeof(u32), high);
3385                 qed_wr(p_hwfn, p_ptt,
3386                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3387                 qed_wr(p_hwfn, p_ptt,
3388                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3389                        i * sizeof(u32), 0);
3390                 qed_wr(p_hwfn, p_ptt,
3391                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3392                 break;
3393         }
3394         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3395                 DP_NOTICE(p_hwfn,
3396                           "Failed to find an empty LLH filter to utilize\n");
3397                 return -EINVAL;
3398         }
3399
3400         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3401                    "mac: %pM is added at %d\n",
3402                    p_filter, i);
3403
3404         return 0;
3405 }
3406
3407 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3408                                struct qed_ptt *p_ptt, u8 *p_filter)
3409 {
3410         u32 high = 0, low = 0;
3411         int i;
3412
3413         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3414                 return;
3415
3416         qed_llh_mac_to_filter(&high, &low, p_filter);
3417
3418         /* Find the entry and clean it */
3419         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3420                 if (qed_rd(p_hwfn, p_ptt,
3421                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3422                            2 * i * sizeof(u32)) != low)
3423                         continue;
3424                 if (qed_rd(p_hwfn, p_ptt,
3425                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3426                            (2 * i + 1) * sizeof(u32)) != high)
3427                         continue;
3428
3429                 qed_wr(p_hwfn, p_ptt,
3430                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3431                 qed_wr(p_hwfn, p_ptt,
3432                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3433                 qed_wr(p_hwfn, p_ptt,
3434                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3435                        (2 * i + 1) * sizeof(u32), 0);
3436
3437                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3438                            "mac: %pM is removed from %d\n",
3439                            p_filter, i);
3440                 break;
3441         }
3442         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3443                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3444 }
3445
3446 int
3447 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3448                             struct qed_ptt *p_ptt,
3449                             u16 source_port_or_eth_type,
3450                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3451 {
3452         u32 high = 0, low = 0, en;
3453         int i;
3454
3455         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3456                 return 0;
3457
3458         switch (type) {
3459         case QED_LLH_FILTER_ETHERTYPE:
3460                 high = source_port_or_eth_type;
3461                 break;
3462         case QED_LLH_FILTER_TCP_SRC_PORT:
3463         case QED_LLH_FILTER_UDP_SRC_PORT:
3464                 low = source_port_or_eth_type << 16;
3465                 break;
3466         case QED_LLH_FILTER_TCP_DEST_PORT:
3467         case QED_LLH_FILTER_UDP_DEST_PORT:
3468                 low = dest_port;
3469                 break;
3470         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3471         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3472                 low = (source_port_or_eth_type << 16) | dest_port;
3473                 break;
3474         default:
3475                 DP_NOTICE(p_hwfn,
3476                           "Non valid LLH protocol filter type %d\n", type);
3477                 return -EINVAL;
3478         }
3479         /* Find a free entry and utilize it */
3480         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3481                 en = qed_rd(p_hwfn, p_ptt,
3482                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3483                 if (en)
3484                         continue;
3485                 qed_wr(p_hwfn, p_ptt,
3486                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3487                        2 * i * sizeof(u32), low);
3488                 qed_wr(p_hwfn, p_ptt,
3489                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3490                        (2 * i + 1) * sizeof(u32), high);
3491                 qed_wr(p_hwfn, p_ptt,
3492                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3493                 qed_wr(p_hwfn, p_ptt,
3494                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3495                        i * sizeof(u32), 1 << type);
3496                 qed_wr(p_hwfn, p_ptt,
3497                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3498                 break;
3499         }
3500         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3501                 DP_NOTICE(p_hwfn,
3502                           "Failed to find an empty LLH filter to utilize\n");
3503                 return -EINVAL;
3504         }
3505         switch (type) {
3506         case QED_LLH_FILTER_ETHERTYPE:
3507                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3508                            "ETH type %x is added at %d\n",
3509                            source_port_or_eth_type, i);
3510                 break;
3511         case QED_LLH_FILTER_TCP_SRC_PORT:
3512                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3513                            "TCP src port %x is added at %d\n",
3514                            source_port_or_eth_type, i);
3515                 break;
3516         case QED_LLH_FILTER_UDP_SRC_PORT:
3517                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3518                            "UDP src port %x is added at %d\n",
3519                            source_port_or_eth_type, i);
3520                 break;
3521         case QED_LLH_FILTER_TCP_DEST_PORT:
3522                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3523                            "TCP dst port %x is added at %d\n", dest_port, i);
3524                 break;
3525         case QED_LLH_FILTER_UDP_DEST_PORT:
3526                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3527                            "UDP dst port %x is added at %d\n", dest_port, i);
3528                 break;
3529         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3530                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3531                            "TCP src/dst ports %x/%x are added at %d\n",
3532                            source_port_or_eth_type, dest_port, i);
3533                 break;
3534         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3535                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3536                            "UDP src/dst ports %x/%x are added at %d\n",
3537                            source_port_or_eth_type, dest_port, i);
3538                 break;
3539         }
3540         return 0;
3541 }
3542
3543 void
3544 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3545                                struct qed_ptt *p_ptt,
3546                                u16 source_port_or_eth_type,
3547                                u16 dest_port,
3548                                enum qed_llh_port_filter_type_t type)
3549 {
3550         u32 high = 0, low = 0;
3551         int i;
3552
3553         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3554                 return;
3555
3556         switch (type) {
3557         case QED_LLH_FILTER_ETHERTYPE:
3558                 high = source_port_or_eth_type;
3559                 break;
3560         case QED_LLH_FILTER_TCP_SRC_PORT:
3561         case QED_LLH_FILTER_UDP_SRC_PORT:
3562                 low = source_port_or_eth_type << 16;
3563                 break;
3564         case QED_LLH_FILTER_TCP_DEST_PORT:
3565         case QED_LLH_FILTER_UDP_DEST_PORT:
3566                 low = dest_port;
3567                 break;
3568         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3569         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3570                 low = (source_port_or_eth_type << 16) | dest_port;
3571                 break;
3572         default:
3573                 DP_NOTICE(p_hwfn,
3574                           "Non valid LLH protocol filter type %d\n", type);
3575                 return;
3576         }
3577
3578         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3579                 if (!qed_rd(p_hwfn, p_ptt,
3580                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3581                         continue;
3582                 if (!qed_rd(p_hwfn, p_ptt,
3583                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3584                         continue;
3585                 if (!(qed_rd(p_hwfn, p_ptt,
3586                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3587                              i * sizeof(u32)) & BIT(type)))
3588                         continue;
3589                 if (qed_rd(p_hwfn, p_ptt,
3590                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3591                            2 * i * sizeof(u32)) != low)
3592                         continue;
3593                 if (qed_rd(p_hwfn, p_ptt,
3594                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3595                            (2 * i + 1) * sizeof(u32)) != high)
3596                         continue;
3597
3598                 qed_wr(p_hwfn, p_ptt,
3599                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3600                 qed_wr(p_hwfn, p_ptt,
3601                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3602                 qed_wr(p_hwfn, p_ptt,
3603                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3604                        i * sizeof(u32), 0);
3605                 qed_wr(p_hwfn, p_ptt,
3606                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3607                 qed_wr(p_hwfn, p_ptt,
3608                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3609                        (2 * i + 1) * sizeof(u32), 0);
3610                 break;
3611         }
3612
3613         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3614                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3615 }
3616
3617 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3618                             u32 hw_addr, void *p_eth_qzone,
3619                             size_t eth_qzone_size, u8 timeset)
3620 {
3621         struct coalescing_timeset *p_coal_timeset;
3622
3623         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3624                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3625                 return -EINVAL;
3626         }
3627
3628         p_coal_timeset = p_eth_qzone;
3629         memset(p_coal_timeset, 0, eth_qzone_size);
3630         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3631         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3632         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3633
3634         return 0;
3635 }
3636
3637 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3638                          u16 coalesce, u16 qid, u16 sb_id)
3639 {
3640         struct ustorm_eth_queue_zone eth_qzone;
3641         u8 timeset, timer_res;
3642         u16 fw_qid = 0;
3643         u32 address;
3644         int rc;
3645
3646         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3647         if (coalesce <= 0x7F) {
3648                 timer_res = 0;
3649         } else if (coalesce <= 0xFF) {
3650                 timer_res = 1;
3651         } else if (coalesce <= 0x1FF) {
3652                 timer_res = 2;
3653         } else {
3654                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3655                 return -EINVAL;
3656         }
3657         timeset = (u8)(coalesce >> timer_res);
3658
3659         rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);
3660         if (rc)
3661                 return rc;
3662
3663         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3664         if (rc)
3665                 goto out;
3666
3667         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3668
3669         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3670                               sizeof(struct ustorm_eth_queue_zone), timeset);
3671         if (rc)
3672                 goto out;
3673
3674         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3675 out:
3676         return rc;
3677 }
3678
3679 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3680                          u16 coalesce, u16 qid, u16 sb_id)
3681 {
3682         struct xstorm_eth_queue_zone eth_qzone;
3683         u8 timeset, timer_res;
3684         u16 fw_qid = 0;
3685         u32 address;
3686         int rc;
3687
3688         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3689         if (coalesce <= 0x7F) {
3690                 timer_res = 0;
3691         } else if (coalesce <= 0xFF) {
3692                 timer_res = 1;
3693         } else if (coalesce <= 0x1FF) {
3694                 timer_res = 2;
3695         } else {
3696                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3697                 return -EINVAL;
3698         }
3699         timeset = (u8)(coalesce >> timer_res);
3700
3701         rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);
3702         if (rc)
3703                 return rc;
3704
3705         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3706         if (rc)
3707                 goto out;
3708
3709         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3710
3711         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3712                               sizeof(struct xstorm_eth_queue_zone), timeset);
3713         if (rc)
3714                 goto out;
3715
3716         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3717 out:
3718         return rc;
3719 }
3720
3721 /* Calculate final WFQ values for all vports and configure them.
3722  * After this configuration each vport will have
3723  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3724  */
3725 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3726                                              struct qed_ptt *p_ptt,
3727                                              u32 min_pf_rate)
3728 {
3729         struct init_qm_vport_params *vport_params;
3730         int i;
3731
3732         vport_params = p_hwfn->qm_info.qm_vport_params;
3733
3734         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3735                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3736
3737                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3738                                                 min_pf_rate;
3739                 qed_init_vport_wfq(p_hwfn, p_ptt,
3740                                    vport_params[i].first_tx_pq_id,
3741                                    vport_params[i].vport_wfq);
3742         }
3743 }
3744
3745 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3746                                        u32 min_pf_rate)
3747
3748 {
3749         int i;
3750
3751         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3752                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3753 }
3754
3755 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3756                                            struct qed_ptt *p_ptt,
3757                                            u32 min_pf_rate)
3758 {
3759         struct init_qm_vport_params *vport_params;
3760         int i;
3761
3762         vport_params = p_hwfn->qm_info.qm_vport_params;
3763
3764         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3765                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3766                 qed_init_vport_wfq(p_hwfn, p_ptt,
3767                                    vport_params[i].first_tx_pq_id,
3768                                    vport_params[i].vport_wfq);
3769         }
3770 }
3771
3772 /* This function performs several validations for WFQ
3773  * configuration and required min rate for a given vport
3774  * 1. req_rate must be greater than one percent of min_pf_rate.
3775  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3776  *    rates to get less than one percent of min_pf_rate.
3777  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3778  */
3779 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3780                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
3781 {
3782         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3783         int non_requested_count = 0, req_count = 0, i, num_vports;
3784
3785         num_vports = p_hwfn->qm_info.num_vports;
3786
3787         /* Accounting for the vports which are configured for WFQ explicitly */
3788         for (i = 0; i < num_vports; i++) {
3789                 u32 tmp_speed;
3790
3791                 if ((i != vport_id) &&
3792                     p_hwfn->qm_info.wfq_data[i].configured) {
3793                         req_count++;
3794                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3795                         total_req_min_rate += tmp_speed;
3796                 }
3797         }
3798
3799         /* Include current vport data as well */
3800         req_count++;
3801         total_req_min_rate += req_rate;
3802         non_requested_count = num_vports - req_count;
3803
3804         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3805                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3806                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3807                            vport_id, req_rate, min_pf_rate);
3808                 return -EINVAL;
3809         }
3810
3811         if (num_vports > QED_WFQ_UNIT) {
3812                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3813                            "Number of vports is greater than %d\n",
3814                            QED_WFQ_UNIT);
3815                 return -EINVAL;
3816         }
3817
3818         if (total_req_min_rate > min_pf_rate) {
3819                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3820                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3821                            total_req_min_rate, min_pf_rate);
3822                 return -EINVAL;
3823         }
3824
3825         total_left_rate = min_pf_rate - total_req_min_rate;
3826
3827         left_rate_per_vp = total_left_rate / non_requested_count;
3828         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
3829                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3830                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3831                            left_rate_per_vp, min_pf_rate);
3832                 return -EINVAL;
3833         }
3834
3835         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3836         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3837
3838         for (i = 0; i < num_vports; i++) {
3839                 if (p_hwfn->qm_info.wfq_data[i].configured)
3840                         continue;
3841
3842                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3843         }
3844
3845         return 0;
3846 }
3847
3848 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3849                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3850 {
3851         struct qed_mcp_link_state *p_link;
3852         int rc = 0;
3853
3854         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3855
3856         if (!p_link->min_pf_rate) {
3857                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3858                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3859                 return rc;
3860         }
3861
3862         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3863
3864         if (!rc)
3865                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3866                                                  p_link->min_pf_rate);
3867         else
3868                 DP_NOTICE(p_hwfn,
3869                           "Validation failed while configuring min rate\n");
3870
3871         return rc;
3872 }
3873
3874 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3875                                                  struct qed_ptt *p_ptt,
3876                                                  u32 min_pf_rate)
3877 {
3878         bool use_wfq = false;
3879         int rc = 0;
3880         u16 i;
3881
3882         /* Validate all pre configured vports for wfq */
3883         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3884                 u32 rate;
3885
3886                 if (!p_hwfn->qm_info.wfq_data[i].configured)
3887                         continue;
3888
3889                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3890                 use_wfq = true;
3891
3892                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3893                 if (rc) {
3894                         DP_NOTICE(p_hwfn,
3895                                   "WFQ validation failed while configuring min rate\n");
3896                         break;
3897                 }
3898         }
3899
3900         if (!rc && use_wfq)
3901                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3902         else
3903                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3904
3905         return rc;
3906 }
3907
3908 /* Main API for qed clients to configure vport min rate.
3909  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3910  * rate - Speed in Mbps needs to be assigned to a given vport.
3911  */
3912 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3913 {
3914         int i, rc = -EINVAL;
3915
3916         /* Currently not supported; Might change in future */
3917         if (cdev->num_hwfns > 1) {
3918                 DP_NOTICE(cdev,
3919                           "WFQ configuration is not supported for this device\n");
3920                 return rc;
3921         }
3922
3923         for_each_hwfn(cdev, i) {
3924                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3925                 struct qed_ptt *p_ptt;
3926
3927                 p_ptt = qed_ptt_acquire(p_hwfn);
3928                 if (!p_ptt)
3929                         return -EBUSY;
3930
3931                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3932
3933                 if (rc) {
3934                         qed_ptt_release(p_hwfn, p_ptt);
3935                         return rc;
3936                 }
3937
3938                 qed_ptt_release(p_hwfn, p_ptt);
3939         }
3940
3941         return rc;
3942 }
3943
3944 /* API to configure WFQ from mcp link change */
3945 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3946                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
3947 {
3948         int i;
3949
3950         if (cdev->num_hwfns > 1) {
3951                 DP_VERBOSE(cdev,
3952                            NETIF_MSG_LINK,
3953                            "WFQ configuration is not supported for this device\n");
3954                 return;
3955         }
3956
3957         for_each_hwfn(cdev, i) {
3958                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3959
3960                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
3961                                                       min_pf_rate);
3962         }
3963 }
3964
3965 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3966                                      struct qed_ptt *p_ptt,
3967                                      struct qed_mcp_link_state *p_link,
3968                                      u8 max_bw)
3969 {
3970         int rc = 0;
3971
3972         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3973
3974         if (!p_link->line_speed && (max_bw != 100))
3975                 return rc;
3976
3977         p_link->speed = (p_link->line_speed * max_bw) / 100;
3978         p_hwfn->qm_info.pf_rl = p_link->speed;
3979
3980         /* Since the limiter also affects Tx-switched traffic, we don't want it
3981          * to limit such traffic in case there's no actual limit.
3982          * In that case, set limit to imaginary high boundary.
3983          */
3984         if (max_bw == 100)
3985                 p_hwfn->qm_info.pf_rl = 100000;
3986
3987         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3988                             p_hwfn->qm_info.pf_rl);
3989
3990         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3991                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3992                    p_link->speed);
3993
3994         return rc;
3995 }
3996
3997 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3998 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3999 {
4000         int i, rc = -EINVAL;
4001
4002         if (max_bw < 1 || max_bw > 100) {
4003                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4004                 return rc;
4005         }
4006
4007         for_each_hwfn(cdev, i) {
4008                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4009                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4010                 struct qed_mcp_link_state *p_link;
4011                 struct qed_ptt *p_ptt;
4012
4013                 p_link = &p_lead->mcp_info->link_output;
4014
4015                 p_ptt = qed_ptt_acquire(p_hwfn);
4016                 if (!p_ptt)
4017                         return -EBUSY;
4018
4019                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4020                                                       p_link, max_bw);
4021
4022                 qed_ptt_release(p_hwfn, p_ptt);
4023
4024                 if (rc)
4025                         break;
4026         }
4027
4028         return rc;
4029 }
4030
4031 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4032                                      struct qed_ptt *p_ptt,
4033                                      struct qed_mcp_link_state *p_link,
4034                                      u8 min_bw)
4035 {
4036         int rc = 0;
4037
4038         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4039         p_hwfn->qm_info.pf_wfq = min_bw;
4040
4041         if (!p_link->line_speed)
4042                 return rc;
4043
4044         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4045
4046         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4047
4048         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4049                    "Configured MIN bandwidth to be %d Mb/sec\n",
4050                    p_link->min_pf_rate);
4051
4052         return rc;
4053 }
4054
4055 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4056 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4057 {
4058         int i, rc = -EINVAL;
4059
4060         if (min_bw < 1 || min_bw > 100) {
4061                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4062                 return rc;
4063         }
4064
4065         for_each_hwfn(cdev, i) {
4066                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4067                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4068                 struct qed_mcp_link_state *p_link;
4069                 struct qed_ptt *p_ptt;
4070
4071                 p_link = &p_lead->mcp_info->link_output;
4072
4073                 p_ptt = qed_ptt_acquire(p_hwfn);
4074                 if (!p_ptt)
4075                         return -EBUSY;
4076
4077                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4078                                                       p_link, min_bw);
4079                 if (rc) {
4080                         qed_ptt_release(p_hwfn, p_ptt);
4081                         return rc;
4082                 }
4083
4084                 if (p_link->min_pf_rate) {
4085                         u32 min_rate = p_link->min_pf_rate;
4086
4087                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4088                                                                    p_ptt,
4089                                                                    min_rate);
4090                 }
4091
4092                 qed_ptt_release(p_hwfn, p_ptt);
4093         }
4094
4095         return rc;
4096 }
4097
4098 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4099 {
4100         struct qed_mcp_link_state *p_link;
4101
4102         p_link = &p_hwfn->mcp_info->link_output;
4103
4104         if (p_link->min_pf_rate)
4105                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4106                                                p_link->min_pf_rate);
4107
4108         memset(p_hwfn->qm_info.wfq_data, 0,
4109                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4110 }
4111
4112 int qed_device_num_engines(struct qed_dev *cdev)
4113 {
4114         return QED_IS_BB(cdev) ? 2 : 1;
4115 }
4116
4117 static int qed_device_num_ports(struct qed_dev *cdev)
4118 {
4119         /* in CMT always only one port */
4120         if (cdev->num_hwfns > 1)
4121                 return 1;
4122
4123         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4124 }
4125
4126 int qed_device_get_port_id(struct qed_dev *cdev)
4127 {
4128         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4129 }
4130
4131 void qed_set_fw_mac_addr(__le16 *fw_msb,
4132                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4133 {
4134         ((u8 *)fw_msb)[0] = mac[1];
4135         ((u8 *)fw_msb)[1] = mac[0];
4136         ((u8 *)fw_mid)[0] = mac[3];
4137         ((u8 *)fw_mid)[1] = mac[2];
4138         ((u8 *)fw_lsb)[0] = mac[5];
4139         ((u8 *)fw_lsb)[1] = mac[4];
4140 }