drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mutex.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/qed/qed_chain.h>
  23 #include <linux/qed/qed_if.h>
  24 #include "qed.h"
  25 #include "qed_cxt.h"
  26 #include "qed_dcbx.h"
  27 #include "qed_dev_api.h"
  28 #include "qed_hsi.h"
  29 #include "qed_hw.h"
  30 #include "qed_init_ops.h"
  31 #include "qed_int.h"
  32 #include "qed_ll2.h"
  33 #include "qed_mcp.h"
  34 #include "qed_reg_addr.h"
  35 #include "qed_sp.h"
  36 #include "qed_sriov.h"
  37 #include "qed_vf.h"
  38
  39 static DEFINE_SPINLOCK(qm_lock);
  40
  41 /* API common to all protocols */
  42 enum BAR_ID {
  43         BAR_ID_0,       /* used for GRC */
  44         BAR_ID_1        /* Used for doorbells */
  45 };
  46
  47 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
  48 {
  49         u32 bar_reg = (bar_id == BAR_ID_0 ?
  50                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  51         u32 val;
  52
  53         if (IS_VF(p_hwfn->cdev))
  54                 return 1 << 17;
  55
  56         val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  57         if (val)
  58                 return 1 << (val + 15);
  59
  60         /* Old MFW initialized above registered only conditionally */
  61         if (p_hwfn->cdev->num_hwfns > 1) {
  62                 DP_INFO(p_hwfn,
  63                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  64                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  65         } else {
  66                 DP_INFO(p_hwfn,
  67                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  68                         return 512 * 1024;
  69         }
  70 }
  71
  72 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  73 {
  74         u32 i;
  75
  76         cdev->dp_level = dp_level;
  77         cdev->dp_module = dp_module;
  78         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  79                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  80
  81                 p_hwfn->dp_level = dp_level;
  82                 p_hwfn->dp_module = dp_module;
  83         }
  84 }
  85
  86 void qed_init_struct(struct qed_dev *cdev)
  87 {
  88         u8 i;
  89
  90         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  91                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  92
  93                 p_hwfn->cdev = cdev;
  94                 p_hwfn->my_id = i;
  95                 p_hwfn->b_active = false;
  96
  97                 mutex_init(&p_hwfn->dmae_info.mutex);
  98         }
  99
 100         /* hwfn 0 is always active */
 101         cdev->hwfns[0].b_active = true;
 102
 103         /* set the default cache alignment to 128 */
 104         cdev->cache_shift = 7;
 105 }
 106
 107 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 108 {
 109         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 110
 111         kfree(qm_info->qm_pq_params);
 112         qm_info->qm_pq_params = NULL;
 113         kfree(qm_info->qm_vport_params);
 114         qm_info->qm_vport_params = NULL;
 115         kfree(qm_info->qm_port_params);
 116         qm_info->qm_port_params = NULL;
 117         kfree(qm_info->wfq_data);
 118         qm_info->wfq_data = NULL;
 119 }
 120
 121 void qed_resc_free(struct qed_dev *cdev)
 122 {
 123         int i;
 124
 125         if (IS_VF(cdev))
 126                 return;
 127
 128         kfree(cdev->fw_data);
 129         cdev->fw_data = NULL;
 130
 131         kfree(cdev->reset_stats);
 132
 133         for_each_hwfn(cdev, i) {
 134                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 135
 136                 kfree(p_hwfn->p_tx_cids);
 137                 p_hwfn->p_tx_cids = NULL;
 138                 kfree(p_hwfn->p_rx_cids);
 139                 p_hwfn->p_rx_cids = NULL;
 140         }
 141
 142         for_each_hwfn(cdev, i) {
 143                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 144
 145                 qed_cxt_mngr_free(p_hwfn);
 146                 qed_qm_info_free(p_hwfn);
 147                 qed_spq_free(p_hwfn);
 148                 qed_eq_free(p_hwfn, p_hwfn->p_eq);
 149                 qed_consq_free(p_hwfn, p_hwfn->p_consq);
 150                 qed_int_free(p_hwfn);
 151 #ifdef CONFIG_QED_LL2
 152                 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 153 #endif
 154                 qed_iov_free(p_hwfn);
 155                 qed_dmae_info_free(p_hwfn);
 156                 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 157         }
 158 }
 159
 160 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
 161 {
 162         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
 163         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 164         struct init_qm_port_params *p_qm_port;
 165         bool init_rdma_offload_pq = false;
 166         bool init_pure_ack_pq = false;
 167         bool init_ooo_pq = false;
 168         u16 num_pqs, multi_cos_tcs = 1;
 169         u8 pf_wfq = qm_info->pf_wfq;
 170         u32 pf_rl = qm_info->pf_rl;
 171         u16 num_pf_rls = 0;
 172         u16 num_vfs = 0;
 173
 174 #ifdef CONFIG_QED_SRIOV
 175         if (p_hwfn->cdev->p_iov_info)
 176                 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
 177 #endif
 178         memset(qm_info, 0, sizeof(*qm_info));
 179
 180         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 181         num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
 182
 183         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 184                 num_pqs++;      /* for RoCE queue */
 185                 init_rdma_offload_pq = true;
 186                 /* we subtract num_vfs because each require a rate limiter,
 187                  * and one default rate limiter
 188                  */
 189                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
 190                         num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
 191
 192                 num_pqs += num_pf_rls;
 193                 qm_info->num_pf_rls = (u8) num_pf_rls;
 194         }
 195
 196         if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 197                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 198                 init_pure_ack_pq = true;
 199                 init_ooo_pq = true;
 200         }
 201
 202         /* Sanity checking that setup requires legal number of resources */
 203         if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
 204                 DP_ERR(p_hwfn,
 205                        "Need too many Physical queues - 0x%04x when only %04x are available\n",
 206                        num_pqs, RESC_NUM(p_hwfn, QED_PQ));
 207                 return -EINVAL;
 208         }
 209
 210         /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
 211          */
 212         qm_info->qm_pq_params = kcalloc(num_pqs,
 213                                         sizeof(struct init_qm_pq_params),
 214                                         b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 215         if (!qm_info->qm_pq_params)
 216                 goto alloc_err;
 217
 218         qm_info->qm_vport_params = kcalloc(num_vports,
 219                                            sizeof(struct init_qm_vport_params),
 220                                            b_sleepable ? GFP_KERNEL
 221                                                        : GFP_ATOMIC);
 222         if (!qm_info->qm_vport_params)
 223                 goto alloc_err;
 224
 225         qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
 226                                           sizeof(struct init_qm_port_params),
 227                                           b_sleepable ? GFP_KERNEL
 228                                                       : GFP_ATOMIC);
 229         if (!qm_info->qm_port_params)
 230                 goto alloc_err;
 231
 232         qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
 233                                     b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 234         if (!qm_info->wfq_data)
 235                 goto alloc_err;
 236
 237         vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
 238
 239         /* First init rate limited queues */
 240         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 241                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 242                 qm_info->qm_pq_params[curr_queue].tc_id =
 243                     p_hwfn->hw_info.non_offload_tc;
 244                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 245                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 246         }
 247
 248         /* First init per-TC PQs */
 249         for (i = 0; i < multi_cos_tcs; i++) {
 250                 struct init_qm_pq_params *params =
 251                     &qm_info->qm_pq_params[curr_queue++];
 252
 253                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
 254                     p_hwfn->hw_info.personality == QED_PCI_ETH) {
 255                         params->vport_id = vport_id;
 256                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 257                         params->wrr_group = 1;
 258                 } else {
 259                         params->vport_id = vport_id;
 260                         params->tc_id = p_hwfn->hw_info.offload_tc;
 261                         params->wrr_group = 1;
 262                 }
 263         }
 264
 265         /* Then init pure-LB PQ */
 266         qm_info->pure_lb_pq = curr_queue;
 267         qm_info->qm_pq_params[curr_queue].vport_id =
 268             (u8) RESC_START(p_hwfn, QED_VPORT);
 269         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 270         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 271         curr_queue++;
 272
 273         qm_info->offload_pq = 0;
 274         if (init_rdma_offload_pq) {
 275                 qm_info->offload_pq = curr_queue;
 276                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 277                 qm_info->qm_pq_params[curr_queue].tc_id =
 278                     p_hwfn->hw_info.offload_tc;
 279                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 280                 curr_queue++;
 281         }
 282
 283         if (init_pure_ack_pq) {
 284                 qm_info->pure_ack_pq = curr_queue;
 285                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 286                 qm_info->qm_pq_params[curr_queue].tc_id =
 287                     p_hwfn->hw_info.offload_tc;
 288                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 289                 curr_queue++;
 290         }
 291
 292         if (init_ooo_pq) {
 293                 qm_info->ooo_pq = curr_queue;
 294                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 295                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 296                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 297                 curr_queue++;
 298         }
 299
 300         /* Then init per-VF PQs */
 301         vf_offset = curr_queue;
 302         for (i = 0; i < num_vfs; i++) {
 303                 /* First vport is used by the PF */
 304                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 305                 qm_info->qm_pq_params[curr_queue].tc_id =
 306                     p_hwfn->hw_info.non_offload_tc;
 307                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 308                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 309                 curr_queue++;
 310         }
 311
 312         qm_info->vf_queues_offset = vf_offset;
 313         qm_info->num_pqs = num_pqs;
 314         qm_info->num_vports = num_vports;
 315
 316         /* Initialize qm port parameters */
 317         num_ports = p_hwfn->cdev->num_ports_in_engines;
 318         for (i = 0; i < num_ports; i++) {
 319                 p_qm_port = &qm_info->qm_port_params[i];
 320                 p_qm_port->active = 1;
 321                 if (num_ports == 4)
 322                         p_qm_port->active_phys_tcs = 0x7;
 323                 else
 324                         p_qm_port->active_phys_tcs = 0x9f;
 325                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 326                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 327         }
 328
 329         qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 330
 331         qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
 332
 333         qm_info->num_vf_pqs = num_vfs;
 334         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 335
 336         for (i = 0; i < qm_info->num_vports; i++)
 337                 qm_info->qm_vport_params[i].vport_wfq = 1;
 338
 339         qm_info->vport_rl_en = 1;
 340         qm_info->vport_wfq_en = 1;
 341         qm_info->pf_rl = pf_rl;
 342         qm_info->pf_wfq = pf_wfq;
 343
 344         return 0;
 345
 346 alloc_err:
 347         qed_qm_info_free(p_hwfn);
 348         return -ENOMEM;
 349 }
 350
 351 /* This function reconfigures the QM pf on the fly.
 352  * For this purpose we:
 353  * 1. reconfigure the QM database
 354  * 2. set new values to runtime arrat
 355  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 356  * 4. activate init tool in QM_PF stage
 357  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 358  */
 359 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 360 {
 361         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 362         bool b_rc;
 363         int rc;
 364
 365         /* qm_info is allocated in qed_init_qm_info() which is already called
 366          * from qed_resc_alloc() or previous call of qed_qm_reconf().
 367          * The allocated size may change each init, so we free it before next
 368          * allocation.
 369          */
 370         qed_qm_info_free(p_hwfn);
 371
 372         /* initialize qed's qm data structure */
 373         rc = qed_init_qm_info(p_hwfn, false);
 374         if (rc)
 375                 return rc;
 376
 377         /* stop PF's qm queues */
 378         spin_lock_bh(&qm_lock);
 379         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 380                                     qm_info->start_pq, qm_info->num_pqs);
 381         spin_unlock_bh(&qm_lock);
 382         if (!b_rc)
 383                 return -EINVAL;
 384
 385         /* clear the QM_PF runtime phase leftovers from previous init */
 386         qed_init_clear_rt_data(p_hwfn);
 387
 388         /* prepare QM portion of runtime array */
 389         qed_qm_init_pf(p_hwfn);
 390
 391         /* activate init tool on runtime array */
 392         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 393                           p_hwfn->hw_info.hw_mode);
 394         if (rc)
 395                 return rc;
 396
 397         /* start PF's qm queues */
 398         spin_lock_bh(&qm_lock);
 399         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 400                                     qm_info->start_pq, qm_info->num_pqs);
 401         spin_unlock_bh(&qm_lock);
 402         if (!b_rc)
 403                 return -EINVAL;
 404
 405         return 0;
 406 }
 407
 408 int qed_resc_alloc(struct qed_dev *cdev)
 409 {
 410 #ifdef CONFIG_QED_LL2
 411         struct qed_ll2_info *p_ll2_info;
 412 #endif
 413         struct qed_consq *p_consq;
 414         struct qed_eq *p_eq;
 415         int i, rc = 0;
 416
 417         if (IS_VF(cdev))
 418                 return rc;
 419
 420         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 421         if (!cdev->fw_data)
 422                 return -ENOMEM;
 423
 424         /* Allocate Memory for the Queue->CID mapping */
 425         for_each_hwfn(cdev, i) {
 426                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 427                 int tx_size = sizeof(struct qed_hw_cid_data) *
 428                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 429                 int rx_size = sizeof(struct qed_hw_cid_data) *
 430                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 431
 432                 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
 433                 if (!p_hwfn->p_tx_cids)
 434                         goto alloc_no_mem;
 435
 436                 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
 437                 if (!p_hwfn->p_rx_cids)
 438                         goto alloc_no_mem;
 439         }
 440
 441         for_each_hwfn(cdev, i) {
 442                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 443                 u32 n_eqes, num_cons;
 444
 445                 /* First allocate the context manager structure */
 446                 rc = qed_cxt_mngr_alloc(p_hwfn);
 447                 if (rc)
 448                         goto alloc_err;
 449
 450                 /* Set the HW cid/tid numbers (in the contest manager)
 451                  * Must be done prior to any further computations.
 452                  */
 453                 rc = qed_cxt_set_pf_params(p_hwfn);
 454                 if (rc)
 455                         goto alloc_err;
 456
 457                 /* Prepare and process QM requirements */
 458                 rc = qed_init_qm_info(p_hwfn, true);
 459                 if (rc)
 460                         goto alloc_err;
 461
 462                 /* Compute the ILT client partition */
 463                 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
 464                 if (rc)
 465                         goto alloc_err;
 466
 467                 /* CID map / ILT shadow table / T2
 468                  * The talbes sizes are determined by the computations above
 469                  */
 470                 rc = qed_cxt_tables_alloc(p_hwfn);
 471                 if (rc)
 472                         goto alloc_err;
 473
 474                 /* SPQ, must follow ILT because initializes SPQ context */
 475                 rc = qed_spq_alloc(p_hwfn);
 476                 if (rc)
 477                         goto alloc_err;
 478
 479                 /* SP status block allocation */
 480                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 481                                                          RESERVED_PTT_DPC);
 482
 483                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 484                 if (rc)
 485                         goto alloc_err;
 486
 487                 rc = qed_iov_alloc(p_hwfn);
 488                 if (rc)
 489                         goto alloc_err;
 490
 491                 /* EQ */
 492                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 493                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 494                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 495                                                                PROTOCOLID_ROCE,
 496                                                                0) * 2;
 497                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 498                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 499                         num_cons =
 500                             qed_cxt_get_proto_cid_count(p_hwfn,
 501                                                         PROTOCOLID_ISCSI, 0);
 502                         n_eqes += 2 * num_cons;
 503                 }
 504
 505                 if (n_eqes > 0xFFFF) {
 506                         DP_ERR(p_hwfn,
 507                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 508                                n_eqes, 0xFFFF);
 509                         rc = -EINVAL;
 510                         goto alloc_err;
 511                 }
 512
 513                 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 514                 if (!p_eq)
 515                         goto alloc_no_mem;
 516                 p_hwfn->p_eq = p_eq;
 517
 518                 p_consq = qed_consq_alloc(p_hwfn);
 519                 if (!p_consq)
 520                         goto alloc_no_mem;
 521                 p_hwfn->p_consq = p_consq;
 522
 523 #ifdef CONFIG_QED_LL2
 524                 if (p_hwfn->using_ll2) {
 525                         p_ll2_info = qed_ll2_alloc(p_hwfn);
 526                         if (!p_ll2_info)
 527                                 goto alloc_no_mem;
 528                         p_hwfn->p_ll2_info = p_ll2_info;
 529                 }
 530 #endif
 531
 532                 /* DMA info initialization */
 533                 rc = qed_dmae_info_alloc(p_hwfn);
 534                 if (rc)
 535                         goto alloc_err;
 536
 537                 /* DCBX initialization */
 538                 rc = qed_dcbx_info_alloc(p_hwfn);
 539                 if (rc)
 540                         goto alloc_err;
 541         }
 542
 543         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 544         if (!cdev->reset_stats)
 545                 goto alloc_no_mem;
 546
 547         return 0;
 548
 549 alloc_no_mem:
 550         rc = -ENOMEM;
 551 alloc_err:
 552         qed_resc_free(cdev);
 553         return rc;
 554 }
 555
 556 void qed_resc_setup(struct qed_dev *cdev)
 557 {
 558         int i;
 559
 560         if (IS_VF(cdev))
 561                 return;
 562
 563         for_each_hwfn(cdev, i) {
 564                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 565
 566                 qed_cxt_mngr_setup(p_hwfn);
 567                 qed_spq_setup(p_hwfn);
 568                 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
 569                 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
 570
 571                 /* Read shadow of current MFW mailbox */
 572                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 573                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 574                        p_hwfn->mcp_info->mfw_mb_cur,
 575                        p_hwfn->mcp_info->mfw_mb_length);
 576
 577                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 578
 579                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 580 #ifdef CONFIG_QED_LL2
 581                 if (p_hwfn->using_ll2)
 582                         qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 583 #endif
 584         }
 585 }
 586
 587 #define FINAL_CLEANUP_POLL_CNT          (100)
 588 #define FINAL_CLEANUP_POLL_TIME         (10)
 589 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
 590                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
 591 {
 592         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 593         int rc = -EBUSY;
 594
 595         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 596                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 597
 598         if (is_vf)
 599                 id += 0x10;
 600
 601         command |= X_FINAL_CLEANUP_AGG_INT <<
 602                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 603         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 604         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 605         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 606
 607         /* Make sure notification is not set before initiating final cleanup */
 608         if (REG_RD(p_hwfn, addr)) {
 609                 DP_NOTICE(p_hwfn,
 610                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
 611                 REG_WR(p_hwfn, addr, 0);
 612         }
 613
 614         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
 615                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 616                    id, command);
 617
 618         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 619
 620         /* Poll until completion */
 621         while (!REG_RD(p_hwfn, addr) && count--)
 622                 msleep(FINAL_CLEANUP_POLL_TIME);
 623
 624         if (REG_RD(p_hwfn, addr))
 625                 rc = 0;
 626         else
 627                 DP_NOTICE(p_hwfn,
 628                           "Failed to receive FW final cleanup notification\n");
 629
 630         /* Cleanup afterwards */
 631         REG_WR(p_hwfn, addr, 0);
 632
 633         return rc;
 634 }
 635
 636 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
 637 {
 638         int hw_mode = 0;
 639
 640         hw_mode = (1 << MODE_BB_B0);
 641
 642         switch (p_hwfn->cdev->num_ports_in_engines) {
 643         case 1:
 644                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 645                 break;
 646         case 2:
 647                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 648                 break;
 649         case 4:
 650                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 651                 break;
 652         default:
 653                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
 654                           p_hwfn->cdev->num_ports_in_engines);
 655                 return;
 656         }
 657
 658         switch (p_hwfn->cdev->mf_mode) {
 659         case QED_MF_DEFAULT:
 660         case QED_MF_NPAR:
 661                 hw_mode |= 1 << MODE_MF_SI;
 662                 break;
 663         case QED_MF_OVLAN:
 664                 hw_mode |= 1 << MODE_MF_SD;
 665                 break;
 666         default:
 667                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 668                 hw_mode |= 1 << MODE_MF_SI;
 669         }
 670
 671         hw_mode |= 1 << MODE_ASIC;
 672
 673         if (p_hwfn->cdev->num_hwfns > 1)
 674                 hw_mode |= 1 << MODE_100G;
 675
 676         p_hwfn->hw_info.hw_mode = hw_mode;
 677
 678         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
 679                    "Configuring function for hw_mode: 0x%08x\n",
 680                    p_hwfn->hw_info.hw_mode);
 681 }
 682
 683 /* Init run time data for all PFs on an engine. */
 684 static void qed_init_cau_rt_data(struct qed_dev *cdev)
 685 {
 686         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 687         int i, sb_id;
 688
 689         for_each_hwfn(cdev, i) {
 690                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 691                 struct qed_igu_info *p_igu_info;
 692                 struct qed_igu_block *p_block;
 693                 struct cau_sb_entry sb_entry;
 694
 695                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 696
 697                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
 698                      sb_id++) {
 699                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 700                         if (!p_block->is_pf)
 701                                 continue;
 702
 703                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
 704                                               p_block->function_id, 0, 0);
 705                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 706                 }
 707         }
 708 }
 709
 710 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
 711                               struct qed_ptt *p_ptt, int hw_mode)
 712 {
 713         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 714         struct qed_qm_common_rt_init_params params;
 715         struct qed_dev *cdev = p_hwfn->cdev;
 716         u16 num_pfs, pf_id;
 717         u32 concrete_fid;
 718         int rc = 0;
 719         u8 vf_id;
 720
 721         qed_init_cau_rt_data(cdev);
 722
 723         /* Program GTT windows */
 724         qed_gtt_init(p_hwfn);
 725
 726         if (p_hwfn->mcp_info) {
 727                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 728                         qm_info->pf_rl_en = 1;
 729                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 730                         qm_info->pf_wfq_en = 1;
 731         }
 732
 733         memset(&params, 0, sizeof(params));
 734         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
 735         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
 736         params.pf_rl_en = qm_info->pf_rl_en;
 737         params.pf_wfq_en = qm_info->pf_wfq_en;
 738         params.vport_rl_en = qm_info->vport_rl_en;
 739         params.vport_wfq_en = qm_info->vport_wfq_en;
 740         params.port_params = qm_info->qm_port_params;
 741
 742         qed_qm_common_rt_init(p_hwfn, &params);
 743
 744         qed_cxt_hw_init_common(p_hwfn);
 745
 746         /* Close gate from NIG to BRB/Storm; By default they are open, but
 747          * we close them to prevent NIG from passing data to reset blocks.
 748          * Should have been done in the ENGINE phase, but init-tool lacks
 749          * proper port-pretend capabilities.
 750          */
 751         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 752         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 753         qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 754         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 755         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 756         qed_port_unpretend(p_hwfn, p_ptt);
 757
 758         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 759         if (rc)
 760                 return rc;
 761
 762         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 763         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 764
 765         if (QED_IS_BB(p_hwfn->cdev)) {
 766                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
 767                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
 768                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
 769                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
 770                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
 771                 }
 772                 /* pretend to original PF */
 773                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 774         }
 775
 776         for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
 777                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
 778                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
 779                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 780                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
 781                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
 782                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
 783         }
 784         /* pretend to original PF */
 785         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 786
 787         return rc;
 788 }
 789
 790 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
 791                             struct qed_ptt *p_ptt, int hw_mode)
 792 {
 793         return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
 794                             p_hwfn->port_id, hw_mode);
 795 }
 796
 797 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
 798                           struct qed_ptt *p_ptt,
 799                           struct qed_tunn_start_params *p_tunn,
 800                           int hw_mode,
 801                           bool b_hw_start,
 802                           enum qed_int_mode int_mode,
 803                           bool allow_npar_tx_switch)
 804 {
 805         u8 rel_pf_id = p_hwfn->rel_pf_id;
 806         int rc = 0;
 807
 808         if (p_hwfn->mcp_info) {
 809                 struct qed_mcp_function_info *p_info;
 810
 811                 p_info = &p_hwfn->mcp_info->func_info;
 812                 if (p_info->bandwidth_min)
 813                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
 814
 815                 /* Update rate limit once we'll actually have a link */
 816                 p_hwfn->qm_info.pf_rl = 100000;
 817         }
 818
 819         qed_cxt_hw_init_pf(p_hwfn);
 820
 821         qed_int_igu_init_rt(p_hwfn);
 822
 823         /* Set VLAN in NIG if needed */
 824         if (hw_mode & BIT(MODE_MF_SD)) {
 825                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
 826                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
 827                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
 828                              p_hwfn->hw_info.ovlan);
 829         }
 830
 831         /* Enable classification by MAC if needed */
 832         if (hw_mode & BIT(MODE_MF_SI)) {
 833                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
 834                            "Configuring TAGMAC_CLS_TYPE\n");
 835                 STORE_RT_REG(p_hwfn,
 836                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
 837         }
 838
 839         /* Protocl Configuration  */
 840         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
 841                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
 842         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
 843         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
 844
 845         /* Cleanup chip from previous driver if such remains exist */
 846         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
 847         if (rc)
 848                 return rc;
 849
 850         /* PF Init sequence */
 851         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
 852         if (rc)
 853                 return rc;
 854
 855         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
 856         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
 857         if (rc)
 858                 return rc;
 859
 860         /* Pure runtime initializations - directly to the HW  */
 861         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
 862
 863         if (b_hw_start) {
 864                 /* enable interrupts */
 865                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
 866
 867                 /* send function start command */
 868                 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
 869                                      allow_npar_tx_switch);
 870                 if (rc)
 871                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
 872         }
 873         return rc;
 874 }
 875
 876 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
 877                                struct qed_ptt *p_ptt,
 878                                u8 enable)
 879 {
 880         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
 881
 882         /* Change PF in PXP */
 883         qed_wr(p_hwfn, p_ptt,
 884                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
 885
 886         /* wait until value is set - try for 1 second every 50us */
 887         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
 888                 val = qed_rd(p_hwfn, p_ptt,
 889                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
 890                 if (val == set_val)
 891                         break;
 892
 893                 usleep_range(50, 60);
 894         }
 895
 896         if (val != set_val) {
 897                 DP_NOTICE(p_hwfn,
 898                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
 899                 return -EAGAIN;
 900         }
 901
 902         return 0;
 903 }
 904
 905 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
 906                                 struct qed_ptt *p_main_ptt)
 907 {
 908         /* Read shadow of current MFW mailbox */
 909         qed_mcp_read_mb(p_hwfn, p_main_ptt);
 910         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 911                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
 912 }
 913
 914 int qed_hw_init(struct qed_dev *cdev,
 915                 struct qed_tunn_start_params *p_tunn,
 916                 bool b_hw_start,
 917                 enum qed_int_mode int_mode,
 918                 bool allow_npar_tx_switch,
 919                 const u8 *bin_fw_data)
 920 {
 921         u32 load_code, param;
 922         int rc, mfw_rc, i;
 923
 924         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
 925                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
 926                 return -EINVAL;
 927         }
 928
 929         if (IS_PF(cdev)) {
 930                 rc = qed_init_fw_data(cdev, bin_fw_data);
 931                 if (rc)
 932                         return rc;
 933         }
 934
 935         for_each_hwfn(cdev, i) {
 936                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 937
 938                 if (IS_VF(cdev)) {
 939                         p_hwfn->b_int_enabled = 1;
 940                         continue;
 941                 }
 942
 943                 /* Enable DMAE in PXP */
 944                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
 945
 946                 qed_calc_hw_mode(p_hwfn);
 947
 948                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
 949                 if (rc) {
 950                         DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
 951                         return rc;
 952                 }
 953
 954                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
 955
 956                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 957                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
 958                            rc, load_code);
 959
 960                 p_hwfn->first_on_engine = (load_code ==
 961                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
 962
 963                 switch (load_code) {
 964                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
 965                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
 966                                                 p_hwfn->hw_info.hw_mode);
 967                         if (rc)
 968                                 break;
 969                 /* Fall into */
 970                 case FW_MSG_CODE_DRV_LOAD_PORT:
 971                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
 972                                               p_hwfn->hw_info.hw_mode);
 973                         if (rc)
 974                                 break;
 975
 976                 /* Fall into */
 977                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
 978                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
 979                                             p_tunn, p_hwfn->hw_info.hw_mode,
 980                                             b_hw_start, int_mode,
 981                                             allow_npar_tx_switch);
 982                         break;
 983                 default:
 984                         rc = -EINVAL;
 985                         break;
 986                 }
 987
 988                 if (rc)
 989                         DP_NOTICE(p_hwfn,
 990                                   "init phase failed for loadcode 0x%x (rc %d)\n",
 991                                    load_code, rc);
 992
 993                 /* ACK mfw regardless of success or failure of initialization */
 994                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
 995                                      DRV_MSG_CODE_LOAD_DONE,
 996                                      0, &load_code, &param);
 997                 if (rc)
 998                         return rc;
 999                 if (mfw_rc) {
1000                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1001                         return mfw_rc;
1002                 }
1003
1004                 /* send DCBX attention request command */
1005                 DP_VERBOSE(p_hwfn,
1006                            QED_MSG_DCB,
1007                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1008                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1009                                      DRV_MSG_CODE_SET_DCBX,
1010                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1011                                      &load_code, &param);
1012                 if (mfw_rc) {
1013                         DP_NOTICE(p_hwfn,
1014                                   "Failed to send DCBX attention request\n");
1015                         return mfw_rc;
1016                 }
1017
1018                 p_hwfn->hw_init_done = true;
1019         }
1020
1021         return 0;
1022 }
1023
1024 #define QED_HW_STOP_RETRY_LIMIT (10)
1025 static void qed_hw_timers_stop(struct qed_dev *cdev,
1026                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1027 {
1028         int i;
1029
1030         /* close timers */
1031         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1032         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1033
1034         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1035                 if ((!qed_rd(p_hwfn, p_ptt,
1036                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1037                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1038                         break;
1039
1040                 /* Dependent on number of connection/tasks, possibly
1041                  * 1ms sleep is required between polls
1042                  */
1043                 usleep_range(1000, 2000);
1044         }
1045
1046         if (i < QED_HW_STOP_RETRY_LIMIT)
1047                 return;
1048
1049         DP_NOTICE(p_hwfn,
1050                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1051                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1052                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1053 }
1054
1055 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1056 {
1057         int j;
1058
1059         for_each_hwfn(cdev, j) {
1060                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1061                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1062
1063                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1064         }
1065 }
1066
1067 int qed_hw_stop(struct qed_dev *cdev)
1068 {
1069         int rc = 0, t_rc;
1070         int j;
1071
1072         for_each_hwfn(cdev, j) {
1073                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1074                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1075
1076                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1077
1078                 if (IS_VF(cdev)) {
1079                         qed_vf_pf_int_cleanup(p_hwfn);
1080                         continue;
1081                 }
1082
1083                 /* mark the hw as uninitialized... */
1084                 p_hwfn->hw_init_done = false;
1085
1086                 rc = qed_sp_pf_stop(p_hwfn);
1087                 if (rc)
1088                         DP_NOTICE(p_hwfn,
1089                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1090
1091                 qed_wr(p_hwfn, p_ptt,
1092                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1093
1094                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1095                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1096                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1097                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1098                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1099
1100                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1101
1102                 /* Disable Attention Generation */
1103                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1104
1105                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1106                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1107
1108                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1109
1110                 /* Need to wait 1ms to guarantee SBs are cleared */
1111                 usleep_range(1000, 2000);
1112         }
1113
1114         if (IS_PF(cdev)) {
1115                 /* Disable DMAE in PXP - in CMT, this should only be done for
1116                  * first hw-function, and only after all transactions have
1117                  * stopped for all active hw-functions.
1118                  */
1119                 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1120                                            cdev->hwfns[0].p_main_ptt, false);
1121                 if (t_rc != 0)
1122                         rc = t_rc;
1123         }
1124
1125         return rc;
1126 }
1127
1128 void qed_hw_stop_fastpath(struct qed_dev *cdev)
1129 {
1130         int j;
1131
1132         for_each_hwfn(cdev, j) {
1133                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1134                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1135
1136                 if (IS_VF(cdev)) {
1137                         qed_vf_pf_int_cleanup(p_hwfn);
1138                         continue;
1139                 }
1140
1141                 DP_VERBOSE(p_hwfn,
1142                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1143
1144                 qed_wr(p_hwfn, p_ptt,
1145                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1146
1147                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1148                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1149                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1150                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1151                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1152
1153                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1154
1155                 /* Need to wait 1ms to guarantee SBs are cleared */
1156                 usleep_range(1000, 2000);
1157         }
1158 }
1159
1160 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1161 {
1162         if (IS_VF(p_hwfn->cdev))
1163                 return;
1164
1165         /* Re-open incoming traffic */
1166         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1167                NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1168 }
1169
1170 static int qed_reg_assert(struct qed_hwfn *p_hwfn,
1171                           struct qed_ptt *p_ptt, u32 reg, bool expected)
1172 {
1173         u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);
1174
1175         if (assert_val != expected) {
1176                 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",
1177                           reg, expected);
1178                 return -EINVAL;
1179         }
1180
1181         return 0;
1182 }
1183
1184 int qed_hw_reset(struct qed_dev *cdev)
1185 {
1186         int rc = 0;
1187         u32 unload_resp, unload_param;
1188         int i;
1189
1190         for_each_hwfn(cdev, i) {
1191                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1192
1193                 if (IS_VF(cdev)) {
1194                         rc = qed_vf_pf_reset(p_hwfn);
1195                         if (rc)
1196                                 return rc;
1197                         continue;
1198                 }
1199
1200                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1201
1202                 /* Check for incorrect states */
1203                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1204                                QM_REG_USG_CNT_PF_TX, 0);
1205                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1206                                QM_REG_USG_CNT_PF_OTHER, 0);
1207
1208                 /* Disable PF in HW blocks */
1209                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1210                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1211                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1212                        TCFC_REG_STRONG_ENABLE_PF, 0);
1213                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1214                        CCFC_REG_STRONG_ENABLE_PF, 0);
1215
1216                 /* Send unload command to MCP */
1217                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1218                                  DRV_MSG_CODE_UNLOAD_REQ,
1219                                  DRV_MB_PARAM_UNLOAD_WOL_MCP,
1220                                  &unload_resp, &unload_param);
1221                 if (rc) {
1222                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1223                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1224                 }
1225
1226                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1227                                  DRV_MSG_CODE_UNLOAD_DONE,
1228                                  0, &unload_resp, &unload_param);
1229                 if (rc) {
1230                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1231                         return rc;
1232                 }
1233         }
1234
1235         return rc;
1236 }
1237
1238 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1239 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1240 {
1241         qed_ptt_pool_free(p_hwfn);
1242         kfree(p_hwfn->hw_info.p_igu_info);
1243 }
1244
1245 /* Setup bar access */
1246 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1247 {
1248         /* clear indirect access */
1249         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1250         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1251         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1252         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1253
1254         /* Clean Previous errors if such exist */
1255         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1256                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1257
1258         /* enable internal target-read */
1259         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1260                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1261 }
1262
1263 static void get_function_id(struct qed_hwfn *p_hwfn)
1264 {
1265         /* ME Register */
1266         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1267                                                   PXP_PF_ME_OPAQUE_ADDR);
1268
1269         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1270
1271         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1272         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1273                                       PXP_CONCRETE_FID_PFID);
1274         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1275                                     PXP_CONCRETE_FID_PORT);
1276
1277         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1278                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1279                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1280 }
1281
1282 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1283 {
1284         u32 *feat_num = p_hwfn->hw_info.feat_num;
1285         int num_features = 1;
1286
1287         feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1288                                                 num_features,
1289                                         RESC_NUM(p_hwfn, QED_L2_QUEUE));
1290         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1291                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1292                    feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1293                    num_features);
1294 }
1295
1296 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1297 {
1298         u8 enabled_func_idx = p_hwfn->enabled_func_idx;
1299         u32 *resc_start = p_hwfn->hw_info.resc_start;
1300         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1301         u32 *resc_num = p_hwfn->hw_info.resc_num;
1302         struct qed_sb_cnt_info sb_cnt_info;
1303         int i, max_vf_vlan_filters;
1304
1305         memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1306
1307 #ifdef CONFIG_QED_SRIOV
1308         max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1309 #else
1310         max_vf_vlan_filters = 0;
1311 #endif
1312
1313         qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1314
1315         resc_num[QED_SB] = min_t(u32,
1316                                  (MAX_SB_PER_PATH_BB / num_funcs),
1317                                  sb_cnt_info.sb_cnt);
1318         resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1319         resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1320         resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1321         resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1322         resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
1323         resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1324         resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1325                              num_funcs;
1326         resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
1327         resc_num[QED_LL2_QUEUE] = MAX_NUM_LL2_RX_QUEUES / num_funcs;
1328
1329         for (i = 0; i < QED_MAX_RESC; i++)
1330                 resc_start[i] = resc_num[i] * enabled_func_idx;
1331
1332         /* Sanity for ILT */
1333         if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
1334                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1335                           RESC_START(p_hwfn, QED_ILT),
1336                           RESC_END(p_hwfn, QED_ILT) - 1);
1337                 return -EINVAL;
1338         }
1339
1340         qed_hw_set_feat(p_hwfn);
1341
1342         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1343                    "The numbers for each resource are:\n"
1344                    "SB = %d start = %d\n"
1345                    "L2_QUEUE = %d start = %d\n"
1346                    "VPORT = %d start = %d\n"
1347                    "PQ = %d start = %d\n"
1348                    "RL = %d start = %d\n"
1349                    "MAC = %d start = %d\n"
1350                    "VLAN = %d start = %d\n"
1351                    "ILT = %d start = %d\n"
1352                    "LL2_QUEUE = %d start = %d\n",
1353                    p_hwfn->hw_info.resc_num[QED_SB],
1354                    p_hwfn->hw_info.resc_start[QED_SB],
1355                    p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1356                    p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1357                    p_hwfn->hw_info.resc_num[QED_VPORT],
1358                    p_hwfn->hw_info.resc_start[QED_VPORT],
1359                    p_hwfn->hw_info.resc_num[QED_PQ],
1360                    p_hwfn->hw_info.resc_start[QED_PQ],
1361                    p_hwfn->hw_info.resc_num[QED_RL],
1362                    p_hwfn->hw_info.resc_start[QED_RL],
1363                    p_hwfn->hw_info.resc_num[QED_MAC],
1364                    p_hwfn->hw_info.resc_start[QED_MAC],
1365                    p_hwfn->hw_info.resc_num[QED_VLAN],
1366                    p_hwfn->hw_info.resc_start[QED_VLAN],
1367                    p_hwfn->hw_info.resc_num[QED_ILT],
1368                    p_hwfn->hw_info.resc_start[QED_ILT],
1369                    RESC_NUM(p_hwfn, QED_LL2_QUEUE),
1370                    RESC_START(p_hwfn, QED_LL2_QUEUE));
1371
1372         return 0;
1373 }
1374
1375 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1376 {
1377         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1378         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1379         struct qed_mcp_link_params *link;
1380
1381         /* Read global nvm_cfg address */
1382         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1383
1384         /* Verify MCP has initialized it */
1385         if (!nvm_cfg_addr) {
1386                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1387                 return -EINVAL;
1388         }
1389
1390         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1391         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1392
1393         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1394                offsetof(struct nvm_cfg1, glob) +
1395                offsetof(struct nvm_cfg1_glob, core_cfg);
1396
1397         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1398
1399         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1400                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1401         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
1402                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1403                 break;
1404         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
1405                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1406                 break;
1407         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
1408                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1409                 break;
1410         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
1411                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1412                 break;
1413         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
1414                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1415                 break;
1416         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
1417                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1418                 break;
1419         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
1420                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1421                 break;
1422         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
1423                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1424                 break;
1425         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
1426                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1427                 break;
1428         default:
1429                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
1430                 break;
1431         }
1432
1433         /* Read default link configuration */
1434         link = &p_hwfn->mcp_info->link_input;
1435         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1436                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1437         link_temp = qed_rd(p_hwfn, p_ptt,
1438                            port_cfg_addr +
1439                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
1440         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1441         link->speed.advertised_speeds = link_temp;
1442
1443         link_temp = link->speed.advertised_speeds;
1444         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1445
1446         link_temp = qed_rd(p_hwfn, p_ptt,
1447                            port_cfg_addr +
1448                            offsetof(struct nvm_cfg1_port, link_settings));
1449         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1450                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1451         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1452                 link->speed.autoneg = true;
1453                 break;
1454         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1455                 link->speed.forced_speed = 1000;
1456                 break;
1457         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1458                 link->speed.forced_speed = 10000;
1459                 break;
1460         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1461                 link->speed.forced_speed = 25000;
1462                 break;
1463         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1464                 link->speed.forced_speed = 40000;
1465                 break;
1466         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1467                 link->speed.forced_speed = 50000;
1468                 break;
1469         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
1470                 link->speed.forced_speed = 100000;
1471                 break;
1472         default:
1473                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
1474         }
1475
1476         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1477         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1478         link->pause.autoneg = !!(link_temp &
1479                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1480         link->pause.forced_rx = !!(link_temp &
1481                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1482         link->pause.forced_tx = !!(link_temp &
1483                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1484         link->loopback_mode = 0;
1485
1486         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1487                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1488                    link->speed.forced_speed, link->speed.advertised_speeds,
1489                    link->speed.autoneg, link->pause.autoneg);
1490
1491         /* Read Multi-function information from shmem */
1492         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1493                offsetof(struct nvm_cfg1, glob) +
1494                offsetof(struct nvm_cfg1_glob, generic_cont0);
1495
1496         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1497
1498         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1499                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
1500
1501         switch (mf_mode) {
1502         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1503                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1504                 break;
1505         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1506                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1507                 break;
1508         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1509                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1510                 break;
1511         }
1512         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1513                 p_hwfn->cdev->mf_mode);
1514
1515         /* Read Multi-function information from shmem */
1516         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1517                 offsetof(struct nvm_cfg1, glob) +
1518                 offsetof(struct nvm_cfg1_glob, device_capabilities);
1519
1520         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1521         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1522                 __set_bit(QED_DEV_CAP_ETH,
1523                           &p_hwfn->hw_info.device_capabilities);
1524         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1525                 __set_bit(QED_DEV_CAP_ISCSI,
1526                           &p_hwfn->hw_info.device_capabilities);
1527         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1528                 __set_bit(QED_DEV_CAP_ROCE,
1529                           &p_hwfn->hw_info.device_capabilities);
1530
1531         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1532 }
1533
1534 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1535 {
1536         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
1537         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
1538
1539         num_funcs = MAX_NUM_PFS_BB;
1540
1541         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1542          * in the other bits are selected.
1543          * Bits 1-15 are for functions 1-15, respectively, and their value is
1544          * '0' only for enabled functions (function 0 always exists and
1545          * enabled).
1546          * In case of CMT, only the "even" functions are enabled, and thus the
1547          * number of functions for both hwfns is learnt from the same bits.
1548          */
1549         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1550
1551         if (reg_function_hide & 0x1) {
1552                 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1553                         num_funcs = 0;
1554                         eng_mask = 0xaaaa;
1555                 } else {
1556                         num_funcs = 1;
1557                         eng_mask = 0x5554;
1558                 }
1559
1560                 /* Get the number of the enabled functions on the engine */
1561                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1562                 while (tmp) {
1563                         if (tmp & 0x1)
1564                                 num_funcs++;
1565                         tmp >>= 0x1;
1566                 }
1567
1568                 /* Get the PF index within the enabled functions */
1569                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
1570                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
1571                 while (tmp) {
1572                         if (tmp & 0x1)
1573                                 enabled_func_idx--;
1574                         tmp >>= 0x1;
1575                 }
1576         }
1577
1578         p_hwfn->num_funcs_on_engine = num_funcs;
1579         p_hwfn->enabled_func_idx = enabled_func_idx;
1580
1581         DP_VERBOSE(p_hwfn,
1582                    NETIF_MSG_PROBE,
1583                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1584                    p_hwfn->rel_pf_id,
1585                    p_hwfn->abs_pf_id,
1586                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1587 }
1588
1589 static int
1590 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1591                 struct qed_ptt *p_ptt,
1592                 enum qed_pci_personality personality)
1593 {
1594         u32 port_mode;
1595         int rc;
1596
1597         /* Since all information is common, only first hwfns should do this */
1598         if (IS_LEAD_HWFN(p_hwfn)) {
1599                 rc = qed_iov_hw_info(p_hwfn);
1600                 if (rc)
1601                         return rc;
1602         }
1603
1604         /* Read the port mode */
1605         port_mode = qed_rd(p_hwfn, p_ptt,
1606                            CNIG_REG_NW_PORT_MODE_BB_B0);
1607
1608         if (port_mode < 3) {
1609                 p_hwfn->cdev->num_ports_in_engines = 1;
1610         } else if (port_mode <= 5) {
1611                 p_hwfn->cdev->num_ports_in_engines = 2;
1612         } else {
1613                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1614                           p_hwfn->cdev->num_ports_in_engines);
1615
1616                 /* Default num_ports_in_engines to something */
1617                 p_hwfn->cdev->num_ports_in_engines = 1;
1618         }
1619
1620         qed_hw_get_nvm_info(p_hwfn, p_ptt);
1621
1622         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1623         if (rc)
1624                 return rc;
1625
1626         if (qed_mcp_is_init(p_hwfn))
1627                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1628                                 p_hwfn->mcp_info->func_info.mac);
1629         else
1630                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1631
1632         if (qed_mcp_is_init(p_hwfn)) {
1633                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1634                         p_hwfn->hw_info.ovlan =
1635                                 p_hwfn->mcp_info->func_info.ovlan;
1636
1637                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1638         }
1639
1640         if (qed_mcp_is_init(p_hwfn)) {
1641                 enum qed_pci_personality protocol;
1642
1643                 protocol = p_hwfn->mcp_info->func_info.protocol;
1644                 p_hwfn->hw_info.personality = protocol;
1645         }
1646
1647         qed_get_num_funcs(p_hwfn, p_ptt);
1648
1649         return qed_hw_get_resc(p_hwfn);
1650 }
1651
1652 static int qed_get_dev_info(struct qed_dev *cdev)
1653 {
1654         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1655         u32 tmp;
1656
1657         /* Read Vendor Id / Device Id */
1658         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
1659         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
1660
1661         cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1662                                      MISCS_REG_CHIP_NUM);
1663         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1664                                      MISCS_REG_CHIP_REV);
1665         MASK_FIELD(CHIP_REV, cdev->chip_rev);
1666
1667         cdev->type = QED_DEV_TYPE_BB;
1668         /* Learn number of HW-functions */
1669         tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1670                      MISCS_REG_CMT_ENABLED_FOR_PAIR);
1671
1672         if (tmp & (1 << p_hwfn->rel_pf_id)) {
1673                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1674                 cdev->num_hwfns = 2;
1675         } else {
1676                 cdev->num_hwfns = 1;
1677         }
1678
1679         cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1680                                     MISCS_REG_CHIP_TEST_REG) >> 4;
1681         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1682         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1683                                        MISCS_REG_CHIP_METAL);
1684         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1685
1686         DP_INFO(cdev->hwfns,
1687                 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1688                 cdev->chip_num, cdev->chip_rev,
1689                 cdev->chip_bond_id, cdev->chip_metal);
1690
1691         if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1692                 DP_NOTICE(cdev->hwfns,
1693                           "The chip type/rev (BB A0) is not supported!\n");
1694                 return -EINVAL;
1695         }
1696
1697         return 0;
1698 }
1699
1700 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1701                                  void __iomem *p_regview,
1702                                  void __iomem *p_doorbells,
1703                                  enum qed_pci_personality personality)
1704 {
1705         int rc = 0;
1706
1707         /* Split PCI bars evenly between hwfns */
1708         p_hwfn->regview = p_regview;
1709         p_hwfn->doorbells = p_doorbells;
1710
1711         if (IS_VF(p_hwfn->cdev))
1712                 return qed_vf_hw_prepare(p_hwfn);
1713
1714         /* Validate that chip access is feasible */
1715         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1716                 DP_ERR(p_hwfn,
1717                        "Reading the ME register returns all Fs; Preventing further chip access\n");
1718                 return -EINVAL;
1719         }
1720
1721         get_function_id(p_hwfn);
1722
1723         /* Allocate PTT pool */
1724         rc = qed_ptt_pool_alloc(p_hwfn);
1725         if (rc)
1726                 goto err0;
1727
1728         /* Allocate the main PTT */
1729         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1730
1731         /* First hwfn learns basic information, e.g., number of hwfns */
1732         if (!p_hwfn->my_id) {
1733                 rc = qed_get_dev_info(p_hwfn->cdev);
1734                 if (rc)
1735                         goto err1;
1736         }
1737
1738         qed_hw_hwfn_prepare(p_hwfn);
1739
1740         /* Initialize MCP structure */
1741         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1742         if (rc) {
1743                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1744                 goto err1;
1745         }
1746
1747         /* Read the device configuration information from the HW and SHMEM */
1748         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1749         if (rc) {
1750                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1751                 goto err2;
1752         }
1753
1754         /* Allocate the init RT array and initialize the init-ops engine */
1755         rc = qed_init_alloc(p_hwfn);
1756         if (rc)
1757                 goto err2;
1758
1759         return rc;
1760 err2:
1761         if (IS_LEAD_HWFN(p_hwfn))
1762                 qed_iov_free_hw_info(p_hwfn->cdev);
1763         qed_mcp_free(p_hwfn);
1764 err1:
1765         qed_hw_hwfn_free(p_hwfn);
1766 err0:
1767         return rc;
1768 }
1769
1770 int qed_hw_prepare(struct qed_dev *cdev,
1771                    int personality)
1772 {
1773         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1774         int rc;
1775
1776         /* Store the precompiled init data ptrs */
1777         if (IS_PF(cdev))
1778                 qed_init_iro_array(cdev);
1779
1780         /* Initialize the first hwfn - will learn number of hwfns */
1781         rc = qed_hw_prepare_single(p_hwfn,
1782                                    cdev->regview,
1783                                    cdev->doorbells, personality);
1784         if (rc)
1785                 return rc;
1786
1787         personality = p_hwfn->hw_info.personality;
1788
1789         /* Initialize the rest of the hwfns */
1790         if (cdev->num_hwfns > 1) {
1791                 void __iomem *p_regview, *p_doorbell;
1792                 u8 __iomem *addr;
1793
1794                 /* adjust bar offset for second engine */
1795                 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1796                 p_regview = addr;
1797
1798                 /* adjust doorbell bar offset for second engine */
1799                 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1800                 p_doorbell = addr;
1801
1802                 /* prepare second hw function */
1803                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1804                                            p_doorbell, personality);
1805
1806                 /* in case of error, need to free the previously
1807                  * initiliazed hwfn 0.
1808                  */
1809                 if (rc) {
1810                         if (IS_PF(cdev)) {
1811                                 qed_init_free(p_hwfn);
1812                                 qed_mcp_free(p_hwfn);
1813                                 qed_hw_hwfn_free(p_hwfn);
1814                         }
1815                 }
1816         }
1817
1818         return rc;
1819 }
1820
1821 void qed_hw_remove(struct qed_dev *cdev)
1822 {
1823         int i;
1824
1825         for_each_hwfn(cdev, i) {
1826                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1827
1828                 if (IS_VF(cdev)) {
1829                         qed_vf_pf_release(p_hwfn);
1830                         continue;
1831                 }
1832
1833                 qed_init_free(p_hwfn);
1834                 qed_hw_hwfn_free(p_hwfn);
1835                 qed_mcp_free(p_hwfn);
1836         }
1837
1838         qed_iov_free_hw_info(cdev);
1839 }
1840
1841 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
1842                                     struct qed_chain *p_chain)
1843 {
1844         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
1845         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
1846         struct qed_chain_next *p_next;
1847         u32 size, i;
1848
1849         if (!p_virt)
1850                 return;
1851
1852         size = p_chain->elem_size * p_chain->usable_per_page;
1853
1854         for (i = 0; i < p_chain->page_cnt; i++) {
1855                 if (!p_virt)
1856                         break;
1857
1858                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
1859                 p_virt_next = p_next->next_virt;
1860                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
1861
1862                 dma_free_coherent(&cdev->pdev->dev,
1863                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
1864
1865                 p_virt = p_virt_next;
1866                 p_phys = p_phys_next;
1867         }
1868 }
1869
1870 static void qed_chain_free_single(struct qed_dev *cdev,
1871                                   struct qed_chain *p_chain)
1872 {
1873         if (!p_chain->p_virt_addr)
1874                 return;
1875
1876         dma_free_coherent(&cdev->pdev->dev,
1877                           QED_CHAIN_PAGE_SIZE,
1878                           p_chain->p_virt_addr, p_chain->p_phys_addr);
1879 }
1880
1881 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
1882 {
1883         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
1884         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
1885         u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
1886
1887         if (!pp_virt_addr_tbl)
1888                 return;
1889
1890         if (!p_chain->pbl.p_virt_table)
1891                 goto out;
1892
1893         for (i = 0; i < page_cnt; i++) {
1894                 if (!pp_virt_addr_tbl[i])
1895                         break;
1896
1897                 dma_free_coherent(&cdev->pdev->dev,
1898                                   QED_CHAIN_PAGE_SIZE,
1899                                   pp_virt_addr_tbl[i],
1900                                   *(dma_addr_t *)p_pbl_virt);
1901
1902                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
1903         }
1904
1905         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1906         dma_free_coherent(&cdev->pdev->dev,
1907                           pbl_size,
1908                           p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
1909 out:
1910         vfree(p_chain->pbl.pp_virt_addr_tbl);
1911 }
1912
1913 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
1914 {
1915         switch (p_chain->mode) {
1916         case QED_CHAIN_MODE_NEXT_PTR:
1917                 qed_chain_free_next_ptr(cdev, p_chain);
1918                 break;
1919         case QED_CHAIN_MODE_SINGLE:
1920                 qed_chain_free_single(cdev, p_chain);
1921                 break;
1922         case QED_CHAIN_MODE_PBL:
1923                 qed_chain_free_pbl(cdev, p_chain);
1924                 break;
1925         }
1926 }
1927
1928 static int
1929 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
1930                              enum qed_chain_cnt_type cnt_type,
1931                              size_t elem_size, u32 page_cnt)
1932 {
1933         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
1934
1935         /* The actual chain size can be larger than the maximal possible value
1936          * after rounding up the requested elements number to pages, and after
1937          * taking into acount the unusuable elements (next-ptr elements).
1938          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
1939          * size/capacity fields are of a u32 type.
1940          */
1941         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
1942              chain_size > 0x10000) ||
1943             (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
1944              chain_size > 0x100000000ULL)) {
1945                 DP_NOTICE(cdev,
1946                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
1947                           chain_size);
1948                 return -EINVAL;
1949         }
1950
1951         return 0;
1952 }
1953
1954 static int
1955 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
1956 {
1957         void *p_virt = NULL, *p_virt_prev = NULL;
1958         dma_addr_t p_phys = 0;
1959         u32 i;
1960
1961         for (i = 0; i < p_chain->page_cnt; i++) {
1962                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1963                                             QED_CHAIN_PAGE_SIZE,
1964                                             &p_phys, GFP_KERNEL);
1965                 if (!p_virt)
1966                         return -ENOMEM;
1967
1968                 if (i == 0) {
1969                         qed_chain_init_mem(p_chain, p_virt, p_phys);
1970                         qed_chain_reset(p_chain);
1971                 } else {
1972                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
1973                                                      p_virt, p_phys);
1974                 }
1975
1976                 p_virt_prev = p_virt;
1977         }
1978         /* Last page's next element should point to the beginning of the
1979          * chain.
1980          */
1981         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
1982                                      p_chain->p_virt_addr,
1983                                      p_chain->p_phys_addr);
1984
1985         return 0;
1986 }
1987
1988 static int
1989 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
1990 {
1991         dma_addr_t p_phys = 0;
1992         void *p_virt = NULL;
1993
1994         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1995                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
1996         if (!p_virt)
1997                 return -ENOMEM;
1998
1999         qed_chain_init_mem(p_chain, p_virt, p_phys);
2000         qed_chain_reset(p_chain);
2001
2002         return 0;
2003 }
2004
2005 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2006 {
2007         u32 page_cnt = p_chain->page_cnt, size, i;
2008         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2009         void **pp_virt_addr_tbl = NULL;
2010         u8 *p_pbl_virt = NULL;
2011         void *p_virt = NULL;
2012
2013         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2014         pp_virt_addr_tbl = vzalloc(size);
2015         if (!pp_virt_addr_tbl)
2016                 return -ENOMEM;
2017
2018         /* The allocation of the PBL table is done with its full size, since it
2019          * is expected to be successive.
2020          * qed_chain_init_pbl_mem() is called even in a case of an allocation
2021          * failure, since pp_virt_addr_tbl was previously allocated, and it
2022          * should be saved to allow its freeing during the error flow.
2023          */
2024         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2025         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2026                                         size, &p_pbl_phys, GFP_KERNEL);
2027         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2028                                pp_virt_addr_tbl);
2029         if (!p_pbl_virt)
2030                 return -ENOMEM;
2031
2032         for (i = 0; i < page_cnt; i++) {
2033                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2034                                             QED_CHAIN_PAGE_SIZE,
2035                                             &p_phys, GFP_KERNEL);
2036                 if (!p_virt)
2037                         return -ENOMEM;
2038
2039                 if (i == 0) {
2040                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2041                         qed_chain_reset(p_chain);
2042                 }
2043
2044                 /* Fill the PBL table with the physical address of the page */
2045                 *(dma_addr_t *)p_pbl_virt = p_phys;
2046                 /* Keep the virtual address of the page */
2047                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2048
2049                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2050         }
2051
2052         return 0;
2053 }
2054
2055 int qed_chain_alloc(struct qed_dev *cdev,
2056                     enum qed_chain_use_mode intended_use,
2057                     enum qed_chain_mode mode,
2058                     enum qed_chain_cnt_type cnt_type,
2059                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
2060 {
2061         u32 page_cnt;
2062         int rc = 0;
2063
2064         if (mode == QED_CHAIN_MODE_SINGLE)
2065                 page_cnt = 1;
2066         else
2067                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2068
2069         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2070         if (rc) {
2071                 DP_NOTICE(cdev,
2072                           "Cannot allocate a chain with the given arguments:\n");
2073                 DP_NOTICE(cdev,
2074                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2075                           intended_use, mode, cnt_type, num_elems, elem_size);
2076                 return rc;
2077         }
2078
2079         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2080                               mode, cnt_type);
2081
2082         switch (mode) {
2083         case QED_CHAIN_MODE_NEXT_PTR:
2084                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2085                 break;
2086         case QED_CHAIN_MODE_SINGLE:
2087                 rc = qed_chain_alloc_single(cdev, p_chain);
2088                 break;
2089         case QED_CHAIN_MODE_PBL:
2090                 rc = qed_chain_alloc_pbl(cdev, p_chain);
2091                 break;
2092         }
2093         if (rc)
2094                 goto nomem;
2095
2096         return 0;
2097
2098 nomem:
2099         qed_chain_free(cdev, p_chain);
2100         return rc;
2101 }
2102
2103 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
2104 {
2105         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2106                 u16 min, max;
2107
2108                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
2109                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2110                 DP_NOTICE(p_hwfn,
2111                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2112                           src_id, min, max);
2113
2114                 return -EINVAL;
2115         }
2116
2117         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2118
2119         return 0;
2120 }
2121
2122 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2123 {
2124         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2125                 u8 min, max;
2126
2127                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2128                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2129                 DP_NOTICE(p_hwfn,
2130                           "vport id [%d] is not valid, available indices [%d - %d]\n",
2131                           src_id, min, max);
2132
2133                 return -EINVAL;
2134         }
2135
2136         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2137
2138         return 0;
2139 }
2140
2141 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2142 {
2143         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2144                 u8 min, max;
2145
2146                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2147                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2148                 DP_NOTICE(p_hwfn,
2149                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2150                           src_id, min, max);
2151
2152                 return -EINVAL;
2153         }
2154
2155         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2156
2157         return 0;
2158 }
2159
2160 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
2161                                   u8 *p_filter)
2162 {
2163         *p_high = p_filter[1] | (p_filter[0] << 8);
2164         *p_low = p_filter[5] | (p_filter[4] << 8) |
2165                  (p_filter[3] << 16) | (p_filter[2] << 24);
2166 }
2167
2168 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
2169                            struct qed_ptt *p_ptt, u8 *p_filter)
2170 {
2171         u32 high = 0, low = 0, en;
2172         int i;
2173
2174         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2175                 return 0;
2176
2177         qed_llh_mac_to_filter(&high, &low, p_filter);
2178
2179         /* Find a free entry and utilize it */
2180         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2181                 en = qed_rd(p_hwfn, p_ptt,
2182                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2183                 if (en)
2184                         continue;
2185                 qed_wr(p_hwfn, p_ptt,
2186                        NIG_REG_LLH_FUNC_FILTER_VALUE +
2187                        2 * i * sizeof(u32), low);
2188                 qed_wr(p_hwfn, p_ptt,
2189                        NIG_REG_LLH_FUNC_FILTER_VALUE +
2190                        (2 * i + 1) * sizeof(u32), high);
2191                 qed_wr(p_hwfn, p_ptt,
2192                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2193                 qed_wr(p_hwfn, p_ptt,
2194                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2195                        i * sizeof(u32), 0);
2196                 qed_wr(p_hwfn, p_ptt,
2197                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2198                 break;
2199         }
2200         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2201                 DP_NOTICE(p_hwfn,
2202                           "Failed to find an empty LLH filter to utilize\n");
2203                 return -EINVAL;
2204         }
2205
2206         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2207                    "mac: %pM is added at %d\n",
2208                    p_filter, i);
2209
2210         return 0;
2211 }
2212
2213 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
2214                                struct qed_ptt *p_ptt, u8 *p_filter)
2215 {
2216         u32 high = 0, low = 0;
2217         int i;
2218
2219         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2220                 return;
2221
2222         qed_llh_mac_to_filter(&high, &low, p_filter);
2223
2224         /* Find the entry and clean it */
2225         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2226                 if (qed_rd(p_hwfn, p_ptt,
2227                            NIG_REG_LLH_FUNC_FILTER_VALUE +
2228                            2 * i * sizeof(u32)) != low)
2229                         continue;
2230                 if (qed_rd(p_hwfn, p_ptt,
2231                            NIG_REG_LLH_FUNC_FILTER_VALUE +
2232                            (2 * i + 1) * sizeof(u32)) != high)
2233                         continue;
2234
2235                 qed_wr(p_hwfn, p_ptt,
2236                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2237                 qed_wr(p_hwfn, p_ptt,
2238                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2239                 qed_wr(p_hwfn, p_ptt,
2240                        NIG_REG_LLH_FUNC_FILTER_VALUE +
2241                        (2 * i + 1) * sizeof(u32), 0);
2242
2243                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2244                            "mac: %pM is removed from %d\n",
2245                            p_filter, i);
2246                 break;
2247         }
2248         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2249                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2250 }
2251
2252 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2253                             u32 hw_addr, void *p_eth_qzone,
2254                             size_t eth_qzone_size, u8 timeset)
2255 {
2256         struct coalescing_timeset *p_coal_timeset;
2257
2258         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2259                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2260                 return -EINVAL;
2261         }
2262
2263         p_coal_timeset = p_eth_qzone;
2264         memset(p_coal_timeset, 0, eth_qzone_size);
2265         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2266         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2267         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2268
2269         return 0;
2270 }
2271
2272 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2273                          u16 coalesce, u8 qid, u16 sb_id)
2274 {
2275         struct ustorm_eth_queue_zone eth_qzone;
2276         u8 timeset, timer_res;
2277         u16 fw_qid = 0;
2278         u32 address;
2279         int rc;
2280
2281         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2282         if (coalesce <= 0x7F) {
2283                 timer_res = 0;
2284         } else if (coalesce <= 0xFF) {
2285                 timer_res = 1;
2286         } else if (coalesce <= 0x1FF) {
2287                 timer_res = 2;
2288         } else {
2289                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2290                 return -EINVAL;
2291         }
2292         timeset = (u8)(coalesce >> timer_res);
2293
2294         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2295         if (rc)
2296                 return rc;
2297
2298         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
2299         if (rc)
2300                 goto out;
2301
2302         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2303
2304         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2305                               sizeof(struct ustorm_eth_queue_zone), timeset);
2306         if (rc)
2307                 goto out;
2308
2309         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
2310 out:
2311         return rc;
2312 }
2313
2314 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2315                          u16 coalesce, u8 qid, u16 sb_id)
2316 {
2317         struct xstorm_eth_queue_zone eth_qzone;
2318         u8 timeset, timer_res;
2319         u16 fw_qid = 0;
2320         u32 address;
2321         int rc;
2322
2323         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2324         if (coalesce <= 0x7F) {
2325                 timer_res = 0;
2326         } else if (coalesce <= 0xFF) {
2327                 timer_res = 1;
2328         } else if (coalesce <= 0x1FF) {
2329                 timer_res = 2;
2330         } else {
2331                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2332                 return -EINVAL;
2333         }
2334         timeset = (u8)(coalesce >> timer_res);
2335
2336         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2337         if (rc)
2338                 return rc;
2339
2340         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
2341         if (rc)
2342                 goto out;
2343
2344         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2345
2346         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2347                               sizeof(struct xstorm_eth_queue_zone), timeset);
2348         if (rc)
2349                 goto out;
2350
2351         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
2352 out:
2353         return rc;
2354 }
2355
2356 /* Calculate final WFQ values for all vports and configure them.
2357  * After this configuration each vport will have
2358  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2359  */
2360 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2361                                              struct qed_ptt *p_ptt,
2362                                              u32 min_pf_rate)
2363 {
2364         struct init_qm_vport_params *vport_params;
2365         int i;
2366
2367         vport_params = p_hwfn->qm_info.qm_vport_params;
2368
2369         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2370                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2371
2372                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
2373                                                 min_pf_rate;
2374                 qed_init_vport_wfq(p_hwfn, p_ptt,
2375                                    vport_params[i].first_tx_pq_id,
2376                                    vport_params[i].vport_wfq);
2377         }
2378 }
2379
2380 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
2381                                        u32 min_pf_rate)
2382
2383 {
2384         int i;
2385
2386         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
2387                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
2388 }
2389
2390 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2391                                            struct qed_ptt *p_ptt,
2392                                            u32 min_pf_rate)
2393 {
2394         struct init_qm_vport_params *vport_params;
2395         int i;
2396
2397         vport_params = p_hwfn->qm_info.qm_vport_params;
2398
2399         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2400                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
2401                 qed_init_vport_wfq(p_hwfn, p_ptt,
2402                                    vport_params[i].first_tx_pq_id,
2403                                    vport_params[i].vport_wfq);
2404         }
2405 }
2406
2407 /* This function performs several validations for WFQ
2408  * configuration and required min rate for a given vport
2409  * 1. req_rate must be greater than one percent of min_pf_rate.
2410  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2411  *    rates to get less than one percent of min_pf_rate.
2412  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2413  */
2414 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
2415                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
2416 {
2417         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
2418         int non_requested_count = 0, req_count = 0, i, num_vports;
2419
2420         num_vports = p_hwfn->qm_info.num_vports;
2421
2422         /* Accounting for the vports which are configured for WFQ explicitly */
2423         for (i = 0; i < num_vports; i++) {
2424                 u32 tmp_speed;
2425
2426                 if ((i != vport_id) &&
2427                     p_hwfn->qm_info.wfq_data[i].configured) {
2428                         req_count++;
2429                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2430                         total_req_min_rate += tmp_speed;
2431                 }
2432         }
2433
2434         /* Include current vport data as well */
2435         req_count++;
2436         total_req_min_rate += req_rate;
2437         non_requested_count = num_vports - req_count;
2438
2439         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2440                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2441                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2442                            vport_id, req_rate, min_pf_rate);
2443                 return -EINVAL;
2444         }
2445
2446         if (num_vports > QED_WFQ_UNIT) {
2447                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2448                            "Number of vports is greater than %d\n",
2449                            QED_WFQ_UNIT);
2450                 return -EINVAL;
2451         }
2452
2453         if (total_req_min_rate > min_pf_rate) {
2454                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2455                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2456                            total_req_min_rate, min_pf_rate);
2457                 return -EINVAL;
2458         }
2459
2460         total_left_rate = min_pf_rate - total_req_min_rate;
2461
2462         left_rate_per_vp = total_left_rate / non_requested_count;
2463         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
2464                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2465                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2466                            left_rate_per_vp, min_pf_rate);
2467                 return -EINVAL;
2468         }
2469
2470         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2471         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2472
2473         for (i = 0; i < num_vports; i++) {
2474                 if (p_hwfn->qm_info.wfq_data[i].configured)
2475                         continue;
2476
2477                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2478         }
2479
2480         return 0;
2481 }
2482
2483 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2484                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2485 {
2486         struct qed_mcp_link_state *p_link;
2487         int rc = 0;
2488
2489         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2490
2491         if (!p_link->min_pf_rate) {
2492                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2493                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2494                 return rc;
2495         }
2496
2497         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2498
2499         if (!rc)
2500                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2501                                                  p_link->min_pf_rate);
2502         else
2503                 DP_NOTICE(p_hwfn,
2504                           "Validation failed while configuring min rate\n");
2505
2506         return rc;
2507 }
2508
2509 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2510                                                  struct qed_ptt *p_ptt,
2511                                                  u32 min_pf_rate)
2512 {
2513         bool use_wfq = false;
2514         int rc = 0;
2515         u16 i;
2516
2517         /* Validate all pre configured vports for wfq */
2518         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2519                 u32 rate;
2520
2521                 if (!p_hwfn->qm_info.wfq_data[i].configured)
2522                         continue;
2523
2524                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2525                 use_wfq = true;
2526
2527                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2528                 if (rc) {
2529                         DP_NOTICE(p_hwfn,
2530                                   "WFQ validation failed while configuring min rate\n");
2531                         break;
2532                 }
2533         }
2534
2535         if (!rc && use_wfq)
2536                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2537         else
2538                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2539
2540         return rc;
2541 }
2542
2543 /* Main API for qed clients to configure vport min rate.
2544  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2545  * rate - Speed in Mbps needs to be assigned to a given vport.
2546  */
2547 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2548 {
2549         int i, rc = -EINVAL;
2550
2551         /* Currently not supported; Might change in future */
2552         if (cdev->num_hwfns > 1) {
2553                 DP_NOTICE(cdev,
2554                           "WFQ configuration is not supported for this device\n");
2555                 return rc;
2556         }
2557
2558         for_each_hwfn(cdev, i) {
2559                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2560                 struct qed_ptt *p_ptt;
2561
2562                 p_ptt = qed_ptt_acquire(p_hwfn);
2563                 if (!p_ptt)
2564                         return -EBUSY;
2565
2566                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2567
2568                 if (rc) {
2569                         qed_ptt_release(p_hwfn, p_ptt);
2570                         return rc;
2571                 }
2572
2573                 qed_ptt_release(p_hwfn, p_ptt);
2574         }
2575
2576         return rc;
2577 }
2578
2579 /* API to configure WFQ from mcp link change */
2580 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
2581 {
2582         int i;
2583
2584         if (cdev->num_hwfns > 1) {
2585                 DP_VERBOSE(cdev,
2586                            NETIF_MSG_LINK,
2587                            "WFQ configuration is not supported for this device\n");
2588                 return;
2589         }
2590
2591         for_each_hwfn(cdev, i) {
2592                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2593
2594                 __qed_configure_vp_wfq_on_link_change(p_hwfn,
2595                                                       p_hwfn->p_dpc_ptt,
2596                                                       min_pf_rate);
2597         }
2598 }
2599
2600 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2601                                      struct qed_ptt *p_ptt,
2602                                      struct qed_mcp_link_state *p_link,
2603                                      u8 max_bw)
2604 {
2605         int rc = 0;
2606
2607         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2608
2609         if (!p_link->line_speed && (max_bw != 100))
2610                 return rc;
2611
2612         p_link->speed = (p_link->line_speed * max_bw) / 100;
2613         p_hwfn->qm_info.pf_rl = p_link->speed;
2614
2615         /* Since the limiter also affects Tx-switched traffic, we don't want it
2616          * to limit such traffic in case there's no actual limit.
2617          * In that case, set limit to imaginary high boundary.
2618          */
2619         if (max_bw == 100)
2620                 p_hwfn->qm_info.pf_rl = 100000;
2621
2622         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2623                             p_hwfn->qm_info.pf_rl);
2624
2625         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2626                    "Configured MAX bandwidth to be %08x Mb/sec\n",
2627                    p_link->speed);
2628
2629         return rc;
2630 }
2631
2632 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2633 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2634 {
2635         int i, rc = -EINVAL;
2636
2637         if (max_bw < 1 || max_bw > 100) {
2638                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2639                 return rc;
2640         }
2641
2642         for_each_hwfn(cdev, i) {
2643                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2644                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2645                 struct qed_mcp_link_state *p_link;
2646                 struct qed_ptt *p_ptt;
2647
2648                 p_link = &p_lead->mcp_info->link_output;
2649
2650                 p_ptt = qed_ptt_acquire(p_hwfn);
2651                 if (!p_ptt)
2652                         return -EBUSY;
2653
2654                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2655                                                       p_link, max_bw);
2656
2657                 qed_ptt_release(p_hwfn, p_ptt);
2658
2659                 if (rc)
2660                         break;
2661         }
2662
2663         return rc;
2664 }
2665
2666 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2667                                      struct qed_ptt *p_ptt,
2668                                      struct qed_mcp_link_state *p_link,
2669                                      u8 min_bw)
2670 {
2671         int rc = 0;
2672
2673         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2674         p_hwfn->qm_info.pf_wfq = min_bw;
2675
2676         if (!p_link->line_speed)
2677                 return rc;
2678
2679         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2680
2681         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2682
2683         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2684                    "Configured MIN bandwidth to be %d Mb/sec\n",
2685                    p_link->min_pf_rate);
2686
2687         return rc;
2688 }
2689
2690 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2691 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2692 {
2693         int i, rc = -EINVAL;
2694
2695         if (min_bw < 1 || min_bw > 100) {
2696                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2697                 return rc;
2698         }
2699
2700         for_each_hwfn(cdev, i) {
2701                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2702                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2703                 struct qed_mcp_link_state *p_link;
2704                 struct qed_ptt *p_ptt;
2705
2706                 p_link = &p_lead->mcp_info->link_output;
2707
2708                 p_ptt = qed_ptt_acquire(p_hwfn);
2709                 if (!p_ptt)
2710                         return -EBUSY;
2711
2712                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2713                                                       p_link, min_bw);
2714                 if (rc) {
2715                         qed_ptt_release(p_hwfn, p_ptt);
2716                         return rc;
2717                 }
2718
2719                 if (p_link->min_pf_rate) {
2720                         u32 min_rate = p_link->min_pf_rate;
2721
2722                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2723                                                                    p_ptt,
2724                                                                    min_rate);
2725                 }
2726
2727                 qed_ptt_release(p_hwfn, p_ptt);
2728         }
2729
2730         return rc;
2731 }
2732
2733 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2734 {
2735         struct qed_mcp_link_state *p_link;
2736
2737         p_link = &p_hwfn->mcp_info->link_output;
2738
2739         if (p_link->min_pf_rate)
2740                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2741                                                p_link->min_pf_rate);
2742
2743         memset(p_hwfn->qm_info.wfq_data, 0,
2744                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
2745 }