drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_roce.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 /* API common to all protocols */
  73 enum BAR_ID {
  74         BAR_ID_0,       /* used for GRC */
  75         BAR_ID_1        /* Used for doorbells */
  76 };
  77
  78 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  79                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  80 {
  81         u32 bar_reg = (bar_id == BAR_ID_0 ?
  82                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  83         u32 val;
  84
  85         if (IS_VF(p_hwfn->cdev))
  86                 return 1 << 17;
  87
  88         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  89         if (val)
  90                 return 1 << (val + 15);
  91
  92         /* Old MFW initialized above registered only conditionally */
  93         if (p_hwfn->cdev->num_hwfns > 1) {
  94                 DP_INFO(p_hwfn,
  95                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  96                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  97         } else {
  98                 DP_INFO(p_hwfn,
  99                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 100                         return 512 * 1024;
 101         }
 102 }
 103
 104 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
 105 {
 106         u32 i;
 107
 108         cdev->dp_level = dp_level;
 109         cdev->dp_module = dp_module;
 110         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 111                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 112
 113                 p_hwfn->dp_level = dp_level;
 114                 p_hwfn->dp_module = dp_module;
 115         }
 116 }
 117
 118 void qed_init_struct(struct qed_dev *cdev)
 119 {
 120         u8 i;
 121
 122         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 123                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 124
 125                 p_hwfn->cdev = cdev;
 126                 p_hwfn->my_id = i;
 127                 p_hwfn->b_active = false;
 128
 129                 mutex_init(&p_hwfn->dmae_info.mutex);
 130         }
 131
 132         /* hwfn 0 is always active */
 133         cdev->hwfns[0].b_active = true;
 134
 135         /* set the default cache alignment to 128 */
 136         cdev->cache_shift = 7;
 137 }
 138
 139 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 140 {
 141         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 142
 143         kfree(qm_info->qm_pq_params);
 144         qm_info->qm_pq_params = NULL;
 145         kfree(qm_info->qm_vport_params);
 146         qm_info->qm_vport_params = NULL;
 147         kfree(qm_info->qm_port_params);
 148         qm_info->qm_port_params = NULL;
 149         kfree(qm_info->wfq_data);
 150         qm_info->wfq_data = NULL;
 151 }
 152
 153 void qed_resc_free(struct qed_dev *cdev)
 154 {
 155         int i;
 156
 157         if (IS_VF(cdev))
 158                 return;
 159
 160         kfree(cdev->fw_data);
 161         cdev->fw_data = NULL;
 162
 163         kfree(cdev->reset_stats);
 164
 165         for_each_hwfn(cdev, i) {
 166                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 167
 168                 qed_cxt_mngr_free(p_hwfn);
 169                 qed_qm_info_free(p_hwfn);
 170                 qed_spq_free(p_hwfn);
 171                 qed_eq_free(p_hwfn, p_hwfn->p_eq);
 172                 qed_consq_free(p_hwfn, p_hwfn->p_consq);
 173                 qed_int_free(p_hwfn);
 174 #ifdef CONFIG_QED_LL2
 175                 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 176 #endif
 177                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 178                         qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info);
 179
 180                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 181                         qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
 182                         qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
 183                 }
 184                 qed_iov_free(p_hwfn);
 185                 qed_dmae_info_free(p_hwfn);
 186                 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 187         }
 188 }
 189
 190 /******************** QM initialization *******************/
 191 #define ACTIVE_TCS_BMAP 0x9f
 192 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 193
 194 /* determines the physical queue flags for a given PF. */
 195 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 196 {
 197         u32 flags;
 198
 199         /* common flags */
 200         flags = PQ_FLAGS_LB;
 201
 202         /* feature flags */
 203         if (IS_QED_SRIOV(p_hwfn->cdev))
 204                 flags |= PQ_FLAGS_VFS;
 205
 206         /* protocol flags */
 207         switch (p_hwfn->hw_info.personality) {
 208         case QED_PCI_ETH:
 209                 flags |= PQ_FLAGS_MCOS;
 210                 break;
 211         case QED_PCI_FCOE:
 212                 flags |= PQ_FLAGS_OFLD;
 213                 break;
 214         case QED_PCI_ISCSI:
 215                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 216                 break;
 217         case QED_PCI_ETH_ROCE:
 218                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 219                 break;
 220         default:
 221                 DP_ERR(p_hwfn,
 222                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 223                 return 0;
 224         }
 225
 226         return flags;
 227 }
 228
 229 /* Getters for resource amounts necessary for qm initialization */
 230 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 231 {
 232         return p_hwfn->hw_info.num_hw_tc;
 233 }
 234
 235 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 236 {
 237         return IS_QED_SRIOV(p_hwfn->cdev) ?
 238                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 239 }
 240
 241 #define NUM_DEFAULT_RLS 1
 242
 243 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 244 {
 245         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 246
 247         /* num RLs can't exceed resource amount of rls or vports */
 248         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 249                                  RESC_NUM(p_hwfn, QED_VPORT));
 250
 251         /* Make sure after we reserve there's something left */
 252         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 253                 return 0;
 254
 255         /* subtract rls necessary for VFs and one default one for the PF */
 256         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 257
 258         return num_pf_rls;
 259 }
 260
 261 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 262 {
 263         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 264
 265         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 266         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 267                qed_init_qm_get_num_pf_rls(p_hwfn) +
 268                (!!(PQ_FLAGS_VFS & pq_flags)) *
 269                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 270 }
 271
 272 /* calc amount of PQs according to the requested flags */
 273 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 274 {
 275         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 276
 277         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 278                qed_init_qm_get_num_pf_rls(p_hwfn) +
 279                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 280                qed_init_qm_get_num_tcs(p_hwfn) +
 281                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 282                (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
 283                (!!(PQ_FLAGS_LLT & pq_flags)) +
 284                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 285 }
 286
 287 /* initialize the top level QM params */
 288 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 289 {
 290         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 291         bool four_port;
 292
 293         /* pq and vport bases for this PF */
 294         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 295         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 296
 297         /* rate limiting and weighted fair queueing are always enabled */
 298         qm_info->vport_rl_en = 1;
 299         qm_info->vport_wfq_en = 1;
 300
 301         /* TC config is different for AH 4 port */
 302         four_port = p_hwfn->cdev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 303
 304         /* in AH 4 port we have fewer TCs per port */
 305         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 306                                                      NUM_OF_PHYS_TCS;
 307
 308         /* unless MFW indicated otherwise, ooo_tc == 3 for
 309          * AH 4-port and 4 otherwise.
 310          */
 311         if (!qm_info->ooo_tc)
 312                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 313                                               DCBX_TCP_OOO_TC;
 314 }
 315
 316 /* initialize qm vport params */
 317 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 318 {
 319         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 320         u8 i;
 321
 322         /* all vports participate in weighted fair queueing */
 323         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 324                 qm_info->qm_vport_params[i].vport_wfq = 1;
 325 }
 326
 327 /* initialize qm port params */
 328 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 329 {
 330         /* Initialize qm port parameters */
 331         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engines;
 332
 333         /* indicate how ooo and high pri traffic is dealt with */
 334         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 335                           ACTIVE_TCS_BMAP_4PORT_K2 :
 336                           ACTIVE_TCS_BMAP;
 337
 338         for (i = 0; i < num_ports; i++) {
 339                 struct init_qm_port_params *p_qm_port =
 340                     &p_hwfn->qm_info.qm_port_params[i];
 341
 342                 p_qm_port->active = 1;
 343                 p_qm_port->active_phys_tcs = active_phys_tcs;
 344                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 345                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 346         }
 347 }
 348
 349 /* Reset the params which must be reset for qm init. QM init may be called as
 350  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 351  * params may be affected by the init but would simply recalculate to the same
 352  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 353  * affected as these amounts stay the same.
 354  */
 355 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 356 {
 357         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 358
 359         qm_info->num_pqs = 0;
 360         qm_info->num_vports = 0;
 361         qm_info->num_pf_rls = 0;
 362         qm_info->num_vf_pqs = 0;
 363         qm_info->first_vf_pq = 0;
 364         qm_info->first_mcos_pq = 0;
 365         qm_info->first_rl_pq = 0;
 366 }
 367
 368 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 369 {
 370         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 371
 372         qm_info->num_vports++;
 373
 374         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 375                 DP_ERR(p_hwfn,
 376                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 377                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 378 }
 379
 380 /* initialize a single pq and manage qm_info resources accounting.
 381  * The pq_init_flags param determines whether the PQ is rate limited
 382  * (for VF or PF) and whether a new vport is allocated to the pq or not
 383  * (i.e. vport will be shared).
 384  */
 385
 386 /* flags for pq init */
 387 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 388 #define PQ_INIT_PF_RL           (1 << 1)
 389 #define PQ_INIT_VF_RL           (1 << 2)
 390
 391 /* defines for pq init */
 392 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 393 #define PQ_INIT_DEFAULT_TC              0
 394 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 395
 396 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 397                            struct qed_qm_info *qm_info,
 398                            u8 tc, u32 pq_init_flags)
 399 {
 400         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 401
 402         if (pq_idx > max_pq)
 403                 DP_ERR(p_hwfn,
 404                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 405
 406         /* init pq params */
 407         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 408             qm_info->num_vports;
 409         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 410         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 411         qm_info->qm_pq_params[pq_idx].rl_valid =
 412             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 413
 414         /* qm params accounting */
 415         qm_info->num_pqs++;
 416         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 417                 qm_info->num_vports++;
 418
 419         if (pq_init_flags & PQ_INIT_PF_RL)
 420                 qm_info->num_pf_rls++;
 421
 422         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 423                 DP_ERR(p_hwfn,
 424                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 425                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 426
 427         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 428                 DP_ERR(p_hwfn,
 429                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 430                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 431 }
 432
 433 /* get pq index according to PQ_FLAGS */
 434 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 435                                            u32 pq_flags)
 436 {
 437         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 438
 439         /* Can't have multiple flags set here */
 440         if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
 441                 goto err;
 442
 443         switch (pq_flags) {
 444         case PQ_FLAGS_RLS:
 445                 return &qm_info->first_rl_pq;
 446         case PQ_FLAGS_MCOS:
 447                 return &qm_info->first_mcos_pq;
 448         case PQ_FLAGS_LB:
 449                 return &qm_info->pure_lb_pq;
 450         case PQ_FLAGS_OOO:
 451                 return &qm_info->ooo_pq;
 452         case PQ_FLAGS_ACK:
 453                 return &qm_info->pure_ack_pq;
 454         case PQ_FLAGS_OFLD:
 455                 return &qm_info->offload_pq;
 456         case PQ_FLAGS_LLT:
 457                 return &qm_info->low_latency_pq;
 458         case PQ_FLAGS_VFS:
 459                 return &qm_info->first_vf_pq;
 460         default:
 461                 goto err;
 462         }
 463
 464 err:
 465         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 466         return NULL;
 467 }
 468
 469 /* save pq index in qm info */
 470 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 471                                 u32 pq_flags, u16 pq_val)
 472 {
 473         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 474
 475         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 476 }
 477
 478 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 479 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 480 {
 481         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 482
 483         return *base_pq_idx + CM_TX_PQ_BASE;
 484 }
 485
 486 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 487 {
 488         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 489
 490         if (tc > max_tc)
 491                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 492
 493         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 494 }
 495
 496 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 497 {
 498         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 499
 500         if (vf > max_vf)
 501                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 502
 503         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 504 }
 505
 506 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
 507 {
 508         u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
 509
 510         if (rl > max_rl)
 511                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 512
 513         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 514 }
 515
 516 /* Functions for creating specific types of pqs */
 517 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 518 {
 519         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 520
 521         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 522                 return;
 523
 524         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 525         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 526 }
 527
 528 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 529 {
 530         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 531
 532         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 533                 return;
 534
 535         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 536         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 537 }
 538
 539 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 540 {
 541         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 542
 543         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 544                 return;
 545
 546         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 547         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 548 }
 549
 550 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 551 {
 552         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 553
 554         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 555                 return;
 556
 557         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 558         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 559 }
 560
 561 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 562 {
 563         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 564
 565         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 566                 return;
 567
 568         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 569         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 570 }
 571
 572 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 573 {
 574         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 575         u8 tc_idx;
 576
 577         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 578                 return;
 579
 580         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 581         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 582                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 583 }
 584
 585 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 586 {
 587         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 588         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 589
 590         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 591                 return;
 592
 593         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 594         qm_info->num_vf_pqs = num_vfs;
 595         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 596                 qed_init_qm_pq(p_hwfn,
 597                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 598 }
 599
 600 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 601 {
 602         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 603         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 604
 605         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 606                 return;
 607
 608         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 609         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 610                 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
 611 }
 612
 613 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 614 {
 615         /* rate limited pqs, must come first (FW assumption) */
 616         qed_init_qm_rl_pqs(p_hwfn);
 617
 618         /* pqs for multi cos */
 619         qed_init_qm_mcos_pqs(p_hwfn);
 620
 621         /* pure loopback pq */
 622         qed_init_qm_lb_pq(p_hwfn);
 623
 624         /* out of order pq */
 625         qed_init_qm_ooo_pq(p_hwfn);
 626
 627         /* pure ack pq */
 628         qed_init_qm_pure_ack_pq(p_hwfn);
 629
 630         /* pq for offloaded protocol */
 631         qed_init_qm_offload_pq(p_hwfn);
 632
 633         /* low latency pq */
 634         qed_init_qm_low_latency_pq(p_hwfn);
 635
 636         /* done sharing vports */
 637         qed_init_qm_advance_vport(p_hwfn);
 638
 639         /* pqs for vfs */
 640         qed_init_qm_vf_pqs(p_hwfn);
 641 }
 642
 643 /* compare values of getters against resources amounts */
 644 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 645 {
 646         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 647                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 648                 return -EINVAL;
 649         }
 650
 651         if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
 652                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 653                 return -EINVAL;
 654         }
 655
 656         return 0;
 657 }
 658
 659 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 660 {
 661         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 662         struct init_qm_vport_params *vport;
 663         struct init_qm_port_params *port;
 664         struct init_qm_pq_params *pq;
 665         int i, tc;
 666
 667         /* top level params */
 668         DP_VERBOSE(p_hwfn,
 669                    NETIF_MSG_HW,
 670                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 671                    qm_info->start_pq,
 672                    qm_info->start_vport,
 673                    qm_info->pure_lb_pq,
 674                    qm_info->offload_pq, qm_info->pure_ack_pq);
 675         DP_VERBOSE(p_hwfn,
 676                    NETIF_MSG_HW,
 677                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 678                    qm_info->ooo_pq,
 679                    qm_info->first_vf_pq,
 680                    qm_info->num_pqs,
 681                    qm_info->num_vf_pqs,
 682                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 683         DP_VERBOSE(p_hwfn,
 684                    NETIF_MSG_HW,
 685                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 686                    qm_info->pf_rl_en,
 687                    qm_info->pf_wfq_en,
 688                    qm_info->vport_rl_en,
 689                    qm_info->vport_wfq_en,
 690                    qm_info->pf_wfq,
 691                    qm_info->pf_rl,
 692                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 693
 694         /* port table */
 695         for (i = 0; i < p_hwfn->cdev->num_ports_in_engines; i++) {
 696                 port = &(qm_info->qm_port_params[i]);
 697                 DP_VERBOSE(p_hwfn,
 698                            NETIF_MSG_HW,
 699                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 700                            i,
 701                            port->active,
 702                            port->active_phys_tcs,
 703                            port->num_pbf_cmd_lines,
 704                            port->num_btb_blocks, port->reserved);
 705         }
 706
 707         /* vport table */
 708         for (i = 0; i < qm_info->num_vports; i++) {
 709                 vport = &(qm_info->qm_vport_params[i]);
 710                 DP_VERBOSE(p_hwfn,
 711                            NETIF_MSG_HW,
 712                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 713                            qm_info->start_vport + i,
 714                            vport->vport_rl, vport->vport_wfq);
 715                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 716                         DP_VERBOSE(p_hwfn,
 717                                    NETIF_MSG_HW,
 718                                    "%d ", vport->first_tx_pq_id[tc]);
 719                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 720         }
 721
 722         /* pq table */
 723         for (i = 0; i < qm_info->num_pqs; i++) {
 724                 pq = &(qm_info->qm_pq_params[i]);
 725                 DP_VERBOSE(p_hwfn,
 726                            NETIF_MSG_HW,
 727                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 728                            qm_info->start_pq + i,
 729                            pq->vport_id,
 730                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 731         }
 732 }
 733
 734 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 735 {
 736         /* reset params required for init run */
 737         qed_init_qm_reset_params(p_hwfn);
 738
 739         /* init QM top level params */
 740         qed_init_qm_params(p_hwfn);
 741
 742         /* init QM port params */
 743         qed_init_qm_port_params(p_hwfn);
 744
 745         /* init QM vport params */
 746         qed_init_qm_vport_params(p_hwfn);
 747
 748         /* init QM physical queue params */
 749         qed_init_qm_pq_params(p_hwfn);
 750
 751         /* display all that init */
 752         qed_dp_init_qm_params(p_hwfn);
 753 }
 754
 755 /* This function reconfigures the QM pf on the fly.
 756  * For this purpose we:
 757  * 1. reconfigure the QM database
 758  * 2. set new values to runtime arrat
 759  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 760  * 4. activate init tool in QM_PF stage
 761  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 762  */
 763 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 764 {
 765         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 766         bool b_rc;
 767         int rc;
 768
 769         /* initialize qed's qm data structure */
 770         qed_init_qm_info(p_hwfn);
 771
 772         /* stop PF's qm queues */
 773         spin_lock_bh(&qm_lock);
 774         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 775                                     qm_info->start_pq, qm_info->num_pqs);
 776         spin_unlock_bh(&qm_lock);
 777         if (!b_rc)
 778                 return -EINVAL;
 779
 780         /* clear the QM_PF runtime phase leftovers from previous init */
 781         qed_init_clear_rt_data(p_hwfn);
 782
 783         /* prepare QM portion of runtime array */
 784         qed_qm_init_pf(p_hwfn, p_ptt);
 785
 786         /* activate init tool on runtime array */
 787         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 788                           p_hwfn->hw_info.hw_mode);
 789         if (rc)
 790                 return rc;
 791
 792         /* start PF's qm queues */
 793         spin_lock_bh(&qm_lock);
 794         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 795                                     qm_info->start_pq, qm_info->num_pqs);
 796         spin_unlock_bh(&qm_lock);
 797         if (!b_rc)
 798                 return -EINVAL;
 799
 800         return 0;
 801 }
 802
 803 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 804 {
 805         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 806         int rc;
 807
 808         rc = qed_init_qm_sanity(p_hwfn);
 809         if (rc)
 810                 goto alloc_err;
 811
 812         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 813                                         qed_init_qm_get_num_pqs(p_hwfn),
 814                                         GFP_KERNEL);
 815         if (!qm_info->qm_pq_params)
 816                 goto alloc_err;
 817
 818         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 819                                            qed_init_qm_get_num_vports(p_hwfn),
 820                                            GFP_KERNEL);
 821         if (!qm_info->qm_vport_params)
 822                 goto alloc_err;
 823
 824         qm_info->qm_port_params = kzalloc(sizeof(qm_info->qm_port_params) *
 825                                           p_hwfn->cdev->num_ports_in_engines,
 826                                           GFP_KERNEL);
 827         if (!qm_info->qm_port_params)
 828                 goto alloc_err;
 829
 830         qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
 831                                     qed_init_qm_get_num_vports(p_hwfn),
 832                                     GFP_KERNEL);
 833         if (!qm_info->wfq_data)
 834                 goto alloc_err;
 835
 836         return 0;
 837
 838 alloc_err:
 839         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 840         qed_qm_info_free(p_hwfn);
 841         return -ENOMEM;
 842 }
 843
 844 int qed_resc_alloc(struct qed_dev *cdev)
 845 {
 846         struct qed_iscsi_info *p_iscsi_info;
 847         struct qed_fcoe_info *p_fcoe_info;
 848         struct qed_ooo_info *p_ooo_info;
 849 #ifdef CONFIG_QED_LL2
 850         struct qed_ll2_info *p_ll2_info;
 851 #endif
 852         u32 rdma_tasks, excess_tasks;
 853         struct qed_consq *p_consq;
 854         struct qed_eq *p_eq;
 855         u32 line_count;
 856         int i, rc = 0;
 857
 858         if (IS_VF(cdev))
 859                 return rc;
 860
 861         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 862         if (!cdev->fw_data)
 863                 return -ENOMEM;
 864
 865         for_each_hwfn(cdev, i) {
 866                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 867                 u32 n_eqes, num_cons;
 868
 869                 /* First allocate the context manager structure */
 870                 rc = qed_cxt_mngr_alloc(p_hwfn);
 871                 if (rc)
 872                         goto alloc_err;
 873
 874                 /* Set the HW cid/tid numbers (in the contest manager)
 875                  * Must be done prior to any further computations.
 876                  */
 877                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 878                 if (rc)
 879                         goto alloc_err;
 880
 881                 rc = qed_alloc_qm_data(p_hwfn);
 882                 if (rc)
 883                         goto alloc_err;
 884
 885                 /* init qm info */
 886                 qed_init_qm_info(p_hwfn);
 887
 888                 /* Compute the ILT client partition */
 889                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 890                 if (rc) {
 891                         DP_NOTICE(p_hwfn,
 892                                   "too many ILT lines; re-computing with less lines\n");
 893                         /* In case there are not enough ILT lines we reduce the
 894                          * number of RDMA tasks and re-compute.
 895                          */
 896                         excess_tasks =
 897                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 898                         if (!excess_tasks)
 899                                 goto alloc_err;
 900
 901                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 902                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 903                         if (rc)
 904                                 goto alloc_err;
 905
 906                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 907                         if (rc) {
 908                                 DP_ERR(p_hwfn,
 909                                        "failed ILT compute. Requested too many lines: %u\n",
 910                                        line_count);
 911
 912                                 goto alloc_err;
 913                         }
 914                 }
 915
 916                 /* CID map / ILT shadow table / T2
 917                  * The talbes sizes are determined by the computations above
 918                  */
 919                 rc = qed_cxt_tables_alloc(p_hwfn);
 920                 if (rc)
 921                         goto alloc_err;
 922
 923                 /* SPQ, must follow ILT because initializes SPQ context */
 924                 rc = qed_spq_alloc(p_hwfn);
 925                 if (rc)
 926                         goto alloc_err;
 927
 928                 /* SP status block allocation */
 929                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 930                                                          RESERVED_PTT_DPC);
 931
 932                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 933                 if (rc)
 934                         goto alloc_err;
 935
 936                 rc = qed_iov_alloc(p_hwfn);
 937                 if (rc)
 938                         goto alloc_err;
 939
 940                 /* EQ */
 941                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 942                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 943                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 944                                                                PROTOCOLID_ROCE,
 945                                                                NULL) * 2;
 946                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 947                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 948                         num_cons =
 949                             qed_cxt_get_proto_cid_count(p_hwfn,
 950                                                         PROTOCOLID_ISCSI,
 951                                                         NULL);
 952                         n_eqes += 2 * num_cons;
 953                 }
 954
 955                 if (n_eqes > 0xFFFF) {
 956                         DP_ERR(p_hwfn,
 957                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 958                                n_eqes, 0xFFFF);
 959                         rc = -EINVAL;
 960                         goto alloc_err;
 961                 }
 962
 963                 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 964                 if (!p_eq)
 965                         goto alloc_no_mem;
 966                 p_hwfn->p_eq = p_eq;
 967
 968                 p_consq = qed_consq_alloc(p_hwfn);
 969                 if (!p_consq)
 970                         goto alloc_no_mem;
 971                 p_hwfn->p_consq = p_consq;
 972
 973 #ifdef CONFIG_QED_LL2
 974                 if (p_hwfn->using_ll2) {
 975                         p_ll2_info = qed_ll2_alloc(p_hwfn);
 976                         if (!p_ll2_info)
 977                                 goto alloc_no_mem;
 978                         p_hwfn->p_ll2_info = p_ll2_info;
 979                 }
 980 #endif
 981
 982                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
 983                         p_fcoe_info = qed_fcoe_alloc(p_hwfn);
 984                         if (!p_fcoe_info)
 985                                 goto alloc_no_mem;
 986                         p_hwfn->p_fcoe_info = p_fcoe_info;
 987                 }
 988
 989                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 990                         p_iscsi_info = qed_iscsi_alloc(p_hwfn);
 991                         if (!p_iscsi_info)
 992                                 goto alloc_no_mem;
 993                         p_hwfn->p_iscsi_info = p_iscsi_info;
 994                         p_ooo_info = qed_ooo_alloc(p_hwfn);
 995                         if (!p_ooo_info)
 996                                 goto alloc_no_mem;
 997                         p_hwfn->p_ooo_info = p_ooo_info;
 998                 }
 999
1000                 /* DMA info initialization */
1001                 rc = qed_dmae_info_alloc(p_hwfn);
1002                 if (rc)
1003                         goto alloc_err;
1004
1005                 /* DCBX initialization */
1006                 rc = qed_dcbx_info_alloc(p_hwfn);
1007                 if (rc)
1008                         goto alloc_err;
1009         }
1010
1011         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1012         if (!cdev->reset_stats)
1013                 goto alloc_no_mem;
1014
1015         return 0;
1016
1017 alloc_no_mem:
1018         rc = -ENOMEM;
1019 alloc_err:
1020         qed_resc_free(cdev);
1021         return rc;
1022 }
1023
1024 void qed_resc_setup(struct qed_dev *cdev)
1025 {
1026         int i;
1027
1028         if (IS_VF(cdev))
1029                 return;
1030
1031         for_each_hwfn(cdev, i) {
1032                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1033
1034                 qed_cxt_mngr_setup(p_hwfn);
1035                 qed_spq_setup(p_hwfn);
1036                 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
1037                 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
1038
1039                 /* Read shadow of current MFW mailbox */
1040                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1041                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1042                        p_hwfn->mcp_info->mfw_mb_cur,
1043                        p_hwfn->mcp_info->mfw_mb_length);
1044
1045                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1046
1047                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1048 #ifdef CONFIG_QED_LL2
1049                 if (p_hwfn->using_ll2)
1050                         qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
1051 #endif
1052                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1053                         qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info);
1054
1055                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1056                         qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
1057                         qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
1058                 }
1059         }
1060 }
1061
1062 #define FINAL_CLEANUP_POLL_CNT          (100)
1063 #define FINAL_CLEANUP_POLL_TIME         (10)
1064 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1065                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1066 {
1067         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1068         int rc = -EBUSY;
1069
1070         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1071                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1072
1073         if (is_vf)
1074                 id += 0x10;
1075
1076         command |= X_FINAL_CLEANUP_AGG_INT <<
1077                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1078         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1079         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1080         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1081
1082         /* Make sure notification is not set before initiating final cleanup */
1083         if (REG_RD(p_hwfn, addr)) {
1084                 DP_NOTICE(p_hwfn,
1085                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1086                 REG_WR(p_hwfn, addr, 0);
1087         }
1088
1089         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1090                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1091                    id, command);
1092
1093         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1094
1095         /* Poll until completion */
1096         while (!REG_RD(p_hwfn, addr) && count--)
1097                 msleep(FINAL_CLEANUP_POLL_TIME);
1098
1099         if (REG_RD(p_hwfn, addr))
1100                 rc = 0;
1101         else
1102                 DP_NOTICE(p_hwfn,
1103                           "Failed to receive FW final cleanup notification\n");
1104
1105         /* Cleanup afterwards */
1106         REG_WR(p_hwfn, addr, 0);
1107
1108         return rc;
1109 }
1110
1111 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1112 {
1113         int hw_mode = 0;
1114
1115         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1116                 hw_mode |= 1 << MODE_BB;
1117         } else if (QED_IS_AH(p_hwfn->cdev)) {
1118                 hw_mode |= 1 << MODE_K2;
1119         } else {
1120                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1121                           p_hwfn->cdev->type);
1122                 return -EINVAL;
1123         }
1124
1125         switch (p_hwfn->cdev->num_ports_in_engines) {
1126         case 1:
1127                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1128                 break;
1129         case 2:
1130                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1131                 break;
1132         case 4:
1133                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1134                 break;
1135         default:
1136                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1137                           p_hwfn->cdev->num_ports_in_engines);
1138                 return -EINVAL;
1139         }
1140
1141         switch (p_hwfn->cdev->mf_mode) {
1142         case QED_MF_DEFAULT:
1143         case QED_MF_NPAR:
1144                 hw_mode |= 1 << MODE_MF_SI;
1145                 break;
1146         case QED_MF_OVLAN:
1147                 hw_mode |= 1 << MODE_MF_SD;
1148                 break;
1149         default:
1150                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1151                 hw_mode |= 1 << MODE_MF_SI;
1152         }
1153
1154         hw_mode |= 1 << MODE_ASIC;
1155
1156         if (p_hwfn->cdev->num_hwfns > 1)
1157                 hw_mode |= 1 << MODE_100G;
1158
1159         p_hwfn->hw_info.hw_mode = hw_mode;
1160
1161         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1162                    "Configuring function for hw_mode: 0x%08x\n",
1163                    p_hwfn->hw_info.hw_mode);
1164
1165         return 0;
1166 }
1167
1168 /* Init run time data for all PFs on an engine. */
1169 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1170 {
1171         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1172         int i, sb_id;
1173
1174         for_each_hwfn(cdev, i) {
1175                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1176                 struct qed_igu_info *p_igu_info;
1177                 struct qed_igu_block *p_block;
1178                 struct cau_sb_entry sb_entry;
1179
1180                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1181
1182                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
1183                      sb_id++) {
1184                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1185                         if (!p_block->is_pf)
1186                                 continue;
1187
1188                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1189                                               p_block->function_id, 0, 0);
1190                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1191                 }
1192         }
1193 }
1194
1195 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1196                                      struct qed_ptt *p_ptt)
1197 {
1198         u32 val, wr_mbs, cache_line_size;
1199
1200         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1201         switch (val) {
1202         case 0:
1203                 wr_mbs = 128;
1204                 break;
1205         case 1:
1206                 wr_mbs = 256;
1207                 break;
1208         case 2:
1209                 wr_mbs = 512;
1210                 break;
1211         default:
1212                 DP_INFO(p_hwfn,
1213                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1214                         val);
1215                 return;
1216         }
1217
1218         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1219         switch (cache_line_size) {
1220         case 32:
1221                 val = 0;
1222                 break;
1223         case 64:
1224                 val = 1;
1225                 break;
1226         case 128:
1227                 val = 2;
1228                 break;
1229         case 256:
1230                 val = 3;
1231                 break;
1232         default:
1233                 DP_INFO(p_hwfn,
1234                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1235                         cache_line_size);
1236         }
1237
1238         if (L1_CACHE_BYTES > wr_mbs)
1239                 DP_INFO(p_hwfn,
1240                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1241                         L1_CACHE_BYTES, wr_mbs);
1242
1243         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1244 }
1245
1246 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1247                               struct qed_ptt *p_ptt, int hw_mode)
1248 {
1249         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1250         struct qed_qm_common_rt_init_params params;
1251         struct qed_dev *cdev = p_hwfn->cdev;
1252         u8 vf_id, max_num_vfs;
1253         u16 num_pfs, pf_id;
1254         u32 concrete_fid;
1255         int rc = 0;
1256
1257         qed_init_cau_rt_data(cdev);
1258
1259         /* Program GTT windows */
1260         qed_gtt_init(p_hwfn);
1261
1262         if (p_hwfn->mcp_info) {
1263                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1264                         qm_info->pf_rl_en = 1;
1265                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1266                         qm_info->pf_wfq_en = 1;
1267         }
1268
1269         memset(&params, 0, sizeof(params));
1270         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
1271         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1272         params.pf_rl_en = qm_info->pf_rl_en;
1273         params.pf_wfq_en = qm_info->pf_wfq_en;
1274         params.vport_rl_en = qm_info->vport_rl_en;
1275         params.vport_wfq_en = qm_info->vport_wfq_en;
1276         params.port_params = qm_info->qm_port_params;
1277
1278         qed_qm_common_rt_init(p_hwfn, &params);
1279
1280         qed_cxt_hw_init_common(p_hwfn);
1281
1282         qed_init_cache_line_size(p_hwfn, p_ptt);
1283
1284         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1285         if (rc)
1286                 return rc;
1287
1288         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1289         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1290
1291         if (QED_IS_BB(p_hwfn->cdev)) {
1292                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1293                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1294                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1295                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1296                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1297                 }
1298                 /* pretend to original PF */
1299                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1300         }
1301
1302         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1303         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1304                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1305                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1306                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1307                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1308                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1309                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1310         }
1311         /* pretend to original PF */
1312         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1313
1314         return rc;
1315 }
1316
1317 static int
1318 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1319                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1320 {
1321         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1322         u32 dpi_bit_shift, dpi_count;
1323         u32 min_dpis;
1324
1325         /* Calculate DPI size */
1326         dpi_page_size_1 = QED_WID_SIZE * n_cpus;
1327         dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
1328         dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
1329         dpi_page_size = roundup_pow_of_two(dpi_page_size);
1330         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1331
1332         dpi_count = pwm_region_size / dpi_page_size;
1333
1334         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1335         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1336
1337         p_hwfn->dpi_size = dpi_page_size;
1338         p_hwfn->dpi_count = dpi_count;
1339
1340         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1341
1342         if (dpi_count < min_dpis)
1343                 return -EINVAL;
1344
1345         return 0;
1346 }
1347
1348 enum QED_ROCE_EDPM_MODE {
1349         QED_ROCE_EDPM_MODE_ENABLE = 0,
1350         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1351         QED_ROCE_EDPM_MODE_DISABLE = 2,
1352 };
1353
1354 static int
1355 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1356 {
1357         u32 pwm_regsize, norm_regsize;
1358         u32 non_pwm_conn, min_addr_reg1;
1359         u32 db_bar_size, n_cpus;
1360         u32 roce_edpm_mode;
1361         u32 pf_dems_shift;
1362         int rc = 0;
1363         u8 cond;
1364
1365         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1366         if (p_hwfn->cdev->num_hwfns > 1)
1367                 db_bar_size /= 2;
1368
1369         /* Calculate doorbell regions */
1370         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1371                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1372                                                    NULL) +
1373                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1374                                                    NULL);
1375         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
1376         min_addr_reg1 = norm_regsize / 4096;
1377         pwm_regsize = db_bar_size - norm_regsize;
1378
1379         /* Check that the normal and PWM sizes are valid */
1380         if (db_bar_size < norm_regsize) {
1381                 DP_ERR(p_hwfn->cdev,
1382                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1383                        db_bar_size, norm_regsize);
1384                 return -EINVAL;
1385         }
1386
1387         if (pwm_regsize < QED_MIN_PWM_REGION) {
1388                 DP_ERR(p_hwfn->cdev,
1389                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1390                        pwm_regsize,
1391                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1392                 return -EINVAL;
1393         }
1394
1395         /* Calculate number of DPIs */
1396         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1397         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1398             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1399                 /* Either EDPM is mandatory, or we are attempting to allocate a
1400                  * WID per CPU.
1401                  */
1402                 n_cpus = num_present_cpus();
1403                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1404         }
1405
1406         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1407                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1408         if (cond || p_hwfn->dcbx_no_edpm) {
1409                 /* Either EDPM is disabled from user configuration, or it is
1410                  * disabled via DCBx, or it is not mandatory and we failed to
1411                  * allocated a WID per CPU.
1412                  */
1413                 n_cpus = 1;
1414                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1415
1416                 if (cond)
1417                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1418         }
1419
1420         DP_INFO(p_hwfn,
1421                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1422                 norm_regsize,
1423                 pwm_regsize,
1424                 p_hwfn->dpi_size,
1425                 p_hwfn->dpi_count,
1426                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1427                 "disabled" : "enabled");
1428
1429         if (rc) {
1430                 DP_ERR(p_hwfn,
1431                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1432                        p_hwfn->dpi_count,
1433                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1434                 return -EINVAL;
1435         }
1436
1437         p_hwfn->dpi_start_offset = norm_regsize;
1438
1439         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1440         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1441         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1442         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1443
1444         return 0;
1445 }
1446
1447 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1448                             struct qed_ptt *p_ptt, int hw_mode)
1449 {
1450         return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
1451                             p_hwfn->port_id, hw_mode);
1452 }
1453
1454 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1455                           struct qed_ptt *p_ptt,
1456                           struct qed_tunn_start_params *p_tunn,
1457                           int hw_mode,
1458                           bool b_hw_start,
1459                           enum qed_int_mode int_mode,
1460                           bool allow_npar_tx_switch)
1461 {
1462         u8 rel_pf_id = p_hwfn->rel_pf_id;
1463         int rc = 0;
1464
1465         if (p_hwfn->mcp_info) {
1466                 struct qed_mcp_function_info *p_info;
1467
1468                 p_info = &p_hwfn->mcp_info->func_info;
1469                 if (p_info->bandwidth_min)
1470                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1471
1472                 /* Update rate limit once we'll actually have a link */
1473                 p_hwfn->qm_info.pf_rl = 100000;
1474         }
1475
1476         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1477
1478         qed_int_igu_init_rt(p_hwfn);
1479
1480         /* Set VLAN in NIG if needed */
1481         if (hw_mode & BIT(MODE_MF_SD)) {
1482                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1483                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1484                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1485                              p_hwfn->hw_info.ovlan);
1486         }
1487
1488         /* Enable classification by MAC if needed */
1489         if (hw_mode & BIT(MODE_MF_SI)) {
1490                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1491                            "Configuring TAGMAC_CLS_TYPE\n");
1492                 STORE_RT_REG(p_hwfn,
1493                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1494         }
1495
1496         /* Protocl Configuration  */
1497         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1498                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1499         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1500                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1501         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1502
1503         /* Cleanup chip from previous driver if such remains exist */
1504         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1505         if (rc)
1506                 return rc;
1507
1508         /* PF Init sequence */
1509         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1510         if (rc)
1511                 return rc;
1512
1513         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1514         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1515         if (rc)
1516                 return rc;
1517
1518         /* Pure runtime initializations - directly to the HW  */
1519         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1520
1521         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1522         if (rc)
1523                 return rc;
1524
1525         if (b_hw_start) {
1526                 /* enable interrupts */
1527                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1528
1529                 /* send function start command */
1530                 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1531                                      allow_npar_tx_switch);
1532                 if (rc) {
1533                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1534                         return rc;
1535                 }
1536                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1537                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1538                         qed_wr(p_hwfn, p_ptt,
1539                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1540                                0x100);
1541                 }
1542         }
1543         return rc;
1544 }
1545
1546 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1547                                struct qed_ptt *p_ptt,
1548                                u8 enable)
1549 {
1550         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1551
1552         /* Change PF in PXP */
1553         qed_wr(p_hwfn, p_ptt,
1554                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1555
1556         /* wait until value is set - try for 1 second every 50us */
1557         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1558                 val = qed_rd(p_hwfn, p_ptt,
1559                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1560                 if (val == set_val)
1561                         break;
1562
1563                 usleep_range(50, 60);
1564         }
1565
1566         if (val != set_val) {
1567                 DP_NOTICE(p_hwfn,
1568                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1569                 return -EAGAIN;
1570         }
1571
1572         return 0;
1573 }
1574
1575 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1576                                 struct qed_ptt *p_main_ptt)
1577 {
1578         /* Read shadow of current MFW mailbox */
1579         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1580         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1581                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1582 }
1583
1584 static void
1585 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1586                          struct qed_drv_load_params *p_drv_load)
1587 {
1588         memset(p_load_req, 0, sizeof(*p_load_req));
1589
1590         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1591                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1592         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1593         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1594         p_load_req->override_force_load = p_drv_load->override_force_load;
1595 }
1596
1597 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1598 {
1599         struct qed_load_req_params load_req_params;
1600         u32 load_code, param, drv_mb_param;
1601         bool b_default_mtu = true;
1602         struct qed_hwfn *p_hwfn;
1603         int rc = 0, mfw_rc, i;
1604
1605         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1606                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1607                 return -EINVAL;
1608         }
1609
1610         if (IS_PF(cdev)) {
1611                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1612                 if (rc)
1613                         return rc;
1614         }
1615
1616         for_each_hwfn(cdev, i) {
1617                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1618
1619                 /* If management didn't provide a default, set one of our own */
1620                 if (!p_hwfn->hw_info.mtu) {
1621                         p_hwfn->hw_info.mtu = 1500;
1622                         b_default_mtu = false;
1623                 }
1624
1625                 if (IS_VF(cdev)) {
1626                         p_hwfn->b_int_enabled = 1;
1627                         continue;
1628                 }
1629
1630                 /* Enable DMAE in PXP */
1631                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1632
1633                 rc = qed_calc_hw_mode(p_hwfn);
1634                 if (rc)
1635                         return rc;
1636
1637                 qed_fill_load_req_params(&load_req_params,
1638                                          p_params->p_drv_load_params);
1639                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1640                                       &load_req_params);
1641                 if (rc) {
1642                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1643                         return rc;
1644                 }
1645
1646                 load_code = load_req_params.load_code;
1647                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1648                            "Load request was sent. Load code: 0x%x\n",
1649                            load_code);
1650
1651                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1652
1653                 p_hwfn->first_on_engine = (load_code ==
1654                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1655
1656                 switch (load_code) {
1657                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1658                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1659                                                 p_hwfn->hw_info.hw_mode);
1660                         if (rc)
1661                                 break;
1662                 /* Fall into */
1663                 case FW_MSG_CODE_DRV_LOAD_PORT:
1664                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1665                                               p_hwfn->hw_info.hw_mode);
1666                         if (rc)
1667                                 break;
1668
1669                 /* Fall into */
1670                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1671                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1672                                             p_params->p_tunn,
1673                                             p_hwfn->hw_info.hw_mode,
1674                                             p_params->b_hw_start,
1675                                             p_params->int_mode,
1676                                             p_params->allow_npar_tx_switch);
1677                         break;
1678                 default:
1679                         DP_NOTICE(p_hwfn,
1680                                   "Unexpected load code [0x%08x]", load_code);
1681                         rc = -EINVAL;
1682                         break;
1683                 }
1684
1685                 if (rc)
1686                         DP_NOTICE(p_hwfn,
1687                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1688                                    load_code, rc);
1689
1690                 /* ACK mfw regardless of success or failure of initialization */
1691                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1692                                      DRV_MSG_CODE_LOAD_DONE,
1693                                      0, &load_code, &param);
1694                 if (rc)
1695                         return rc;
1696                 if (mfw_rc) {
1697                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1698                         return mfw_rc;
1699                 }
1700
1701                 /* send DCBX attention request command */
1702                 DP_VERBOSE(p_hwfn,
1703                            QED_MSG_DCB,
1704                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1705                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1706                                      DRV_MSG_CODE_SET_DCBX,
1707                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1708                                      &load_code, &param);
1709                 if (mfw_rc) {
1710                         DP_NOTICE(p_hwfn,
1711                                   "Failed to send DCBX attention request\n");
1712                         return mfw_rc;
1713                 }
1714
1715                 p_hwfn->hw_init_done = true;
1716         }
1717
1718         if (IS_PF(cdev)) {
1719                 p_hwfn = QED_LEADING_HWFN(cdev);
1720                 drv_mb_param = STORM_FW_VERSION;
1721                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1722                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1723                                  drv_mb_param, &load_code, &param);
1724                 if (rc)
1725                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1726
1727                 if (!b_default_mtu) {
1728                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1729                                                    p_hwfn->hw_info.mtu);
1730                         if (rc)
1731                                 DP_INFO(p_hwfn,
1732                                         "Failed to update default mtu\n");
1733                 }
1734
1735                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1736                                                     p_hwfn->p_main_ptt,
1737                                                   QED_OV_DRIVER_STATE_DISABLED);
1738                 if (rc)
1739                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1740
1741                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1742                                                QED_OV_ESWITCH_VEB);
1743                 if (rc)
1744                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1745         }
1746
1747         return 0;
1748 }
1749
1750 #define QED_HW_STOP_RETRY_LIMIT (10)
1751 static void qed_hw_timers_stop(struct qed_dev *cdev,
1752                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1753 {
1754         int i;
1755
1756         /* close timers */
1757         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1758         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1759
1760         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1761                 if ((!qed_rd(p_hwfn, p_ptt,
1762                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1763                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1764                         break;
1765
1766                 /* Dependent on number of connection/tasks, possibly
1767                  * 1ms sleep is required between polls
1768                  */
1769                 usleep_range(1000, 2000);
1770         }
1771
1772         if (i < QED_HW_STOP_RETRY_LIMIT)
1773                 return;
1774
1775         DP_NOTICE(p_hwfn,
1776                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1777                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1778                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1779 }
1780
1781 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1782 {
1783         int j;
1784
1785         for_each_hwfn(cdev, j) {
1786                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1787                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1788
1789                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1790         }
1791 }
1792
1793 int qed_hw_stop(struct qed_dev *cdev)
1794 {
1795         struct qed_hwfn *p_hwfn;
1796         struct qed_ptt *p_ptt;
1797         int rc, rc2 = 0;
1798         int j;
1799
1800         for_each_hwfn(cdev, j) {
1801                 p_hwfn = &cdev->hwfns[j];
1802                 p_ptt = p_hwfn->p_main_ptt;
1803
1804                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1805
1806                 if (IS_VF(cdev)) {
1807                         qed_vf_pf_int_cleanup(p_hwfn);
1808                         rc = qed_vf_pf_reset(p_hwfn);
1809                         if (rc) {
1810                                 DP_NOTICE(p_hwfn,
1811                                           "qed_vf_pf_reset failed. rc = %d.\n",
1812                                           rc);
1813                                 rc2 = -EINVAL;
1814                         }
1815                         continue;
1816                 }
1817
1818                 /* mark the hw as uninitialized... */
1819                 p_hwfn->hw_init_done = false;
1820
1821                 /* Send unload command to MCP */
1822                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1823                 if (rc) {
1824                         DP_NOTICE(p_hwfn,
1825                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1826                                   rc);
1827                         rc2 = -EINVAL;
1828                 }
1829
1830                 qed_slowpath_irq_sync(p_hwfn);
1831
1832                 /* After this point no MFW attentions are expected, e.g. prevent
1833                  * race between pf stop and dcbx pf update.
1834                  */
1835                 rc = qed_sp_pf_stop(p_hwfn);
1836                 if (rc) {
1837                         DP_NOTICE(p_hwfn,
1838                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1839                                   rc);
1840                         rc2 = -EINVAL;
1841                 }
1842
1843                 qed_wr(p_hwfn, p_ptt,
1844                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1845
1846                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1847                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1848                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1849                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1850                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1851
1852                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1853
1854                 /* Disable Attention Generation */
1855                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1856
1857                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1858                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1859
1860                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1861
1862                 /* Need to wait 1ms to guarantee SBs are cleared */
1863                 usleep_range(1000, 2000);
1864
1865                 /* Disable PF in HW blocks */
1866                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1867                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1868
1869                 qed_mcp_unload_done(p_hwfn, p_ptt);
1870                 if (rc) {
1871                         DP_NOTICE(p_hwfn,
1872                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1873                                   rc);
1874                         rc2 = -EINVAL;
1875                 }
1876         }
1877
1878         if (IS_PF(cdev)) {
1879                 p_hwfn = QED_LEADING_HWFN(cdev);
1880                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1881
1882                 /* Disable DMAE in PXP - in CMT, this should only be done for
1883                  * first hw-function, and only after all transactions have
1884                  * stopped for all active hw-functions.
1885                  */
1886                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1887                 if (rc) {
1888                         DP_NOTICE(p_hwfn,
1889                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1890                         rc2 = -EINVAL;
1891                 }
1892         }
1893
1894         return rc2;
1895 }
1896
1897 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1898 {
1899         int j;
1900
1901         for_each_hwfn(cdev, j) {
1902                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1903                 struct qed_ptt *p_ptt;
1904
1905                 if (IS_VF(cdev)) {
1906                         qed_vf_pf_int_cleanup(p_hwfn);
1907                         continue;
1908                 }
1909                 p_ptt = qed_ptt_acquire(p_hwfn);
1910                 if (!p_ptt)
1911                         return -EAGAIN;
1912
1913                 DP_VERBOSE(p_hwfn,
1914                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1915
1916                 qed_wr(p_hwfn, p_ptt,
1917                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1918
1919                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1920                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1921                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1922                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1923                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1924
1925                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1926
1927                 /* Need to wait 1ms to guarantee SBs are cleared */
1928                 usleep_range(1000, 2000);
1929                 qed_ptt_release(p_hwfn, p_ptt);
1930         }
1931
1932         return 0;
1933 }
1934
1935 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1936 {
1937         struct qed_ptt *p_ptt;
1938
1939         if (IS_VF(p_hwfn->cdev))
1940                 return 0;
1941
1942         p_ptt = qed_ptt_acquire(p_hwfn);
1943         if (!p_ptt)
1944                 return -EAGAIN;
1945
1946         /* Re-open incoming traffic */
1947         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1948         qed_ptt_release(p_hwfn, p_ptt);
1949
1950         return 0;
1951 }
1952
1953 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1954 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1955 {
1956         qed_ptt_pool_free(p_hwfn);
1957         kfree(p_hwfn->hw_info.p_igu_info);
1958 }
1959
1960 /* Setup bar access */
1961 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1962 {
1963         /* clear indirect access */
1964         if (QED_IS_AH(p_hwfn->cdev)) {
1965                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1966                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1967                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1968                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1969                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1970                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1971                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1972                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1973         } else {
1974                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1975                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
1976                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1977                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
1978                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1979                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
1980                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1981                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
1982         }
1983
1984         /* Clean Previous errors if such exist */
1985         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1986                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1987
1988         /* enable internal target-read */
1989         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1990                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1991 }
1992
1993 static void get_function_id(struct qed_hwfn *p_hwfn)
1994 {
1995         /* ME Register */
1996         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1997                                                   PXP_PF_ME_OPAQUE_ADDR);
1998
1999         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2000
2001         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2002         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2003                                       PXP_CONCRETE_FID_PFID);
2004         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2005                                     PXP_CONCRETE_FID_PORT);
2006
2007         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2008                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2009                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2010 }
2011
2012 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2013 {
2014         u32 *feat_num = p_hwfn->hw_info.feat_num;
2015         struct qed_sb_cnt_info sb_cnt_info;
2016         u32 non_l2_sbs = 0;
2017
2018         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2019             p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
2020                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2021                  * the status blocks equally between L2 / RoCE but with
2022                  * consideration as to how many l2 queues / cnqs we have.
2023                  */
2024                 feat_num[QED_RDMA_CNQ] =
2025                         min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 2,
2026                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2027
2028                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2029         }
2030
2031         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
2032             p_hwfn->hw_info.personality == QED_PCI_ETH) {
2033                 /* Start by allocating VF queues, then PF's */
2034                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2035                 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2036                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2037                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2038                                                 sb_cnt_info.sb_iov_cnt);
2039                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2040                                                 RESC_NUM(p_hwfn, QED_SB) -
2041                                                 non_l2_sbs,
2042                                                 RESC_NUM(p_hwfn,
2043                                                          QED_L2_QUEUE) -
2044                                                 FEAT_NUM(p_hwfn,
2045                                                          QED_VF_L2_QUE));
2046         }
2047
2048         DP_VERBOSE(p_hwfn,
2049                    NETIF_MSG_PROBE,
2050                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d\n",
2051                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2052                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2053                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2054                    RESC_NUM(p_hwfn, QED_SB));
2055 }
2056
2057 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2058 {
2059         switch (res_id) {
2060         case QED_L2_QUEUE:
2061                 return "L2_QUEUE";
2062         case QED_VPORT:
2063                 return "VPORT";
2064         case QED_RSS_ENG:
2065                 return "RSS_ENG";
2066         case QED_PQ:
2067                 return "PQ";
2068         case QED_RL:
2069                 return "RL";
2070         case QED_MAC:
2071                 return "MAC";
2072         case QED_VLAN:
2073                 return "VLAN";
2074         case QED_RDMA_CNQ_RAM:
2075                 return "RDMA_CNQ_RAM";
2076         case QED_ILT:
2077                 return "ILT";
2078         case QED_LL2_QUEUE:
2079                 return "LL2_QUEUE";
2080         case QED_CMDQS_CQS:
2081                 return "CMDQS_CQS";
2082         case QED_RDMA_STATS_QUEUE:
2083                 return "RDMA_STATS_QUEUE";
2084         case QED_BDQ:
2085                 return "BDQ";
2086         case QED_SB:
2087                 return "SB";
2088         default:
2089                 return "UNKNOWN_RESOURCE";
2090         }
2091 }
2092
2093 static int
2094 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2095                             struct qed_ptt *p_ptt,
2096                             enum qed_resources res_id,
2097                             u32 resc_max_val, u32 *p_mcp_resp)
2098 {
2099         int rc;
2100
2101         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2102                                       resc_max_val, p_mcp_resp);
2103         if (rc) {
2104                 DP_NOTICE(p_hwfn,
2105                           "MFW response failure for a max value setting of resource %d [%s]\n",
2106                           res_id, qed_hw_get_resc_name(res_id));
2107                 return rc;
2108         }
2109
2110         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2111                 DP_INFO(p_hwfn,
2112                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2113                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2114
2115         return 0;
2116 }
2117
2118 static int
2119 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2120 {
2121         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2122         u32 resc_max_val, mcp_resp;
2123         u8 res_id;
2124         int rc;
2125
2126         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2127                 switch (res_id) {
2128                 case QED_LL2_QUEUE:
2129                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2130                         break;
2131                 case QED_RDMA_CNQ_RAM:
2132                         /* No need for a case for QED_CMDQS_CQS since
2133                          * CNQ/CMDQS are the same resource.
2134                          */
2135                         resc_max_val = NUM_OF_CMDQS_CQS;
2136                         break;
2137                 case QED_RDMA_STATS_QUEUE:
2138                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2139                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2140                         break;
2141                 case QED_BDQ:
2142                         resc_max_val = BDQ_NUM_RESOURCES;
2143                         break;
2144                 default:
2145                         continue;
2146                 }
2147
2148                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2149                                                  resc_max_val, &mcp_resp);
2150                 if (rc)
2151                         return rc;
2152
2153                 /* There's no point to continue to the next resource if the
2154                  * command is not supported by the MFW.
2155                  * We do continue if the command is supported but the resource
2156                  * is unknown to the MFW. Such a resource will be later
2157                  * configured with the default allocation values.
2158                  */
2159                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2160                         return -EINVAL;
2161         }
2162
2163         return 0;
2164 }
2165
2166 static
2167 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2168                          enum qed_resources res_id,
2169                          u32 *p_resc_num, u32 *p_resc_start)
2170 {
2171         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2172         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2173         struct qed_sb_cnt_info sb_cnt_info;
2174
2175         switch (res_id) {
2176         case QED_L2_QUEUE:
2177                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2178                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2179                 break;
2180         case QED_VPORT:
2181                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2182                                MAX_NUM_VPORTS_BB) / num_funcs;
2183                 break;
2184         case QED_RSS_ENG:
2185                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2186                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2187                 break;
2188         case QED_PQ:
2189                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2190                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2191                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2192                 break;
2193         case QED_RL:
2194                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2195                 break;
2196         case QED_MAC:
2197         case QED_VLAN:
2198                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2199                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2200                 break;
2201         case QED_ILT:
2202                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2203                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2204                 break;
2205         case QED_LL2_QUEUE:
2206                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2207                 break;
2208         case QED_RDMA_CNQ_RAM:
2209         case QED_CMDQS_CQS:
2210                 /* CNQ/CMDQS are the same resource */
2211                 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2212                 break;
2213         case QED_RDMA_STATS_QUEUE:
2214                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2215                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2216                 break;
2217         case QED_BDQ:
2218                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2219                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2220                         *p_resc_num = 0;
2221                 else
2222                         *p_resc_num = 1;
2223                 break;
2224         case QED_SB:
2225                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2226                 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2227                 *p_resc_num = sb_cnt_info.sb_cnt;
2228                 break;
2229         default:
2230                 return -EINVAL;
2231         }
2232
2233         switch (res_id) {
2234         case QED_BDQ:
2235                 if (!*p_resc_num)
2236                         *p_resc_start = 0;
2237                 else if (p_hwfn->cdev->num_ports_in_engines == 4)
2238                         *p_resc_start = p_hwfn->port_id;
2239                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2240                         *p_resc_start = p_hwfn->port_id;
2241                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2242                         *p_resc_start = p_hwfn->port_id + 2;
2243                 break;
2244         default:
2245                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2246                 break;
2247         }
2248
2249         return 0;
2250 }
2251
2252 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2253                                   enum qed_resources res_id)
2254 {
2255         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2256         u32 mcp_resp, *p_resc_num, *p_resc_start;
2257         int rc;
2258
2259         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2260         p_resc_start = &RESC_START(p_hwfn, res_id);
2261
2262         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2263                                   &dflt_resc_start);
2264         if (rc) {
2265                 DP_ERR(p_hwfn,
2266                        "Failed to get default amount for resource %d [%s]\n",
2267                        res_id, qed_hw_get_resc_name(res_id));
2268                 return rc;
2269         }
2270
2271         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2272                                    &mcp_resp, p_resc_num, p_resc_start);
2273         if (rc) {
2274                 DP_NOTICE(p_hwfn,
2275                           "MFW response failure for an allocation request for resource %d [%s]\n",
2276                           res_id, qed_hw_get_resc_name(res_id));
2277                 return rc;
2278         }
2279
2280         /* Default driver values are applied in the following cases:
2281          * - The resource allocation MB command is not supported by the MFW
2282          * - There is an internal error in the MFW while processing the request
2283          * - The resource ID is unknown to the MFW
2284          */
2285         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2286                 DP_INFO(p_hwfn,
2287                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2288                         res_id,
2289                         qed_hw_get_resc_name(res_id),
2290                         mcp_resp, dflt_resc_num, dflt_resc_start);
2291                 *p_resc_num = dflt_resc_num;
2292                 *p_resc_start = dflt_resc_start;
2293                 goto out;
2294         }
2295
2296         /* Special handling for status blocks; Would be revised in future */
2297         if (res_id == QED_SB) {
2298                 *p_resc_num -= 1;
2299                 *p_resc_start -= p_hwfn->enabled_func_idx;
2300         }
2301 out:
2302         /* PQs have to divide by 8 [that's the HW granularity].
2303          * Reduce number so it would fit.
2304          */
2305         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2306                 DP_INFO(p_hwfn,
2307                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2308                         *p_resc_num,
2309                         (*p_resc_num) & ~0x7,
2310                         *p_resc_start, (*p_resc_start) & ~0x7);
2311                 *p_resc_num &= ~0x7;
2312                 *p_resc_start &= ~0x7;
2313         }
2314
2315         return 0;
2316 }
2317
2318 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2319 {
2320         int rc;
2321         u8 res_id;
2322
2323         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2324                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2325                 if (rc)
2326                         return rc;
2327         }
2328
2329         return 0;
2330 }
2331
2332 #define QED_RESC_ALLOC_LOCK_RETRY_CNT           10
2333 #define QED_RESC_ALLOC_LOCK_RETRY_INTVL_US      10000   /* 10 msec */
2334
2335 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2336 {
2337         struct qed_resc_unlock_params resc_unlock_params;
2338         struct qed_resc_lock_params resc_lock_params;
2339         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2340         u8 res_id;
2341         int rc;
2342
2343         /* Setting the max values of the soft resources and the following
2344          * resources allocation queries should be atomic. Since several PFs can
2345          * run in parallel - a resource lock is needed.
2346          * If either the resource lock or resource set value commands are not
2347          * supported - skip the the max values setting, release the lock if
2348          * needed, and proceed to the queries. Other failures, including a
2349          * failure to acquire the lock, will cause this function to fail.
2350          */
2351         memset(&resc_lock_params, 0, sizeof(resc_lock_params));
2352         resc_lock_params.resource = QED_RESC_LOCK_RESC_ALLOC;
2353         resc_lock_params.retry_num = QED_RESC_ALLOC_LOCK_RETRY_CNT;
2354         resc_lock_params.retry_interval = QED_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2355         resc_lock_params.sleep_b4_retry = true;
2356         memset(&resc_unlock_params, 0, sizeof(resc_unlock_params));
2357         resc_unlock_params.resource = QED_RESC_LOCK_RESC_ALLOC;
2358
2359         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2360         if (rc && rc != -EINVAL) {
2361                 return rc;
2362         } else if (rc == -EINVAL) {
2363                 DP_INFO(p_hwfn,
2364                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2365         } else if (!rc && !resc_lock_params.b_granted) {
2366                 DP_NOTICE(p_hwfn,
2367                           "Failed to acquire the resource lock for the resource allocation commands\n");
2368                 return -EBUSY;
2369         } else {
2370                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2371                 if (rc && rc != -EINVAL) {
2372                         DP_NOTICE(p_hwfn,
2373                                   "Failed to set the max values of the soft resources\n");
2374                         goto unlock_and_exit;
2375                 } else if (rc == -EINVAL) {
2376                         DP_INFO(p_hwfn,
2377                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2378                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2379                                                  &resc_unlock_params);
2380                         if (rc)
2381                                 DP_INFO(p_hwfn,
2382                                         "Failed to release the resource lock for the resource allocation commands\n");
2383                 }
2384         }
2385
2386         rc = qed_hw_set_resc_info(p_hwfn);
2387         if (rc)
2388                 goto unlock_and_exit;
2389
2390         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2391                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2392                 if (rc)
2393                         DP_INFO(p_hwfn,
2394                                 "Failed to release the resource lock for the resource allocation commands\n");
2395         }
2396
2397         /* Sanity for ILT */
2398         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2399             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2400                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2401                           RESC_START(p_hwfn, QED_ILT),
2402                           RESC_END(p_hwfn, QED_ILT) - 1);
2403                 return -EINVAL;
2404         }
2405
2406         qed_hw_set_feat(p_hwfn);
2407
2408         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2409                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2410                            qed_hw_get_resc_name(res_id),
2411                            RESC_NUM(p_hwfn, res_id),
2412                            RESC_START(p_hwfn, res_id));
2413
2414         return 0;
2415
2416 unlock_and_exit:
2417         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2418                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2419         return rc;
2420 }
2421
2422 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2423 {
2424         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2425         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2426         struct qed_mcp_link_params *link;
2427
2428         /* Read global nvm_cfg address */
2429         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2430
2431         /* Verify MCP has initialized it */
2432         if (!nvm_cfg_addr) {
2433                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2434                 return -EINVAL;
2435         }
2436
2437         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2438         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2439
2440         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2441                offsetof(struct nvm_cfg1, glob) +
2442                offsetof(struct nvm_cfg1_glob, core_cfg);
2443
2444         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2445
2446         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2447                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2448         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2449                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2450                 break;
2451         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2452                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2453                 break;
2454         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2455                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2456                 break;
2457         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2458                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2459                 break;
2460         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2461                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2462                 break;
2463         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2464                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2465                 break;
2466         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2467                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2468                 break;
2469         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2470                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2471                 break;
2472         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2473                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2474                 break;
2475         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2476                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2477                 break;
2478         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2479                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2480                 break;
2481         default:
2482                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2483                 break;
2484         }
2485
2486         /* Read default link configuration */
2487         link = &p_hwfn->mcp_info->link_input;
2488         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2489                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2490         link_temp = qed_rd(p_hwfn, p_ptt,
2491                            port_cfg_addr +
2492                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2493         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2494         link->speed.advertised_speeds = link_temp;
2495
2496         link_temp = link->speed.advertised_speeds;
2497         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2498
2499         link_temp = qed_rd(p_hwfn, p_ptt,
2500                            port_cfg_addr +
2501                            offsetof(struct nvm_cfg1_port, link_settings));
2502         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2503                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2504         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2505                 link->speed.autoneg = true;
2506                 break;
2507         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2508                 link->speed.forced_speed = 1000;
2509                 break;
2510         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2511                 link->speed.forced_speed = 10000;
2512                 break;
2513         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2514                 link->speed.forced_speed = 25000;
2515                 break;
2516         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2517                 link->speed.forced_speed = 40000;
2518                 break;
2519         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2520                 link->speed.forced_speed = 50000;
2521                 break;
2522         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2523                 link->speed.forced_speed = 100000;
2524                 break;
2525         default:
2526                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2527         }
2528
2529         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2530         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2531         link->pause.autoneg = !!(link_temp &
2532                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2533         link->pause.forced_rx = !!(link_temp &
2534                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2535         link->pause.forced_tx = !!(link_temp &
2536                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2537         link->loopback_mode = 0;
2538
2539         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2540                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2541                    link->speed.forced_speed, link->speed.advertised_speeds,
2542                    link->speed.autoneg, link->pause.autoneg);
2543
2544         /* Read Multi-function information from shmem */
2545         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2546                offsetof(struct nvm_cfg1, glob) +
2547                offsetof(struct nvm_cfg1_glob, generic_cont0);
2548
2549         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2550
2551         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2552                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
2553
2554         switch (mf_mode) {
2555         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2556                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2557                 break;
2558         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2559                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2560                 break;
2561         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2562                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2563                 break;
2564         }
2565         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2566                 p_hwfn->cdev->mf_mode);
2567
2568         /* Read Multi-function information from shmem */
2569         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2570                 offsetof(struct nvm_cfg1, glob) +
2571                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2572
2573         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2574         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2575                 __set_bit(QED_DEV_CAP_ETH,
2576                           &p_hwfn->hw_info.device_capabilities);
2577         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2578                 __set_bit(QED_DEV_CAP_FCOE,
2579                           &p_hwfn->hw_info.device_capabilities);
2580         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2581                 __set_bit(QED_DEV_CAP_ISCSI,
2582                           &p_hwfn->hw_info.device_capabilities);
2583         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2584                 __set_bit(QED_DEV_CAP_ROCE,
2585                           &p_hwfn->hw_info.device_capabilities);
2586
2587         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2588 }
2589
2590 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2591 {
2592         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2593         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2594         struct qed_dev *cdev = p_hwfn->cdev;
2595
2596         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2597
2598         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2599          * in the other bits are selected.
2600          * Bits 1-15 are for functions 1-15, respectively, and their value is
2601          * '0' only for enabled functions (function 0 always exists and
2602          * enabled).
2603          * In case of CMT, only the "even" functions are enabled, and thus the
2604          * number of functions for both hwfns is learnt from the same bits.
2605          */
2606         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2607
2608         if (reg_function_hide & 0x1) {
2609                 if (QED_IS_BB(cdev)) {
2610                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2611                                 num_funcs = 0;
2612                                 eng_mask = 0xaaaa;
2613                         } else {
2614                                 num_funcs = 1;
2615                                 eng_mask = 0x5554;
2616                         }
2617                 } else {
2618                         num_funcs = 1;
2619                         eng_mask = 0xfffe;
2620                 }
2621
2622                 /* Get the number of the enabled functions on the engine */
2623                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2624                 while (tmp) {
2625                         if (tmp & 0x1)
2626                                 num_funcs++;
2627                         tmp >>= 0x1;
2628                 }
2629
2630                 /* Get the PF index within the enabled functions */
2631                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2632                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2633                 while (tmp) {
2634                         if (tmp & 0x1)
2635                                 enabled_func_idx--;
2636                         tmp >>= 0x1;
2637                 }
2638         }
2639
2640         p_hwfn->num_funcs_on_engine = num_funcs;
2641         p_hwfn->enabled_func_idx = enabled_func_idx;
2642
2643         DP_VERBOSE(p_hwfn,
2644                    NETIF_MSG_PROBE,
2645                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2646                    p_hwfn->rel_pf_id,
2647                    p_hwfn->abs_pf_id,
2648                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2649 }
2650
2651 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2652                                     struct qed_ptt *p_ptt)
2653 {
2654         u32 port_mode;
2655
2656         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2657
2658         if (port_mode < 3) {
2659                 p_hwfn->cdev->num_ports_in_engines = 1;
2660         } else if (port_mode <= 5) {
2661                 p_hwfn->cdev->num_ports_in_engines = 2;
2662         } else {
2663                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2664                           p_hwfn->cdev->num_ports_in_engines);
2665
2666                 /* Default num_ports_in_engines to something */
2667                 p_hwfn->cdev->num_ports_in_engines = 1;
2668         }
2669 }
2670
2671 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2672                                     struct qed_ptt *p_ptt)
2673 {
2674         u32 port;
2675         int i;
2676
2677         p_hwfn->cdev->num_ports_in_engines = 0;
2678
2679         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2680                 port = qed_rd(p_hwfn, p_ptt,
2681                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2682                 if (port & 1)
2683                         p_hwfn->cdev->num_ports_in_engines++;
2684         }
2685
2686         if (!p_hwfn->cdev->num_ports_in_engines) {
2687                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2688
2689                 /* Default num_ports_in_engine to something */
2690                 p_hwfn->cdev->num_ports_in_engines = 1;
2691         }
2692 }
2693
2694 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2695 {
2696         if (QED_IS_BB(p_hwfn->cdev))
2697                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2698         else
2699                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2700 }
2701
2702 static int
2703 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2704                 struct qed_ptt *p_ptt,
2705                 enum qed_pci_personality personality)
2706 {
2707         int rc;
2708
2709         /* Since all information is common, only first hwfns should do this */
2710         if (IS_LEAD_HWFN(p_hwfn)) {
2711                 rc = qed_iov_hw_info(p_hwfn);
2712                 if (rc)
2713                         return rc;
2714         }
2715
2716         qed_hw_info_port_num(p_hwfn, p_ptt);
2717
2718         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2719
2720         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2721         if (rc)
2722                 return rc;
2723
2724         if (qed_mcp_is_init(p_hwfn))
2725                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2726                                 p_hwfn->mcp_info->func_info.mac);
2727         else
2728                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2729
2730         if (qed_mcp_is_init(p_hwfn)) {
2731                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2732                         p_hwfn->hw_info.ovlan =
2733                                 p_hwfn->mcp_info->func_info.ovlan;
2734
2735                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2736         }
2737
2738         if (qed_mcp_is_init(p_hwfn)) {
2739                 enum qed_pci_personality protocol;
2740
2741                 protocol = p_hwfn->mcp_info->func_info.protocol;
2742                 p_hwfn->hw_info.personality = protocol;
2743         }
2744
2745         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2746         p_hwfn->hw_info.num_active_tc = 1;
2747
2748         qed_get_num_funcs(p_hwfn, p_ptt);
2749
2750         if (qed_mcp_is_init(p_hwfn))
2751                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2752
2753         return qed_hw_get_resc(p_hwfn, p_ptt);
2754 }
2755
2756 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2757 {
2758         struct qed_dev *cdev = p_hwfn->cdev;
2759         u16 device_id_mask;
2760         u32 tmp;
2761
2762         /* Read Vendor Id / Device Id */
2763         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2764         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2765
2766         /* Determine type */
2767         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2768         switch (device_id_mask) {
2769         case QED_DEV_ID_MASK_BB:
2770                 cdev->type = QED_DEV_TYPE_BB;
2771                 break;
2772         case QED_DEV_ID_MASK_AH:
2773                 cdev->type = QED_DEV_TYPE_AH;
2774                 break;
2775         default:
2776                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2777                 return -EBUSY;
2778         }
2779
2780         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2781         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2782
2783         MASK_FIELD(CHIP_REV, cdev->chip_rev);
2784
2785         /* Learn number of HW-functions */
2786         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2787
2788         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2789                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2790                 cdev->num_hwfns = 2;
2791         } else {
2792                 cdev->num_hwfns = 1;
2793         }
2794
2795         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2796                                     MISCS_REG_CHIP_TEST_REG) >> 4;
2797         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2798         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2799         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2800
2801         DP_INFO(cdev->hwfns,
2802                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2803                 QED_IS_BB(cdev) ? "BB" : "AH",
2804                 'A' + cdev->chip_rev,
2805                 (int)cdev->chip_metal,
2806                 cdev->chip_num, cdev->chip_rev,
2807                 cdev->chip_bond_id, cdev->chip_metal);
2808
2809         if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
2810                 DP_NOTICE(cdev->hwfns,
2811                           "The chip type/rev (BB A0) is not supported!\n");
2812                 return -EINVAL;
2813         }
2814
2815         return 0;
2816 }
2817
2818 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2819                                  void __iomem *p_regview,
2820                                  void __iomem *p_doorbells,
2821                                  enum qed_pci_personality personality)
2822 {
2823         int rc = 0;
2824
2825         /* Split PCI bars evenly between hwfns */
2826         p_hwfn->regview = p_regview;
2827         p_hwfn->doorbells = p_doorbells;
2828
2829         if (IS_VF(p_hwfn->cdev))
2830                 return qed_vf_hw_prepare(p_hwfn);
2831
2832         /* Validate that chip access is feasible */
2833         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2834                 DP_ERR(p_hwfn,
2835                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2836                 return -EINVAL;
2837         }
2838
2839         get_function_id(p_hwfn);
2840
2841         /* Allocate PTT pool */
2842         rc = qed_ptt_pool_alloc(p_hwfn);
2843         if (rc)
2844                 goto err0;
2845
2846         /* Allocate the main PTT */
2847         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2848
2849         /* First hwfn learns basic information, e.g., number of hwfns */
2850         if (!p_hwfn->my_id) {
2851                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2852                 if (rc)
2853                         goto err1;
2854         }
2855
2856         qed_hw_hwfn_prepare(p_hwfn);
2857
2858         /* Initialize MCP structure */
2859         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2860         if (rc) {
2861                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2862                 goto err1;
2863         }
2864
2865         /* Read the device configuration information from the HW and SHMEM */
2866         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2867         if (rc) {
2868                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2869                 goto err2;
2870         }
2871
2872         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2873          * is called as it sets the ports number in an engine.
2874          */
2875         if (IS_LEAD_HWFN(p_hwfn)) {
2876                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2877                 if (rc)
2878                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2879         }
2880
2881         /* Allocate the init RT array and initialize the init-ops engine */
2882         rc = qed_init_alloc(p_hwfn);
2883         if (rc)
2884                 goto err2;
2885
2886         return rc;
2887 err2:
2888         if (IS_LEAD_HWFN(p_hwfn))
2889                 qed_iov_free_hw_info(p_hwfn->cdev);
2890         qed_mcp_free(p_hwfn);
2891 err1:
2892         qed_hw_hwfn_free(p_hwfn);
2893 err0:
2894         return rc;
2895 }
2896
2897 int qed_hw_prepare(struct qed_dev *cdev,
2898                    int personality)
2899 {
2900         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2901         int rc;
2902
2903         /* Store the precompiled init data ptrs */
2904         if (IS_PF(cdev))
2905                 qed_init_iro_array(cdev);
2906
2907         /* Initialize the first hwfn - will learn number of hwfns */
2908         rc = qed_hw_prepare_single(p_hwfn,
2909                                    cdev->regview,
2910                                    cdev->doorbells, personality);
2911         if (rc)
2912                 return rc;
2913
2914         personality = p_hwfn->hw_info.personality;
2915
2916         /* Initialize the rest of the hwfns */
2917         if (cdev->num_hwfns > 1) {
2918                 void __iomem *p_regview, *p_doorbell;
2919                 u8 __iomem *addr;
2920
2921                 /* adjust bar offset for second engine */
2922                 addr = cdev->regview +
2923                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2924                                        BAR_ID_0) / 2;
2925                 p_regview = addr;
2926
2927                 addr = cdev->doorbells +
2928                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2929                                        BAR_ID_1) / 2;
2930                 p_doorbell = addr;
2931
2932                 /* prepare second hw function */
2933                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
2934                                            p_doorbell, personality);
2935
2936                 /* in case of error, need to free the previously
2937                  * initiliazed hwfn 0.
2938                  */
2939                 if (rc) {
2940                         if (IS_PF(cdev)) {
2941                                 qed_init_free(p_hwfn);
2942                                 qed_mcp_free(p_hwfn);
2943                                 qed_hw_hwfn_free(p_hwfn);
2944                         }
2945                 }
2946         }
2947
2948         return rc;
2949 }
2950
2951 void qed_hw_remove(struct qed_dev *cdev)
2952 {
2953         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2954         int i;
2955
2956         if (IS_PF(cdev))
2957                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2958                                                QED_OV_DRIVER_STATE_NOT_LOADED);
2959
2960         for_each_hwfn(cdev, i) {
2961                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2962
2963                 if (IS_VF(cdev)) {
2964                         qed_vf_pf_release(p_hwfn);
2965                         continue;
2966                 }
2967
2968                 qed_init_free(p_hwfn);
2969                 qed_hw_hwfn_free(p_hwfn);
2970                 qed_mcp_free(p_hwfn);
2971         }
2972
2973         qed_iov_free_hw_info(cdev);
2974 }
2975
2976 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2977                                     struct qed_chain *p_chain)
2978 {
2979         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2980         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2981         struct qed_chain_next *p_next;
2982         u32 size, i;
2983
2984         if (!p_virt)
2985                 return;
2986
2987         size = p_chain->elem_size * p_chain->usable_per_page;
2988
2989         for (i = 0; i < p_chain->page_cnt; i++) {
2990                 if (!p_virt)
2991                         break;
2992
2993                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2994                 p_virt_next = p_next->next_virt;
2995                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2996
2997                 dma_free_coherent(&cdev->pdev->dev,
2998                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2999
3000                 p_virt = p_virt_next;
3001                 p_phys = p_phys_next;
3002         }
3003 }
3004
3005 static void qed_chain_free_single(struct qed_dev *cdev,
3006                                   struct qed_chain *p_chain)
3007 {
3008         if (!p_chain->p_virt_addr)
3009                 return;
3010
3011         dma_free_coherent(&cdev->pdev->dev,
3012                           QED_CHAIN_PAGE_SIZE,
3013                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3014 }
3015
3016 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3017 {
3018         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3019         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3020         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3021
3022         if (!pp_virt_addr_tbl)
3023                 return;
3024
3025         if (!p_pbl_virt)
3026                 goto out;
3027
3028         for (i = 0; i < page_cnt; i++) {
3029                 if (!pp_virt_addr_tbl[i])
3030                         break;
3031
3032                 dma_free_coherent(&cdev->pdev->dev,
3033                                   QED_CHAIN_PAGE_SIZE,
3034                                   pp_virt_addr_tbl[i],
3035                                   *(dma_addr_t *)p_pbl_virt);
3036
3037                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3038         }
3039
3040         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3041         dma_free_coherent(&cdev->pdev->dev,
3042                           pbl_size,
3043                           p_chain->pbl_sp.p_virt_table,
3044                           p_chain->pbl_sp.p_phys_table);
3045 out:
3046         vfree(p_chain->pbl.pp_virt_addr_tbl);
3047 }
3048
3049 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3050 {
3051         switch (p_chain->mode) {
3052         case QED_CHAIN_MODE_NEXT_PTR:
3053                 qed_chain_free_next_ptr(cdev, p_chain);
3054                 break;
3055         case QED_CHAIN_MODE_SINGLE:
3056                 qed_chain_free_single(cdev, p_chain);
3057                 break;
3058         case QED_CHAIN_MODE_PBL:
3059                 qed_chain_free_pbl(cdev, p_chain);
3060                 break;
3061         }
3062 }
3063
3064 static int
3065 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3066                              enum qed_chain_cnt_type cnt_type,
3067                              size_t elem_size, u32 page_cnt)
3068 {
3069         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3070
3071         /* The actual chain size can be larger than the maximal possible value
3072          * after rounding up the requested elements number to pages, and after
3073          * taking into acount the unusuable elements (next-ptr elements).
3074          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3075          * size/capacity fields are of a u32 type.
3076          */
3077         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3078              chain_size > ((u32)U16_MAX + 1)) ||
3079             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3080                 DP_NOTICE(cdev,
3081                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3082                           chain_size);
3083                 return -EINVAL;
3084         }
3085
3086         return 0;
3087 }
3088
3089 static int
3090 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3091 {
3092         void *p_virt = NULL, *p_virt_prev = NULL;
3093         dma_addr_t p_phys = 0;
3094         u32 i;
3095
3096         for (i = 0; i < p_chain->page_cnt; i++) {
3097                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3098                                             QED_CHAIN_PAGE_SIZE,
3099                                             &p_phys, GFP_KERNEL);
3100                 if (!p_virt)
3101                         return -ENOMEM;
3102
3103                 if (i == 0) {
3104                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3105                         qed_chain_reset(p_chain);
3106                 } else {
3107                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3108                                                      p_virt, p_phys);
3109                 }
3110
3111                 p_virt_prev = p_virt;
3112         }
3113         /* Last page's next element should point to the beginning of the
3114          * chain.
3115          */
3116         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3117                                      p_chain->p_virt_addr,
3118                                      p_chain->p_phys_addr);
3119
3120         return 0;
3121 }
3122
3123 static int
3124 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3125 {
3126         dma_addr_t p_phys = 0;
3127         void *p_virt = NULL;
3128
3129         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3130                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3131         if (!p_virt)
3132                 return -ENOMEM;
3133
3134         qed_chain_init_mem(p_chain, p_virt, p_phys);
3135         qed_chain_reset(p_chain);
3136
3137         return 0;
3138 }
3139
3140 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3141 {
3142         u32 page_cnt = p_chain->page_cnt, size, i;
3143         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3144         void **pp_virt_addr_tbl = NULL;
3145         u8 *p_pbl_virt = NULL;
3146         void *p_virt = NULL;
3147
3148         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3149         pp_virt_addr_tbl = vzalloc(size);
3150         if (!pp_virt_addr_tbl)
3151                 return -ENOMEM;
3152
3153         /* The allocation of the PBL table is done with its full size, since it
3154          * is expected to be successive.
3155          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3156          * failure, since pp_virt_addr_tbl was previously allocated, and it
3157          * should be saved to allow its freeing during the error flow.
3158          */
3159         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3160         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3161                                         size, &p_pbl_phys, GFP_KERNEL);
3162         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3163                                pp_virt_addr_tbl);
3164         if (!p_pbl_virt)
3165                 return -ENOMEM;
3166
3167         for (i = 0; i < page_cnt; i++) {
3168                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3169                                             QED_CHAIN_PAGE_SIZE,
3170                                             &p_phys, GFP_KERNEL);
3171                 if (!p_virt)
3172                         return -ENOMEM;
3173
3174                 if (i == 0) {
3175                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3176                         qed_chain_reset(p_chain);
3177                 }
3178
3179                 /* Fill the PBL table with the physical address of the page */
3180                 *(dma_addr_t *)p_pbl_virt = p_phys;
3181                 /* Keep the virtual address of the page */
3182                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3183
3184                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3185         }
3186
3187         return 0;
3188 }
3189
3190 int qed_chain_alloc(struct qed_dev *cdev,
3191                     enum qed_chain_use_mode intended_use,
3192                     enum qed_chain_mode mode,
3193                     enum qed_chain_cnt_type cnt_type,
3194                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
3195 {
3196         u32 page_cnt;
3197         int rc = 0;
3198
3199         if (mode == QED_CHAIN_MODE_SINGLE)
3200                 page_cnt = 1;
3201         else
3202                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3203
3204         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3205         if (rc) {
3206                 DP_NOTICE(cdev,
3207                           "Cannot allocate a chain with the given arguments:\n");
3208                 DP_NOTICE(cdev,
3209                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3210                           intended_use, mode, cnt_type, num_elems, elem_size);
3211                 return rc;
3212         }
3213
3214         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3215                               mode, cnt_type);
3216
3217         switch (mode) {
3218         case QED_CHAIN_MODE_NEXT_PTR:
3219                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3220                 break;
3221         case QED_CHAIN_MODE_SINGLE:
3222                 rc = qed_chain_alloc_single(cdev, p_chain);
3223                 break;
3224         case QED_CHAIN_MODE_PBL:
3225                 rc = qed_chain_alloc_pbl(cdev, p_chain);
3226                 break;
3227         }
3228         if (rc)
3229                 goto nomem;
3230
3231         return 0;
3232
3233 nomem:
3234         qed_chain_free(cdev, p_chain);
3235         return rc;
3236 }
3237
3238 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3239 {
3240         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3241                 u16 min, max;
3242
3243                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3244                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3245                 DP_NOTICE(p_hwfn,
3246                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3247                           src_id, min, max);
3248
3249                 return -EINVAL;
3250         }
3251
3252         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3253
3254         return 0;
3255 }
3256
3257 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3258 {
3259         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3260                 u8 min, max;
3261
3262                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3263                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3264                 DP_NOTICE(p_hwfn,
3265                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3266                           src_id, min, max);
3267
3268                 return -EINVAL;
3269         }
3270
3271         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3272
3273         return 0;
3274 }
3275
3276 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3277 {
3278         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3279                 u8 min, max;
3280
3281                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3282                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3283                 DP_NOTICE(p_hwfn,
3284                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3285                           src_id, min, max);
3286
3287                 return -EINVAL;
3288         }
3289
3290         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3291
3292         return 0;
3293 }
3294
3295 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3296                                   u8 *p_filter)
3297 {
3298         *p_high = p_filter[1] | (p_filter[0] << 8);
3299         *p_low = p_filter[5] | (p_filter[4] << 8) |
3300                  (p_filter[3] << 16) | (p_filter[2] << 24);
3301 }
3302
3303 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3304                            struct qed_ptt *p_ptt, u8 *p_filter)
3305 {
3306         u32 high = 0, low = 0, en;
3307         int i;
3308
3309         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3310                 return 0;
3311
3312         qed_llh_mac_to_filter(&high, &low, p_filter);
3313
3314         /* Find a free entry and utilize it */
3315         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3316                 en = qed_rd(p_hwfn, p_ptt,
3317                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3318                 if (en)
3319                         continue;
3320                 qed_wr(p_hwfn, p_ptt,
3321                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3322                        2 * i * sizeof(u32), low);
3323                 qed_wr(p_hwfn, p_ptt,
3324                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3325                        (2 * i + 1) * sizeof(u32), high);
3326                 qed_wr(p_hwfn, p_ptt,
3327                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3328                 qed_wr(p_hwfn, p_ptt,
3329                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3330                        i * sizeof(u32), 0);
3331                 qed_wr(p_hwfn, p_ptt,
3332                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3333                 break;
3334         }
3335         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3336                 DP_NOTICE(p_hwfn,
3337                           "Failed to find an empty LLH filter to utilize\n");
3338                 return -EINVAL;
3339         }
3340
3341         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3342                    "mac: %pM is added at %d\n",
3343                    p_filter, i);
3344
3345         return 0;
3346 }
3347
3348 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3349                                struct qed_ptt *p_ptt, u8 *p_filter)
3350 {
3351         u32 high = 0, low = 0;
3352         int i;
3353
3354         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3355                 return;
3356
3357         qed_llh_mac_to_filter(&high, &low, p_filter);
3358
3359         /* Find the entry and clean it */
3360         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3361                 if (qed_rd(p_hwfn, p_ptt,
3362                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3363                            2 * i * sizeof(u32)) != low)
3364                         continue;
3365                 if (qed_rd(p_hwfn, p_ptt,
3366                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3367                            (2 * i + 1) * sizeof(u32)) != high)
3368                         continue;
3369
3370                 qed_wr(p_hwfn, p_ptt,
3371                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3372                 qed_wr(p_hwfn, p_ptt,
3373                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3374                 qed_wr(p_hwfn, p_ptt,
3375                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3376                        (2 * i + 1) * sizeof(u32), 0);
3377
3378                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3379                            "mac: %pM is removed from %d\n",
3380                            p_filter, i);
3381                 break;
3382         }
3383         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3384                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3385 }
3386
3387 int
3388 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3389                             struct qed_ptt *p_ptt,
3390                             u16 source_port_or_eth_type,
3391                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3392 {
3393         u32 high = 0, low = 0, en;
3394         int i;
3395
3396         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3397                 return 0;
3398
3399         switch (type) {
3400         case QED_LLH_FILTER_ETHERTYPE:
3401                 high = source_port_or_eth_type;
3402                 break;
3403         case QED_LLH_FILTER_TCP_SRC_PORT:
3404         case QED_LLH_FILTER_UDP_SRC_PORT:
3405                 low = source_port_or_eth_type << 16;
3406                 break;
3407         case QED_LLH_FILTER_TCP_DEST_PORT:
3408         case QED_LLH_FILTER_UDP_DEST_PORT:
3409                 low = dest_port;
3410                 break;
3411         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3412         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3413                 low = (source_port_or_eth_type << 16) | dest_port;
3414                 break;
3415         default:
3416                 DP_NOTICE(p_hwfn,
3417                           "Non valid LLH protocol filter type %d\n", type);
3418                 return -EINVAL;
3419         }
3420         /* Find a free entry and utilize it */
3421         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3422                 en = qed_rd(p_hwfn, p_ptt,
3423                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3424                 if (en)
3425                         continue;
3426                 qed_wr(p_hwfn, p_ptt,
3427                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3428                        2 * i * sizeof(u32), low);
3429                 qed_wr(p_hwfn, p_ptt,
3430                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3431                        (2 * i + 1) * sizeof(u32), high);
3432                 qed_wr(p_hwfn, p_ptt,
3433                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3434                 qed_wr(p_hwfn, p_ptt,
3435                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3436                        i * sizeof(u32), 1 << type);
3437                 qed_wr(p_hwfn, p_ptt,
3438                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3439                 break;
3440         }
3441         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3442                 DP_NOTICE(p_hwfn,
3443                           "Failed to find an empty LLH filter to utilize\n");
3444                 return -EINVAL;
3445         }
3446         switch (type) {
3447         case QED_LLH_FILTER_ETHERTYPE:
3448                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3449                            "ETH type %x is added at %d\n",
3450                            source_port_or_eth_type, i);
3451                 break;
3452         case QED_LLH_FILTER_TCP_SRC_PORT:
3453                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3454                            "TCP src port %x is added at %d\n",
3455                            source_port_or_eth_type, i);
3456                 break;
3457         case QED_LLH_FILTER_UDP_SRC_PORT:
3458                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3459                            "UDP src port %x is added at %d\n",
3460                            source_port_or_eth_type, i);
3461                 break;
3462         case QED_LLH_FILTER_TCP_DEST_PORT:
3463                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3464                            "TCP dst port %x is added at %d\n", dest_port, i);
3465                 break;
3466         case QED_LLH_FILTER_UDP_DEST_PORT:
3467                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3468                            "UDP dst port %x is added at %d\n", dest_port, i);
3469                 break;
3470         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3471                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3472                            "TCP src/dst ports %x/%x are added at %d\n",
3473                            source_port_or_eth_type, dest_port, i);
3474                 break;
3475         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3476                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3477                            "UDP src/dst ports %x/%x are added at %d\n",
3478                            source_port_or_eth_type, dest_port, i);
3479                 break;
3480         }
3481         return 0;
3482 }
3483
3484 void
3485 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3486                                struct qed_ptt *p_ptt,
3487                                u16 source_port_or_eth_type,
3488                                u16 dest_port,
3489                                enum qed_llh_port_filter_type_t type)
3490 {
3491         u32 high = 0, low = 0;
3492         int i;
3493
3494         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3495                 return;
3496
3497         switch (type) {
3498         case QED_LLH_FILTER_ETHERTYPE:
3499                 high = source_port_or_eth_type;
3500                 break;
3501         case QED_LLH_FILTER_TCP_SRC_PORT:
3502         case QED_LLH_FILTER_UDP_SRC_PORT:
3503                 low = source_port_or_eth_type << 16;
3504                 break;
3505         case QED_LLH_FILTER_TCP_DEST_PORT:
3506         case QED_LLH_FILTER_UDP_DEST_PORT:
3507                 low = dest_port;
3508                 break;
3509         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3510         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3511                 low = (source_port_or_eth_type << 16) | dest_port;
3512                 break;
3513         default:
3514                 DP_NOTICE(p_hwfn,
3515                           "Non valid LLH protocol filter type %d\n", type);
3516                 return;
3517         }
3518
3519         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3520                 if (!qed_rd(p_hwfn, p_ptt,
3521                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3522                         continue;
3523                 if (!qed_rd(p_hwfn, p_ptt,
3524                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3525                         continue;
3526                 if (!(qed_rd(p_hwfn, p_ptt,
3527                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3528                              i * sizeof(u32)) & BIT(type)))
3529                         continue;
3530                 if (qed_rd(p_hwfn, p_ptt,
3531                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3532                            2 * i * sizeof(u32)) != low)
3533                         continue;
3534                 if (qed_rd(p_hwfn, p_ptt,
3535                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3536                            (2 * i + 1) * sizeof(u32)) != high)
3537                         continue;
3538
3539                 qed_wr(p_hwfn, p_ptt,
3540                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3541                 qed_wr(p_hwfn, p_ptt,
3542                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3543                 qed_wr(p_hwfn, p_ptt,
3544                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3545                        i * sizeof(u32), 0);
3546                 qed_wr(p_hwfn, p_ptt,
3547                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3548                 qed_wr(p_hwfn, p_ptt,
3549                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3550                        (2 * i + 1) * sizeof(u32), 0);
3551                 break;
3552         }
3553
3554         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3555                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3556 }
3557
3558 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3559                             u32 hw_addr, void *p_eth_qzone,
3560                             size_t eth_qzone_size, u8 timeset)
3561 {
3562         struct coalescing_timeset *p_coal_timeset;
3563
3564         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3565                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3566                 return -EINVAL;
3567         }
3568
3569         p_coal_timeset = p_eth_qzone;
3570         memset(p_coal_timeset, 0, eth_qzone_size);
3571         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3572         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3573         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3574
3575         return 0;
3576 }
3577
3578 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3579                          u16 coalesce, u8 qid, u16 sb_id)
3580 {
3581         struct ustorm_eth_queue_zone eth_qzone;
3582         u8 timeset, timer_res;
3583         u16 fw_qid = 0;
3584         u32 address;
3585         int rc;
3586
3587         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3588         if (coalesce <= 0x7F) {
3589                 timer_res = 0;
3590         } else if (coalesce <= 0xFF) {
3591                 timer_res = 1;
3592         } else if (coalesce <= 0x1FF) {
3593                 timer_res = 2;
3594         } else {
3595                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3596                 return -EINVAL;
3597         }
3598         timeset = (u8)(coalesce >> timer_res);
3599
3600         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3601         if (rc)
3602                 return rc;
3603
3604         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3605         if (rc)
3606                 goto out;
3607
3608         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3609
3610         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3611                               sizeof(struct ustorm_eth_queue_zone), timeset);
3612         if (rc)
3613                 goto out;
3614
3615         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3616 out:
3617         return rc;
3618 }
3619
3620 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3621                          u16 coalesce, u8 qid, u16 sb_id)
3622 {
3623         struct xstorm_eth_queue_zone eth_qzone;
3624         u8 timeset, timer_res;
3625         u16 fw_qid = 0;
3626         u32 address;
3627         int rc;
3628
3629         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3630         if (coalesce <= 0x7F) {
3631                 timer_res = 0;
3632         } else if (coalesce <= 0xFF) {
3633                 timer_res = 1;
3634         } else if (coalesce <= 0x1FF) {
3635                 timer_res = 2;
3636         } else {
3637                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3638                 return -EINVAL;
3639         }
3640         timeset = (u8)(coalesce >> timer_res);
3641
3642         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3643         if (rc)
3644                 return rc;
3645
3646         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3647         if (rc)
3648                 goto out;
3649
3650         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3651
3652         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3653                               sizeof(struct xstorm_eth_queue_zone), timeset);
3654         if (rc)
3655                 goto out;
3656
3657         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3658 out:
3659         return rc;
3660 }
3661
3662 /* Calculate final WFQ values for all vports and configure them.
3663  * After this configuration each vport will have
3664  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3665  */
3666 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3667                                              struct qed_ptt *p_ptt,
3668                                              u32 min_pf_rate)
3669 {
3670         struct init_qm_vport_params *vport_params;
3671         int i;
3672
3673         vport_params = p_hwfn->qm_info.qm_vport_params;
3674
3675         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3676                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3677
3678                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3679                                                 min_pf_rate;
3680                 qed_init_vport_wfq(p_hwfn, p_ptt,
3681                                    vport_params[i].first_tx_pq_id,
3682                                    vport_params[i].vport_wfq);
3683         }
3684 }
3685
3686 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3687                                        u32 min_pf_rate)
3688
3689 {
3690         int i;
3691
3692         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3693                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3694 }
3695
3696 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3697                                            struct qed_ptt *p_ptt,
3698                                            u32 min_pf_rate)
3699 {
3700         struct init_qm_vport_params *vport_params;
3701         int i;
3702
3703         vport_params = p_hwfn->qm_info.qm_vport_params;
3704
3705         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3706                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3707                 qed_init_vport_wfq(p_hwfn, p_ptt,
3708                                    vport_params[i].first_tx_pq_id,
3709                                    vport_params[i].vport_wfq);
3710         }
3711 }
3712
3713 /* This function performs several validations for WFQ
3714  * configuration and required min rate for a given vport
3715  * 1. req_rate must be greater than one percent of min_pf_rate.
3716  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3717  *    rates to get less than one percent of min_pf_rate.
3718  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3719  */
3720 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3721                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
3722 {
3723         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3724         int non_requested_count = 0, req_count = 0, i, num_vports;
3725
3726         num_vports = p_hwfn->qm_info.num_vports;
3727
3728         /* Accounting for the vports which are configured for WFQ explicitly */
3729         for (i = 0; i < num_vports; i++) {
3730                 u32 tmp_speed;
3731
3732                 if ((i != vport_id) &&
3733                     p_hwfn->qm_info.wfq_data[i].configured) {
3734                         req_count++;
3735                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3736                         total_req_min_rate += tmp_speed;
3737                 }
3738         }
3739
3740         /* Include current vport data as well */
3741         req_count++;
3742         total_req_min_rate += req_rate;
3743         non_requested_count = num_vports - req_count;
3744
3745         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3746                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3747                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3748                            vport_id, req_rate, min_pf_rate);
3749                 return -EINVAL;
3750         }
3751
3752         if (num_vports > QED_WFQ_UNIT) {
3753                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3754                            "Number of vports is greater than %d\n",
3755                            QED_WFQ_UNIT);
3756                 return -EINVAL;
3757         }
3758
3759         if (total_req_min_rate > min_pf_rate) {
3760                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3761                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3762                            total_req_min_rate, min_pf_rate);
3763                 return -EINVAL;
3764         }
3765
3766         total_left_rate = min_pf_rate - total_req_min_rate;
3767
3768         left_rate_per_vp = total_left_rate / non_requested_count;
3769         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
3770                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3771                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3772                            left_rate_per_vp, min_pf_rate);
3773                 return -EINVAL;
3774         }
3775
3776         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3777         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3778
3779         for (i = 0; i < num_vports; i++) {
3780                 if (p_hwfn->qm_info.wfq_data[i].configured)
3781                         continue;
3782
3783                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3784         }
3785
3786         return 0;
3787 }
3788
3789 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3790                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3791 {
3792         struct qed_mcp_link_state *p_link;
3793         int rc = 0;
3794
3795         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3796
3797         if (!p_link->min_pf_rate) {
3798                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3799                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3800                 return rc;
3801         }
3802
3803         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3804
3805         if (!rc)
3806                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3807                                                  p_link->min_pf_rate);
3808         else
3809                 DP_NOTICE(p_hwfn,
3810                           "Validation failed while configuring min rate\n");
3811
3812         return rc;
3813 }
3814
3815 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3816                                                  struct qed_ptt *p_ptt,
3817                                                  u32 min_pf_rate)
3818 {
3819         bool use_wfq = false;
3820         int rc = 0;
3821         u16 i;
3822
3823         /* Validate all pre configured vports for wfq */
3824         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3825                 u32 rate;
3826
3827                 if (!p_hwfn->qm_info.wfq_data[i].configured)
3828                         continue;
3829
3830                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3831                 use_wfq = true;
3832
3833                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3834                 if (rc) {
3835                         DP_NOTICE(p_hwfn,
3836                                   "WFQ validation failed while configuring min rate\n");
3837                         break;
3838                 }
3839         }
3840
3841         if (!rc && use_wfq)
3842                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3843         else
3844                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3845
3846         return rc;
3847 }
3848
3849 /* Main API for qed clients to configure vport min rate.
3850  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3851  * rate - Speed in Mbps needs to be assigned to a given vport.
3852  */
3853 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3854 {
3855         int i, rc = -EINVAL;
3856
3857         /* Currently not supported; Might change in future */
3858         if (cdev->num_hwfns > 1) {
3859                 DP_NOTICE(cdev,
3860                           "WFQ configuration is not supported for this device\n");
3861                 return rc;
3862         }
3863
3864         for_each_hwfn(cdev, i) {
3865                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3866                 struct qed_ptt *p_ptt;
3867
3868                 p_ptt = qed_ptt_acquire(p_hwfn);
3869                 if (!p_ptt)
3870                         return -EBUSY;
3871
3872                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3873
3874                 if (rc) {
3875                         qed_ptt_release(p_hwfn, p_ptt);
3876                         return rc;
3877                 }
3878
3879                 qed_ptt_release(p_hwfn, p_ptt);
3880         }
3881
3882         return rc;
3883 }
3884
3885 /* API to configure WFQ from mcp link change */
3886 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3887                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
3888 {
3889         int i;
3890
3891         if (cdev->num_hwfns > 1) {
3892                 DP_VERBOSE(cdev,
3893                            NETIF_MSG_LINK,
3894                            "WFQ configuration is not supported for this device\n");
3895                 return;
3896         }
3897
3898         for_each_hwfn(cdev, i) {
3899                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3900
3901                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
3902                                                       min_pf_rate);
3903         }
3904 }
3905
3906 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3907                                      struct qed_ptt *p_ptt,
3908                                      struct qed_mcp_link_state *p_link,
3909                                      u8 max_bw)
3910 {
3911         int rc = 0;
3912
3913         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3914
3915         if (!p_link->line_speed && (max_bw != 100))
3916                 return rc;
3917
3918         p_link->speed = (p_link->line_speed * max_bw) / 100;
3919         p_hwfn->qm_info.pf_rl = p_link->speed;
3920
3921         /* Since the limiter also affects Tx-switched traffic, we don't want it
3922          * to limit such traffic in case there's no actual limit.
3923          * In that case, set limit to imaginary high boundary.
3924          */
3925         if (max_bw == 100)
3926                 p_hwfn->qm_info.pf_rl = 100000;
3927
3928         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3929                             p_hwfn->qm_info.pf_rl);
3930
3931         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3932                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3933                    p_link->speed);
3934
3935         return rc;
3936 }
3937
3938 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3939 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3940 {
3941         int i, rc = -EINVAL;
3942
3943         if (max_bw < 1 || max_bw > 100) {
3944                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3945                 return rc;
3946         }
3947
3948         for_each_hwfn(cdev, i) {
3949                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3950                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3951                 struct qed_mcp_link_state *p_link;
3952                 struct qed_ptt *p_ptt;
3953
3954                 p_link = &p_lead->mcp_info->link_output;
3955
3956                 p_ptt = qed_ptt_acquire(p_hwfn);
3957                 if (!p_ptt)
3958                         return -EBUSY;
3959
3960                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3961                                                       p_link, max_bw);
3962
3963                 qed_ptt_release(p_hwfn, p_ptt);
3964
3965                 if (rc)
3966                         break;
3967         }
3968
3969         return rc;
3970 }
3971
3972 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3973                                      struct qed_ptt *p_ptt,
3974                                      struct qed_mcp_link_state *p_link,
3975                                      u8 min_bw)
3976 {
3977         int rc = 0;
3978
3979         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3980         p_hwfn->qm_info.pf_wfq = min_bw;
3981
3982         if (!p_link->line_speed)
3983                 return rc;
3984
3985         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3986
3987         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3988
3989         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3990                    "Configured MIN bandwidth to be %d Mb/sec\n",
3991                    p_link->min_pf_rate);
3992
3993         return rc;
3994 }
3995
3996 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3997 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
3998 {
3999         int i, rc = -EINVAL;
4000
4001         if (min_bw < 1 || min_bw > 100) {
4002                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4003                 return rc;
4004         }
4005
4006         for_each_hwfn(cdev, i) {
4007                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4008                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4009                 struct qed_mcp_link_state *p_link;
4010                 struct qed_ptt *p_ptt;
4011
4012                 p_link = &p_lead->mcp_info->link_output;
4013
4014                 p_ptt = qed_ptt_acquire(p_hwfn);
4015                 if (!p_ptt)
4016                         return -EBUSY;
4017
4018                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4019                                                       p_link, min_bw);
4020                 if (rc) {
4021                         qed_ptt_release(p_hwfn, p_ptt);
4022                         return rc;
4023                 }
4024
4025                 if (p_link->min_pf_rate) {
4026                         u32 min_rate = p_link->min_pf_rate;
4027
4028                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4029                                                                    p_ptt,
4030                                                                    min_rate);
4031                 }
4032
4033                 qed_ptt_release(p_hwfn, p_ptt);
4034         }
4035
4036         return rc;
4037 }
4038
4039 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4040 {
4041         struct qed_mcp_link_state *p_link;
4042
4043         p_link = &p_hwfn->mcp_info->link_output;
4044
4045         if (p_link->min_pf_rate)
4046                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4047                                                p_link->min_pf_rate);
4048
4049         memset(p_hwfn->qm_info.wfq_data, 0,
4050                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4051 }
4052
4053 int qed_device_num_engines(struct qed_dev *cdev)
4054 {
4055         return QED_IS_BB(cdev) ? 2 : 1;
4056 }