drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mutex.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/qed/qed_chain.h>
  23 #include <linux/qed/qed_if.h>
  24 #include "qed.h"
  25 #include "qed_cxt.h"
  26 #include "qed_dcbx.h"
  27 #include "qed_dev_api.h"
  28 #include "qed_hsi.h"
  29 #include "qed_hw.h"
  30 #include "qed_init_ops.h"
  31 #include "qed_int.h"
  32 #include "qed_mcp.h"
  33 #include "qed_reg_addr.h"
  34 #include "qed_sp.h"
  35 #include "qed_sriov.h"
  36 #include "qed_vf.h"
  37
  38 static DEFINE_SPINLOCK(qm_lock);
  39
  40 /* API common to all protocols */
  41 enum BAR_ID {
  42         BAR_ID_0,       /* used for GRC */
  43         BAR_ID_1        /* Used for doorbells */
  44 };
  45
  46 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
  47 {
  48         u32 bar_reg = (bar_id == BAR_ID_0 ?
  49                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  50         u32 val;
  51
  52         if (IS_VF(p_hwfn->cdev))
  53                 return 1 << 17;
  54
  55         val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  56         if (val)
  57                 return 1 << (val + 15);
  58
  59         /* Old MFW initialized above registered only conditionally */
  60         if (p_hwfn->cdev->num_hwfns > 1) {
  61                 DP_INFO(p_hwfn,
  62                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  63                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  64         } else {
  65                 DP_INFO(p_hwfn,
  66                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  67                         return 512 * 1024;
  68         }
  69 }
  70
  71 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  72 {
  73         u32 i;
  74
  75         cdev->dp_level = dp_level;
  76         cdev->dp_module = dp_module;
  77         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  78                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  79
  80                 p_hwfn->dp_level = dp_level;
  81                 p_hwfn->dp_module = dp_module;
  82         }
  83 }
  84
  85 void qed_init_struct(struct qed_dev *cdev)
  86 {
  87         u8 i;
  88
  89         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  90                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  91
  92                 p_hwfn->cdev = cdev;
  93                 p_hwfn->my_id = i;
  94                 p_hwfn->b_active = false;
  95
  96                 mutex_init(&p_hwfn->dmae_info.mutex);
  97         }
  98
  99         /* hwfn 0 is always active */
 100         cdev->hwfns[0].b_active = true;
 101
 102         /* set the default cache alignment to 128 */
 103         cdev->cache_shift = 7;
 104 }
 105
 106 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 107 {
 108         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 109
 110         kfree(qm_info->qm_pq_params);
 111         qm_info->qm_pq_params = NULL;
 112         kfree(qm_info->qm_vport_params);
 113         qm_info->qm_vport_params = NULL;
 114         kfree(qm_info->qm_port_params);
 115         qm_info->qm_port_params = NULL;
 116         kfree(qm_info->wfq_data);
 117         qm_info->wfq_data = NULL;
 118 }
 119
 120 void qed_resc_free(struct qed_dev *cdev)
 121 {
 122         int i;
 123
 124         if (IS_VF(cdev))
 125                 return;
 126
 127         kfree(cdev->fw_data);
 128         cdev->fw_data = NULL;
 129
 130         kfree(cdev->reset_stats);
 131
 132         for_each_hwfn(cdev, i) {
 133                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 134
 135                 kfree(p_hwfn->p_tx_cids);
 136                 p_hwfn->p_tx_cids = NULL;
 137                 kfree(p_hwfn->p_rx_cids);
 138                 p_hwfn->p_rx_cids = NULL;
 139         }
 140
 141         for_each_hwfn(cdev, i) {
 142                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 143
 144                 qed_cxt_mngr_free(p_hwfn);
 145                 qed_qm_info_free(p_hwfn);
 146                 qed_spq_free(p_hwfn);
 147                 qed_eq_free(p_hwfn, p_hwfn->p_eq);
 148                 qed_consq_free(p_hwfn, p_hwfn->p_consq);
 149                 qed_int_free(p_hwfn);
 150                 qed_iov_free(p_hwfn);
 151                 qed_dmae_info_free(p_hwfn);
 152                 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 153         }
 154 }
 155
 156 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
 157 {
 158         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
 159         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 160         struct init_qm_port_params *p_qm_port;
 161         bool init_rdma_offload_pq = false;
 162         bool init_pure_ack_pq = false;
 163         bool init_ooo_pq = false;
 164         u16 num_pqs, multi_cos_tcs = 1;
 165         u8 pf_wfq = qm_info->pf_wfq;
 166         u32 pf_rl = qm_info->pf_rl;
 167         u16 num_pf_rls = 0;
 168         u16 num_vfs = 0;
 169
 170 #ifdef CONFIG_QED_SRIOV
 171         if (p_hwfn->cdev->p_iov_info)
 172                 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
 173 #endif
 174         memset(qm_info, 0, sizeof(*qm_info));
 175
 176         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 177         num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
 178
 179         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 180                 num_pqs++;      /* for RoCE queue */
 181                 init_rdma_offload_pq = true;
 182                 /* we subtract num_vfs because each require a rate limiter,
 183                  * and one default rate limiter
 184                  */
 185                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
 186                         num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
 187
 188                 num_pqs += num_pf_rls;
 189                 qm_info->num_pf_rls = (u8) num_pf_rls;
 190         }
 191
 192         if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 193                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 194                 init_pure_ack_pq = true;
 195                 init_ooo_pq = true;
 196         }
 197
 198         /* Sanity checking that setup requires legal number of resources */
 199         if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
 200                 DP_ERR(p_hwfn,
 201                        "Need too many Physical queues - 0x%04x when only %04x are available\n",
 202                        num_pqs, RESC_NUM(p_hwfn, QED_PQ));
 203                 return -EINVAL;
 204         }
 205
 206         /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
 207          */
 208         qm_info->qm_pq_params = kcalloc(num_pqs,
 209                                         sizeof(struct init_qm_pq_params),
 210                                         b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 211         if (!qm_info->qm_pq_params)
 212                 goto alloc_err;
 213
 214         qm_info->qm_vport_params = kcalloc(num_vports,
 215                                            sizeof(struct init_qm_vport_params),
 216                                            b_sleepable ? GFP_KERNEL
 217                                                        : GFP_ATOMIC);
 218         if (!qm_info->qm_vport_params)
 219                 goto alloc_err;
 220
 221         qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
 222                                           sizeof(struct init_qm_port_params),
 223                                           b_sleepable ? GFP_KERNEL
 224                                                       : GFP_ATOMIC);
 225         if (!qm_info->qm_port_params)
 226                 goto alloc_err;
 227
 228         qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
 229                                     b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 230         if (!qm_info->wfq_data)
 231                 goto alloc_err;
 232
 233         vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
 234
 235         /* First init rate limited queues */
 236         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 237                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 238                 qm_info->qm_pq_params[curr_queue].tc_id =
 239                     p_hwfn->hw_info.non_offload_tc;
 240                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 241                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 242         }
 243
 244         /* First init per-TC PQs */
 245         for (i = 0; i < multi_cos_tcs; i++) {
 246                 struct init_qm_pq_params *params =
 247                     &qm_info->qm_pq_params[curr_queue++];
 248
 249                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
 250                     p_hwfn->hw_info.personality == QED_PCI_ETH) {
 251                         params->vport_id = vport_id;
 252                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 253                         params->wrr_group = 1;
 254                 } else {
 255                         params->vport_id = vport_id;
 256                         params->tc_id = p_hwfn->hw_info.offload_tc;
 257                         params->wrr_group = 1;
 258                 }
 259         }
 260
 261         /* Then init pure-LB PQ */
 262         qm_info->pure_lb_pq = curr_queue;
 263         qm_info->qm_pq_params[curr_queue].vport_id =
 264             (u8) RESC_START(p_hwfn, QED_VPORT);
 265         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 266         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 267         curr_queue++;
 268
 269         qm_info->offload_pq = 0;
 270         if (init_rdma_offload_pq) {
 271                 qm_info->offload_pq = curr_queue;
 272                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 273                 qm_info->qm_pq_params[curr_queue].tc_id =
 274                     p_hwfn->hw_info.offload_tc;
 275                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 276                 curr_queue++;
 277         }
 278
 279         if (init_pure_ack_pq) {
 280                 qm_info->pure_ack_pq = curr_queue;
 281                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 282                 qm_info->qm_pq_params[curr_queue].tc_id =
 283                     p_hwfn->hw_info.offload_tc;
 284                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 285                 curr_queue++;
 286         }
 287
 288         if (init_ooo_pq) {
 289                 qm_info->ooo_pq = curr_queue;
 290                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 291                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 292                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 293                 curr_queue++;
 294         }
 295
 296         /* Then init per-VF PQs */
 297         vf_offset = curr_queue;
 298         for (i = 0; i < num_vfs; i++) {
 299                 /* First vport is used by the PF */
 300                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 301                 qm_info->qm_pq_params[curr_queue].tc_id =
 302                     p_hwfn->hw_info.non_offload_tc;
 303                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 304                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 305                 curr_queue++;
 306         }
 307
 308         qm_info->vf_queues_offset = vf_offset;
 309         qm_info->num_pqs = num_pqs;
 310         qm_info->num_vports = num_vports;
 311
 312         /* Initialize qm port parameters */
 313         num_ports = p_hwfn->cdev->num_ports_in_engines;
 314         for (i = 0; i < num_ports; i++) {
 315                 p_qm_port = &qm_info->qm_port_params[i];
 316                 p_qm_port->active = 1;
 317                 if (num_ports == 4)
 318                         p_qm_port->active_phys_tcs = 0x7;
 319                 else
 320                         p_qm_port->active_phys_tcs = 0x9f;
 321                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 322                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 323         }
 324
 325         qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 326
 327         qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
 328
 329         qm_info->num_vf_pqs = num_vfs;
 330         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 331
 332         for (i = 0; i < qm_info->num_vports; i++)
 333                 qm_info->qm_vport_params[i].vport_wfq = 1;
 334
 335         qm_info->vport_rl_en = 1;
 336         qm_info->vport_wfq_en = 1;
 337         qm_info->pf_rl = pf_rl;
 338         qm_info->pf_wfq = pf_wfq;
 339
 340         return 0;
 341
 342 alloc_err:
 343         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 344         qed_qm_info_free(p_hwfn);
 345         return -ENOMEM;
 346 }
 347
 348 /* This function reconfigures the QM pf on the fly.
 349  * For this purpose we:
 350  * 1. reconfigure the QM database
 351  * 2. set new values to runtime arrat
 352  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 353  * 4. activate init tool in QM_PF stage
 354  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 355  */
 356 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 357 {
 358         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 359         bool b_rc;
 360         int rc;
 361
 362         /* qm_info is allocated in qed_init_qm_info() which is already called
 363          * from qed_resc_alloc() or previous call of qed_qm_reconf().
 364          * The allocated size may change each init, so we free it before next
 365          * allocation.
 366          */
 367         qed_qm_info_free(p_hwfn);
 368
 369         /* initialize qed's qm data structure */
 370         rc = qed_init_qm_info(p_hwfn, false);
 371         if (rc)
 372                 return rc;
 373
 374         /* stop PF's qm queues */
 375         spin_lock_bh(&qm_lock);
 376         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 377                                     qm_info->start_pq, qm_info->num_pqs);
 378         spin_unlock_bh(&qm_lock);
 379         if (!b_rc)
 380                 return -EINVAL;
 381
 382         /* clear the QM_PF runtime phase leftovers from previous init */
 383         qed_init_clear_rt_data(p_hwfn);
 384
 385         /* prepare QM portion of runtime array */
 386         qed_qm_init_pf(p_hwfn);
 387
 388         /* activate init tool on runtime array */
 389         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 390                           p_hwfn->hw_info.hw_mode);
 391         if (rc)
 392                 return rc;
 393
 394         /* start PF's qm queues */
 395         spin_lock_bh(&qm_lock);
 396         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 397                                     qm_info->start_pq, qm_info->num_pqs);
 398         spin_unlock_bh(&qm_lock);
 399         if (!b_rc)
 400                 return -EINVAL;
 401
 402         return 0;
 403 }
 404
 405 int qed_resc_alloc(struct qed_dev *cdev)
 406 {
 407         struct qed_consq *p_consq;
 408         struct qed_eq *p_eq;
 409         int i, rc = 0;
 410
 411         if (IS_VF(cdev))
 412                 return rc;
 413
 414         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 415         if (!cdev->fw_data)
 416                 return -ENOMEM;
 417
 418         /* Allocate Memory for the Queue->CID mapping */
 419         for_each_hwfn(cdev, i) {
 420                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 421                 int tx_size = sizeof(struct qed_hw_cid_data) *
 422                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 423                 int rx_size = sizeof(struct qed_hw_cid_data) *
 424                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 425
 426                 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
 427                 if (!p_hwfn->p_tx_cids) {
 428                         DP_NOTICE(p_hwfn,
 429                                   "Failed to allocate memory for Tx Cids\n");
 430                         goto alloc_no_mem;
 431                 }
 432
 433                 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
 434                 if (!p_hwfn->p_rx_cids) {
 435                         DP_NOTICE(p_hwfn,
 436                                   "Failed to allocate memory for Rx Cids\n");
 437                         goto alloc_no_mem;
 438                 }
 439         }
 440
 441         for_each_hwfn(cdev, i) {
 442                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 443                 u32 n_eqes, num_cons;
 444
 445                 /* First allocate the context manager structure */
 446                 rc = qed_cxt_mngr_alloc(p_hwfn);
 447                 if (rc)
 448                         goto alloc_err;
 449
 450                 /* Set the HW cid/tid numbers (in the contest manager)
 451                  * Must be done prior to any further computations.
 452                  */
 453                 rc = qed_cxt_set_pf_params(p_hwfn);
 454                 if (rc)
 455                         goto alloc_err;
 456
 457                 /* Prepare and process QM requirements */
 458                 rc = qed_init_qm_info(p_hwfn, true);
 459                 if (rc)
 460                         goto alloc_err;
 461
 462                 /* Compute the ILT client partition */
 463                 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
 464                 if (rc)
 465                         goto alloc_err;
 466
 467                 /* CID map / ILT shadow table / T2
 468                  * The talbes sizes are determined by the computations above
 469                  */
 470                 rc = qed_cxt_tables_alloc(p_hwfn);
 471                 if (rc)
 472                         goto alloc_err;
 473
 474                 /* SPQ, must follow ILT because initializes SPQ context */
 475                 rc = qed_spq_alloc(p_hwfn);
 476                 if (rc)
 477                         goto alloc_err;
 478
 479                 /* SP status block allocation */
 480                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 481                                                          RESERVED_PTT_DPC);
 482
 483                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 484                 if (rc)
 485                         goto alloc_err;
 486
 487                 rc = qed_iov_alloc(p_hwfn);
 488                 if (rc)
 489                         goto alloc_err;
 490
 491                 /* EQ */
 492                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 493                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 494                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 495                                                                PROTOCOLID_ROCE,
 496                                                                0) * 2;
 497                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 498                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 499                         num_cons =
 500                             qed_cxt_get_proto_cid_count(p_hwfn,
 501                                                         PROTOCOLID_ISCSI, 0);
 502                         n_eqes += 2 * num_cons;
 503                 }
 504
 505                 if (n_eqes > 0xFFFF) {
 506                         DP_ERR(p_hwfn,
 507                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 508                                n_eqes, 0xFFFF);
 509                         rc = -EINVAL;
 510                         goto alloc_err;
 511                 }
 512
 513                 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 514                 if (!p_eq)
 515                         goto alloc_no_mem;
 516                 p_hwfn->p_eq = p_eq;
 517
 518                 p_consq = qed_consq_alloc(p_hwfn);
 519                 if (!p_consq)
 520                         goto alloc_no_mem;
 521                 p_hwfn->p_consq = p_consq;
 522
 523                 /* DMA info initialization */
 524                 rc = qed_dmae_info_alloc(p_hwfn);
 525                 if (rc) {
 526                         DP_NOTICE(p_hwfn,
 527                                   "Failed to allocate memory for dmae_info structure\n");
 528                         goto alloc_err;
 529                 }
 530
 531                 /* DCBX initialization */
 532                 rc = qed_dcbx_info_alloc(p_hwfn);
 533                 if (rc) {
 534                         DP_NOTICE(p_hwfn,
 535                                   "Failed to allocate memory for dcbx structure\n");
 536                         goto alloc_err;
 537                 }
 538         }
 539
 540         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 541         if (!cdev->reset_stats) {
 542                 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
 543                 goto alloc_no_mem;
 544         }
 545
 546         return 0;
 547
 548 alloc_no_mem:
 549         rc = -ENOMEM;
 550 alloc_err:
 551         qed_resc_free(cdev);
 552         return rc;
 553 }
 554
 555 void qed_resc_setup(struct qed_dev *cdev)
 556 {
 557         int i;
 558
 559         if (IS_VF(cdev))
 560                 return;
 561
 562         for_each_hwfn(cdev, i) {
 563                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 564
 565                 qed_cxt_mngr_setup(p_hwfn);
 566                 qed_spq_setup(p_hwfn);
 567                 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
 568                 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
 569
 570                 /* Read shadow of current MFW mailbox */
 571                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 572                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 573                        p_hwfn->mcp_info->mfw_mb_cur,
 574                        p_hwfn->mcp_info->mfw_mb_length);
 575
 576                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 577
 578                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 579         }
 580 }
 581
 582 #define FINAL_CLEANUP_POLL_CNT          (100)
 583 #define FINAL_CLEANUP_POLL_TIME         (10)
 584 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
 585                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
 586 {
 587         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 588         int rc = -EBUSY;
 589
 590         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 591                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 592
 593         if (is_vf)
 594                 id += 0x10;
 595
 596         command |= X_FINAL_CLEANUP_AGG_INT <<
 597                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 598         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 599         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 600         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 601
 602         /* Make sure notification is not set before initiating final cleanup */
 603         if (REG_RD(p_hwfn, addr)) {
 604                 DP_NOTICE(p_hwfn,
 605                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
 606                 REG_WR(p_hwfn, addr, 0);
 607         }
 608
 609         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
 610                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 611                    id, command);
 612
 613         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 614
 615         /* Poll until completion */
 616         while (!REG_RD(p_hwfn, addr) && count--)
 617                 msleep(FINAL_CLEANUP_POLL_TIME);
 618
 619         if (REG_RD(p_hwfn, addr))
 620                 rc = 0;
 621         else
 622                 DP_NOTICE(p_hwfn,
 623                           "Failed to receive FW final cleanup notification\n");
 624
 625         /* Cleanup afterwards */
 626         REG_WR(p_hwfn, addr, 0);
 627
 628         return rc;
 629 }
 630
 631 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
 632 {
 633         int hw_mode = 0;
 634
 635         hw_mode = (1 << MODE_BB_B0);
 636
 637         switch (p_hwfn->cdev->num_ports_in_engines) {
 638         case 1:
 639                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 640                 break;
 641         case 2:
 642                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 643                 break;
 644         case 4:
 645                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 646                 break;
 647         default:
 648                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
 649                           p_hwfn->cdev->num_ports_in_engines);
 650                 return;
 651         }
 652
 653         switch (p_hwfn->cdev->mf_mode) {
 654         case QED_MF_DEFAULT:
 655         case QED_MF_NPAR:
 656                 hw_mode |= 1 << MODE_MF_SI;
 657                 break;
 658         case QED_MF_OVLAN:
 659                 hw_mode |= 1 << MODE_MF_SD;
 660                 break;
 661         default:
 662                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 663                 hw_mode |= 1 << MODE_MF_SI;
 664         }
 665
 666         hw_mode |= 1 << MODE_ASIC;
 667
 668         if (p_hwfn->cdev->num_hwfns > 1)
 669                 hw_mode |= 1 << MODE_100G;
 670
 671         p_hwfn->hw_info.hw_mode = hw_mode;
 672
 673         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
 674                    "Configuring function for hw_mode: 0x%08x\n",
 675                    p_hwfn->hw_info.hw_mode);
 676 }
 677
 678 /* Init run time data for all PFs on an engine. */
 679 static void qed_init_cau_rt_data(struct qed_dev *cdev)
 680 {
 681         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 682         int i, sb_id;
 683
 684         for_each_hwfn(cdev, i) {
 685                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 686                 struct qed_igu_info *p_igu_info;
 687                 struct qed_igu_block *p_block;
 688                 struct cau_sb_entry sb_entry;
 689
 690                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 691
 692                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
 693                      sb_id++) {
 694                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 695                         if (!p_block->is_pf)
 696                                 continue;
 697
 698                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
 699                                               p_block->function_id, 0, 0);
 700                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 701                 }
 702         }
 703 }
 704
 705 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
 706                               struct qed_ptt *p_ptt, int hw_mode)
 707 {
 708         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 709         struct qed_qm_common_rt_init_params params;
 710         struct qed_dev *cdev = p_hwfn->cdev;
 711         u16 num_pfs, pf_id;
 712         u32 concrete_fid;
 713         int rc = 0;
 714         u8 vf_id;
 715
 716         qed_init_cau_rt_data(cdev);
 717
 718         /* Program GTT windows */
 719         qed_gtt_init(p_hwfn);
 720
 721         if (p_hwfn->mcp_info) {
 722                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 723                         qm_info->pf_rl_en = 1;
 724                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 725                         qm_info->pf_wfq_en = 1;
 726         }
 727
 728         memset(&params, 0, sizeof(params));
 729         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
 730         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
 731         params.pf_rl_en = qm_info->pf_rl_en;
 732         params.pf_wfq_en = qm_info->pf_wfq_en;
 733         params.vport_rl_en = qm_info->vport_rl_en;
 734         params.vport_wfq_en = qm_info->vport_wfq_en;
 735         params.port_params = qm_info->qm_port_params;
 736
 737         qed_qm_common_rt_init(p_hwfn, &params);
 738
 739         qed_cxt_hw_init_common(p_hwfn);
 740
 741         /* Close gate from NIG to BRB/Storm; By default they are open, but
 742          * we close them to prevent NIG from passing data to reset blocks.
 743          * Should have been done in the ENGINE phase, but init-tool lacks
 744          * proper port-pretend capabilities.
 745          */
 746         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 747         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 748         qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 749         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 750         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 751         qed_port_unpretend(p_hwfn, p_ptt);
 752
 753         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 754         if (rc)
 755                 return rc;
 756
 757         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 758         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 759
 760         if (QED_IS_BB(p_hwfn->cdev)) {
 761                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
 762                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
 763                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
 764                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
 765                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
 766                 }
 767                 /* pretend to original PF */
 768                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 769         }
 770
 771         for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
 772                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
 773                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
 774                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 775         }
 776         /* pretend to original PF */
 777         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 778
 779         return rc;
 780 }
 781
 782 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
 783                             struct qed_ptt *p_ptt, int hw_mode)
 784 {
 785         int rc = 0;
 786
 787         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
 788         if (rc)
 789                 return rc;
 790
 791         if (hw_mode & (1 << MODE_MF_SI)) {
 792                 u8 pf_id = 0;
 793
 794                 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
 795                         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
 796                                    "PF[%08x] is first eth on engine\n", pf_id);
 797
 798                         /* We should have configured BIT for ppfid, i.e., the
 799                          * relative function number in the port. But there's a
 800                          * bug in LLH in BB where the ppfid is actually engine
 801                          * based, so we need to take this into account.
 802                          */
 803                         qed_wr(p_hwfn, p_ptt,
 804                                NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
 805                 }
 806
 807                 /* Take the protocol-based hit vector if there is a hit,
 808                  * otherwise take the other vector.
 809                  */
 810                 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2);
 811         }
 812         return rc;
 813 }
 814
 815 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
 816                           struct qed_ptt *p_ptt,
 817                           struct qed_tunn_start_params *p_tunn,
 818                           int hw_mode,
 819                           bool b_hw_start,
 820                           enum qed_int_mode int_mode,
 821                           bool allow_npar_tx_switch)
 822 {
 823         u8 rel_pf_id = p_hwfn->rel_pf_id;
 824         int rc = 0;
 825
 826         if (p_hwfn->mcp_info) {
 827                 struct qed_mcp_function_info *p_info;
 828
 829                 p_info = &p_hwfn->mcp_info->func_info;
 830                 if (p_info->bandwidth_min)
 831                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
 832
 833                 /* Update rate limit once we'll actually have a link */
 834                 p_hwfn->qm_info.pf_rl = 100000;
 835         }
 836
 837         qed_cxt_hw_init_pf(p_hwfn);
 838
 839         qed_int_igu_init_rt(p_hwfn);
 840
 841         /* Set VLAN in NIG if needed */
 842         if (hw_mode & BIT(MODE_MF_SD)) {
 843                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
 844                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
 845                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
 846                              p_hwfn->hw_info.ovlan);
 847         }
 848
 849         /* Enable classification by MAC if needed */
 850         if (hw_mode & BIT(MODE_MF_SI)) {
 851                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
 852                            "Configuring TAGMAC_CLS_TYPE\n");
 853                 STORE_RT_REG(p_hwfn,
 854                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
 855         }
 856
 857         /* Protocl Configuration  */
 858         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
 859                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
 860         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
 861         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
 862
 863         /* Cleanup chip from previous driver if such remains exist */
 864         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
 865         if (rc)
 866                 return rc;
 867
 868         /* PF Init sequence */
 869         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
 870         if (rc)
 871                 return rc;
 872
 873         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
 874         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
 875         if (rc)
 876                 return rc;
 877
 878         /* Pure runtime initializations - directly to the HW  */
 879         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
 880
 881         if (hw_mode & (1 << MODE_MF_SI)) {
 882                 u8 pf_id = 0;
 883                 u32 val = 0;
 884
 885                 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
 886                         if (p_hwfn->rel_pf_id == pf_id) {
 887                                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
 888                                            "PF[%d] is first ETH on engine\n",
 889                                            pf_id);
 890                                 val = 1;
 891                         }
 892                         qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
 893                 }
 894         }
 895
 896         if (b_hw_start) {
 897                 /* enable interrupts */
 898                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
 899
 900                 /* send function start command */
 901                 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
 902                                      allow_npar_tx_switch);
 903                 if (rc)
 904                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
 905         }
 906         return rc;
 907 }
 908
 909 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
 910                                struct qed_ptt *p_ptt,
 911                                u8 enable)
 912 {
 913         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
 914
 915         /* Change PF in PXP */
 916         qed_wr(p_hwfn, p_ptt,
 917                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
 918
 919         /* wait until value is set - try for 1 second every 50us */
 920         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
 921                 val = qed_rd(p_hwfn, p_ptt,
 922                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
 923                 if (val == set_val)
 924                         break;
 925
 926                 usleep_range(50, 60);
 927         }
 928
 929         if (val != set_val) {
 930                 DP_NOTICE(p_hwfn,
 931                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
 932                 return -EAGAIN;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
 939                                 struct qed_ptt *p_main_ptt)
 940 {
 941         /* Read shadow of current MFW mailbox */
 942         qed_mcp_read_mb(p_hwfn, p_main_ptt);
 943         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 944                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
 945 }
 946
 947 int qed_hw_init(struct qed_dev *cdev,
 948                 struct qed_tunn_start_params *p_tunn,
 949                 bool b_hw_start,
 950                 enum qed_int_mode int_mode,
 951                 bool allow_npar_tx_switch,
 952                 const u8 *bin_fw_data)
 953 {
 954         u32 load_code, param;
 955         int rc, mfw_rc, i;
 956
 957         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
 958                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
 959                 return -EINVAL;
 960         }
 961
 962         if (IS_PF(cdev)) {
 963                 rc = qed_init_fw_data(cdev, bin_fw_data);
 964                 if (rc)
 965                         return rc;
 966         }
 967
 968         for_each_hwfn(cdev, i) {
 969                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 970
 971                 if (IS_VF(cdev)) {
 972                         p_hwfn->b_int_enabled = 1;
 973                         continue;
 974                 }
 975
 976                 /* Enable DMAE in PXP */
 977                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
 978
 979                 qed_calc_hw_mode(p_hwfn);
 980
 981                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
 982                 if (rc) {
 983                         DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
 984                         return rc;
 985                 }
 986
 987                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
 988
 989                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 990                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
 991                            rc, load_code);
 992
 993                 p_hwfn->first_on_engine = (load_code ==
 994                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
 995
 996                 switch (load_code) {
 997                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
 998                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
 999                                                 p_hwfn->hw_info.hw_mode);
1000                         if (rc)
1001                                 break;
1002                 /* Fall into */
1003                 case FW_MSG_CODE_DRV_LOAD_PORT:
1004                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1005                                               p_hwfn->hw_info.hw_mode);
1006                         if (rc)
1007                                 break;
1008
1009                 /* Fall into */
1010                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1011                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1012                                             p_tunn, p_hwfn->hw_info.hw_mode,
1013                                             b_hw_start, int_mode,
1014                                             allow_npar_tx_switch);
1015                         break;
1016                 default:
1017                         rc = -EINVAL;
1018                         break;
1019                 }
1020
1021                 if (rc)
1022                         DP_NOTICE(p_hwfn,
1023                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1024                                    load_code, rc);
1025
1026                 /* ACK mfw regardless of success or failure of initialization */
1027                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1028                                      DRV_MSG_CODE_LOAD_DONE,
1029                                      0, &load_code, &param);
1030                 if (rc)
1031                         return rc;
1032                 if (mfw_rc) {
1033                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1034                         return mfw_rc;
1035                 }
1036
1037                 /* send DCBX attention request command */
1038                 DP_VERBOSE(p_hwfn,
1039                            QED_MSG_DCB,
1040                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1041                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1042                                      DRV_MSG_CODE_SET_DCBX,
1043                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1044                                      &load_code, &param);
1045                 if (mfw_rc) {
1046                         DP_NOTICE(p_hwfn,
1047                                   "Failed to send DCBX attention request\n");
1048                         return mfw_rc;
1049                 }
1050
1051                 p_hwfn->hw_init_done = true;
1052         }
1053
1054         return 0;
1055 }
1056
1057 #define QED_HW_STOP_RETRY_LIMIT (10)
1058 static void qed_hw_timers_stop(struct qed_dev *cdev,
1059                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1060 {
1061         int i;
1062
1063         /* close timers */
1064         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1065         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1066
1067         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1068                 if ((!qed_rd(p_hwfn, p_ptt,
1069                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1070                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1071                         break;
1072
1073                 /* Dependent on number of connection/tasks, possibly
1074                  * 1ms sleep is required between polls
1075                  */
1076                 usleep_range(1000, 2000);
1077         }
1078
1079         if (i < QED_HW_STOP_RETRY_LIMIT)
1080                 return;
1081
1082         DP_NOTICE(p_hwfn,
1083                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1084                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1085                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1086 }
1087
1088 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1089 {
1090         int j;
1091
1092         for_each_hwfn(cdev, j) {
1093                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1094                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1095
1096                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1097         }
1098 }
1099
1100 int qed_hw_stop(struct qed_dev *cdev)
1101 {
1102         int rc = 0, t_rc;
1103         int j;
1104
1105         for_each_hwfn(cdev, j) {
1106                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1107                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1108
1109                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1110
1111                 if (IS_VF(cdev)) {
1112                         qed_vf_pf_int_cleanup(p_hwfn);
1113                         continue;
1114                 }
1115
1116                 /* mark the hw as uninitialized... */
1117                 p_hwfn->hw_init_done = false;
1118
1119                 rc = qed_sp_pf_stop(p_hwfn);
1120                 if (rc)
1121                         DP_NOTICE(p_hwfn,
1122                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1123
1124                 qed_wr(p_hwfn, p_ptt,
1125                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1126
1127                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1128                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1129                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1130                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1131                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1132
1133                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1134
1135                 /* Disable Attention Generation */
1136                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1137
1138                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1139                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1140
1141                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1142
1143                 /* Need to wait 1ms to guarantee SBs are cleared */
1144                 usleep_range(1000, 2000);
1145         }
1146
1147         if (IS_PF(cdev)) {
1148                 /* Disable DMAE in PXP - in CMT, this should only be done for
1149                  * first hw-function, and only after all transactions have
1150                  * stopped for all active hw-functions.
1151                  */
1152                 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1153                                            cdev->hwfns[0].p_main_ptt, false);
1154                 if (t_rc != 0)
1155                         rc = t_rc;
1156         }
1157
1158         return rc;
1159 }
1160
1161 void qed_hw_stop_fastpath(struct qed_dev *cdev)
1162 {
1163         int j;
1164
1165         for_each_hwfn(cdev, j) {
1166                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1167                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1168
1169                 if (IS_VF(cdev)) {
1170                         qed_vf_pf_int_cleanup(p_hwfn);
1171                         continue;
1172                 }
1173
1174                 DP_VERBOSE(p_hwfn,
1175                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1176
1177                 qed_wr(p_hwfn, p_ptt,
1178                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1179
1180                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1181                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1182                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1183                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1184                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1185
1186                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1187
1188                 /* Need to wait 1ms to guarantee SBs are cleared */
1189                 usleep_range(1000, 2000);
1190         }
1191 }
1192
1193 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1194 {
1195         if (IS_VF(p_hwfn->cdev))
1196                 return;
1197
1198         /* Re-open incoming traffic */
1199         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1200                NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1201 }
1202
1203 static int qed_reg_assert(struct qed_hwfn *p_hwfn,
1204                           struct qed_ptt *p_ptt, u32 reg, bool expected)
1205 {
1206         u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);
1207
1208         if (assert_val != expected) {
1209                 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",
1210                           reg, expected);
1211                 return -EINVAL;
1212         }
1213
1214         return 0;
1215 }
1216
1217 int qed_hw_reset(struct qed_dev *cdev)
1218 {
1219         int rc = 0;
1220         u32 unload_resp, unload_param;
1221         int i;
1222
1223         for_each_hwfn(cdev, i) {
1224                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1225
1226                 if (IS_VF(cdev)) {
1227                         rc = qed_vf_pf_reset(p_hwfn);
1228                         if (rc)
1229                                 return rc;
1230                         continue;
1231                 }
1232
1233                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1234
1235                 /* Check for incorrect states */
1236                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1237                                QM_REG_USG_CNT_PF_TX, 0);
1238                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1239                                QM_REG_USG_CNT_PF_OTHER, 0);
1240
1241                 /* Disable PF in HW blocks */
1242                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1243                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1244                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1245                        TCFC_REG_STRONG_ENABLE_PF, 0);
1246                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1247                        CCFC_REG_STRONG_ENABLE_PF, 0);
1248
1249                 /* Send unload command to MCP */
1250                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1251                                  DRV_MSG_CODE_UNLOAD_REQ,
1252                                  DRV_MB_PARAM_UNLOAD_WOL_MCP,
1253                                  &unload_resp, &unload_param);
1254                 if (rc) {
1255                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1256                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1257                 }
1258
1259                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1260                                  DRV_MSG_CODE_UNLOAD_DONE,
1261                                  0, &unload_resp, &unload_param);
1262                 if (rc) {
1263                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1264                         return rc;
1265                 }
1266         }
1267
1268         return rc;
1269 }
1270
1271 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1272 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1273 {
1274         qed_ptt_pool_free(p_hwfn);
1275         kfree(p_hwfn->hw_info.p_igu_info);
1276 }
1277
1278 /* Setup bar access */
1279 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1280 {
1281         /* clear indirect access */
1282         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1283         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1284         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1285         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1286
1287         /* Clean Previous errors if such exist */
1288         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1289                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1290
1291         /* enable internal target-read */
1292         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1293                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1294 }
1295
1296 static void get_function_id(struct qed_hwfn *p_hwfn)
1297 {
1298         /* ME Register */
1299         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1300                                                   PXP_PF_ME_OPAQUE_ADDR);
1301
1302         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1303
1304         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1305         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1306                                       PXP_CONCRETE_FID_PFID);
1307         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1308                                     PXP_CONCRETE_FID_PORT);
1309
1310         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1311                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1312                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1313 }
1314
1315 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1316 {
1317         u32 *feat_num = p_hwfn->hw_info.feat_num;
1318         int num_features = 1;
1319
1320         feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1321                                                 num_features,
1322                                         RESC_NUM(p_hwfn, QED_L2_QUEUE));
1323         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1324                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1325                    feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1326                    num_features);
1327 }
1328
1329 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1330 {
1331         u8 enabled_func_idx = p_hwfn->enabled_func_idx;
1332         u32 *resc_start = p_hwfn->hw_info.resc_start;
1333         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1334         u32 *resc_num = p_hwfn->hw_info.resc_num;
1335         struct qed_sb_cnt_info sb_cnt_info;
1336         int i, max_vf_vlan_filters;
1337
1338         memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1339
1340 #ifdef CONFIG_QED_SRIOV
1341         max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1342 #else
1343         max_vf_vlan_filters = 0;
1344 #endif
1345
1346         qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1347
1348         resc_num[QED_SB] = min_t(u32,
1349                                  (MAX_SB_PER_PATH_BB / num_funcs),
1350                                  sb_cnt_info.sb_cnt);
1351         resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1352         resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1353         resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1354         resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1355         resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
1356         resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1357         resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1358                              num_funcs;
1359         resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
1360
1361         for (i = 0; i < QED_MAX_RESC; i++)
1362                 resc_start[i] = resc_num[i] * enabled_func_idx;
1363
1364         /* Sanity for ILT */
1365         if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
1366                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1367                           RESC_START(p_hwfn, QED_ILT),
1368                           RESC_END(p_hwfn, QED_ILT) - 1);
1369                 return -EINVAL;
1370         }
1371
1372         qed_hw_set_feat(p_hwfn);
1373
1374         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1375                    "The numbers for each resource are:\n"
1376                    "SB = %d start = %d\n"
1377                    "L2_QUEUE = %d start = %d\n"
1378                    "VPORT = %d start = %d\n"
1379                    "PQ = %d start = %d\n"
1380                    "RL = %d start = %d\n"
1381                    "MAC = %d start = %d\n"
1382                    "VLAN = %d start = %d\n"
1383                    "ILT = %d start = %d\n",
1384                    p_hwfn->hw_info.resc_num[QED_SB],
1385                    p_hwfn->hw_info.resc_start[QED_SB],
1386                    p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1387                    p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1388                    p_hwfn->hw_info.resc_num[QED_VPORT],
1389                    p_hwfn->hw_info.resc_start[QED_VPORT],
1390                    p_hwfn->hw_info.resc_num[QED_PQ],
1391                    p_hwfn->hw_info.resc_start[QED_PQ],
1392                    p_hwfn->hw_info.resc_num[QED_RL],
1393                    p_hwfn->hw_info.resc_start[QED_RL],
1394                    p_hwfn->hw_info.resc_num[QED_MAC],
1395                    p_hwfn->hw_info.resc_start[QED_MAC],
1396                    p_hwfn->hw_info.resc_num[QED_VLAN],
1397                    p_hwfn->hw_info.resc_start[QED_VLAN],
1398                    p_hwfn->hw_info.resc_num[QED_ILT],
1399                    p_hwfn->hw_info.resc_start[QED_ILT]);
1400
1401         return 0;
1402 }
1403
1404 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1405 {
1406         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1407         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1408         struct qed_mcp_link_params *link;
1409
1410         /* Read global nvm_cfg address */
1411         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1412
1413         /* Verify MCP has initialized it */
1414         if (!nvm_cfg_addr) {
1415                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1416                 return -EINVAL;
1417         }
1418
1419         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1420         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1421
1422         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1423                offsetof(struct nvm_cfg1, glob) +
1424                offsetof(struct nvm_cfg1_glob, core_cfg);
1425
1426         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1427
1428         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1429                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1430         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
1431                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1432                 break;
1433         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
1434                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1435                 break;
1436         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
1437                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1438                 break;
1439         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
1440                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1441                 break;
1442         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
1443                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1444                 break;
1445         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
1446                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1447                 break;
1448         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
1449                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1450                 break;
1451         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
1452                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1453                 break;
1454         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
1455                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1456                 break;
1457         default:
1458                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
1459                 break;
1460         }
1461
1462         /* Read default link configuration */
1463         link = &p_hwfn->mcp_info->link_input;
1464         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1465                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1466         link_temp = qed_rd(p_hwfn, p_ptt,
1467                            port_cfg_addr +
1468                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
1469         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1470         link->speed.advertised_speeds = link_temp;
1471
1472         link_temp = link->speed.advertised_speeds;
1473         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1474
1475         link_temp = qed_rd(p_hwfn, p_ptt,
1476                            port_cfg_addr +
1477                            offsetof(struct nvm_cfg1_port, link_settings));
1478         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1479                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1480         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1481                 link->speed.autoneg = true;
1482                 break;
1483         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1484                 link->speed.forced_speed = 1000;
1485                 break;
1486         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1487                 link->speed.forced_speed = 10000;
1488                 break;
1489         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1490                 link->speed.forced_speed = 25000;
1491                 break;
1492         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1493                 link->speed.forced_speed = 40000;
1494                 break;
1495         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1496                 link->speed.forced_speed = 50000;
1497                 break;
1498         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
1499                 link->speed.forced_speed = 100000;
1500                 break;
1501         default:
1502                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
1503         }
1504
1505         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1506         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1507         link->pause.autoneg = !!(link_temp &
1508                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1509         link->pause.forced_rx = !!(link_temp &
1510                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1511         link->pause.forced_tx = !!(link_temp &
1512                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1513         link->loopback_mode = 0;
1514
1515         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1516                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1517                    link->speed.forced_speed, link->speed.advertised_speeds,
1518                    link->speed.autoneg, link->pause.autoneg);
1519
1520         /* Read Multi-function information from shmem */
1521         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1522                offsetof(struct nvm_cfg1, glob) +
1523                offsetof(struct nvm_cfg1_glob, generic_cont0);
1524
1525         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1526
1527         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1528                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
1529
1530         switch (mf_mode) {
1531         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1532                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1533                 break;
1534         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1535                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1536                 break;
1537         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1538                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1539                 break;
1540         }
1541         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1542                 p_hwfn->cdev->mf_mode);
1543
1544         /* Read Multi-function information from shmem */
1545         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1546                 offsetof(struct nvm_cfg1, glob) +
1547                 offsetof(struct nvm_cfg1_glob, device_capabilities);
1548
1549         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1550         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1551                 __set_bit(QED_DEV_CAP_ETH,
1552                           &p_hwfn->hw_info.device_capabilities);
1553         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1554                 __set_bit(QED_DEV_CAP_ISCSI,
1555                           &p_hwfn->hw_info.device_capabilities);
1556         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1557                 __set_bit(QED_DEV_CAP_ROCE,
1558                           &p_hwfn->hw_info.device_capabilities);
1559
1560         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1561 }
1562
1563 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1564 {
1565         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
1566         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
1567
1568         num_funcs = MAX_NUM_PFS_BB;
1569
1570         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1571          * in the other bits are selected.
1572          * Bits 1-15 are for functions 1-15, respectively, and their value is
1573          * '0' only for enabled functions (function 0 always exists and
1574          * enabled).
1575          * In case of CMT, only the "even" functions are enabled, and thus the
1576          * number of functions for both hwfns is learnt from the same bits.
1577          */
1578         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1579
1580         if (reg_function_hide & 0x1) {
1581                 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1582                         num_funcs = 0;
1583                         eng_mask = 0xaaaa;
1584                 } else {
1585                         num_funcs = 1;
1586                         eng_mask = 0x5554;
1587                 }
1588
1589                 /* Get the number of the enabled functions on the engine */
1590                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1591                 while (tmp) {
1592                         if (tmp & 0x1)
1593                                 num_funcs++;
1594                         tmp >>= 0x1;
1595                 }
1596
1597                 /* Get the PF index within the enabled functions */
1598                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
1599                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
1600                 while (tmp) {
1601                         if (tmp & 0x1)
1602                                 enabled_func_idx--;
1603                         tmp >>= 0x1;
1604                 }
1605         }
1606
1607         p_hwfn->num_funcs_on_engine = num_funcs;
1608         p_hwfn->enabled_func_idx = enabled_func_idx;
1609
1610         DP_VERBOSE(p_hwfn,
1611                    NETIF_MSG_PROBE,
1612                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1613                    p_hwfn->rel_pf_id,
1614                    p_hwfn->abs_pf_id,
1615                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1616 }
1617
1618 static int
1619 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1620                 struct qed_ptt *p_ptt,
1621                 enum qed_pci_personality personality)
1622 {
1623         u32 port_mode;
1624         int rc;
1625
1626         /* Since all information is common, only first hwfns should do this */
1627         if (IS_LEAD_HWFN(p_hwfn)) {
1628                 rc = qed_iov_hw_info(p_hwfn);
1629                 if (rc)
1630                         return rc;
1631         }
1632
1633         /* Read the port mode */
1634         port_mode = qed_rd(p_hwfn, p_ptt,
1635                            CNIG_REG_NW_PORT_MODE_BB_B0);
1636
1637         if (port_mode < 3) {
1638                 p_hwfn->cdev->num_ports_in_engines = 1;
1639         } else if (port_mode <= 5) {
1640                 p_hwfn->cdev->num_ports_in_engines = 2;
1641         } else {
1642                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1643                           p_hwfn->cdev->num_ports_in_engines);
1644
1645                 /* Default num_ports_in_engines to something */
1646                 p_hwfn->cdev->num_ports_in_engines = 1;
1647         }
1648
1649         qed_hw_get_nvm_info(p_hwfn, p_ptt);
1650
1651         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1652         if (rc)
1653                 return rc;
1654
1655         if (qed_mcp_is_init(p_hwfn))
1656                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1657                                 p_hwfn->mcp_info->func_info.mac);
1658         else
1659                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1660
1661         if (qed_mcp_is_init(p_hwfn)) {
1662                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1663                         p_hwfn->hw_info.ovlan =
1664                                 p_hwfn->mcp_info->func_info.ovlan;
1665
1666                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1667         }
1668
1669         if (qed_mcp_is_init(p_hwfn)) {
1670                 enum qed_pci_personality protocol;
1671
1672                 protocol = p_hwfn->mcp_info->func_info.protocol;
1673                 p_hwfn->hw_info.personality = protocol;
1674         }
1675
1676         qed_get_num_funcs(p_hwfn, p_ptt);
1677
1678         return qed_hw_get_resc(p_hwfn);
1679 }
1680
1681 static int qed_get_dev_info(struct qed_dev *cdev)
1682 {
1683         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1684         u32 tmp;
1685
1686         /* Read Vendor Id / Device Id */
1687         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
1688         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
1689
1690         cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1691                                      MISCS_REG_CHIP_NUM);
1692         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1693                                      MISCS_REG_CHIP_REV);
1694         MASK_FIELD(CHIP_REV, cdev->chip_rev);
1695
1696         cdev->type = QED_DEV_TYPE_BB;
1697         /* Learn number of HW-functions */
1698         tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1699                      MISCS_REG_CMT_ENABLED_FOR_PAIR);
1700
1701         if (tmp & (1 << p_hwfn->rel_pf_id)) {
1702                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1703                 cdev->num_hwfns = 2;
1704         } else {
1705                 cdev->num_hwfns = 1;
1706         }
1707
1708         cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1709                                     MISCS_REG_CHIP_TEST_REG) >> 4;
1710         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1711         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1712                                        MISCS_REG_CHIP_METAL);
1713         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1714
1715         DP_INFO(cdev->hwfns,
1716                 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1717                 cdev->chip_num, cdev->chip_rev,
1718                 cdev->chip_bond_id, cdev->chip_metal);
1719
1720         if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1721                 DP_NOTICE(cdev->hwfns,
1722                           "The chip type/rev (BB A0) is not supported!\n");
1723                 return -EINVAL;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1730                                  void __iomem *p_regview,
1731                                  void __iomem *p_doorbells,
1732                                  enum qed_pci_personality personality)
1733 {
1734         int rc = 0;
1735
1736         /* Split PCI bars evenly between hwfns */
1737         p_hwfn->regview = p_regview;
1738         p_hwfn->doorbells = p_doorbells;
1739
1740         if (IS_VF(p_hwfn->cdev))
1741                 return qed_vf_hw_prepare(p_hwfn);
1742
1743         /* Validate that chip access is feasible */
1744         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1745                 DP_ERR(p_hwfn,
1746                        "Reading the ME register returns all Fs; Preventing further chip access\n");
1747                 return -EINVAL;
1748         }
1749
1750         get_function_id(p_hwfn);
1751
1752         /* Allocate PTT pool */
1753         rc = qed_ptt_pool_alloc(p_hwfn);
1754         if (rc) {
1755                 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1756                 goto err0;
1757         }
1758
1759         /* Allocate the main PTT */
1760         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1761
1762         /* First hwfn learns basic information, e.g., number of hwfns */
1763         if (!p_hwfn->my_id) {
1764                 rc = qed_get_dev_info(p_hwfn->cdev);
1765                 if (rc)
1766                         goto err1;
1767         }
1768
1769         qed_hw_hwfn_prepare(p_hwfn);
1770
1771         /* Initialize MCP structure */
1772         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1773         if (rc) {
1774                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1775                 goto err1;
1776         }
1777
1778         /* Read the device configuration information from the HW and SHMEM */
1779         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1780         if (rc) {
1781                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1782                 goto err2;
1783         }
1784
1785         /* Allocate the init RT array and initialize the init-ops engine */
1786         rc = qed_init_alloc(p_hwfn);
1787         if (rc) {
1788                 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1789                 goto err2;
1790         }
1791
1792         return rc;
1793 err2:
1794         if (IS_LEAD_HWFN(p_hwfn))
1795                 qed_iov_free_hw_info(p_hwfn->cdev);
1796         qed_mcp_free(p_hwfn);
1797 err1:
1798         qed_hw_hwfn_free(p_hwfn);
1799 err0:
1800         return rc;
1801 }
1802
1803 int qed_hw_prepare(struct qed_dev *cdev,
1804                    int personality)
1805 {
1806         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1807         int rc;
1808
1809         /* Store the precompiled init data ptrs */
1810         if (IS_PF(cdev))
1811                 qed_init_iro_array(cdev);
1812
1813         /* Initialize the first hwfn - will learn number of hwfns */
1814         rc = qed_hw_prepare_single(p_hwfn,
1815                                    cdev->regview,
1816                                    cdev->doorbells, personality);
1817         if (rc)
1818                 return rc;
1819
1820         personality = p_hwfn->hw_info.personality;
1821
1822         /* Initialize the rest of the hwfns */
1823         if (cdev->num_hwfns > 1) {
1824                 void __iomem *p_regview, *p_doorbell;
1825                 u8 __iomem *addr;
1826
1827                 /* adjust bar offset for second engine */
1828                 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1829                 p_regview = addr;
1830
1831                 /* adjust doorbell bar offset for second engine */
1832                 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1833                 p_doorbell = addr;
1834
1835                 /* prepare second hw function */
1836                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1837                                            p_doorbell, personality);
1838
1839                 /* in case of error, need to free the previously
1840                  * initiliazed hwfn 0.
1841                  */
1842                 if (rc) {
1843                         if (IS_PF(cdev)) {
1844                                 qed_init_free(p_hwfn);
1845                                 qed_mcp_free(p_hwfn);
1846                                 qed_hw_hwfn_free(p_hwfn);
1847                         }
1848                 }
1849         }
1850
1851         return rc;
1852 }
1853
1854 void qed_hw_remove(struct qed_dev *cdev)
1855 {
1856         int i;
1857
1858         for_each_hwfn(cdev, i) {
1859                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1860
1861                 if (IS_VF(cdev)) {
1862                         qed_vf_pf_release(p_hwfn);
1863                         continue;
1864                 }
1865
1866                 qed_init_free(p_hwfn);
1867                 qed_hw_hwfn_free(p_hwfn);
1868                 qed_mcp_free(p_hwfn);
1869         }
1870
1871         qed_iov_free_hw_info(cdev);
1872 }
1873
1874 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
1875                                     struct qed_chain *p_chain)
1876 {
1877         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
1878         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
1879         struct qed_chain_next *p_next;
1880         u32 size, i;
1881
1882         if (!p_virt)
1883                 return;
1884
1885         size = p_chain->elem_size * p_chain->usable_per_page;
1886
1887         for (i = 0; i < p_chain->page_cnt; i++) {
1888                 if (!p_virt)
1889                         break;
1890
1891                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
1892                 p_virt_next = p_next->next_virt;
1893                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
1894
1895                 dma_free_coherent(&cdev->pdev->dev,
1896                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
1897
1898                 p_virt = p_virt_next;
1899                 p_phys = p_phys_next;
1900         }
1901 }
1902
1903 static void qed_chain_free_single(struct qed_dev *cdev,
1904                                   struct qed_chain *p_chain)
1905 {
1906         if (!p_chain->p_virt_addr)
1907                 return;
1908
1909         dma_free_coherent(&cdev->pdev->dev,
1910                           QED_CHAIN_PAGE_SIZE,
1911                           p_chain->p_virt_addr, p_chain->p_phys_addr);
1912 }
1913
1914 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
1915 {
1916         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
1917         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
1918         u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
1919
1920         if (!pp_virt_addr_tbl)
1921                 return;
1922
1923         if (!p_chain->pbl.p_virt_table)
1924                 goto out;
1925
1926         for (i = 0; i < page_cnt; i++) {
1927                 if (!pp_virt_addr_tbl[i])
1928                         break;
1929
1930                 dma_free_coherent(&cdev->pdev->dev,
1931                                   QED_CHAIN_PAGE_SIZE,
1932                                   pp_virt_addr_tbl[i],
1933                                   *(dma_addr_t *)p_pbl_virt);
1934
1935                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
1936         }
1937
1938         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1939         dma_free_coherent(&cdev->pdev->dev,
1940                           pbl_size,
1941                           p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
1942 out:
1943         vfree(p_chain->pbl.pp_virt_addr_tbl);
1944 }
1945
1946 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
1947 {
1948         switch (p_chain->mode) {
1949         case QED_CHAIN_MODE_NEXT_PTR:
1950                 qed_chain_free_next_ptr(cdev, p_chain);
1951                 break;
1952         case QED_CHAIN_MODE_SINGLE:
1953                 qed_chain_free_single(cdev, p_chain);
1954                 break;
1955         case QED_CHAIN_MODE_PBL:
1956                 qed_chain_free_pbl(cdev, p_chain);
1957                 break;
1958         }
1959 }
1960
1961 static int
1962 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
1963                              enum qed_chain_cnt_type cnt_type,
1964                              size_t elem_size, u32 page_cnt)
1965 {
1966         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
1967
1968         /* The actual chain size can be larger than the maximal possible value
1969          * after rounding up the requested elements number to pages, and after
1970          * taking into acount the unusuable elements (next-ptr elements).
1971          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
1972          * size/capacity fields are of a u32 type.
1973          */
1974         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
1975              chain_size > 0x10000) ||
1976             (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
1977              chain_size > 0x100000000ULL)) {
1978                 DP_NOTICE(cdev,
1979                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
1980                           chain_size);
1981                 return -EINVAL;
1982         }
1983
1984         return 0;
1985 }
1986
1987 static int
1988 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
1989 {
1990         void *p_virt = NULL, *p_virt_prev = NULL;
1991         dma_addr_t p_phys = 0;
1992         u32 i;
1993
1994         for (i = 0; i < p_chain->page_cnt; i++) {
1995                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1996                                             QED_CHAIN_PAGE_SIZE,
1997                                             &p_phys, GFP_KERNEL);
1998                 if (!p_virt) {
1999                         DP_NOTICE(cdev, "Failed to allocate chain memory\n");
2000                         return -ENOMEM;
2001                 }
2002
2003                 if (i == 0) {
2004                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2005                         qed_chain_reset(p_chain);
2006                 } else {
2007                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2008                                                      p_virt, p_phys);
2009                 }
2010
2011                 p_virt_prev = p_virt;
2012         }
2013         /* Last page's next element should point to the beginning of the
2014          * chain.
2015          */
2016         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2017                                      p_chain->p_virt_addr,
2018                                      p_chain->p_phys_addr);
2019
2020         return 0;
2021 }
2022
2023 static int
2024 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2025 {
2026         dma_addr_t p_phys = 0;
2027         void *p_virt = NULL;
2028
2029         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2030                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2031         if (!p_virt) {
2032                 DP_NOTICE(cdev, "Failed to allocate chain memory\n");
2033                 return -ENOMEM;
2034         }
2035
2036         qed_chain_init_mem(p_chain, p_virt, p_phys);
2037         qed_chain_reset(p_chain);
2038
2039         return 0;
2040 }
2041
2042 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2043 {
2044         u32 page_cnt = p_chain->page_cnt, size, i;
2045         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2046         void **pp_virt_addr_tbl = NULL;
2047         u8 *p_pbl_virt = NULL;
2048         void *p_virt = NULL;
2049
2050         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2051         pp_virt_addr_tbl = vmalloc(size);
2052         if (!pp_virt_addr_tbl) {
2053                 DP_NOTICE(cdev,
2054                           "Failed to allocate memory for the chain virtual addresses table\n");
2055                 return -ENOMEM;
2056         }
2057         memset(pp_virt_addr_tbl, 0, size);
2058
2059         /* The allocation of the PBL table is done with its full size, since it
2060          * is expected to be successive.
2061          * qed_chain_init_pbl_mem() is called even in a case of an allocation
2062          * failure, since pp_virt_addr_tbl was previously allocated, and it
2063          * should be saved to allow its freeing during the error flow.
2064          */
2065         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2066         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2067                                         size, &p_pbl_phys, GFP_KERNEL);
2068         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2069                                pp_virt_addr_tbl);
2070         if (!p_pbl_virt) {
2071                 DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n");
2072                 return -ENOMEM;
2073         }
2074
2075         for (i = 0; i < page_cnt; i++) {
2076                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2077                                             QED_CHAIN_PAGE_SIZE,
2078                                             &p_phys, GFP_KERNEL);
2079                 if (!p_virt) {
2080                         DP_NOTICE(cdev, "Failed to allocate chain memory\n");
2081                         return -ENOMEM;
2082                 }
2083
2084                 if (i == 0) {
2085                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2086                         qed_chain_reset(p_chain);
2087                 }
2088
2089                 /* Fill the PBL table with the physical address of the page */
2090                 *(dma_addr_t *)p_pbl_virt = p_phys;
2091                 /* Keep the virtual address of the page */
2092                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2093
2094                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2095         }
2096
2097         return 0;
2098 }
2099
2100 int qed_chain_alloc(struct qed_dev *cdev,
2101                     enum qed_chain_use_mode intended_use,
2102                     enum qed_chain_mode mode,
2103                     enum qed_chain_cnt_type cnt_type,
2104                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
2105 {
2106         u32 page_cnt;
2107         int rc = 0;
2108
2109         if (mode == QED_CHAIN_MODE_SINGLE)
2110                 page_cnt = 1;
2111         else
2112                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2113
2114         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2115         if (rc) {
2116                 DP_NOTICE(cdev,
2117                           "Cannot allocate a chain with the given arguments:\n"
2118                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2119                           intended_use, mode, cnt_type, num_elems, elem_size);
2120                 return rc;
2121         }
2122
2123         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2124                               mode, cnt_type);
2125
2126         switch (mode) {
2127         case QED_CHAIN_MODE_NEXT_PTR:
2128                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2129                 break;
2130         case QED_CHAIN_MODE_SINGLE:
2131                 rc = qed_chain_alloc_single(cdev, p_chain);
2132                 break;
2133         case QED_CHAIN_MODE_PBL:
2134                 rc = qed_chain_alloc_pbl(cdev, p_chain);
2135                 break;
2136         }
2137         if (rc)
2138                 goto nomem;
2139
2140         return 0;
2141
2142 nomem:
2143         qed_chain_free(cdev, p_chain);
2144         return rc;
2145 }
2146
2147 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
2148 {
2149         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2150                 u16 min, max;
2151
2152                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
2153                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2154                 DP_NOTICE(p_hwfn,
2155                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2156                           src_id, min, max);
2157
2158                 return -EINVAL;
2159         }
2160
2161         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2162
2163         return 0;
2164 }
2165
2166 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2167 {
2168         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2169                 u8 min, max;
2170
2171                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2172                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2173                 DP_NOTICE(p_hwfn,
2174                           "vport id [%d] is not valid, available indices [%d - %d]\n",
2175                           src_id, min, max);
2176
2177                 return -EINVAL;
2178         }
2179
2180         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2181
2182         return 0;
2183 }
2184
2185 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2186 {
2187         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2188                 u8 min, max;
2189
2190                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2191                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2192                 DP_NOTICE(p_hwfn,
2193                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2194                           src_id, min, max);
2195
2196                 return -EINVAL;
2197         }
2198
2199         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2200
2201         return 0;
2202 }
2203
2204 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2205                             u32 hw_addr, void *p_eth_qzone,
2206                             size_t eth_qzone_size, u8 timeset)
2207 {
2208         struct coalescing_timeset *p_coal_timeset;
2209
2210         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2211                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2212                 return -EINVAL;
2213         }
2214
2215         p_coal_timeset = p_eth_qzone;
2216         memset(p_coal_timeset, 0, eth_qzone_size);
2217         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2218         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2219         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2220
2221         return 0;
2222 }
2223
2224 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2225                          u16 coalesce, u8 qid, u16 sb_id)
2226 {
2227         struct ustorm_eth_queue_zone eth_qzone;
2228         u8 timeset, timer_res;
2229         u16 fw_qid = 0;
2230         u32 address;
2231         int rc;
2232
2233         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2234         if (coalesce <= 0x7F) {
2235                 timer_res = 0;
2236         } else if (coalesce <= 0xFF) {
2237                 timer_res = 1;
2238         } else if (coalesce <= 0x1FF) {
2239                 timer_res = 2;
2240         } else {
2241                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2242                 return -EINVAL;
2243         }
2244         timeset = (u8)(coalesce >> timer_res);
2245
2246         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2247         if (rc)
2248                 return rc;
2249
2250         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
2251         if (rc)
2252                 goto out;
2253
2254         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2255
2256         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2257                               sizeof(struct ustorm_eth_queue_zone), timeset);
2258         if (rc)
2259                 goto out;
2260
2261         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
2262 out:
2263         return rc;
2264 }
2265
2266 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2267                          u16 coalesce, u8 qid, u16 sb_id)
2268 {
2269         struct xstorm_eth_queue_zone eth_qzone;
2270         u8 timeset, timer_res;
2271         u16 fw_qid = 0;
2272         u32 address;
2273         int rc;
2274
2275         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2276         if (coalesce <= 0x7F) {
2277                 timer_res = 0;
2278         } else if (coalesce <= 0xFF) {
2279                 timer_res = 1;
2280         } else if (coalesce <= 0x1FF) {
2281                 timer_res = 2;
2282         } else {
2283                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2284                 return -EINVAL;
2285         }
2286         timeset = (u8)(coalesce >> timer_res);
2287
2288         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2289         if (rc)
2290                 return rc;
2291
2292         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
2293         if (rc)
2294                 goto out;
2295
2296         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2297
2298         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2299                               sizeof(struct xstorm_eth_queue_zone), timeset);
2300         if (rc)
2301                 goto out;
2302
2303         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
2304 out:
2305         return rc;
2306 }
2307
2308 /* Calculate final WFQ values for all vports and configure them.
2309  * After this configuration each vport will have
2310  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2311  */
2312 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2313                                              struct qed_ptt *p_ptt,
2314                                              u32 min_pf_rate)
2315 {
2316         struct init_qm_vport_params *vport_params;
2317         int i;
2318
2319         vport_params = p_hwfn->qm_info.qm_vport_params;
2320
2321         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2322                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2323
2324                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
2325                                                 min_pf_rate;
2326                 qed_init_vport_wfq(p_hwfn, p_ptt,
2327                                    vport_params[i].first_tx_pq_id,
2328                                    vport_params[i].vport_wfq);
2329         }
2330 }
2331
2332 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
2333                                        u32 min_pf_rate)
2334
2335 {
2336         int i;
2337
2338         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
2339                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
2340 }
2341
2342 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2343                                            struct qed_ptt *p_ptt,
2344                                            u32 min_pf_rate)
2345 {
2346         struct init_qm_vport_params *vport_params;
2347         int i;
2348
2349         vport_params = p_hwfn->qm_info.qm_vport_params;
2350
2351         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2352                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
2353                 qed_init_vport_wfq(p_hwfn, p_ptt,
2354                                    vport_params[i].first_tx_pq_id,
2355                                    vport_params[i].vport_wfq);
2356         }
2357 }
2358
2359 /* This function performs several validations for WFQ
2360  * configuration and required min rate for a given vport
2361  * 1. req_rate must be greater than one percent of min_pf_rate.
2362  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2363  *    rates to get less than one percent of min_pf_rate.
2364  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2365  */
2366 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
2367                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
2368 {
2369         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
2370         int non_requested_count = 0, req_count = 0, i, num_vports;
2371
2372         num_vports = p_hwfn->qm_info.num_vports;
2373
2374         /* Accounting for the vports which are configured for WFQ explicitly */
2375         for (i = 0; i < num_vports; i++) {
2376                 u32 tmp_speed;
2377
2378                 if ((i != vport_id) &&
2379                     p_hwfn->qm_info.wfq_data[i].configured) {
2380                         req_count++;
2381                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2382                         total_req_min_rate += tmp_speed;
2383                 }
2384         }
2385
2386         /* Include current vport data as well */
2387         req_count++;
2388         total_req_min_rate += req_rate;
2389         non_requested_count = num_vports - req_count;
2390
2391         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2392                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2393                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2394                            vport_id, req_rate, min_pf_rate);
2395                 return -EINVAL;
2396         }
2397
2398         if (num_vports > QED_WFQ_UNIT) {
2399                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2400                            "Number of vports is greater than %d\n",
2401                            QED_WFQ_UNIT);
2402                 return -EINVAL;
2403         }
2404
2405         if (total_req_min_rate > min_pf_rate) {
2406                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2407                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2408                            total_req_min_rate, min_pf_rate);
2409                 return -EINVAL;
2410         }
2411
2412         total_left_rate = min_pf_rate - total_req_min_rate;
2413
2414         left_rate_per_vp = total_left_rate / non_requested_count;
2415         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
2416                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2417                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2418                            left_rate_per_vp, min_pf_rate);
2419                 return -EINVAL;
2420         }
2421
2422         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2423         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2424
2425         for (i = 0; i < num_vports; i++) {
2426                 if (p_hwfn->qm_info.wfq_data[i].configured)
2427                         continue;
2428
2429                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2430         }
2431
2432         return 0;
2433 }
2434
2435 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2436                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2437 {
2438         struct qed_mcp_link_state *p_link;
2439         int rc = 0;
2440
2441         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2442
2443         if (!p_link->min_pf_rate) {
2444                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2445                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2446                 return rc;
2447         }
2448
2449         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2450
2451         if (!rc)
2452                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2453                                                  p_link->min_pf_rate);
2454         else
2455                 DP_NOTICE(p_hwfn,
2456                           "Validation failed while configuring min rate\n");
2457
2458         return rc;
2459 }
2460
2461 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2462                                                  struct qed_ptt *p_ptt,
2463                                                  u32 min_pf_rate)
2464 {
2465         bool use_wfq = false;
2466         int rc = 0;
2467         u16 i;
2468
2469         /* Validate all pre configured vports for wfq */
2470         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2471                 u32 rate;
2472
2473                 if (!p_hwfn->qm_info.wfq_data[i].configured)
2474                         continue;
2475
2476                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2477                 use_wfq = true;
2478
2479                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2480                 if (rc) {
2481                         DP_NOTICE(p_hwfn,
2482                                   "WFQ validation failed while configuring min rate\n");
2483                         break;
2484                 }
2485         }
2486
2487         if (!rc && use_wfq)
2488                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2489         else
2490                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2491
2492         return rc;
2493 }
2494
2495 /* Main API for qed clients to configure vport min rate.
2496  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2497  * rate - Speed in Mbps needs to be assigned to a given vport.
2498  */
2499 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2500 {
2501         int i, rc = -EINVAL;
2502
2503         /* Currently not supported; Might change in future */
2504         if (cdev->num_hwfns > 1) {
2505                 DP_NOTICE(cdev,
2506                           "WFQ configuration is not supported for this device\n");
2507                 return rc;
2508         }
2509
2510         for_each_hwfn(cdev, i) {
2511                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2512                 struct qed_ptt *p_ptt;
2513
2514                 p_ptt = qed_ptt_acquire(p_hwfn);
2515                 if (!p_ptt)
2516                         return -EBUSY;
2517
2518                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2519
2520                 if (rc) {
2521                         qed_ptt_release(p_hwfn, p_ptt);
2522                         return rc;
2523                 }
2524
2525                 qed_ptt_release(p_hwfn, p_ptt);
2526         }
2527
2528         return rc;
2529 }
2530
2531 /* API to configure WFQ from mcp link change */
2532 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
2533 {
2534         int i;
2535
2536         if (cdev->num_hwfns > 1) {
2537                 DP_VERBOSE(cdev,
2538                            NETIF_MSG_LINK,
2539                            "WFQ configuration is not supported for this device\n");
2540                 return;
2541         }
2542
2543         for_each_hwfn(cdev, i) {
2544                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2545
2546                 __qed_configure_vp_wfq_on_link_change(p_hwfn,
2547                                                       p_hwfn->p_dpc_ptt,
2548                                                       min_pf_rate);
2549         }
2550 }
2551
2552 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2553                                      struct qed_ptt *p_ptt,
2554                                      struct qed_mcp_link_state *p_link,
2555                                      u8 max_bw)
2556 {
2557         int rc = 0;
2558
2559         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2560
2561         if (!p_link->line_speed && (max_bw != 100))
2562                 return rc;
2563
2564         p_link->speed = (p_link->line_speed * max_bw) / 100;
2565         p_hwfn->qm_info.pf_rl = p_link->speed;
2566
2567         /* Since the limiter also affects Tx-switched traffic, we don't want it
2568          * to limit such traffic in case there's no actual limit.
2569          * In that case, set limit to imaginary high boundary.
2570          */
2571         if (max_bw == 100)
2572                 p_hwfn->qm_info.pf_rl = 100000;
2573
2574         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2575                             p_hwfn->qm_info.pf_rl);
2576
2577         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2578                    "Configured MAX bandwidth to be %08x Mb/sec\n",
2579                    p_link->speed);
2580
2581         return rc;
2582 }
2583
2584 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2585 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2586 {
2587         int i, rc = -EINVAL;
2588
2589         if (max_bw < 1 || max_bw > 100) {
2590                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2591                 return rc;
2592         }
2593
2594         for_each_hwfn(cdev, i) {
2595                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2596                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2597                 struct qed_mcp_link_state *p_link;
2598                 struct qed_ptt *p_ptt;
2599
2600                 p_link = &p_lead->mcp_info->link_output;
2601
2602                 p_ptt = qed_ptt_acquire(p_hwfn);
2603                 if (!p_ptt)
2604                         return -EBUSY;
2605
2606                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2607                                                       p_link, max_bw);
2608
2609                 qed_ptt_release(p_hwfn, p_ptt);
2610
2611                 if (rc)
2612                         break;
2613         }
2614
2615         return rc;
2616 }
2617
2618 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2619                                      struct qed_ptt *p_ptt,
2620                                      struct qed_mcp_link_state *p_link,
2621                                      u8 min_bw)
2622 {
2623         int rc = 0;
2624
2625         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2626         p_hwfn->qm_info.pf_wfq = min_bw;
2627
2628         if (!p_link->line_speed)
2629                 return rc;
2630
2631         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2632
2633         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2634
2635         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2636                    "Configured MIN bandwidth to be %d Mb/sec\n",
2637                    p_link->min_pf_rate);
2638
2639         return rc;
2640 }
2641
2642 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2643 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2644 {
2645         int i, rc = -EINVAL;
2646
2647         if (min_bw < 1 || min_bw > 100) {
2648                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2649                 return rc;
2650         }
2651
2652         for_each_hwfn(cdev, i) {
2653                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2654                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2655                 struct qed_mcp_link_state *p_link;
2656                 struct qed_ptt *p_ptt;
2657
2658                 p_link = &p_lead->mcp_info->link_output;
2659
2660                 p_ptt = qed_ptt_acquire(p_hwfn);
2661                 if (!p_ptt)
2662                         return -EBUSY;
2663
2664                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2665                                                       p_link, min_bw);
2666                 if (rc) {
2667                         qed_ptt_release(p_hwfn, p_ptt);
2668                         return rc;
2669                 }
2670
2671                 if (p_link->min_pf_rate) {
2672                         u32 min_rate = p_link->min_pf_rate;
2673
2674                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2675                                                                    p_ptt,
2676                                                                    min_rate);
2677                 }
2678
2679                 qed_ptt_release(p_hwfn, p_ptt);
2680         }
2681
2682         return rc;
2683 }
2684
2685 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2686 {
2687         struct qed_mcp_link_state *p_link;
2688
2689         p_link = &p_hwfn->mcp_info->link_output;
2690
2691         if (p_link->min_pf_rate)
2692                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2693                                                p_link->min_pf_rate);
2694
2695         memset(p_hwfn->qm_info.wfq_data, 0,
2696                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
2697 }