1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <linux/bitops.h>
39 #include <linux/delay.h>
40 #include <linux/kernel.h>
41 #include <linux/list.h>
42 #include <linux/slab.h>
43 #include <linux/qed/common_hsi.h>
44 #include <linux/qed/storage_common.h>
45 #include <linux/qed/tcp_common.h>
46 #include <linux/qed/fcoe_common.h>
47 #include <linux/qed/eth_common.h>
48 #include <linux/qed/iscsi_common.h>
49 #include <linux/qed/rdma_common.h>
50 #include <linux/qed/roce_common.h>
51 #include <linux/qed/qed_fcoe_if.h>
56 /* opcodes for the event ring */
57 enum common_event_opcode {
58 COMMON_EVENT_PF_START,
60 COMMON_EVENT_VF_START,
62 COMMON_EVENT_VF_PF_CHANNEL,
64 COMMON_EVENT_PF_UPDATE,
65 COMMON_EVENT_MALICIOUS_VF,
66 COMMON_EVENT_RL_UPDATE,
68 MAX_COMMON_EVENT_OPCODE
71 /* Common Ramrod Command IDs */
72 enum common_ramrod_cmd_id {
74 COMMON_RAMROD_PF_START,
75 COMMON_RAMROD_PF_STOP,
76 COMMON_RAMROD_VF_START,
77 COMMON_RAMROD_VF_STOP,
78 COMMON_RAMROD_PF_UPDATE,
79 COMMON_RAMROD_RL_UPDATE,
81 MAX_COMMON_RAMROD_CMD_ID
84 /* The core storm context for the Ystorm */
85 struct ystorm_core_conn_st_ctx {
89 /* The core storm context for the Pstorm */
90 struct pstorm_core_conn_st_ctx {
94 /* Core Slowpath Connection storm context of Xstorm */
95 struct xstorm_core_conn_st_ctx {
98 struct regpair consolid_base_addr;
100 __le16 consolid_cons;
101 __le32 reserved0[55];
104 struct xstorm_core_conn_ag_ctx {
108 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
109 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
110 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
111 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
112 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
113 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
114 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
115 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
116 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
117 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
118 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
119 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
120 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
121 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
122 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
123 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
125 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
126 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
127 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
128 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
129 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
130 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
131 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
132 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
133 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
134 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
135 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
136 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
137 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
138 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
139 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
140 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
142 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
143 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
144 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
145 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
146 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
147 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
148 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
149 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
151 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
152 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
153 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
154 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
155 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
156 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
157 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
158 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
160 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
161 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
162 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
163 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
164 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
165 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
166 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
167 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
169 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
170 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
171 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
172 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
173 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
174 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
175 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
176 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
178 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
179 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
180 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
181 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
182 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
183 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
184 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
185 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
187 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
188 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
189 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
190 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
191 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
192 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
193 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
194 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
195 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
196 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
198 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
199 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
200 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
201 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
202 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
203 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
204 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
205 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
206 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
207 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
208 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
209 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
210 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
211 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
212 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
213 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
215 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
216 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
217 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
218 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
219 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
220 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
221 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
222 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
223 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
224 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
225 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
226 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
227 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
228 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
229 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
230 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
232 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
233 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
234 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
235 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
236 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
237 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
238 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
239 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
240 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
241 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
242 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
243 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
244 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
245 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
246 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
247 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
249 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
250 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
251 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
252 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
253 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
254 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
255 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
256 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
257 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
258 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
259 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
260 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
263 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
264 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
266 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
267 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
268 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
269 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
270 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
271 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
272 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
273 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
274 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
275 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
276 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
277 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
278 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
279 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
280 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
281 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
283 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
284 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
285 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
286 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
287 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
288 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
289 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
290 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
291 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
292 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
293 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
294 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
295 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
296 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
297 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
298 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
300 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
301 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
302 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
303 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
304 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
305 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
306 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
307 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
308 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
309 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
310 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
311 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
312 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
313 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
316 __le16 consolid_prod;
319 __le16 tx_bd_or_spq_prod;
367 struct tstorm_core_conn_ag_ctx {
371 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
372 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
373 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
374 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
375 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
376 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
377 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
378 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
379 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
380 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
381 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
382 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
383 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
384 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
386 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
387 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
388 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
389 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
390 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
391 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
392 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
393 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
395 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
396 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
397 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
398 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
399 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
400 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
401 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
402 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
404 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
405 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
406 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
407 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
408 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
409 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
410 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
411 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
412 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
413 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
414 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
415 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
417 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
418 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
419 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
420 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
421 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
422 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
423 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
424 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
425 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
426 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
427 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
428 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
429 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
430 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
431 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
432 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
434 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
435 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
436 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
437 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
438 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
439 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
440 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
441 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
442 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
443 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
444 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
445 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
446 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
447 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
448 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
449 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
471 struct ustorm_core_conn_ag_ctx {
475 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
476 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
477 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
478 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
479 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
480 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
481 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
482 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
483 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
484 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
486 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
487 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
488 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
489 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
490 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
491 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
492 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
493 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
495 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
496 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
497 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
498 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
499 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
500 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
501 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
502 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
503 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
504 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
505 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
506 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
507 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
508 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
509 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
510 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
512 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
513 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
514 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
515 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
516 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
517 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
518 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
519 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
520 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
521 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
522 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
523 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
524 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
525 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
526 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
527 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
540 /* The core storm context for the Mstorm */
541 struct mstorm_core_conn_st_ctx {
545 /* The core storm context for the Ustorm */
546 struct ustorm_core_conn_st_ctx {
550 /* core connection context */
551 struct core_conn_context {
552 struct ystorm_core_conn_st_ctx ystorm_st_context;
553 struct regpair ystorm_st_padding[2];
554 struct pstorm_core_conn_st_ctx pstorm_st_context;
555 struct regpair pstorm_st_padding[2];
556 struct xstorm_core_conn_st_ctx xstorm_st_context;
557 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
558 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
559 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
560 struct mstorm_core_conn_st_ctx mstorm_st_context;
561 struct ustorm_core_conn_st_ctx ustorm_st_context;
562 struct regpair ustorm_st_padding[2];
565 enum core_error_handle {
569 MAX_CORE_ERROR_HANDLE
572 enum core_event_opcode {
573 CORE_EVENT_TX_QUEUE_START,
574 CORE_EVENT_TX_QUEUE_STOP,
575 CORE_EVENT_RX_QUEUE_START,
576 CORE_EVENT_RX_QUEUE_STOP,
577 CORE_EVENT_RX_QUEUE_FLUSH,
578 MAX_CORE_EVENT_OPCODE
581 enum core_l4_pseudo_checksum_mode {
582 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
583 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
584 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
587 struct core_ll2_port_stats {
588 struct regpair gsi_invalid_hdr;
589 struct regpair gsi_invalid_pkt_length;
590 struct regpair gsi_unsupported_pkt_typ;
591 struct regpair gsi_crcchksm_error;
594 struct core_ll2_pstorm_per_queue_stat {
595 struct regpair sent_ucast_bytes;
596 struct regpair sent_mcast_bytes;
597 struct regpair sent_bcast_bytes;
598 struct regpair sent_ucast_pkts;
599 struct regpair sent_mcast_pkts;
600 struct regpair sent_bcast_pkts;
603 struct core_ll2_rx_prod {
609 struct core_ll2_tstorm_per_queue_stat {
610 struct regpair packet_too_big_discard;
611 struct regpair no_buff_discard;
614 struct core_ll2_ustorm_per_queue_stat {
615 struct regpair rcv_ucast_bytes;
616 struct regpair rcv_mcast_bytes;
617 struct regpair rcv_bcast_bytes;
618 struct regpair rcv_ucast_pkts;
619 struct regpair rcv_mcast_pkts;
620 struct regpair rcv_bcast_pkts;
623 enum core_ramrod_cmd_id {
625 CORE_RAMROD_RX_QUEUE_START,
626 CORE_RAMROD_TX_QUEUE_START,
627 CORE_RAMROD_RX_QUEUE_STOP,
628 CORE_RAMROD_TX_QUEUE_STOP,
629 CORE_RAMROD_RX_QUEUE_FLUSH,
630 MAX_CORE_RAMROD_CMD_ID
633 enum core_roce_flavor_type {
636 MAX_CORE_ROCE_FLAVOR_TYPE
639 struct core_rx_action_on_error {
641 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
642 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
643 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
644 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
645 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
646 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
654 struct core_rx_bd_with_buff_len {
660 union core_rx_bd_union {
661 struct core_rx_bd rx_bd;
662 struct core_rx_bd_with_buff_len rx_bd_with_len;
665 struct core_rx_cqe_opaque_data {
669 enum core_rx_cqe_type {
670 CORE_RX_CQE_ILLIGAL_TYPE,
671 CORE_RX_CQE_TYPE_REGULAR,
672 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
673 CORE_RX_CQE_TYPE_SLOW_PATH,
677 struct core_rx_fast_path_cqe {
680 struct parsing_and_err_flags parse_flags;
681 __le16 packet_length;
683 struct core_rx_cqe_opaque_data opaque_data;
687 struct core_rx_gsi_offload_cqe {
689 u8 data_length_error;
690 struct parsing_and_err_flags parse_flags;
693 __le32 src_mac_addrhi;
694 __le16 src_mac_addrlo;
699 struct core_rx_slow_path_cqe {
703 struct core_rx_cqe_opaque_data opaque_data;
707 union core_rx_cqe_union {
708 struct core_rx_fast_path_cqe rx_cqe_fp;
709 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
710 struct core_rx_slow_path_cqe rx_cqe_sp;
713 struct core_rx_start_ramrod_data {
714 struct regpair bd_base;
715 struct regpair cqe_pbl_addr;
720 u8 complete_event_flg;
722 __le16 num_of_pbl_pages;
723 u8 inner_vlan_removal_en;
726 u8 mf_si_bcast_accept_all;
727 u8 mf_si_mcast_accept_all;
728 struct core_rx_action_on_error action_on_error;
733 struct core_rx_stop_ramrod_data {
735 u8 complete_event_flg;
741 struct core_tx_bd_data {
743 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
744 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
745 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
746 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
747 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
748 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
749 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
750 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
751 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
752 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
753 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
754 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
755 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
756 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
757 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
758 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
759 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
760 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
761 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
762 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
763 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
764 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
765 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
766 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
772 __le16 nw_vlan_or_lb_echo;
773 struct core_tx_bd_data bd_data;
775 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
776 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
777 #define CORE_TX_BD_TX_DST_MASK 0x1
778 #define CORE_TX_BD_TX_DST_SHIFT 14
779 #define CORE_TX_BD_RESERVED_MASK 0x1
780 #define CORE_TX_BD_RESERVED_SHIFT 15
789 struct core_tx_start_ramrod_data {
790 struct regpair pbl_base_addr;
803 struct core_tx_stop_ramrod_data {
807 enum dcb_dhcp_update_flag {
808 DONT_UPDATE_DCB_DHCP,
812 MAX_DCB_DHCP_UPDATE_FLAG
815 struct eth_mstorm_per_pf_stat {
816 struct regpair gre_discard_pkts;
817 struct regpair vxlan_discard_pkts;
818 struct regpair geneve_discard_pkts;
819 struct regpair lb_discard_pkts;
822 struct eth_mstorm_per_queue_stat {
823 struct regpair ttl0_discard;
824 struct regpair packet_too_big_discard;
825 struct regpair no_buff_discard;
826 struct regpair not_active_discard;
827 struct regpair tpa_coalesced_pkts;
828 struct regpair tpa_coalesced_events;
829 struct regpair tpa_aborts_num;
830 struct regpair tpa_coalesced_bytes;
833 /* Ethernet TX Per PF */
834 struct eth_pstorm_per_pf_stat {
835 struct regpair sent_lb_ucast_bytes;
836 struct regpair sent_lb_mcast_bytes;
837 struct regpair sent_lb_bcast_bytes;
838 struct regpair sent_lb_ucast_pkts;
839 struct regpair sent_lb_mcast_pkts;
840 struct regpair sent_lb_bcast_pkts;
841 struct regpair sent_gre_bytes;
842 struct regpair sent_vxlan_bytes;
843 struct regpair sent_geneve_bytes;
844 struct regpair sent_gre_pkts;
845 struct regpair sent_vxlan_pkts;
846 struct regpair sent_geneve_pkts;
847 struct regpair gre_drop_pkts;
848 struct regpair vxlan_drop_pkts;
849 struct regpair geneve_drop_pkts;
852 /* Ethernet TX Per Queue Stats */
853 struct eth_pstorm_per_queue_stat {
854 struct regpair sent_ucast_bytes;
855 struct regpair sent_mcast_bytes;
856 struct regpair sent_bcast_bytes;
857 struct regpair sent_ucast_pkts;
858 struct regpair sent_mcast_pkts;
859 struct regpair sent_bcast_pkts;
860 struct regpair error_drop_pkts;
863 /* ETH Rx producers data */
864 struct eth_rx_rate_limit {
872 struct eth_ustorm_per_pf_stat {
873 struct regpair rcv_lb_ucast_bytes;
874 struct regpair rcv_lb_mcast_bytes;
875 struct regpair rcv_lb_bcast_bytes;
876 struct regpair rcv_lb_ucast_pkts;
877 struct regpair rcv_lb_mcast_pkts;
878 struct regpair rcv_lb_bcast_pkts;
879 struct regpair rcv_gre_bytes;
880 struct regpair rcv_vxlan_bytes;
881 struct regpair rcv_geneve_bytes;
882 struct regpair rcv_gre_pkts;
883 struct regpair rcv_vxlan_pkts;
884 struct regpair rcv_geneve_pkts;
887 struct eth_ustorm_per_queue_stat {
888 struct regpair rcv_ucast_bytes;
889 struct regpair rcv_mcast_bytes;
890 struct regpair rcv_bcast_bytes;
891 struct regpair rcv_ucast_pkts;
892 struct regpair rcv_mcast_pkts;
893 struct regpair rcv_bcast_pkts;
896 /* Event Ring Next Page Address */
897 struct event_ring_next_addr {
902 /* Event Ring Element */
903 union event_ring_element {
904 struct event_ring_entry entry;
905 struct event_ring_next_addr next_addr;
908 enum fw_flow_ctrl_mode {
911 MAX_FW_FLOW_CTRL_MODE
914 /* Major and Minor hsi Versions */
915 struct hsi_fp_ver_struct {
920 /* Mstorm non-triggering VF zone */
921 enum malicious_vf_error_id {
922 MALICIOUS_VF_NO_ERROR,
923 VF_PF_CHANNEL_NOT_READY,
924 VF_ZONE_MSG_NOT_VALID,
925 VF_ZONE_FUNC_NOT_ENABLED,
926 ETH_PACKET_TOO_SMALL,
927 ETH_ILLEGAL_VLAN_MODE,
929 ETH_ILLEGAL_INBAND_TAGS,
930 ETH_VLAN_INSERT_AND_INBAND_VLAN,
933 ETH_INSUFFICIENT_BDS,
934 ETH_ILLEGAL_LSO_HDR_NBDS,
937 ETH_ILLEGAL_LSO_HDR_LEN,
938 ETH_INSUFFICIENT_PAYLOAD,
939 ETH_EDPM_OUT_OF_SYNC,
940 ETH_TUNN_IPV6_EXT_NBD_ERR,
941 ETH_CONTROL_PACKET_VIOLATION,
942 ETH_ANTI_SPOOFING_ERR,
943 MAX_MALICIOUS_VF_ERROR_ID
946 struct mstorm_non_trigger_vf_zone {
947 struct eth_mstorm_per_queue_stat eth_queue_stat;
948 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
952 struct mstorm_vf_zone {
953 struct mstorm_non_trigger_vf_zone non_trigger;
957 /* personality per PF */
958 enum personality_type {
962 PERSONALITY_RDMA_AND_ETH,
963 PERSONALITY_RESERVED3,
966 PERSONALITY_RESERVED4,
970 /* tunnel configuration */
971 struct pf_start_tunnel_config {
972 u8 set_vxlan_udp_port_flg;
973 u8 set_geneve_udp_port_flg;
975 u8 tx_enable_l2geneve;
976 u8 tx_enable_ipgeneve;
979 u8 tunnel_clss_vxlan;
980 u8 tunnel_clss_l2geneve;
981 u8 tunnel_clss_ipgeneve;
982 u8 tunnel_clss_l2gre;
983 u8 tunnel_clss_ipgre;
984 __le16 vxlan_udp_port;
985 __le16 geneve_udp_port;
988 /* Ramrod data for PF start ramrod */
989 struct pf_start_ramrod_data {
990 struct regpair event_ring_pbl_addr;
991 struct regpair consolid_q_pbl_addr;
992 struct pf_start_tunnel_config tunnel_config;
993 __le16 event_ring_sb_id;
996 u8 event_ring_num_pages;
997 u8 event_ring_sb_index;
1000 u8 dont_log_ramrods;
1002 __le16 log_type_mask;
1005 u8 allow_npar_tx_switching;
1006 u8 inner_to_outer_pri_map[8];
1009 struct hsi_fp_ver_struct hsi_fp_ver;
1013 struct protocol_dcb_data {
1022 struct pf_update_tunnel_config {
1023 u8 update_rx_pf_clss;
1024 u8 update_rx_def_ucast_clss;
1025 u8 update_rx_def_non_ucast_clss;
1026 u8 update_tx_pf_clss;
1027 u8 set_vxlan_udp_port_flg;
1028 u8 set_geneve_udp_port_flg;
1030 u8 tx_enable_l2geneve;
1031 u8 tx_enable_ipgeneve;
1034 u8 tunnel_clss_vxlan;
1035 u8 tunnel_clss_l2geneve;
1036 u8 tunnel_clss_ipgeneve;
1037 u8 tunnel_clss_l2gre;
1038 u8 tunnel_clss_ipgre;
1039 __le16 vxlan_udp_port;
1040 __le16 geneve_udp_port;
1044 struct pf_update_ramrod_data {
1046 u8 update_eth_dcb_data_flag;
1047 u8 update_fcoe_dcb_data_flag;
1048 u8 update_iscsi_dcb_data_flag;
1049 u8 update_roce_dcb_data_flag;
1050 u8 update_rroce_dcb_data_flag;
1051 u8 update_iwarp_dcb_data_flag;
1052 u8 update_mf_vlan_flag;
1053 struct protocol_dcb_data eth_dcb_data;
1054 struct protocol_dcb_data fcoe_dcb_data;
1055 struct protocol_dcb_data iscsi_dcb_data;
1056 struct protocol_dcb_data roce_dcb_data;
1057 struct protocol_dcb_data rroce_dcb_data;
1058 struct protocol_dcb_data iwarp_dcb_data;
1061 struct pf_update_tunnel_config tunnel_config;
1074 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1075 enum protocol_version_array_key {
1078 MAX_PROTOCOL_VERSION_ARRAY_KEY
1081 struct rdma_sent_stats {
1082 struct regpair sent_bytes;
1083 struct regpair sent_pkts;
1086 struct pstorm_non_trigger_vf_zone {
1087 struct eth_pstorm_per_queue_stat eth_queue_stat;
1088 struct rdma_sent_stats rdma_stats;
1091 /* Pstorm VF zone */
1092 struct pstorm_vf_zone {
1093 struct pstorm_non_trigger_vf_zone non_trigger;
1094 struct regpair reserved[7];
1097 /* Ramrod Header of SPQE */
1098 struct ramrod_header {
1105 struct rdma_rcv_stats {
1106 struct regpair rcv_bytes;
1107 struct regpair rcv_pkts;
1110 struct slow_path_element {
1111 struct ramrod_header hdr;
1112 struct regpair data_ptr;
1115 /* Tstorm non-triggering VF zone */
1116 struct tstorm_non_trigger_vf_zone {
1117 struct rdma_rcv_stats rdma_stats;
1120 struct tstorm_per_port_stat {
1121 struct regpair trunc_error_discard;
1122 struct regpair mac_error_discard;
1123 struct regpair mftag_filter_discard;
1124 struct regpair eth_mac_filter_discard;
1125 struct regpair ll2_mac_filter_discard;
1126 struct regpair ll2_conn_disabled_discard;
1127 struct regpair iscsi_irregular_pkt;
1128 struct regpair fcoe_irregular_pkt;
1129 struct regpair roce_irregular_pkt;
1130 struct regpair reserved;
1131 struct regpair eth_irregular_pkt;
1132 struct regpair reserved1;
1133 struct regpair preroce_irregular_pkt;
1134 struct regpair eth_gre_tunn_filter_discard;
1135 struct regpair eth_vxlan_tunn_filter_discard;
1136 struct regpair eth_geneve_tunn_filter_discard;
1139 /* Tstorm VF zone */
1140 struct tstorm_vf_zone {
1141 struct tstorm_non_trigger_vf_zone non_trigger;
1144 /* Tunnel classification scheme */
1146 TUNNEL_CLSS_MAC_VLAN = 0,
1147 TUNNEL_CLSS_MAC_VNI,
1148 TUNNEL_CLSS_INNER_MAC_VLAN,
1149 TUNNEL_CLSS_INNER_MAC_VNI,
1150 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1154 /* Ustorm non-triggering VF zone */
1155 struct ustorm_non_trigger_vf_zone {
1156 struct eth_ustorm_per_queue_stat eth_queue_stat;
1157 struct regpair vf_pf_msg_addr;
1160 /* Ustorm triggering VF zone */
1161 struct ustorm_trigger_vf_zone {
1166 /* Ustorm VF zone */
1167 struct ustorm_vf_zone {
1168 struct ustorm_non_trigger_vf_zone non_trigger;
1169 struct ustorm_trigger_vf_zone trigger;
1172 /* VF-PF channel data */
1173 struct vf_pf_channel_data {
1180 /* Ramrod data for VF start ramrod */
1181 struct vf_start_ramrod_data {
1187 struct hsi_fp_ver_struct hsi_fp_ver;
1191 /* Ramrod data for VF start ramrod */
1192 struct vf_stop_ramrod_data {
1199 enum vf_zone_size_mode {
1200 VF_ZONE_SIZE_MODE_DEFAULT,
1201 VF_ZONE_SIZE_MODE_DOUBLE,
1202 VF_ZONE_SIZE_MODE_QUAD,
1203 MAX_VF_ZONE_SIZE_MODE
1206 struct atten_status_block {
1214 enum command_type_bit {
1215 IGU_COMMAND_TYPE_NOP = 0,
1216 IGU_COMMAND_TYPE_SET = 1,
1217 MAX_COMMAND_TYPE_BIT
1223 #define DMAE_CMD_SRC_MASK 0x1
1224 #define DMAE_CMD_SRC_SHIFT 0
1225 #define DMAE_CMD_DST_MASK 0x3
1226 #define DMAE_CMD_DST_SHIFT 1
1227 #define DMAE_CMD_C_DST_MASK 0x1
1228 #define DMAE_CMD_C_DST_SHIFT 3
1229 #define DMAE_CMD_CRC_RESET_MASK 0x1
1230 #define DMAE_CMD_CRC_RESET_SHIFT 4
1231 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1232 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1233 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1234 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1235 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1236 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1237 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1238 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1239 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1240 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1241 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1242 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1243 #define DMAE_CMD_RESERVED1_MASK 0x1
1244 #define DMAE_CMD_RESERVED1_SHIFT 13
1245 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1246 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1247 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1248 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1249 #define DMAE_CMD_PORT_ID_MASK 0x3
1250 #define DMAE_CMD_PORT_ID_SHIFT 18
1251 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1252 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1253 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1254 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1255 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1256 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1257 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1258 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1259 #define DMAE_CMD_RESERVED2_MASK 0x3
1260 #define DMAE_CMD_RESERVED2_SHIFT 30
1267 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1268 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1269 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1270 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1271 __le32 comp_addr_lo;
1272 __le32 comp_addr_hi;
1284 enum dmae_cmd_comp_crc_en_enum {
1285 dmae_cmd_comp_crc_disabled,
1286 dmae_cmd_comp_crc_enabled,
1287 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1290 enum dmae_cmd_comp_func_enum {
1291 dmae_cmd_comp_func_to_src,
1292 dmae_cmd_comp_func_to_dst,
1293 MAX_DMAE_CMD_COMP_FUNC_ENUM
1296 enum dmae_cmd_comp_word_en_enum {
1297 dmae_cmd_comp_word_disabled,
1298 dmae_cmd_comp_word_enabled,
1299 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1302 enum dmae_cmd_c_dst_enum {
1303 dmae_cmd_c_dst_pcie,
1305 MAX_DMAE_CMD_C_DST_ENUM
1308 enum dmae_cmd_dst_enum {
1309 dmae_cmd_dst_none_0,
1312 dmae_cmd_dst_none_3,
1313 MAX_DMAE_CMD_DST_ENUM
1316 enum dmae_cmd_error_handling_enum {
1317 dmae_cmd_error_handling_send_regular_comp,
1318 dmae_cmd_error_handling_send_comp_with_err,
1319 dmae_cmd_error_handling_dont_send_comp,
1320 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1323 enum dmae_cmd_src_enum {
1326 MAX_DMAE_CMD_SRC_ENUM
1329 /* IGU cleanup command */
1330 struct igu_cleanup {
1331 __le32 sb_id_and_flags;
1332 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1333 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1334 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1335 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1336 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1337 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1338 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1339 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1343 /* IGU firmware driver command */
1345 struct igu_prod_cons_update prod_cons_update;
1346 struct igu_cleanup cleanup;
1349 /* IGU firmware driver command */
1350 struct igu_command_reg_ctrl {
1352 __le16 igu_command_reg_ctrl_fields;
1353 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1354 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1355 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1356 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1357 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1358 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1361 /* IGU mapping line structure */
1362 struct igu_mapping_line {
1363 __le32 igu_mapping_line_fields;
1364 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1365 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1366 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1367 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1368 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1369 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1370 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1371 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1372 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1373 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1374 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1375 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1378 /* IGU MSIX line structure */
1379 struct igu_msix_vector {
1380 struct regpair address;
1382 __le32 msix_vector_fields;
1383 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1384 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1385 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1386 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1387 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1388 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1389 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1390 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1393 struct mstorm_core_conn_ag_ctx {
1397 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1398 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1399 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1400 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1401 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1402 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1403 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1404 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1405 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1406 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1408 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1409 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1410 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1411 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1412 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1413 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1414 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1415 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1416 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1417 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1418 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1419 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1420 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1421 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1422 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1423 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1430 /* per encapsulation type enabling flags */
1431 struct prs_reg_encapsulation_type_en {
1433 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1434 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1435 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1436 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1437 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1438 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1439 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1440 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1441 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1442 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1443 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1444 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1445 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1446 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1449 enum pxp_tph_st_hint {
1451 TPH_ST_HINT_REQUESTER,
1453 TPH_ST_HINT_TARGET_PRIO,
1457 /* QM hardware structure of enable bypass credit mask */
1458 struct qm_rf_bypass_mask {
1460 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1461 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1462 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1463 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1464 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1465 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1466 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1467 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1468 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1469 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1470 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1471 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1472 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1473 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1474 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1475 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1478 /* QM hardware structure of opportunistic credit mask */
1479 struct qm_rf_opportunistic_mask {
1481 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1482 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1483 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1484 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1485 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1486 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1487 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1488 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1489 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1490 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1491 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1492 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1493 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1494 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1495 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1496 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1497 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1498 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1499 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1500 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1503 /* QM hardware structure of QM map memory */
1504 struct qm_rf_pq_map {
1506 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1507 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1508 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1509 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1510 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1511 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1512 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1513 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
1514 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1515 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1516 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1517 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1518 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1519 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1522 /* Completion params for aggregated interrupt completion */
1523 struct sdm_agg_int_comp_params {
1525 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1526 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1527 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1528 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1529 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1530 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1533 /* SDM operation gen command (generate aggregative interrupt) */
1536 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1537 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1538 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1539 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1540 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
1541 #define SDM_OP_GEN_RESERVED_SHIFT 20
1544 struct ystorm_core_conn_ag_ctx {
1548 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1549 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1550 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1551 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1552 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1553 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1554 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1555 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1556 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1557 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1559 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1560 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1561 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1562 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1563 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1564 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1565 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1566 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1567 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1568 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1569 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1570 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1571 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1572 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1573 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1574 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1588 /****************************************/
1589 /* Debug Tools HSI constants and macros */
1590 /****************************************/
1593 GRCBASE_GRC = 0x50000,
1594 GRCBASE_MISCS = 0x9000,
1595 GRCBASE_MISC = 0x8000,
1596 GRCBASE_DBU = 0xa000,
1597 GRCBASE_PGLUE_B = 0x2a8000,
1598 GRCBASE_CNIG = 0x218000,
1599 GRCBASE_CPMU = 0x30000,
1600 GRCBASE_NCSI = 0x40000,
1601 GRCBASE_OPTE = 0x53000,
1602 GRCBASE_BMB = 0x540000,
1603 GRCBASE_PCIE = 0x54000,
1604 GRCBASE_MCP = 0xe00000,
1605 GRCBASE_MCP2 = 0x52000,
1606 GRCBASE_PSWHST = 0x2a0000,
1607 GRCBASE_PSWHST2 = 0x29e000,
1608 GRCBASE_PSWRD = 0x29c000,
1609 GRCBASE_PSWRD2 = 0x29d000,
1610 GRCBASE_PSWWR = 0x29a000,
1611 GRCBASE_PSWWR2 = 0x29b000,
1612 GRCBASE_PSWRQ = 0x280000,
1613 GRCBASE_PSWRQ2 = 0x240000,
1614 GRCBASE_PGLCS = 0x0,
1615 GRCBASE_DMAE = 0xc000,
1616 GRCBASE_PTU = 0x560000,
1617 GRCBASE_TCM = 0x1180000,
1618 GRCBASE_MCM = 0x1200000,
1619 GRCBASE_UCM = 0x1280000,
1620 GRCBASE_XCM = 0x1000000,
1621 GRCBASE_YCM = 0x1080000,
1622 GRCBASE_PCM = 0x1100000,
1623 GRCBASE_QM = 0x2f0000,
1624 GRCBASE_TM = 0x2c0000,
1625 GRCBASE_DORQ = 0x100000,
1626 GRCBASE_BRB = 0x340000,
1627 GRCBASE_SRC = 0x238000,
1628 GRCBASE_PRS = 0x1f0000,
1629 GRCBASE_TSDM = 0xfb0000,
1630 GRCBASE_MSDM = 0xfc0000,
1631 GRCBASE_USDM = 0xfd0000,
1632 GRCBASE_XSDM = 0xf80000,
1633 GRCBASE_YSDM = 0xf90000,
1634 GRCBASE_PSDM = 0xfa0000,
1635 GRCBASE_TSEM = 0x1700000,
1636 GRCBASE_MSEM = 0x1800000,
1637 GRCBASE_USEM = 0x1900000,
1638 GRCBASE_XSEM = 0x1400000,
1639 GRCBASE_YSEM = 0x1500000,
1640 GRCBASE_PSEM = 0x1600000,
1641 GRCBASE_RSS = 0x238800,
1642 GRCBASE_TMLD = 0x4d0000,
1643 GRCBASE_MULD = 0x4e0000,
1644 GRCBASE_YULD = 0x4c8000,
1645 GRCBASE_XYLD = 0x4c0000,
1646 GRCBASE_PRM = 0x230000,
1647 GRCBASE_PBF_PB1 = 0xda0000,
1648 GRCBASE_PBF_PB2 = 0xda4000,
1649 GRCBASE_RPB = 0x23c000,
1650 GRCBASE_BTB = 0xdb0000,
1651 GRCBASE_PBF = 0xd80000,
1652 GRCBASE_RDIF = 0x300000,
1653 GRCBASE_TDIF = 0x310000,
1654 GRCBASE_CDU = 0x580000,
1655 GRCBASE_CCFC = 0x2e0000,
1656 GRCBASE_TCFC = 0x2d0000,
1657 GRCBASE_IGU = 0x180000,
1658 GRCBASE_CAU = 0x1c0000,
1659 GRCBASE_UMAC = 0x51000,
1660 GRCBASE_XMAC = 0x210000,
1661 GRCBASE_DBG = 0x10000,
1662 GRCBASE_NIG = 0x500000,
1663 GRCBASE_WOL = 0x600000,
1664 GRCBASE_BMBN = 0x610000,
1665 GRCBASE_IPC = 0x20000,
1666 GRCBASE_NWM = 0x800000,
1667 GRCBASE_NWS = 0x700000,
1668 GRCBASE_MS = 0x6a0000,
1669 GRCBASE_PHY_PCIE = 0x620000,
1670 GRCBASE_LED = 0x6b8000,
1671 GRCBASE_AVS_WRAP = 0x6b0000,
1672 GRCBASE_RGFS = 0x19d0000,
1673 GRCBASE_TGFS = 0x19e0000,
1674 GRCBASE_PTLD = 0x19f0000,
1675 GRCBASE_YPLD = 0x1a10000,
1676 GRCBASE_MISC_AEU = 0x8000,
1677 GRCBASE_BAR0_MAP = 0x1c00000,
1770 /* binary debug buffer types */
1771 enum bin_dbg_buffer_type {
1772 BIN_BUF_DBG_MODE_TREE,
1773 BIN_BUF_DBG_DUMP_REG,
1774 BIN_BUF_DBG_DUMP_MEM,
1775 BIN_BUF_DBG_IDLE_CHK_REGS,
1776 BIN_BUF_DBG_IDLE_CHK_IMMS,
1777 BIN_BUF_DBG_IDLE_CHK_RULES,
1778 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1779 BIN_BUF_DBG_ATTN_BLOCKS,
1780 BIN_BUF_DBG_ATTN_REGS,
1781 BIN_BUF_DBG_ATTN_INDEXES,
1782 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1783 BIN_BUF_DBG_PARSING_STRINGS,
1784 MAX_BIN_DBG_BUFFER_TYPE
1788 /* Attention bit mapping */
1789 struct dbg_attn_bit_mapping {
1791 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1792 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1793 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1794 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
1797 /* Attention block per-type data */
1798 struct dbg_attn_block_type_data {
1799 __le16 names_offset;
1806 /* Block attentions */
1807 struct dbg_attn_block {
1808 struct dbg_attn_block_type_data per_type_data[2];
1811 /* Attention register result */
1812 struct dbg_attn_reg_result {
1814 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1815 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
1816 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
1817 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
1818 __le16 block_attn_offset;
1824 /* Attention block result */
1825 struct dbg_attn_block_result {
1828 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
1829 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
1830 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
1831 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
1832 __le16 names_offset;
1833 struct dbg_attn_reg_result reg_results[15];
1837 struct dbg_mode_hdr {
1839 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
1840 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
1841 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
1842 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
1845 /* Attention register */
1846 struct dbg_attn_reg {
1847 struct dbg_mode_hdr mode;
1848 __le16 block_attn_offset;
1850 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
1851 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
1852 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
1853 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
1854 __le32 sts_clr_address;
1855 __le32 mask_address;
1858 /* attention types */
1859 enum dbg_attn_type {
1860 ATTN_TYPE_INTERRUPT,
1865 /* condition header for registers dump */
1866 struct dbg_dump_cond_hdr {
1867 struct dbg_mode_hdr mode; /* Mode header */
1868 u8 block_id; /* block ID */
1869 u8 data_size; /* size in dwords of the data following this header */
1872 /* memory data for registers dump */
1873 struct dbg_dump_mem {
1875 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
1876 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
1877 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
1878 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
1880 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
1881 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
1882 #define DBG_DUMP_MEM_RESERVED_MASK 0xFF
1883 #define DBG_DUMP_MEM_RESERVED_SHIFT 24
1886 /* register data for registers dump */
1887 struct dbg_dump_reg {
1889 #define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */
1890 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
1891 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
1892 #define DBG_DUMP_REG_LENGTH_SHIFT 24
1895 /* split header for registers dump */
1896 struct dbg_dump_split_hdr {
1898 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
1899 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
1900 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
1901 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
1904 /* condition header for idle check */
1905 struct dbg_idle_chk_cond_hdr {
1906 struct dbg_mode_hdr mode; /* Mode header */
1907 __le16 data_size; /* size in dwords of the data following this header */
1910 /* Idle Check condition register */
1911 struct dbg_idle_chk_cond_reg {
1913 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF
1914 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
1915 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
1916 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
1917 __le16 num_entries; /* number of registers entries to check */
1918 u8 entry_size; /* size of registers entry (in dwords) */
1919 u8 start_entry; /* index of the first entry to check */
1922 /* Idle Check info register */
1923 struct dbg_idle_chk_info_reg {
1925 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF
1926 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
1927 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
1928 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
1929 __le16 size; /* register size in dwords */
1930 struct dbg_mode_hdr mode; /* Mode header */
1933 /* Idle Check register */
1934 union dbg_idle_chk_reg {
1935 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
1936 struct dbg_idle_chk_info_reg info_reg; /* info register */
1939 /* Idle Check result header */
1940 struct dbg_idle_chk_result_hdr {
1941 __le16 rule_id; /* Failing rule index */
1942 __le16 mem_entry_id; /* Failing memory entry index */
1943 u8 num_dumped_cond_regs; /* number of dumped condition registers */
1944 u8 num_dumped_info_regs; /* number of dumped condition registers */
1945 u8 severity; /* from dbg_idle_chk_severity_types enum */
1949 /* Idle Check result register header */
1950 struct dbg_idle_chk_result_reg_hdr {
1952 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
1953 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
1954 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
1955 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
1956 u8 start_entry; /* index of the first checked entry */
1957 __le16 size; /* register size in dwords */
1960 /* Idle Check rule */
1961 struct dbg_idle_chk_rule {
1962 __le16 rule_id; /* Idle Check rule ID */
1963 u8 severity; /* value from dbg_idle_chk_severity_types enum */
1964 u8 cond_id; /* Condition ID */
1965 u8 num_cond_regs; /* number of condition registers */
1966 u8 num_info_regs; /* number of info registers */
1967 u8 num_imms; /* number of immediates in the condition */
1969 __le16 reg_offset; /* offset of this rules registers in the idle check
1970 * register array (in dbg_idle_chk_reg units).
1972 __le16 imm_offset; /* offset of this rules immediate values in the
1973 * immediate values array (in dwords).
1977 /* Idle Check rule parsing data */
1978 struct dbg_idle_chk_rule_parsing_data {
1980 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
1981 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
1982 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
1983 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
1986 /* idle check severity types */
1987 enum dbg_idle_chk_severity_types {
1988 /* idle check failure should cause an error */
1989 IDLE_CHK_SEVERITY_ERROR,
1990 /* idle check failure should cause an error only if theres no traffic */
1991 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
1992 /* idle check failure should cause a warning */
1993 IDLE_CHK_SEVERITY_WARNING,
1994 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
1997 /* Debug Bus block data */
1998 struct dbg_bus_block_data {
1999 u8 enabled; /* Indicates if the block is enabled for recording (0/1) */
2000 u8 hw_id; /* HW ID associated with the block */
2001 u8 line_num; /* Debug line number to select */
2002 u8 right_shift; /* Number of units to right the debug data (0-3) */
2003 u8 cycle_en; /* 4-bit value: bit i set -> unit i is enabled. */
2004 u8 force_valid; /* 4-bit value: bit i set -> unit i is forced valid. */
2005 u8 force_frame; /* 4-bit value: bit i set -> unit i frame bit is forced.
2010 /* Debug Bus Clients */
2011 enum dbg_bus_clients {
2012 DBG_BUS_CLIENT_RBCN,
2013 DBG_BUS_CLIENT_RBCP,
2014 DBG_BUS_CLIENT_RBCR,
2015 DBG_BUS_CLIENT_RBCT,
2016 DBG_BUS_CLIENT_RBCU,
2017 DBG_BUS_CLIENT_RBCF,
2018 DBG_BUS_CLIENT_RBCX,
2019 DBG_BUS_CLIENT_RBCS,
2020 DBG_BUS_CLIENT_RBCH,
2021 DBG_BUS_CLIENT_RBCZ,
2022 DBG_BUS_CLIENT_OTHER_ENGINE,
2023 DBG_BUS_CLIENT_TIMESTAMP,
2025 DBG_BUS_CLIENT_RBCY,
2026 DBG_BUS_CLIENT_RBCQ,
2027 DBG_BUS_CLIENT_RBCM,
2028 DBG_BUS_CLIENT_RBCB,
2029 DBG_BUS_CLIENT_RBCW,
2030 DBG_BUS_CLIENT_RBCV,
2034 enum dbg_bus_constraint_ops {
2035 DBG_BUS_CONSTRAINT_OP_EQ,
2036 DBG_BUS_CONSTRAINT_OP_NE,
2037 DBG_BUS_CONSTRAINT_OP_LT,
2038 DBG_BUS_CONSTRAINT_OP_LTC,
2039 DBG_BUS_CONSTRAINT_OP_LE,
2040 DBG_BUS_CONSTRAINT_OP_LEC,
2041 DBG_BUS_CONSTRAINT_OP_GT,
2042 DBG_BUS_CONSTRAINT_OP_GTC,
2043 DBG_BUS_CONSTRAINT_OP_GE,
2044 DBG_BUS_CONSTRAINT_OP_GEC,
2045 MAX_DBG_BUS_CONSTRAINT_OPS
2048 /* Debug Bus memory address */
2049 struct dbg_bus_mem_addr {
2054 /* Debug Bus PCI buffer data */
2055 struct dbg_bus_pci_buf_data {
2056 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2057 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2058 __le32 size; /* PCI buffer size in bytes */
2061 /* Debug Bus Storm EID range filter params */
2062 struct dbg_bus_storm_eid_range_params {
2063 u8 min; /* Minimal event ID to filter on */
2064 u8 max; /* Maximal event ID to filter on */
2067 /* Debug Bus Storm EID mask filter params */
2068 struct dbg_bus_storm_eid_mask_params {
2069 u8 val; /* Event ID value */
2070 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2073 /* Debug Bus Storm EID filter params */
2074 union dbg_bus_storm_eid_params {
2075 struct dbg_bus_storm_eid_range_params range;
2076 struct dbg_bus_storm_eid_mask_params mask;
2079 /* Debug Bus Storm data */
2080 struct dbg_bus_storm_data {
2087 u8 eid_range_not_mask;
2089 union dbg_bus_storm_eid_params eid_filter_params;
2094 /* Debug Bus data */
2095 struct dbg_bus_data {
2096 __le32 app_version; /* The tools version number of the application */
2097 u8 state; /* The current debug bus state */
2098 u8 hw_dwords; /* HW dwords per cycle */
2099 u8 next_hw_id; /* Next HW ID to be associated with an input */
2100 u8 num_enabled_blocks; /* Number of blocks enabled for recording */
2101 u8 num_enabled_storms; /* Number of Storms enabled for recording */
2102 u8 target; /* Output target */
2103 u8 next_trigger_state; /* ID of next trigger state to be added */
2104 u8 next_constraint_id; /* ID of next filter/trigger constraint to be
2107 u8 one_shot_en; /* Indicates if one-shot mode is enabled (0/1) */
2108 u8 grc_input_en; /* Indicates if GRC recording is enabled (0/1) */
2109 u8 timestamp_input_en; /* Indicates if timestamp recording is enabled
2112 u8 filter_en; /* Indicates if the recording filter is enabled (0/1) */
2113 u8 trigger_en; /* Indicates if the recording trigger is enabled (0/1) */
2114 u8 adding_filter; /* If true, the next added constraint belong to the
2115 * filter. Otherwise, it belongs to the last added
2116 * trigger state. Valid only if either filter or
2117 * triggers are enabled.
2119 u8 filter_pre_trigger; /* Indicates if the recording filter should be
2120 * applied before the trigger. Valid only if both
2121 * filter and trigger are enabled (0/1).
2123 u8 filter_post_trigger; /* Indicates if the recording filter should be
2124 * applied after the trigger. Valid only if both
2125 * filter and trigger are enabled (0/1).
2127 u8 unify_inputs; /* If true, all inputs are associated with HW ID 0.
2128 * Otherwise, each input is assigned a different HW ID
2131 u8 rcv_from_other_engine; /* Indicates if the other engine sends it NW
2132 * recording to this engine (0/1).
2134 struct dbg_bus_pci_buf_data pci_buf; /* Debug Bus PCI buffer data. Valid
2135 * only when the target is
2136 * DBG_BUS_TARGET_ID_PCI.
2139 struct dbg_bus_block_data blocks[88];/* Debug Bus data for each block */
2140 struct dbg_bus_storm_data storms[6]; /* Debug Bus data for each block */
2143 enum dbg_bus_filter_types {
2144 DBG_BUS_FILTER_TYPE_OFF,
2145 DBG_BUS_FILTER_TYPE_PRE,
2146 DBG_BUS_FILTER_TYPE_POST,
2147 DBG_BUS_FILTER_TYPE_ON,
2148 MAX_DBG_BUS_FILTER_TYPES
2151 /* Debug bus frame modes */
2152 enum dbg_bus_frame_modes {
2153 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2154 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2155 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2156 MAX_DBG_BUS_FRAME_MODES
2159 enum dbg_bus_input_types {
2160 DBG_BUS_INPUT_TYPE_STORM,
2161 DBG_BUS_INPUT_TYPE_BLOCK,
2162 MAX_DBG_BUS_INPUT_TYPES
2165 enum dbg_bus_other_engine_modes {
2166 DBG_BUS_OTHER_ENGINE_MODE_NONE,
2167 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2168 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2169 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2170 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2171 MAX_DBG_BUS_OTHER_ENGINE_MODES
2174 enum dbg_bus_post_trigger_types {
2175 DBG_BUS_POST_TRIGGER_RECORD,
2176 DBG_BUS_POST_TRIGGER_DROP,
2177 MAX_DBG_BUS_POST_TRIGGER_TYPES
2180 enum dbg_bus_pre_trigger_types {
2181 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2182 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2183 DBG_BUS_PRE_TRIGGER_DROP,
2184 MAX_DBG_BUS_PRE_TRIGGER_TYPES
2187 enum dbg_bus_semi_frame_modes {
2188 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2189 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2190 MAX_DBG_BUS_SEMI_FRAME_MODES
2193 /* Debug bus states */
2194 enum dbg_bus_states {
2195 DBG_BUS_STATE_IDLE, /* debug bus idle state (not recording) */
2196 DBG_BUS_STATE_READY, /* debug bus is ready for configuration and
2199 DBG_BUS_STATE_RECORDING, /* debug bus is currently recording */
2200 DBG_BUS_STATE_STOPPED, /* debug bus recording has stopped */
2204 enum dbg_bus_storm_modes {
2205 DBG_BUS_STORM_MODE_PRINTF,
2206 DBG_BUS_STORM_MODE_PRAM_ADDR,
2207 DBG_BUS_STORM_MODE_DRA_RW,
2208 DBG_BUS_STORM_MODE_DRA_W,
2209 DBG_BUS_STORM_MODE_LD_ST_ADDR,
2210 DBG_BUS_STORM_MODE_DRA_FSM,
2211 DBG_BUS_STORM_MODE_RH,
2212 DBG_BUS_STORM_MODE_FOC,
2213 DBG_BUS_STORM_MODE_EXT_STORE,
2214 MAX_DBG_BUS_STORM_MODES
2217 /* Debug bus target IDs */
2218 enum dbg_bus_targets {
2219 /* records debug bus to DBG block internal buffer */
2220 DBG_BUS_TARGET_ID_INT_BUF,
2221 /* records debug bus to the NW */
2222 DBG_BUS_TARGET_ID_NIG,
2223 /* records debug bus to a PCI buffer */
2224 DBG_BUS_TARGET_ID_PCI,
2229 struct dbg_grc_data {
2230 u8 params_initialized;
2233 __le32 param_val[48];
2236 /* Debug GRC params */
2237 enum dbg_grc_params {
2238 DBG_GRC_PARAM_DUMP_TSTORM, /* dump Tstorm memories (0/1) */
2239 DBG_GRC_PARAM_DUMP_MSTORM, /* dump Mstorm memories (0/1) */
2240 DBG_GRC_PARAM_DUMP_USTORM, /* dump Ustorm memories (0/1) */
2241 DBG_GRC_PARAM_DUMP_XSTORM, /* dump Xstorm memories (0/1) */
2242 DBG_GRC_PARAM_DUMP_YSTORM, /* dump Ystorm memories (0/1) */
2243 DBG_GRC_PARAM_DUMP_PSTORM, /* dump Pstorm memories (0/1) */
2244 DBG_GRC_PARAM_DUMP_REGS, /* dump non-memory registers (0/1) */
2245 DBG_GRC_PARAM_DUMP_RAM, /* dump Storm internal RAMs (0/1) */
2246 DBG_GRC_PARAM_DUMP_PBUF, /* dump Storm passive buffer (0/1) */
2247 DBG_GRC_PARAM_DUMP_IOR, /* dump Storm IORs (0/1) */
2248 DBG_GRC_PARAM_DUMP_VFC, /* dump VFC memories (0/1) */
2249 DBG_GRC_PARAM_DUMP_CM_CTX, /* dump CM contexts (0/1) */
2250 DBG_GRC_PARAM_DUMP_PXP, /* dump PXP memories (0/1) */
2251 DBG_GRC_PARAM_DUMP_RSS, /* dump RSS memories (0/1) */
2252 DBG_GRC_PARAM_DUMP_CAU, /* dump CAU memories (0/1) */
2253 DBG_GRC_PARAM_DUMP_QM, /* dump QM memories (0/1) */
2254 DBG_GRC_PARAM_DUMP_MCP, /* dump MCP memories (0/1) */
2255 DBG_GRC_PARAM_RESERVED, /* reserved */
2256 DBG_GRC_PARAM_DUMP_CFC, /* dump CFC memories (0/1) */
2257 DBG_GRC_PARAM_DUMP_IGU, /* dump IGU memories (0/1) */
2258 DBG_GRC_PARAM_DUMP_BRB, /* dump BRB memories (0/1) */
2259 DBG_GRC_PARAM_DUMP_BTB, /* dump BTB memories (0/1) */
2260 DBG_GRC_PARAM_DUMP_BMB, /* dump BMB memories (0/1) */
2261 DBG_GRC_PARAM_DUMP_NIG, /* dump NIG memories (0/1) */
2262 DBG_GRC_PARAM_DUMP_MULD, /* dump MULD memories (0/1) */
2263 DBG_GRC_PARAM_DUMP_PRS, /* dump PRS memories (0/1) */
2264 DBG_GRC_PARAM_DUMP_DMAE, /* dump PRS memories (0/1) */
2265 DBG_GRC_PARAM_DUMP_TM, /* dump TM (timers) memories (0/1) */
2266 DBG_GRC_PARAM_DUMP_SDM, /* dump SDM memories (0/1) */
2267 DBG_GRC_PARAM_DUMP_DIF, /* dump DIF memories (0/1) */
2268 DBG_GRC_PARAM_DUMP_STATIC, /* dump static debug data (0/1) */
2269 DBG_GRC_PARAM_UNSTALL, /* un-stall Storms after dump (0/1) */
2270 DBG_GRC_PARAM_NUM_LCIDS, /* number of LCIDs (0..320) */
2271 DBG_GRC_PARAM_NUM_LTIDS, /* number of LTIDs (0..320) */
2272 /* preset: exclude all memories from dump (1 only) */
2273 DBG_GRC_PARAM_EXCLUDE_ALL,
2274 /* preset: include memories for crash dump (1 only) */
2275 DBG_GRC_PARAM_CRASH,
2276 /* perform dump only if MFW is responding (0/1) */
2277 DBG_GRC_PARAM_PARITY_SAFE,
2278 DBG_GRC_PARAM_DUMP_CM, /* dump CM memories (0/1) */
2279 DBG_GRC_PARAM_DUMP_PHY, /* dump PHY memories (0/1) */
2280 DBG_GRC_PARAM_NO_MCP,
2281 DBG_GRC_PARAM_NO_FW_VER,
2285 /* Debug reset registers */
2286 enum dbg_reset_regs {
2287 DBG_RESET_REG_MISCS_PL_UA,
2288 DBG_RESET_REG_MISCS_PL_HV,
2289 DBG_RESET_REG_MISCS_PL_HV_2,
2290 DBG_RESET_REG_MISC_PL_UA,
2291 DBG_RESET_REG_MISC_PL_HV,
2292 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2293 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2294 DBG_RESET_REG_MISC_PL_PDA_VAUX,
2298 /* Debug status codes */
2301 DBG_STATUS_APP_VERSION_NOT_SET,
2302 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2303 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2304 DBG_STATUS_INVALID_ARGS,
2305 DBG_STATUS_OUTPUT_ALREADY_SET,
2306 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2307 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2308 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2309 DBG_STATUS_TOO_MANY_INPUTS,
2310 DBG_STATUS_INPUT_OVERLAP,
2311 DBG_STATUS_HW_ONLY_RECORDING,
2312 DBG_STATUS_STORM_ALREADY_ENABLED,
2313 DBG_STATUS_STORM_NOT_ENABLED,
2314 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2315 DBG_STATUS_BLOCK_NOT_ENABLED,
2316 DBG_STATUS_NO_INPUT_ENABLED,
2317 DBG_STATUS_NO_FILTER_TRIGGER_64B,
2318 DBG_STATUS_FILTER_ALREADY_ENABLED,
2319 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2320 DBG_STATUS_TRIGGER_NOT_ENABLED,
2321 DBG_STATUS_CANT_ADD_CONSTRAINT,
2322 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2323 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2324 DBG_STATUS_RECORDING_NOT_STARTED,
2325 DBG_STATUS_DATA_DIDNT_TRIGGER,
2326 DBG_STATUS_NO_DATA_RECORDED,
2327 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2328 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2329 DBG_STATUS_UNKNOWN_CHIP,
2330 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2331 DBG_STATUS_BLOCK_IN_RESET,
2332 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2333 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2334 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2335 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2336 DBG_STATUS_NVRAM_READ_FAILED,
2337 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2338 DBG_STATUS_MCP_TRACE_BAD_DATA,
2339 DBG_STATUS_MCP_TRACE_NO_META,
2340 DBG_STATUS_MCP_COULD_NOT_HALT,
2341 DBG_STATUS_MCP_COULD_NOT_RESUME,
2342 DBG_STATUS_DMAE_FAILED,
2343 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2344 DBG_STATUS_IGU_FIFO_BAD_DATA,
2345 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2346 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2347 DBG_STATUS_REG_FIFO_BAD_DATA,
2348 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2349 DBG_STATUS_DBG_ARRAY_NOT_SET,
2350 DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
2354 /* Debug Storms IDs */
2365 /* Idle Check data */
2366 struct idle_chk_data {
2367 __le32 buf_size; /* Idle check buffer size in dwords */
2368 u8 buf_size_set; /* Indicates if the idle check buffer size was set
2375 /* Debug Tools data (per HW function) */
2376 struct dbg_tools_data {
2377 struct dbg_grc_data grc; /* GRC Dump data */
2378 struct dbg_bus_data bus; /* Debug Bus data */
2379 struct idle_chk_data idle_chk; /* Idle Check data */
2380 u8 mode_enable[40]; /* Indicates if a mode is enabled (0/1) */
2381 u8 block_in_reset[88]; /* Indicates if a block is in reset state (0/1).
2383 u8 chip_id; /* Chip ID (from enum chip_ids) */
2384 u8 platform_id; /* Platform ID (from enum platform_ids) */
2385 u8 initialized; /* Indicates if the data was initialized */
2389 /********************************/
2390 /* HSI Init Functions constants */
2391 /********************************/
2393 /* Number of VLAN priorities */
2394 #define NUM_OF_VLAN_PRIORITIES 8
2396 struct init_brb_ram_req {
2397 __le32 guranteed_per_tc;
2398 __le32 headroom_per_tc;
2399 __le32 min_pkt_size;
2400 __le32 max_ports_per_engine;
2401 u8 num_active_tcs[MAX_NUM_PORTS];
2404 struct init_ets_tc_req {
2410 struct init_ets_req {
2412 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2415 struct init_nig_lb_rl_req {
2419 __le16 tc_rate[NUM_OF_PHYS_TCS];
2422 struct init_nig_pri_tc_map_entry {
2427 struct init_nig_pri_tc_map_req {
2428 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2431 struct init_qm_port_params {
2434 __le16 num_pbf_cmd_lines;
2435 __le16 num_btb_blocks;
2439 /* QM per-PQ init parameters */
2440 struct init_qm_pq_params {
2447 /* QM per-vport init parameters */
2448 struct init_qm_vport_params {
2451 __le16 first_tx_pq_id[NUM_OF_TCS];
2454 /**************************************/
2455 /* Init Tool HSI constants and macros */
2456 /**************************************/
2458 /* Width of GRC address in bits (addresses are specified in dwords) */
2459 #define GRC_ADDR_BITS 23
2460 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
2462 /* indicates an init that should be applied to any phase ID */
2463 #define ANY_PHASE_ID 0xffff
2465 /* Max size in dwords of a zipped array */
2466 #define MAX_ZIPPED_SIZE 8192
2468 struct fw_asserts_ram_section {
2469 __le16 section_ram_line_offset;
2470 __le16 section_ram_line_size;
2471 u8 list_dword_offset;
2472 u8 list_element_dword_size;
2473 u8 list_num_elements;
2474 u8 list_next_index_dword_offset;
2478 u8 major; /* Firmware major version number */
2479 u8 minor; /* Firmware minor version number */
2480 u8 rev; /* Firmware revision version number */
2481 u8 eng; /* Firmware engineering version number (for bootleg versions) */
2484 struct fw_ver_info {
2485 __le16 tools_ver; /* Tools version number */
2486 u8 image_id; /* FW image ID (e.g. main) */
2488 struct fw_ver_num num; /* FW version number */
2489 __le32 timestamp; /* FW Timestamp in unix time (sec. since 1970) */
2494 struct fw_ver_info ver;
2495 struct fw_asserts_ram_section fw_asserts_section;
2498 struct fw_info_location {
2515 MODE_PORTS_PER_ENG_1,
2516 MODE_PORTS_PER_ENG_2,
2517 MODE_PORTS_PER_ENG_4,
2532 enum init_split_types {
2538 MAX_INIT_SPLIT_TYPES
2541 /* Binary buffer header */
2542 struct bin_buffer_hdr {
2547 /* binary init buffer types */
2548 enum bin_init_buffer_type {
2549 BIN_BUF_INIT_FW_VER_INFO,
2552 BIN_BUF_INIT_MODE_TREE,
2554 MAX_BIN_INIT_BUFFER_TYPE
2557 /* init array header: raw */
2558 struct init_array_raw_hdr {
2560 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2561 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2562 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2563 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2566 /* init array header: standard */
2567 struct init_array_standard_hdr {
2569 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2570 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2571 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2572 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2575 /* init array header: zipped */
2576 struct init_array_zipped_hdr {
2578 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2579 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2580 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2581 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2584 /* init array header: pattern */
2585 struct init_array_pattern_hdr {
2587 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2588 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2589 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2590 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2591 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2592 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
2595 /* init array header union */
2596 union init_array_hdr {
2597 struct init_array_raw_hdr raw;
2598 struct init_array_standard_hdr standard;
2599 struct init_array_zipped_hdr zipped;
2600 struct init_array_pattern_hdr pattern;
2603 /* init array types */
2604 enum init_array_types {
2608 MAX_INIT_ARRAY_TYPES
2611 /* init operation: callback */
2612 struct init_callback_op {
2614 #define INIT_CALLBACK_OP_OP_MASK 0xF
2615 #define INIT_CALLBACK_OP_OP_SHIFT 0
2616 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2617 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2622 /* init operation: delay */
2623 struct init_delay_op {
2625 #define INIT_DELAY_OP_OP_MASK 0xF
2626 #define INIT_DELAY_OP_OP_SHIFT 0
2627 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2628 #define INIT_DELAY_OP_RESERVED_SHIFT 4
2632 /* init operation: if_mode */
2633 struct init_if_mode_op {
2635 #define INIT_IF_MODE_OP_OP_MASK 0xF
2636 #define INIT_IF_MODE_OP_OP_SHIFT 0
2637 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2638 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2639 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2640 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2642 __le16 modes_buf_offset;
2645 /* init operation: if_phase */
2646 struct init_if_phase_op {
2648 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2649 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2650 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2651 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2652 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2653 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2654 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2655 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2657 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2658 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2659 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2660 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2661 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2662 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
2665 /* init mode operators */
2666 enum init_mode_ops {
2673 /* init operation: raw */
2674 struct init_raw_op {
2676 #define INIT_RAW_OP_OP_MASK 0xF
2677 #define INIT_RAW_OP_OP_SHIFT 0
2678 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2679 #define INIT_RAW_OP_PARAM1_SHIFT 4
2683 /* init array params */
2684 struct init_op_array_params {
2689 /* Write init operation arguments */
2690 union init_write_args {
2693 __le32 array_offset;
2694 struct init_op_array_params runtime;
2697 /* init operation: write */
2698 struct init_write_op {
2700 #define INIT_WRITE_OP_OP_MASK 0xF
2701 #define INIT_WRITE_OP_OP_SHIFT 0
2702 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2703 #define INIT_WRITE_OP_SOURCE_SHIFT 4
2704 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2705 #define INIT_WRITE_OP_RESERVED_SHIFT 7
2706 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2707 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2708 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2709 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
2710 union init_write_args args;
2713 /* init operation: read */
2714 struct init_read_op {
2716 #define INIT_READ_OP_OP_MASK 0xF
2717 #define INIT_READ_OP_OP_SHIFT 0
2718 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2719 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
2720 #define INIT_READ_OP_RESERVED_MASK 0x1
2721 #define INIT_READ_OP_RESERVED_SHIFT 8
2722 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2723 #define INIT_READ_OP_ADDRESS_SHIFT 9
2724 __le32 expected_val;
2728 /* Init operations union */
2730 struct init_raw_op raw;
2731 struct init_write_op write;
2732 struct init_read_op read;
2733 struct init_if_mode_op if_mode;
2734 struct init_if_phase_op if_phase;
2735 struct init_callback_op callback;
2736 struct init_delay_op delay;
2739 /* Init command operation types */
2740 enum init_op_types {
2750 /* init polling types */
2751 enum init_poll_types {
2759 /* init source types */
2760 enum init_source_types {
2765 MAX_INIT_SOURCE_TYPES
2768 /* Internal RAM Offsets macro data */
2777 /***************************** Public Functions *******************************/
2779 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2782 * @param bin_ptr - a pointer to the binary data with debug arrays.
2784 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2786 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
2789 * @param p_hwfn - HW device data
2791 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
2793 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
2796 * @param p_hwfn - HW device data
2797 * @param p_ptt - Ptt window used for writing the registers.
2798 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
2801 * @return error if one of the following holds:
2802 * - the version wasn't set
2803 * Otherwise, returns ok.
2805 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2806 struct qed_ptt *p_ptt,
2809 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
2811 * @param p_hwfn - HW device data
2812 * @param p_ptt - Ptt window used for writing the registers.
2813 * @param dump_buf - Pointer to write the collected GRC data into.
2814 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2815 * @param num_dumped_dwords - OUT: number of dumped dwords.
2817 * @return error if one of the following holds:
2818 * - the version wasn't set
2819 * - the specified dump buffer is too small
2820 * Otherwise, returns ok.
2822 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
2823 struct qed_ptt *p_ptt,
2825 u32 buf_size_in_dwords,
2826 u32 *num_dumped_dwords);
2828 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
2829 * for idle check results.
2831 * @param p_hwfn - HW device data
2832 * @param p_ptt - Ptt window used for writing the registers.
2833 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
2836 * @return error if one of the following holds:
2837 * - the version wasn't set
2838 * Otherwise, returns ok.
2840 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2841 struct qed_ptt *p_ptt,
2844 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
2845 * into the specified buffer.
2847 * @param p_hwfn - HW device data
2848 * @param p_ptt - Ptt window used for writing the registers.
2849 * @param dump_buf - Pointer to write the idle check data into.
2850 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2851 * @param num_dumped_dwords - OUT: number of dumped dwords.
2853 * @return error if one of the following holds:
2854 * - the version wasn't set
2855 * - the specified buffer is too small
2856 * Otherwise, returns ok.
2858 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
2859 struct qed_ptt *p_ptt,
2861 u32 buf_size_in_dwords,
2862 u32 *num_dumped_dwords);
2864 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
2865 * for mcp trace results.
2867 * @param p_hwfn - HW device data
2868 * @param p_ptt - Ptt window used for writing the registers.
2869 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
2871 * @return error if one of the following holds:
2872 * - the version wasn't set
2873 * - the trace data in MCP scratchpad contain an invalid signature
2874 * - the bundle ID in NVRAM is invalid
2875 * - the trace meta data cannot be found (in NVRAM or image file)
2876 * Otherwise, returns ok.
2878 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2879 struct qed_ptt *p_ptt,
2882 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
2883 * into the specified buffer.
2885 * @param p_hwfn - HW device data
2886 * @param p_ptt - Ptt window used for writing the registers.
2887 * @param dump_buf - Pointer to write the mcp trace data into.
2888 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2889 * @param num_dumped_dwords - OUT: number of dumped dwords.
2891 * @return error if one of the following holds:
2892 * - the version wasn't set
2893 * - the specified buffer is too small
2894 * - the trace data in MCP scratchpad contain an invalid signature
2895 * - the bundle ID in NVRAM is invalid
2896 * - the trace meta data cannot be found (in NVRAM or image file)
2897 * - the trace meta data cannot be read (from NVRAM or image file)
2898 * Otherwise, returns ok.
2900 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
2901 struct qed_ptt *p_ptt,
2903 u32 buf_size_in_dwords,
2904 u32 *num_dumped_dwords);
2906 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
2907 * for grc trace fifo results.
2909 * @param p_hwfn - HW device data
2910 * @param p_ptt - Ptt window used for writing the registers.
2911 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
2913 * @return error if one of the following holds:
2914 * - the version wasn't set
2915 * Otherwise, returns ok.
2917 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2918 struct qed_ptt *p_ptt,
2921 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
2922 * the specified buffer.
2924 * @param p_hwfn - HW device data
2925 * @param p_ptt - Ptt window used for writing the registers.
2926 * @param dump_buf - Pointer to write the reg fifo data into.
2927 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2928 * @param num_dumped_dwords - OUT: number of dumped dwords.
2930 * @return error if one of the following holds:
2931 * - the version wasn't set
2932 * - the specified buffer is too small
2933 * - DMAE transaction failed
2934 * Otherwise, returns ok.
2936 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
2937 struct qed_ptt *p_ptt,
2939 u32 buf_size_in_dwords,
2940 u32 *num_dumped_dwords);
2942 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
2943 * for the IGU fifo results.
2945 * @param p_hwfn - HW device data
2946 * @param p_ptt - Ptt window used for writing the registers.
2947 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
2950 * @return error if one of the following holds:
2951 * - the version wasn't set
2952 * Otherwise, returns ok.
2954 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2955 struct qed_ptt *p_ptt,
2958 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
2959 * the specified buffer.
2961 * @param p_hwfn - HW device data
2962 * @param p_ptt - Ptt window used for writing the registers.
2963 * @param dump_buf - Pointer to write the IGU fifo data into.
2964 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2965 * @param num_dumped_dwords - OUT: number of dumped dwords.
2967 * @return error if one of the following holds:
2968 * - the version wasn't set
2969 * - the specified buffer is too small
2970 * - DMAE transaction failed
2971 * Otherwise, returns ok.
2973 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
2974 struct qed_ptt *p_ptt,
2976 u32 buf_size_in_dwords,
2977 u32 *num_dumped_dwords);
2979 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
2980 * buffer size for protection override window results.
2982 * @param p_hwfn - HW device data
2983 * @param p_ptt - Ptt window used for writing the registers.
2984 * @param buf_size - OUT: required buffer size (in dwords) for protection
2987 * @return error if one of the following holds:
2988 * - the version wasn't set
2989 * Otherwise, returns ok.
2992 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2993 struct qed_ptt *p_ptt,
2996 * @brief qed_dbg_protection_override_dump - Reads protection override window
2997 * entries and writes the results into the specified buffer.
2999 * @param p_hwfn - HW device data
3000 * @param p_ptt - Ptt window used for writing the registers.
3001 * @param dump_buf - Pointer to write the protection override data into.
3002 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3003 * @param num_dumped_dwords - OUT: number of dumped dwords.
3005 * @return error if one of the following holds:
3006 * - the version wasn't set
3007 * - the specified buffer is too small
3008 * - DMAE transaction failed
3009 * Otherwise, returns ok.
3011 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3012 struct qed_ptt *p_ptt,
3014 u32 buf_size_in_dwords,
3015 u32 *num_dumped_dwords);
3017 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3018 * size for FW Asserts results.
3020 * @param p_hwfn - HW device data
3021 * @param p_ptt - Ptt window used for writing the registers.
3022 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3024 * @return error if one of the following holds:
3025 * - the version wasn't set
3026 * Otherwise, returns ok.
3028 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3029 struct qed_ptt *p_ptt,
3032 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3033 * into the specified buffer.
3035 * @param p_hwfn - HW device data
3036 * @param p_ptt - Ptt window used for writing the registers.
3037 * @param dump_buf - Pointer to write the FW Asserts data into.
3038 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3039 * @param num_dumped_dwords - OUT: number of dumped dwords.
3041 * @return error if one of the following holds:
3042 * - the version wasn't set
3043 * - the specified buffer is too small
3044 * Otherwise, returns ok.
3046 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3047 struct qed_ptt *p_ptt,
3049 u32 buf_size_in_dwords,
3050 u32 *num_dumped_dwords);
3052 * @brief qed_dbg_print_attn - Prints attention registers values in the
3053 * specified results struct.
3056 * @param results - Pointer to the attention read results
3058 * @return error if one of the following holds:
3059 * - the version wasn't set
3060 * Otherwise, returns ok.
3062 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3063 struct dbg_attn_block_result *results);
3065 /******************************** Constants **********************************/
3067 #define MAX_NAME_LEN 16
3069 /***************************** Public Functions *******************************/
3071 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3074 * @param bin_ptr - a pointer to the binary data with debug arrays.
3076 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3078 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3080 * @param status - a debug status code.
3082 * @return a string for the specified status
3084 const char *qed_dbg_get_status_str(enum dbg_status status);
3086 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3087 * for idle check results (in bytes).
3089 * @param p_hwfn - HW device data
3090 * @param dump_buf - idle check dump buffer.
3091 * @param num_dumped_dwords - number of dwords that were dumped.
3092 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3095 * @return error if the parsing fails, ok otherwise.
3097 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3099 u32 num_dumped_dwords,
3100 u32 *results_buf_size);
3102 * @brief qed_print_idle_chk_results - Prints idle check results
3104 * @param p_hwfn - HW device data
3105 * @param dump_buf - idle check dump buffer.
3106 * @param num_dumped_dwords - number of dwords that were dumped.
3107 * @param results_buf - buffer for printing the idle check results.
3108 * @param num_errors - OUT: number of errors found in idle check.
3109 * @param num_warnings - OUT: number of warnings found in idle check.
3111 * @return error if the parsing fails, ok otherwise.
3113 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3115 u32 num_dumped_dwords,
3120 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3121 * for MCP Trace results (in bytes).
3123 * @param p_hwfn - HW device data
3124 * @param dump_buf - MCP Trace dump buffer.
3125 * @param num_dumped_dwords - number of dwords that were dumped.
3126 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3129 * @return error if the parsing fails, ok otherwise.
3131 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3133 u32 num_dumped_dwords,
3134 u32 *results_buf_size);
3136 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3138 * @param p_hwfn - HW device data
3139 * @param dump_buf - mcp trace dump buffer, starting from the header.
3140 * @param num_dumped_dwords - number of dwords that were dumped.
3141 * @param results_buf - buffer for printing the mcp trace results.
3143 * @return error if the parsing fails, ok otherwise.
3145 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3147 u32 num_dumped_dwords,
3150 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3151 * for reg_fifo results (in bytes).
3153 * @param p_hwfn - HW device data
3154 * @param dump_buf - reg fifo dump buffer.
3155 * @param num_dumped_dwords - number of dwords that were dumped.
3156 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3159 * @return error if the parsing fails, ok otherwise.
3161 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3163 u32 num_dumped_dwords,
3164 u32 *results_buf_size);
3166 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3168 * @param p_hwfn - HW device data
3169 * @param dump_buf - reg fifo dump buffer, starting from the header.
3170 * @param num_dumped_dwords - number of dwords that were dumped.
3171 * @param results_buf - buffer for printing the reg fifo results.
3173 * @return error if the parsing fails, ok otherwise.
3175 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3177 u32 num_dumped_dwords,
3180 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3181 * for igu_fifo results (in bytes).
3183 * @param p_hwfn - HW device data
3184 * @param dump_buf - IGU fifo dump buffer.
3185 * @param num_dumped_dwords - number of dwords that were dumped.
3186 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3189 * @return error if the parsing fails, ok otherwise.
3191 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3193 u32 num_dumped_dwords,
3194 u32 *results_buf_size);
3196 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3198 * @param p_hwfn - HW device data
3199 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3200 * @param num_dumped_dwords - number of dwords that were dumped.
3201 * @param results_buf - buffer for printing the IGU fifo results.
3203 * @return error if the parsing fails, ok otherwise.
3205 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3207 u32 num_dumped_dwords,
3210 * @brief qed_get_protection_override_results_buf_size - Returns the required
3211 * buffer size for protection override results (in bytes).
3213 * @param p_hwfn - HW device data
3214 * @param dump_buf - protection override dump buffer.
3215 * @param num_dumped_dwords - number of dwords that were dumped.
3216 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3219 * @return error if the parsing fails, ok otherwise.
3222 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3224 u32 num_dumped_dwords,
3225 u32 *results_buf_size);
3227 * @brief qed_print_protection_override_results - Prints protection override
3230 * @param p_hwfn - HW device data
3231 * @param dump_buf - protection override dump buffer, starting from the header.
3232 * @param num_dumped_dwords - number of dwords that were dumped.
3233 * @param results_buf - buffer for printing the reg fifo results.
3235 * @return error if the parsing fails, ok otherwise.
3237 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3239 u32 num_dumped_dwords,
3242 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3243 * for FW Asserts results (in bytes).
3245 * @param p_hwfn - HW device data
3246 * @param dump_buf - FW Asserts dump buffer.
3247 * @param num_dumped_dwords - number of dwords that were dumped.
3248 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3251 * @return error if the parsing fails, ok otherwise.
3253 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3255 u32 num_dumped_dwords,
3256 u32 *results_buf_size);
3258 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3260 * @param p_hwfn - HW device data
3261 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3262 * @param num_dumped_dwords - number of dwords that were dumped.
3263 * @param results_buf - buffer for printing the FW Asserts results.
3265 * @return error if the parsing fails, ok otherwise.
3267 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3269 u32 num_dumped_dwords,
3272 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
3275 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
3278 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
3281 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
3284 #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
3287 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
3290 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
3293 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
3296 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
3299 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
3302 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3304 * Returns the required host memory size in 4KB units.
3305 * Must be called before all QM init HSI functions.
3307 * @param pf_id - physical function ID
3308 * @param num_pf_cids - number of connections used by this PF
3309 * @param num_vf_cids - number of connections used by VFs of this PF
3310 * @param num_tids - number of tasks used by this PF
3311 * @param num_pf_pqs - number of PQs used by this PF
3312 * @param num_vf_pqs - number of PQs used by VFs of this PF
3314 * @return The required host memory size in 4KB units.
3316 u32 qed_qm_pf_mem_size(u8 pf_id,
3319 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3321 struct qed_qm_common_rt_init_params {
3322 u8 max_ports_per_engine;
3323 u8 max_phys_tcs_per_port;
3328 struct init_qm_port_params *port_params;
3331 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3332 struct qed_qm_common_rt_init_params *p_params);
3334 struct qed_qm_pf_rt_init_params {
3337 u8 max_phys_tcs_per_port;
3349 struct init_qm_pq_params *pq_params;
3350 struct init_qm_vport_params *vport_params;
3353 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3354 struct qed_ptt *p_ptt,
3355 struct qed_qm_pf_rt_init_params *p_params);
3358 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3361 * @param p_ptt - ptt window used for writing the registers
3362 * @param pf_id - PF ID
3363 * @param pf_wfq - WFQ weight. Must be non-zero.
3365 * @return 0 on success, -1 on error.
3367 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3368 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3371 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3374 * @param p_ptt - ptt window used for writing the registers
3375 * @param pf_id - PF ID
3376 * @param pf_rl - rate limit in Mb/sec units
3378 * @return 0 on success, -1 on error.
3380 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3381 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3384 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3387 * @param p_ptt - ptt window used for writing the registers
3388 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3389 * with the VPORT for each TC. This array is filled by
3391 * @param vport_wfq - WFQ weight. Must be non-zero.
3393 * @return 0 on success, -1 on error.
3395 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3396 struct qed_ptt *p_ptt,
3397 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3400 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3403 * @param p_ptt - ptt window used for writing the registers
3404 * @param vport_id - VPORT ID
3405 * @param vport_rl - rate limit in Mb/sec units
3407 * @return 0 on success, -1 on error.
3409 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3410 struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
3412 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
3416 * @param is_release_cmd - true for release, false for stop.
3417 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3418 * @param start_pq - first PQ ID to stop
3419 * @param num_pqs - Number of PQs to stop, starting from start_pq.
3421 * @return bool, true if successful, false if timeout occured while waiting for QM command done.
3423 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3424 struct qed_ptt *p_ptt,
3425 bool is_release_cmd,
3426 bool is_tx_pq, u16 start_pq, u16 num_pqs);
3429 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3431 * @param p_ptt - ptt window used for writing the registers.
3432 * @param dest_port - vxlan destination udp port.
3434 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3435 struct qed_ptt *p_ptt, u16 dest_port);
3438 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3440 * @param p_ptt - ptt window used for writing the registers.
3441 * @param vxlan_enable - vxlan enable flag.
3443 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3444 struct qed_ptt *p_ptt, bool vxlan_enable);
3447 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3449 * @param p_ptt - ptt window used for writing the registers.
3450 * @param eth_gre_enable - eth GRE enable enable flag.
3451 * @param ip_gre_enable - IP GRE enable enable flag.
3453 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3454 struct qed_ptt *p_ptt,
3455 bool eth_gre_enable, bool ip_gre_enable);
3458 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3460 * @param p_ptt - ptt window used for writing the registers.
3461 * @param dest_port - geneve destination udp port.
3463 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3464 struct qed_ptt *p_ptt, u16 dest_port);
3467 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3469 * @param p_ptt - ptt window used for writing the registers.
3470 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3471 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3473 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
3474 struct qed_ptt *p_ptt,
3475 bool eth_geneve_enable, bool ip_geneve_enable);
3477 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
3478 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
3479 #define TSTORM_PORT_STAT_OFFSET(port_id) \
3480 (IRO[1].base + ((port_id) * IRO[1].m1))
3481 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
3482 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
3483 (IRO[2].base + ((port_id) * IRO[2].m1))
3484 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
3485 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
3486 (IRO[3].base + ((vf_id) * IRO[3].m1))
3487 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
3488 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
3489 (IRO[4].base + (pf_id) * IRO[4].m1)
3490 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
3491 #define USTORM_EQE_CONS_OFFSET(pf_id) \
3492 (IRO[5].base + ((pf_id) * IRO[5].m1))
3493 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
3494 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
3495 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
3496 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
3497 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
3498 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
3499 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
3500 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
3501 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
3502 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
3503 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3504 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
3505 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
3506 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3507 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
3508 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
3509 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
3510 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
3511 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size)
3512 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3513 (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
3514 #define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
3515 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
3516 (IRO[19].base + ((queue_id) * IRO[19].m1))
3517 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
3518 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
3519 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
3520 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
3521 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
3522 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
3523 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3524 (IRO[22].base + ((pf_id) * IRO[22].m1))
3525 #define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
3526 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3527 (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
3528 #define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
3529 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
3530 (IRO[24].base + ((pf_id) * IRO[24].m1))
3531 #define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
3532 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3533 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
3534 #define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
3535 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3536 (IRO[26].base + ((pf_id) * IRO[26].m1))
3537 #define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
3538 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
3539 (IRO[27].base + ((ethtype) * IRO[27].m1))
3540 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
3541 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
3542 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
3543 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
3544 (IRO[29].base + ((pf_id) * IRO[29].m1))
3545 #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
3546 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
3547 (IRO[30].base + ((queue_id) * IRO[30].m1))
3548 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
3549 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
3550 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
3551 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
3552 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3553 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
3554 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
3555 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3556 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
3557 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
3558 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3559 (IRO[37].base + ((pf_id) * IRO[37].m1))
3560 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
3561 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3562 (IRO[38].base + ((pf_id) * IRO[38].m1))
3563 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
3564 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3565 (IRO[39].base + ((pf_id) * IRO[39].m1))
3566 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
3567 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3568 (IRO[40].base + ((pf_id) * IRO[40].m1))
3569 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
3570 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3571 (IRO[41].base + ((pf_id) * IRO[41].m1))
3572 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
3573 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3574 (IRO[42].base + ((pf_id) * IRO[42].m1))
3575 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
3576 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3577 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
3578 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
3579 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3580 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
3581 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
3582 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
3583 (IRO[43].base + ((pf_id) * IRO[43].m1))
3584 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
3585 (IRO[44].base + ((pf_id) * IRO[44].m1))
3587 static const struct iro iro_arr[47] = {
3588 {0x0, 0x0, 0x0, 0x0, 0x8},
3589 {0x4cb0, 0x80, 0x0, 0x0, 0x80},
3590 {0x6318, 0x20, 0x0, 0x0, 0x20},
3591 {0xb00, 0x8, 0x0, 0x0, 0x4},
3592 {0xa80, 0x8, 0x0, 0x0, 0x4},
3593 {0x0, 0x8, 0x0, 0x0, 0x2},
3594 {0x80, 0x8, 0x0, 0x0, 0x4},
3595 {0x84, 0x8, 0x0, 0x0, 0x2},
3596 {0x4bc0, 0x0, 0x0, 0x0, 0x78},
3597 {0x3df0, 0x0, 0x0, 0x0, 0x78},
3598 {0x29b0, 0x0, 0x0, 0x0, 0x78},
3599 {0x4c38, 0x0, 0x0, 0x0, 0x78},
3600 {0x4990, 0x0, 0x0, 0x0, 0x78},
3601 {0x7e48, 0x0, 0x0, 0x0, 0x78},
3602 {0xa28, 0x8, 0x0, 0x0, 0x8},
3603 {0x60f8, 0x10, 0x0, 0x0, 0x10},
3604 {0xb820, 0x30, 0x0, 0x0, 0x30},
3605 {0x95b8, 0x30, 0x0, 0x0, 0x30},
3606 {0x4b60, 0x80, 0x0, 0x0, 0x40},
3607 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3608 {0x53a0, 0x80, 0x4, 0x0, 0x4},
3609 {0xc8f0, 0x0, 0x0, 0x0, 0x4},
3610 {0x4ba0, 0x80, 0x0, 0x0, 0x20},
3611 {0x8050, 0x40, 0x0, 0x0, 0x30},
3612 {0xe770, 0x60, 0x0, 0x0, 0x60},
3613 {0x2b48, 0x80, 0x0, 0x0, 0x38},
3614 {0xf188, 0x78, 0x0, 0x0, 0x78},
3615 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3616 {0xacf0, 0x0, 0x0, 0x0, 0xf0},
3617 {0xade0, 0x8, 0x0, 0x0, 0x8},
3618 {0x1f8, 0x8, 0x0, 0x0, 0x8},
3619 {0xac0, 0x8, 0x0, 0x0, 0x8},
3620 {0x2578, 0x8, 0x0, 0x0, 0x8},
3621 {0x24f8, 0x8, 0x0, 0x0, 0x8},
3622 {0x0, 0x8, 0x0, 0x0, 0x8},
3623 {0x200, 0x10, 0x8, 0x0, 0x8},
3624 {0xb78, 0x10, 0x8, 0x0, 0x2},
3625 {0xd888, 0x38, 0x0, 0x0, 0x24},
3626 {0x12c38, 0x10, 0x0, 0x0, 0x8},
3627 {0x11aa0, 0x38, 0x0, 0x0, 0x18},
3628 {0xa8c0, 0x38, 0x0, 0x0, 0x10},
3629 {0x86f8, 0x30, 0x0, 0x0, 0x18},
3630 {0x101f8, 0x10, 0x0, 0x0, 0x10},
3631 {0xdd08, 0x48, 0x0, 0x0, 0x38},
3632 {0x10660, 0x20, 0x0, 0x0, 0x20},
3633 {0x2b80, 0x80, 0x0, 0x0, 0x10},
3634 {0x5020, 0x10, 0x0, 0x0, 0x10},
3637 /* Runtime array offsets */
3638 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
3639 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
3640 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
3641 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
3642 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
3643 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
3644 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
3645 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
3646 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
3647 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
3648 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
3649 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
3650 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
3651 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
3652 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
3653 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
3654 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
3655 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
3656 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
3657 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
3658 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
3659 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
3660 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
3661 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
3662 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
3663 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
3664 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
3665 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
3666 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
3667 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
3668 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
3669 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
3670 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
3671 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
3672 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
3673 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
3674 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
3675 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
3676 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
3677 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
3678 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
3679 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
3680 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
3681 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
3682 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
3683 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
3684 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
3685 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
3686 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
3687 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
3688 #define SRC_REG_FIRSTFREE_RT_SIZE 2
3689 #define SRC_REG_LASTFREE_RT_OFFSET 6667
3690 #define SRC_REG_LASTFREE_RT_SIZE 2
3691 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
3692 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
3693 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
3694 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
3695 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
3696 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
3697 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
3698 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
3699 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
3700 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
3701 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
3702 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
3703 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
3704 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
3705 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
3706 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
3707 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
3708 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
3709 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
3710 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
3711 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
3712 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
3713 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
3714 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
3715 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
3716 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
3717 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
3718 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
3719 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
3720 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
3721 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
3722 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
3723 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
3724 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
3725 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
3726 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
3727 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
3728 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
3729 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705
3730 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706
3731 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707
3732 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708
3733 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709
3734 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710
3735 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711
3736 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712
3737 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713
3738 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714
3739 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715
3740 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716
3741 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
3742 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132
3743 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
3744 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29644
3745 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29645
3746 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29646
3747 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29647
3748 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29648
3749 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29649
3750 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29650
3751 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29651
3752 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29652
3753 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29653
3754 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29654
3755 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29655
3756 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29656
3757 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29657
3758 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29658
3759 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29659
3760 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29660
3761 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29661
3762 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29662
3763 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29663
3764 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29664
3765 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29665
3766 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29666
3767 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29667
3768 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29668
3769 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29669
3770 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29670
3771 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29671
3772 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29672
3773 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29673
3774 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29674
3775 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29675
3776 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29676
3777 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29677
3778 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29678
3779 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29679
3780 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29680
3781 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29681
3782 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29682
3783 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29683
3784 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29684
3785 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29685
3786 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29686
3787 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29687
3788 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29688
3789 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29689
3790 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29690
3791 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29691
3792 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29692
3793 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29693
3794 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29694
3795 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29695
3796 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29696
3797 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29697
3798 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29698
3799 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29699
3800 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29700
3801 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29701
3802 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29702
3803 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29703
3804 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29704
3805 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29705
3806 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29706
3807 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29707
3808 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29708
3809 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29709
3810 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29710
3811 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29711
3812 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
3813 #define QM_REG_VOQCRDLINE_RT_OFFSET 29839
3814 #define QM_REG_VOQCRDLINE_RT_SIZE 20
3815 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859
3816 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
3817 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29879
3818 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29880
3819 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29881
3820 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29882
3821 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29883
3822 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29884
3823 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29885
3824 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29886
3825 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29887
3826 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29888
3827 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29889
3828 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29890
3829 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29891
3830 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29892
3831 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29893
3832 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29894
3833 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29895
3834 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29896
3835 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29897
3836 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29898
3837 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29899
3838 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29900
3839 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29901
3840 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29902
3841 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29903
3842 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29904
3843 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29905
3844 #define QM_REG_PQTX2PF_0_RT_OFFSET 29906
3845 #define QM_REG_PQTX2PF_1_RT_OFFSET 29907
3846 #define QM_REG_PQTX2PF_2_RT_OFFSET 29908
3847 #define QM_REG_PQTX2PF_3_RT_OFFSET 29909
3848 #define QM_REG_PQTX2PF_4_RT_OFFSET 29910
3849 #define QM_REG_PQTX2PF_5_RT_OFFSET 29911
3850 #define QM_REG_PQTX2PF_6_RT_OFFSET 29912
3851 #define QM_REG_PQTX2PF_7_RT_OFFSET 29913
3852 #define QM_REG_PQTX2PF_8_RT_OFFSET 29914
3853 #define QM_REG_PQTX2PF_9_RT_OFFSET 29915
3854 #define QM_REG_PQTX2PF_10_RT_OFFSET 29916
3855 #define QM_REG_PQTX2PF_11_RT_OFFSET 29917
3856 #define QM_REG_PQTX2PF_12_RT_OFFSET 29918
3857 #define QM_REG_PQTX2PF_13_RT_OFFSET 29919
3858 #define QM_REG_PQTX2PF_14_RT_OFFSET 29920
3859 #define QM_REG_PQTX2PF_15_RT_OFFSET 29921
3860 #define QM_REG_PQTX2PF_16_RT_OFFSET 29922
3861 #define QM_REG_PQTX2PF_17_RT_OFFSET 29923
3862 #define QM_REG_PQTX2PF_18_RT_OFFSET 29924
3863 #define QM_REG_PQTX2PF_19_RT_OFFSET 29925
3864 #define QM_REG_PQTX2PF_20_RT_OFFSET 29926
3865 #define QM_REG_PQTX2PF_21_RT_OFFSET 29927
3866 #define QM_REG_PQTX2PF_22_RT_OFFSET 29928
3867 #define QM_REG_PQTX2PF_23_RT_OFFSET 29929
3868 #define QM_REG_PQTX2PF_24_RT_OFFSET 29930
3869 #define QM_REG_PQTX2PF_25_RT_OFFSET 29931
3870 #define QM_REG_PQTX2PF_26_RT_OFFSET 29932
3871 #define QM_REG_PQTX2PF_27_RT_OFFSET 29933
3872 #define QM_REG_PQTX2PF_28_RT_OFFSET 29934
3873 #define QM_REG_PQTX2PF_29_RT_OFFSET 29935
3874 #define QM_REG_PQTX2PF_30_RT_OFFSET 29936
3875 #define QM_REG_PQTX2PF_31_RT_OFFSET 29937
3876 #define QM_REG_PQTX2PF_32_RT_OFFSET 29938
3877 #define QM_REG_PQTX2PF_33_RT_OFFSET 29939
3878 #define QM_REG_PQTX2PF_34_RT_OFFSET 29940
3879 #define QM_REG_PQTX2PF_35_RT_OFFSET 29941
3880 #define QM_REG_PQTX2PF_36_RT_OFFSET 29942
3881 #define QM_REG_PQTX2PF_37_RT_OFFSET 29943
3882 #define QM_REG_PQTX2PF_38_RT_OFFSET 29944
3883 #define QM_REG_PQTX2PF_39_RT_OFFSET 29945
3884 #define QM_REG_PQTX2PF_40_RT_OFFSET 29946
3885 #define QM_REG_PQTX2PF_41_RT_OFFSET 29947
3886 #define QM_REG_PQTX2PF_42_RT_OFFSET 29948
3887 #define QM_REG_PQTX2PF_43_RT_OFFSET 29949
3888 #define QM_REG_PQTX2PF_44_RT_OFFSET 29950
3889 #define QM_REG_PQTX2PF_45_RT_OFFSET 29951
3890 #define QM_REG_PQTX2PF_46_RT_OFFSET 29952
3891 #define QM_REG_PQTX2PF_47_RT_OFFSET 29953
3892 #define QM_REG_PQTX2PF_48_RT_OFFSET 29954
3893 #define QM_REG_PQTX2PF_49_RT_OFFSET 29955
3894 #define QM_REG_PQTX2PF_50_RT_OFFSET 29956
3895 #define QM_REG_PQTX2PF_51_RT_OFFSET 29957
3896 #define QM_REG_PQTX2PF_52_RT_OFFSET 29958
3897 #define QM_REG_PQTX2PF_53_RT_OFFSET 29959
3898 #define QM_REG_PQTX2PF_54_RT_OFFSET 29960
3899 #define QM_REG_PQTX2PF_55_RT_OFFSET 29961
3900 #define QM_REG_PQTX2PF_56_RT_OFFSET 29962
3901 #define QM_REG_PQTX2PF_57_RT_OFFSET 29963
3902 #define QM_REG_PQTX2PF_58_RT_OFFSET 29964
3903 #define QM_REG_PQTX2PF_59_RT_OFFSET 29965
3904 #define QM_REG_PQTX2PF_60_RT_OFFSET 29966
3905 #define QM_REG_PQTX2PF_61_RT_OFFSET 29967
3906 #define QM_REG_PQTX2PF_62_RT_OFFSET 29968
3907 #define QM_REG_PQTX2PF_63_RT_OFFSET 29969
3908 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29970
3909 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29971
3910 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29972
3911 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29973
3912 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29974
3913 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29975
3914 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29976
3915 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29977
3916 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29978
3917 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29979
3918 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29980
3919 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29981
3920 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29982
3921 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29983
3922 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29984
3923 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29985
3924 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986
3925 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987
3926 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29988
3927 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29989
3928 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29990
3929 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29991
3930 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29992
3931 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29993
3932 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29994
3933 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29995
3934 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29996
3935 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29997
3936 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29998
3937 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
3938 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30254
3939 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
3940 #define QM_REG_RLGLBLCRD_RT_OFFSET 30510
3941 #define QM_REG_RLGLBLCRD_RT_SIZE 256
3942 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30766
3943 #define QM_REG_RLPFPERIOD_RT_OFFSET 30767
3944 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30768
3945 #define QM_REG_RLPFINCVAL_RT_OFFSET 30769
3946 #define QM_REG_RLPFINCVAL_RT_SIZE 16
3947 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785
3948 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
3949 #define QM_REG_RLPFCRD_RT_OFFSET 30801
3950 #define QM_REG_RLPFCRD_RT_SIZE 16
3951 #define QM_REG_RLPFENABLE_RT_OFFSET 30817
3952 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30818
3953 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30819
3954 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
3955 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30835
3956 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
3957 #define QM_REG_WFQPFCRD_RT_OFFSET 30851
3958 #define QM_REG_WFQPFCRD_RT_SIZE 160
3959 #define QM_REG_WFQPFENABLE_RT_OFFSET 31011
3960 #define QM_REG_WFQVPENABLE_RT_OFFSET 31012
3961 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31013
3962 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
3963 #define QM_REG_TXPQMAP_RT_OFFSET 31525
3964 #define QM_REG_TXPQMAP_RT_SIZE 512
3965 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32037
3966 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
3967 #define QM_REG_WFQVPCRD_RT_OFFSET 32549
3968 #define QM_REG_WFQVPCRD_RT_SIZE 512
3969 #define QM_REG_WFQVPMAP_RT_OFFSET 33061
3970 #define QM_REG_WFQVPMAP_RT_SIZE 512
3971 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33573
3972 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
3973 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33733
3974 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734
3975 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735
3976 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736
3977 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737
3978 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33738
3979 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33739
3980 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33740
3981 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
3982 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33744
3983 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
3984 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33748
3985 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
3986 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33752
3987 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753
3988 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
3989 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33785
3990 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
3991 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33801
3992 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
3993 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817
3994 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
3995 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33833
3996 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
3997 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33849
3998 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33850
3999 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33851
4000 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33852
4001 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33853
4002 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33854
4003 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33855
4004 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33856
4005 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33857
4006 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33858
4007 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33859
4008 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33860
4009 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33861
4010 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33862
4011 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863
4012 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33864
4013 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33865
4014 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33866
4015 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33867
4016 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33868
4017 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33869
4018 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33870
4019 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33871
4020 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33872
4021 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33873
4022 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33874
4023 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33875
4024 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33876
4025 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33877
4026 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33878
4027 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33879
4028 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33880
4029 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33881
4030 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33882
4031 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33883
4032 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33884
4033 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33885
4034 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33886
4035 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33887
4036 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33888
4037 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33889
4038 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33890
4039 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33891
4040 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33892
4041 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33893
4042 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33894
4043 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33895
4044 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33896
4045 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33897
4046 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33898
4047 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33899
4048 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33900
4049 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33901
4050 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33902
4051 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33903
4052 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33904
4053 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33905
4054 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33906
4055 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33907
4056 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33908
4057 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33909
4058 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33910
4059 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33911
4060 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33912
4061 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33913
4062 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33914
4063 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33915
4064 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33916
4065 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33917
4066 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33918
4067 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33919
4068 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33920
4069 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33921
4070 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33922
4071 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33923
4072 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33924
4073 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33925
4074 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33926
4076 #define RUNTIME_ARRAY_SIZE 33927
4078 /* The eth storm context for the Tstorm */
4079 struct tstorm_eth_conn_st_ctx {
4083 /* The eth storm context for the Pstorm */
4084 struct pstorm_eth_conn_st_ctx {
4088 /* The eth storm context for the Xstorm */
4089 struct xstorm_eth_conn_st_ctx {
4090 __le32 reserved[60];
4093 struct xstorm_eth_conn_ag_ctx {
4097 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4098 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4099 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
4100 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
4101 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
4102 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
4103 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4104 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
4105 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
4106 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
4107 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
4108 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
4109 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
4110 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
4111 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
4112 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
4114 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
4115 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
4116 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
4117 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
4118 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
4119 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
4120 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
4121 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
4122 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
4123 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
4124 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
4125 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
4126 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4127 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
4128 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4129 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
4131 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4132 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4133 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4134 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4135 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4136 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4137 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4138 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
4140 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4141 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4142 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4143 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4144 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4145 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4146 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4147 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
4149 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4150 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4151 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4152 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4153 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4154 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4155 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4156 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
4158 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4159 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4160 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4161 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
4162 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4163 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
4164 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4165 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
4167 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4168 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4169 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4170 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4171 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4172 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
4173 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4174 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
4176 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4177 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4178 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4179 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
4180 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4181 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4182 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4183 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
4184 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4185 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
4187 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4188 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4189 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4190 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
4191 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4192 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
4193 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4194 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
4195 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4196 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
4197 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4198 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
4199 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4200 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
4201 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4202 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
4204 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4205 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4206 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4207 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4208 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4209 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4210 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4211 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4212 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4213 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4214 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4215 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4216 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4217 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4218 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4219 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
4221 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4222 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4223 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4224 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4225 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4226 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4227 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4228 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4229 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4230 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4231 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4232 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4233 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4234 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4235 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4236 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
4238 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4239 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4240 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
4241 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
4242 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4243 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
4244 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4245 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
4246 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4247 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
4248 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4249 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
4250 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4251 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
4252 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
4253 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
4255 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
4256 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
4257 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
4258 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
4259 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4260 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
4261 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4262 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
4263 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
4264 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
4265 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
4266 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
4267 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
4268 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
4269 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
4270 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
4272 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
4273 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
4274 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
4275 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
4276 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4277 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
4278 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4279 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
4280 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4281 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
4282 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4283 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
4284 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4285 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
4286 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4287 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
4289 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4290 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4291 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4292 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4293 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4294 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4295 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4296 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4297 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4298 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4299 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4300 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4301 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4302 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
4306 __le16 edpm_num_bds;
4356 /* The eth storm context for the Ystorm */
4357 struct ystorm_eth_conn_st_ctx {
4361 struct ystorm_eth_conn_ag_ctx {
4365 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4366 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4367 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4368 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4369 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4370 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
4371 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
4372 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
4373 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4374 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4376 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4377 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
4378 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
4379 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
4380 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4381 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4382 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4383 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
4384 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4385 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
4386 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4387 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
4388 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4389 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
4390 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4391 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
4392 u8 tx_q0_int_coallecing_timeset;
4395 __le32 terminate_spqe;
4397 __le16 tx_bd_cons_upd;
4405 struct tstorm_eth_conn_ag_ctx {
4409 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4410 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4411 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4412 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4413 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
4414 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
4415 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
4416 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
4417 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
4418 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
4419 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
4420 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
4421 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4422 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
4424 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4425 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
4426 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4427 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
4428 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4429 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
4430 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4431 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
4433 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4434 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
4435 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4436 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
4437 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4438 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
4439 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4440 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
4442 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4443 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
4444 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4445 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
4446 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4447 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
4448 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4449 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
4450 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4451 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
4452 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4453 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
4455 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4456 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
4457 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4458 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
4459 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4460 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
4461 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4462 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
4463 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4464 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
4465 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4466 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
4467 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4468 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
4469 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4470 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4472 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4473 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4474 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4475 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4476 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4477 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4478 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4479 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4480 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4481 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4482 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
4483 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
4484 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4485 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4486 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4487 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4509 struct ustorm_eth_conn_ag_ctx {
4513 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4514 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4515 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4516 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4517 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
4518 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
4519 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
4520 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
4521 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4522 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4524 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4525 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
4526 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
4527 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
4528 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
4529 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
4530 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4531 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
4533 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
4534 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
4535 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
4536 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
4537 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4538 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4539 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4540 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
4541 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
4542 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
4543 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
4544 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
4545 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4546 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
4547 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4548 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4550 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4551 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4552 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4553 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4554 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4555 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4556 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4557 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4558 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4559 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4560 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4561 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
4562 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4563 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4564 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4565 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4573 __le32 tx_int_coallecing_timeset;
4574 __le16 tx_drv_bd_cons;
4575 __le16 rx_drv_cqe_cons;
4578 /* The eth storm context for the Ustorm */
4579 struct ustorm_eth_conn_st_ctx {
4580 __le32 reserved[40];
4583 /* The eth storm context for the Mstorm */
4584 struct mstorm_eth_conn_st_ctx {
4588 /* eth connection context */
4589 struct eth_conn_context {
4590 struct tstorm_eth_conn_st_ctx tstorm_st_context;
4591 struct regpair tstorm_st_padding[2];
4592 struct pstorm_eth_conn_st_ctx pstorm_st_context;
4593 struct xstorm_eth_conn_st_ctx xstorm_st_context;
4594 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
4595 struct ystorm_eth_conn_st_ctx ystorm_st_context;
4596 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
4597 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
4598 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
4599 struct ustorm_eth_conn_st_ctx ustorm_st_context;
4600 struct mstorm_eth_conn_st_ctx mstorm_st_context;
4603 enum eth_error_code {
4605 ETH_FILTERS_MAC_ADD_FAIL_FULL,
4606 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
4607 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
4608 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
4609 ETH_FILTERS_MAC_DEL_FAIL_NOF,
4610 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
4611 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
4612 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
4613 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
4614 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
4615 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
4616 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
4617 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
4618 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
4619 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
4620 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
4621 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
4622 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
4623 ETH_FILTERS_VNI_ADD_FAIL_FULL,
4624 ETH_FILTERS_VNI_ADD_FAIL_DUP,
4628 enum eth_event_opcode {
4630 ETH_EVENT_VPORT_START,
4631 ETH_EVENT_VPORT_UPDATE,
4632 ETH_EVENT_VPORT_STOP,
4633 ETH_EVENT_TX_QUEUE_START,
4634 ETH_EVENT_TX_QUEUE_STOP,
4635 ETH_EVENT_RX_QUEUE_START,
4636 ETH_EVENT_RX_QUEUE_UPDATE,
4637 ETH_EVENT_RX_QUEUE_STOP,
4638 ETH_EVENT_FILTERS_UPDATE,
4640 ETH_EVENT_RESERVED2,
4641 ETH_EVENT_RESERVED3,
4642 ETH_EVENT_RX_ADD_UDP_FILTER,
4643 ETH_EVENT_RX_DELETE_UDP_FILTER,
4644 ETH_EVENT_RESERVED4,
4645 ETH_EVENT_RESERVED5,
4646 MAX_ETH_EVENT_OPCODE
4649 /* Classify rule types in E2/E3 */
4650 enum eth_filter_action {
4651 ETH_FILTER_ACTION_UNUSED,
4652 ETH_FILTER_ACTION_REMOVE,
4653 ETH_FILTER_ACTION_ADD,
4654 ETH_FILTER_ACTION_REMOVE_ALL,
4655 MAX_ETH_FILTER_ACTION
4658 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
4659 struct eth_filter_cmd {
4671 /* $$KEEP_ENDIANNESS$$ */
4672 struct eth_filter_cmd_header {
4680 /* Ethernet filter types: mac/vlan/pair */
4681 enum eth_filter_type {
4682 ETH_FILTER_TYPE_UNUSED,
4683 ETH_FILTER_TYPE_MAC,
4684 ETH_FILTER_TYPE_VLAN,
4685 ETH_FILTER_TYPE_PAIR,
4686 ETH_FILTER_TYPE_INNER_MAC,
4687 ETH_FILTER_TYPE_INNER_VLAN,
4688 ETH_FILTER_TYPE_INNER_PAIR,
4689 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
4690 ETH_FILTER_TYPE_MAC_VNI_PAIR,
4691 ETH_FILTER_TYPE_VNI,
4695 enum eth_ipv4_frag_type {
4697 ETH_IPV4_FIRST_FRAG,
4698 ETH_IPV4_NON_FIRST_FRAG,
4699 MAX_ETH_IPV4_FRAG_TYPE
4708 enum eth_ramrod_cmd_id {
4710 ETH_RAMROD_VPORT_START,
4711 ETH_RAMROD_VPORT_UPDATE,
4712 ETH_RAMROD_VPORT_STOP,
4713 ETH_RAMROD_RX_QUEUE_START,
4714 ETH_RAMROD_RX_QUEUE_STOP,
4715 ETH_RAMROD_TX_QUEUE_START,
4716 ETH_RAMROD_TX_QUEUE_STOP,
4717 ETH_RAMROD_FILTERS_UPDATE,
4718 ETH_RAMROD_RX_QUEUE_UPDATE,
4719 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
4720 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
4721 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
4722 ETH_RAMROD_RX_ADD_UDP_FILTER,
4723 ETH_RAMROD_RX_DELETE_UDP_FILTER,
4724 ETH_RAMROD_RX_CREATE_GFT_ACTION,
4725 ETH_RAMROD_GFT_UPDATE_FILTER,
4726 MAX_ETH_RAMROD_CMD_ID
4729 /* return code from eth sp ramrods */
4730 struct eth_return_code {
4732 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
4733 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
4734 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
4735 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
4736 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
4737 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
4740 /* What to do in case an error occurs */
4743 ETH_TX_ERR_ASSERT_MALICIOUS,
4747 /* Array of the different error type behaviors */
4748 struct eth_tx_err_vals {
4750 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
4751 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
4752 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
4753 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
4754 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
4755 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
4756 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
4757 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
4758 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
4759 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
4760 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
4761 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
4762 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
4763 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
4764 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
4765 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
4768 /* vport rss configuration data */
4769 struct eth_vport_rss_config {
4770 __le16 capabilities;
4771 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
4772 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
4773 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
4774 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
4775 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
4776 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
4777 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
4778 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
4779 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
4780 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
4781 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
4782 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
4783 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
4784 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
4785 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
4786 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
4790 u8 update_rss_ind_table;
4791 u8 update_rss_capabilities;
4793 __le32 reserved2[2];
4794 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
4796 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
4797 __le32 reserved3[2];
4800 /* eth vport RSS mode */
4801 enum eth_vport_rss_mode {
4802 ETH_VPORT_RSS_MODE_DISABLED,
4803 ETH_VPORT_RSS_MODE_REGULAR,
4804 MAX_ETH_VPORT_RSS_MODE
4807 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4808 struct eth_vport_rx_mode {
4810 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
4811 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
4812 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4813 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4814 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
4815 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
4816 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
4817 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
4818 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4819 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
4820 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4821 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
4822 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
4823 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
4824 __le16 reserved2[3];
4827 /* Command for setting tpa parameters */
4828 struct eth_vport_tpa_param {
4831 u8 tpa_ipv4_tunn_en_flg;
4832 u8 tpa_ipv6_tunn_en_flg;
4833 u8 tpa_pkt_split_flg;
4834 u8 tpa_hdr_data_split_flg;
4835 u8 tpa_gro_consistent_flg;
4837 u8 tpa_max_aggs_num;
4839 __le16 tpa_max_size;
4840 __le16 tpa_min_size_to_start;
4842 __le16 tpa_min_size_to_cont;
4847 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4848 struct eth_vport_tx_mode {
4850 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4851 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
4852 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4853 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4854 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4855 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
4856 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4857 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
4858 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4859 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
4860 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
4861 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
4862 __le16 reserved2[3];
4865 /* Ramrod data for rx queue start ramrod */
4866 struct rx_queue_start_ramrod_data {
4868 __le16 num_of_pbl_pages;
4869 __le16 bd_max_bytes;
4873 u8 default_rss_queue_flg;
4874 u8 complete_cqe_flg;
4875 u8 complete_event_flg;
4876 u8 stats_counter_id;
4878 u8 pxp_tph_valid_bd;
4879 u8 pxp_tph_valid_pkt;
4882 __le16 pxp_st_index;
4888 u8 vf_rx_prod_index;
4889 u8 vf_rx_prod_use_zone_a;
4892 struct regpair cqe_pbl_addr;
4893 struct regpair bd_base;
4894 struct regpair reserved2;
4897 /* Ramrod data for rx queue start ramrod */
4898 struct rx_queue_stop_ramrod_data {
4900 u8 complete_cqe_flg;
4901 u8 complete_event_flg;
4906 /* Ramrod data for rx queue update ramrod */
4907 struct rx_queue_update_ramrod_data {
4909 u8 complete_cqe_flg;
4910 u8 complete_event_flg;
4918 struct regpair reserved6;
4921 /* Ramrod data for rx Add UDP Filter */
4922 struct rx_udp_filter_data {
4926 u8 tenant_id_exists;
4928 __le32 ip_dst_addr[4];
4929 __le32 ip_src_addr[4];
4930 __le16 udp_dst_port;
4931 __le16 udp_src_port;
4935 /* Ramrod data for rx queue start ramrod */
4936 struct tx_queue_start_ramrod_data {
4941 u8 stats_counter_id;
4944 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4945 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
4946 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4947 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
4948 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
4949 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
4950 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4951 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
4952 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4953 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
4954 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4955 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
4956 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
4957 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
4959 u8 pxp_tph_valid_bd;
4960 u8 pxp_tph_valid_pkt;
4961 __le16 pxp_st_index;
4962 __le16 comp_agg_size;
4963 __le16 queue_zone_id;
4967 __le16 same_as_last_id;
4969 struct regpair pbl_base_addr;
4970 struct regpair bd_cons_address;
4973 /* Ramrod data for tx queue stop ramrod */
4974 struct tx_queue_stop_ramrod_data {
4978 /* Ramrod data for vport update ramrod */
4979 struct vport_filter_update_ramrod_data {
4980 struct eth_filter_cmd_header filter_cmd_hdr;
4981 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
4984 /* Ramrod data for vport start ramrod */
4985 struct vport_start_ramrod_data {
4990 u8 inner_vlan_removal_en;
4991 struct eth_vport_rx_mode rx_mode;
4992 struct eth_vport_tx_mode tx_mode;
4993 struct eth_vport_tpa_param tpa_param;
4994 __le16 default_vlan;
4996 u8 anti_spoofing_en;
5001 u8 silent_vlan_removal_en;
5003 struct eth_tx_err_vals tx_err_behav;
5005 u8 zero_placement_offset;
5006 u8 ctl_frame_mac_check_en;
5007 u8 ctl_frame_ethtype_check_en;
5011 /* Ramrod data for vport stop ramrod */
5012 struct vport_stop_ramrod_data {
5017 /* Ramrod data for vport update ramrod */
5018 struct vport_update_ramrod_data_cmn {
5020 u8 update_rx_active_flg;
5022 u8 update_tx_active_flg;
5024 u8 update_rx_mode_flg;
5025 u8 update_tx_mode_flg;
5026 u8 update_approx_mcast_flg;
5029 u8 update_inner_vlan_removal_en_flg;
5031 u8 inner_vlan_removal_en;
5032 u8 update_tpa_param_flg;
5033 u8 update_tpa_en_flg;
5034 u8 update_tx_switching_en_flg;
5037 u8 update_anti_spoofing_en_flg;
5039 u8 anti_spoofing_en;
5040 u8 update_handle_ptp_pkts;
5043 u8 update_default_vlan_en_flg;
5047 u8 update_default_vlan_flg;
5049 __le16 default_vlan;
5050 u8 update_accept_any_vlan_flg;
5053 u8 silent_vlan_removal_en;
5057 u8 update_ctl_frame_checks_en_flg;
5058 u8 ctl_frame_mac_check_en;
5059 u8 ctl_frame_ethtype_check_en;
5063 struct vport_update_ramrod_mcast {
5064 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
5067 /* Ramrod data for vport update ramrod */
5068 struct vport_update_ramrod_data {
5069 struct vport_update_ramrod_data_cmn common;
5071 struct eth_vport_rx_mode rx_mode;
5072 struct eth_vport_tx_mode tx_mode;
5073 struct eth_vport_tpa_param tpa_param;
5074 struct vport_update_ramrod_mcast approx_mcast;
5075 struct eth_vport_rss_config rss_config;
5078 struct mstorm_eth_conn_ag_ctx {
5082 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5083 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5084 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5085 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5086 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5087 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
5088 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5089 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
5090 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5091 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5093 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5094 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
5095 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5096 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
5097 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5098 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5099 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5100 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5101 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5102 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5103 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5104 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5105 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5106 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5107 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5108 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
5115 struct xstorm_eth_conn_agctxdq_ext_ldpart {
5119 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5120 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5121 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5122 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
5123 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5124 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
5125 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5126 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5127 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5128 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
5129 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5130 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
5131 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5132 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
5133 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5134 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
5136 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5137 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5138 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5139 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
5140 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5141 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
5142 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5143 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5144 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
5145 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
5146 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
5147 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
5148 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
5149 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
5150 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
5151 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
5153 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
5154 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
5155 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
5156 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
5157 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
5158 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
5159 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
5160 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
5162 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
5163 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
5164 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
5165 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
5166 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
5167 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
5168 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
5169 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
5171 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
5172 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
5173 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
5174 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
5175 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
5176 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
5177 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
5178 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
5180 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
5181 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
5182 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
5183 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
5184 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
5185 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
5186 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
5187 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
5189 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
5190 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
5191 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
5192 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
5193 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
5194 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
5195 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
5196 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
5198 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
5199 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
5200 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
5201 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
5202 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
5203 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
5204 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
5205 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
5206 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
5207 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
5209 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
5210 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
5211 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
5212 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
5213 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
5214 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
5215 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
5216 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
5217 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
5218 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
5219 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
5220 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
5221 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
5222 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
5223 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
5224 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
5226 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
5227 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
5228 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
5229 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
5230 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
5231 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
5232 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
5233 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
5234 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
5235 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
5236 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
5237 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
5238 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
5239 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
5240 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
5241 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
5243 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
5244 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
5245 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
5246 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
5247 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
5248 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
5249 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
5250 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
5251 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
5252 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
5253 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
5254 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
5255 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
5256 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
5257 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
5258 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
5260 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
5261 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
5262 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
5263 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
5264 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
5265 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
5266 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
5267 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
5268 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
5269 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
5270 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
5271 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
5272 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
5273 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
5274 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
5275 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
5277 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
5278 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
5279 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
5280 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
5281 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
5282 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
5283 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
5284 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
5285 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
5286 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
5287 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
5288 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
5289 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
5290 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
5291 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
5292 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
5294 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
5295 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
5296 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
5297 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
5298 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
5299 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
5300 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
5301 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
5302 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
5303 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
5304 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
5305 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
5306 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
5307 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
5308 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
5309 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
5311 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
5312 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
5313 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
5314 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
5315 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
5316 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
5317 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5318 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5319 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
5320 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
5321 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
5322 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
5323 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
5324 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
5328 __le16 edpm_num_bds;
5344 struct xstorm_eth_hw_conn_ag_ctx {
5348 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5349 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5350 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
5351 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
5352 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
5353 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
5354 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5355 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5356 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
5357 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
5358 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
5359 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
5360 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
5361 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
5362 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
5363 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
5365 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
5366 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
5367 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
5368 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
5369 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
5370 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
5371 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
5372 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
5373 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
5374 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
5375 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
5376 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
5377 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
5378 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
5379 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
5380 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
5382 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
5383 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
5384 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
5385 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
5386 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
5387 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
5388 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
5389 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
5391 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
5392 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
5393 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
5394 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
5395 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
5396 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
5397 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
5398 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
5400 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
5401 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
5402 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
5403 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
5404 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
5405 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
5406 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
5407 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
5409 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
5410 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
5411 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
5412 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
5413 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
5414 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
5415 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
5416 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
5418 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
5419 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
5420 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
5421 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
5422 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
5423 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
5424 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
5425 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
5427 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5428 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5429 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
5430 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
5431 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5432 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5433 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
5434 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
5435 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
5436 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
5438 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
5439 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
5440 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
5441 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
5442 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
5443 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
5444 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
5445 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
5446 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
5447 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
5448 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
5449 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
5450 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
5451 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
5452 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
5453 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
5455 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
5456 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
5457 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
5458 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
5459 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
5460 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
5461 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
5462 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
5463 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
5464 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
5465 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
5466 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
5467 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
5468 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
5469 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
5470 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
5472 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5473 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
5474 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
5475 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
5476 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5477 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
5478 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
5479 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
5480 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5481 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5482 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
5483 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
5484 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
5485 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
5486 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
5487 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
5489 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
5490 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
5491 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
5492 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
5493 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5494 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
5495 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
5496 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
5497 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
5498 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
5499 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
5500 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
5501 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5502 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5503 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
5504 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
5506 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
5507 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
5508 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
5509 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
5510 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5511 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5512 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5513 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5514 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
5515 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
5516 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
5517 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
5518 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
5519 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
5520 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
5521 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
5523 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
5524 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
5525 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
5526 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
5527 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5528 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5529 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5530 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5531 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5532 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5533 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5534 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5535 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5536 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5537 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5538 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5540 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5541 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5542 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5543 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
5544 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5545 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
5546 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5547 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5548 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5549 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
5550 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5551 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
5552 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5553 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
5557 __le16 edpm_num_bds;
5564 struct mstorm_rdma_task_st_ctx {
5565 struct regpair temp[4];
5568 struct rdma_close_func_ramrod_data {
5569 u8 cnq_start_offset;
5576 struct rdma_cnq_params {
5581 struct regpair pbl_base_addr;
5582 __le16 queue_zone_num;
5586 struct rdma_create_cq_ramrod_data {
5587 struct regpair cq_handle;
5588 struct regpair pbl_addr;
5590 __le16 pbl_num_pages;
5592 u8 is_two_level_pbl;
5594 u8 pbl_log_page_size;
5600 struct rdma_deregister_tid_ramrod_data {
5605 struct rdma_destroy_cq_output_params {
5611 struct rdma_destroy_cq_ramrod_data {
5612 struct regpair output_params_addr;
5615 enum rdma_event_opcode {
5617 RDMA_EVENT_FUNC_INIT,
5618 RDMA_EVENT_FUNC_CLOSE,
5619 RDMA_EVENT_REGISTER_MR,
5620 RDMA_EVENT_DEREGISTER_MR,
5621 RDMA_EVENT_CREATE_CQ,
5622 RDMA_EVENT_RESIZE_CQ,
5623 RDMA_EVENT_DESTROY_CQ,
5624 RDMA_EVENT_CREATE_SRQ,
5625 RDMA_EVENT_MODIFY_SRQ,
5626 RDMA_EVENT_DESTROY_SRQ,
5627 MAX_RDMA_EVENT_OPCODE
5630 enum rdma_fw_return_code {
5632 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
5633 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
5634 RDMA_RETURN_RESIZE_CQ_ERR,
5635 RDMA_RETURN_NIG_DRAIN_REQ,
5636 MAX_RDMA_FW_RETURN_CODE
5639 struct rdma_init_func_hdr {
5640 u8 cnq_start_offset;
5643 u8 cnp_vlan_priority;
5644 __le32 cnp_send_timeout;
5651 struct rdma_init_func_ramrod_data {
5652 struct rdma_init_func_hdr params_header;
5653 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
5656 enum rdma_ramrod_cmd_id {
5658 RDMA_RAMROD_FUNC_INIT,
5659 RDMA_RAMROD_FUNC_CLOSE,
5660 RDMA_RAMROD_REGISTER_MR,
5661 RDMA_RAMROD_DEREGISTER_MR,
5662 RDMA_RAMROD_CREATE_CQ,
5663 RDMA_RAMROD_RESIZE_CQ,
5664 RDMA_RAMROD_DESTROY_CQ,
5665 RDMA_RAMROD_CREATE_SRQ,
5666 RDMA_RAMROD_MODIFY_SRQ,
5667 RDMA_RAMROD_DESTROY_SRQ,
5668 MAX_RDMA_RAMROD_CMD_ID
5671 struct rdma_register_tid_ramrod_data {
5673 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF
5674 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0
5675 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
5676 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18
5677 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
5678 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23
5679 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
5680 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24
5681 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
5682 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25
5683 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
5684 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26
5685 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
5686 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27
5687 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
5688 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28
5689 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
5690 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29
5691 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
5692 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30
5693 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
5694 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31
5696 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
5697 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
5698 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
5699 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
5701 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
5702 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
5703 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
5704 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
5705 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
5706 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
5716 struct regpair pbl_base;
5717 struct regpair dif_error_addr;
5718 struct regpair dif_runt_addr;
5719 __le32 reserved3[2];
5722 struct rdma_resize_cq_output_params {
5727 struct rdma_resize_cq_ramrod_data {
5729 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
5730 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
5731 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
5732 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
5733 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
5734 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
5735 u8 pbl_log_page_size;
5736 __le16 pbl_num_pages;
5738 struct regpair pbl_addr;
5739 struct regpair output_params_addr;
5742 struct rdma_srq_context {
5743 struct regpair temp[8];
5746 struct rdma_srq_create_ramrod_data {
5747 struct regpair pbl_base_addr;
5748 __le16 pages_in_srq_pbl;
5750 struct rdma_srq_id srq_id;
5754 struct regpair producers_addr;
5757 struct rdma_srq_destroy_ramrod_data {
5758 struct rdma_srq_id srq_id;
5762 struct rdma_srq_modify_ramrod_data {
5763 struct rdma_srq_id srq_id;
5767 struct ystorm_rdma_task_st_ctx {
5768 struct regpair temp[4];
5771 struct ystorm_rdma_task_ag_ctx {
5774 __le16 msem_ctx_upd_seq;
5776 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5777 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5778 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5779 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5780 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5781 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5782 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5783 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
5784 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
5785 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
5787 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5788 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5789 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5790 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5791 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5792 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
5793 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5794 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5795 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5796 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5798 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5799 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5800 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5801 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5802 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5803 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5804 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5805 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5806 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5807 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5808 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5809 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5810 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5811 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5812 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5813 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
5819 __le16 tx_ref_count;
5820 __le16 last_used_ltid;
5821 __le16 parent_mr_lo;
5822 __le16 parent_mr_hi;
5827 struct mstorm_rdma_task_ag_ctx {
5832 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5833 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5834 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5835 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5836 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5837 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5838 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5839 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
5840 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
5841 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
5843 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5844 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5845 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5846 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5847 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5848 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
5849 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5850 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5851 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5852 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5854 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5855 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
5856 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5857 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5858 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5859 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5860 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5861 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5862 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5863 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5864 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5865 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5866 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5867 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5868 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5869 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
5875 __le16 tx_ref_count;
5876 __le16 last_used_ltid;
5877 __le16 parent_mr_lo;
5878 __le16 parent_mr_hi;
5883 struct ustorm_rdma_task_st_ctx {
5884 struct regpair temp[2];
5887 struct ustorm_rdma_task_ag_ctx {
5892 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5893 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5894 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5895 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5896 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
5897 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
5898 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5899 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
5901 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5902 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
5903 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5904 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
5905 #define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
5906 #define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
5907 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5908 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
5910 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
5911 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
5912 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
5913 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
5914 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
5915 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
5916 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
5917 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
5918 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
5919 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
5920 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5921 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
5922 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5923 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
5924 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5925 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
5927 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5928 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
5929 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5930 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
5931 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5932 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
5933 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5934 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
5935 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
5936 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
5937 __le32 dif_err_intervals;
5938 __le32 dif_error_1st_interval;
5940 __le32 dif_runt_value;
5945 struct rdma_task_context {
5946 struct ystorm_rdma_task_st_ctx ystorm_st_context;
5947 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
5948 struct tdif_task_context tdif_context;
5949 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
5950 struct mstorm_rdma_task_st_ctx mstorm_st_context;
5951 struct rdif_task_context rdif_context;
5952 struct ustorm_rdma_task_st_ctx ustorm_st_context;
5953 struct regpair ustorm_st_padding[2];
5954 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
5957 enum rdma_tid_type {
5958 RDMA_TID_REGISTERED_MR,
5965 struct mstorm_rdma_conn_ag_ctx {
5969 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
5970 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
5971 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
5972 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
5973 #define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
5974 #define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
5975 #define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
5976 #define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
5977 #define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
5978 #define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
5980 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
5981 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
5982 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
5983 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
5984 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
5985 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
5986 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
5987 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
5988 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
5989 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
5990 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
5991 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
5992 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
5993 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
5994 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
5995 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6002 struct tstorm_rdma_conn_ag_ctx {
6006 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6007 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6008 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6009 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6010 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
6011 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
6012 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
6013 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
6014 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
6015 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
6016 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
6017 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
6018 #define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6019 #define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
6021 #define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6022 #define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
6023 #define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6024 #define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
6025 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6026 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
6027 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6028 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6030 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6031 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6032 #define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6033 #define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
6034 #define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
6035 #define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
6036 #define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
6037 #define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
6039 #define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
6040 #define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
6041 #define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
6042 #define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
6043 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6044 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
6045 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6046 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
6047 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6048 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
6049 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6050 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6052 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6053 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6054 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6055 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
6056 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6057 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
6058 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
6059 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
6060 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
6061 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
6062 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
6063 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
6064 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
6065 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
6066 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6067 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
6069 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6070 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
6071 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6072 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6073 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6074 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6075 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6076 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6077 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6078 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6079 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6080 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6081 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6082 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6083 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6084 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6106 struct tstorm_rdma_task_ag_ctx {
6111 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6112 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6113 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6114 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
6115 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6116 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6117 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6118 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6119 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6120 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6122 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6123 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6124 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6125 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
6126 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6127 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
6128 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6129 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
6130 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6131 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
6133 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6134 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6135 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6136 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
6137 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6138 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
6139 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6140 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
6142 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6143 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6144 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6145 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
6146 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6147 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
6148 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6149 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
6150 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6151 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
6152 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6153 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
6154 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6155 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
6157 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6158 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6159 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6160 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
6161 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6162 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
6163 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6164 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
6165 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6166 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
6167 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6168 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
6169 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6170 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
6171 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6172 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
6185 struct ustorm_rdma_conn_ag_ctx {
6189 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6190 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6191 #define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6192 #define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6193 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6194 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
6195 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6196 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6197 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6198 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6200 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6201 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
6202 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6203 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
6204 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6205 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
6206 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6207 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
6209 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6210 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6211 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6212 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6213 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6214 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6215 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6216 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
6217 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
6218 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
6219 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
6220 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
6221 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6222 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
6223 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
6224 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
6226 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
6227 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
6228 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6229 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6230 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6231 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6232 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6233 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6234 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6235 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6236 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6237 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6238 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6239 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6240 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6241 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6254 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
6258 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
6259 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
6260 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
6261 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
6262 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
6263 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
6264 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
6265 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
6266 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
6267 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
6268 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
6269 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
6270 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
6271 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
6272 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
6273 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
6275 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
6276 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
6277 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
6278 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
6279 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
6280 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
6281 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
6282 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
6283 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
6284 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
6285 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
6286 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
6287 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
6288 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
6289 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
6290 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
6292 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6293 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6294 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6295 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6296 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6297 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6298 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6299 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
6301 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6302 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6303 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6304 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6305 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6306 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6307 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
6308 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
6310 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6311 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6312 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6313 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6314 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6315 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6316 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6317 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
6319 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6320 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6321 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6322 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6323 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6324 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6325 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6326 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
6328 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
6329 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
6330 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
6331 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
6332 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
6333 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
6334 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
6335 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
6337 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
6338 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
6339 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
6340 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
6341 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6342 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6343 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6344 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6345 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6346 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
6348 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6349 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6350 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6351 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6352 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6353 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6354 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6355 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6356 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6357 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6358 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
6359 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
6360 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6361 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6362 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6363 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
6365 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6366 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6367 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6368 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6369 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6370 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6371 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6372 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6373 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6374 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6375 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6376 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6377 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
6378 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
6379 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
6380 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
6382 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
6383 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
6384 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
6385 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
6386 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
6387 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
6388 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
6389 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
6390 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6391 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6392 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
6393 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
6394 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
6395 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
6396 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
6397 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
6399 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
6400 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
6401 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
6402 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
6403 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
6404 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
6405 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6406 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6407 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6408 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6409 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6410 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6411 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6412 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6413 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6414 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
6416 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6417 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6418 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6419 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6420 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6421 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6422 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6423 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6424 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6425 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6426 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6427 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6428 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6429 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6430 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6431 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
6433 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6434 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6435 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6436 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6437 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6438 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6439 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6440 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6441 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6442 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6443 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6444 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6445 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6446 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6447 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6448 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
6450 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
6451 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
6452 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
6453 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
6454 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
6455 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
6456 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
6457 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
6458 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6459 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6460 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
6461 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
6481 struct xstorm_rdma_conn_ag_ctx {
6485 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6486 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6487 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6488 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6489 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
6490 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
6491 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6492 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6493 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
6494 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
6495 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
6496 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
6497 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
6498 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
6499 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
6500 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
6502 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
6503 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
6504 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
6505 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
6506 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
6507 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
6508 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
6509 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
6510 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
6511 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
6512 #define XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1
6513 #define XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5
6514 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
6515 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
6516 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6517 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
6519 #define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6520 #define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
6521 #define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6522 #define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
6523 #define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6524 #define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
6525 #define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6526 #define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
6528 #define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
6529 #define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
6530 #define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
6531 #define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
6532 #define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6533 #define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
6534 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6535 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6537 #define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
6538 #define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
6539 #define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
6540 #define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
6541 #define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
6542 #define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
6543 #define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
6544 #define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
6546 #define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
6547 #define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
6548 #define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
6549 #define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
6550 #define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
6551 #define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
6552 #define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
6553 #define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
6555 #define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
6556 #define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
6557 #define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
6558 #define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
6559 #define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
6560 #define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
6561 #define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
6562 #define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
6564 #define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
6565 #define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
6566 #define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
6567 #define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
6568 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6569 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6570 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6571 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
6572 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6573 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
6575 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6576 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
6577 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6578 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
6579 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
6580 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
6581 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
6582 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
6583 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6584 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
6585 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6586 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
6587 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
6588 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
6589 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
6590 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
6592 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
6593 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
6594 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
6595 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
6596 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
6597 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
6598 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
6599 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
6600 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
6601 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
6602 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
6603 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
6604 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
6605 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
6606 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
6607 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
6609 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
6610 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
6611 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
6612 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
6613 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
6614 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
6615 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
6616 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
6617 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6618 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6619 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
6620 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
6621 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6622 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
6623 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6624 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
6626 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6627 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
6628 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6629 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
6630 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6631 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
6632 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6633 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
6634 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6635 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
6636 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6637 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
6638 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6639 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6640 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
6641 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
6643 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
6644 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
6645 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
6646 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
6647 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6648 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6649 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6650 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6651 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
6652 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
6653 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
6654 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
6655 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
6656 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
6657 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
6658 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
6660 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
6661 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
6662 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
6663 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
6664 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6665 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6666 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6667 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6668 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6669 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6670 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6671 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6672 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6673 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6674 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6675 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6677 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
6678 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
6679 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
6680 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
6681 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6682 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
6683 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
6684 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
6685 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6686 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6687 #define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
6688 #define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
6710 struct ystorm_rdma_conn_ag_ctx {
6714 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
6715 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
6716 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6717 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6718 #define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6719 #define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
6720 #define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6721 #define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6722 #define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6723 #define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6725 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6726 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
6727 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6728 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6729 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6730 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6731 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6732 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
6733 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6734 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
6735 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6736 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
6737 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6738 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
6739 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6740 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6754 struct mstorm_roce_conn_st_ctx {
6755 struct regpair temp[6];
6758 struct pstorm_roce_conn_st_ctx {
6759 struct regpair temp[16];
6762 struct ystorm_roce_conn_st_ctx {
6763 struct regpair temp[2];
6766 struct xstorm_roce_conn_st_ctx {
6767 struct regpair temp[24];
6770 struct tstorm_roce_conn_st_ctx {
6771 struct regpair temp[30];
6774 struct ustorm_roce_conn_st_ctx {
6775 struct regpair temp[12];
6778 struct roce_conn_context {
6779 struct ystorm_roce_conn_st_ctx ystorm_st_context;
6780 struct regpair ystorm_st_padding[2];
6781 struct pstorm_roce_conn_st_ctx pstorm_st_context;
6782 struct xstorm_roce_conn_st_ctx xstorm_st_context;
6783 struct regpair xstorm_st_padding[2];
6784 struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
6785 struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
6786 struct timers_context timer_context;
6787 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
6788 struct tstorm_roce_conn_st_ctx tstorm_st_context;
6789 struct mstorm_roce_conn_st_ctx mstorm_st_context;
6790 struct ustorm_roce_conn_st_ctx ustorm_st_context;
6791 struct regpair ustorm_st_padding[2];
6794 struct roce_create_qp_req_ramrod_data {
6796 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6797 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6798 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6799 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
6800 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6801 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
6802 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6803 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
6804 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
6805 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
6806 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6807 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
6808 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6809 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
6817 __le32 ack_timeout_val;
6821 __le16 sq_num_pages;
6822 __le16 low_latency_phy_queue;
6823 struct regpair sq_pbl_addr;
6824 struct regpair orq_pbl_addr;
6825 __le16 local_mac_addr[3];
6826 __le16 remote_mac_addr[3];
6828 __le16 udp_src_port;
6831 struct regpair qp_handle_for_cqe;
6832 struct regpair qp_handle_for_async;
6833 u8 stats_counter_id;
6836 __le16 regular_latency_phy_queue;
6840 struct roce_create_qp_resp_ramrod_data {
6842 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6843 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6844 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6845 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
6846 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6847 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
6848 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6849 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
6850 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
6851 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
6852 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
6853 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
6854 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6855 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
6856 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6857 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
6858 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6859 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
6867 u8 stats_counter_id;
6872 __le16 rq_num_pages;
6873 struct rdma_srq_id srq_id;
6874 struct regpair rq_pbl_addr;
6875 struct regpair irq_pbl_addr;
6876 __le16 local_mac_addr[3];
6877 __le16 remote_mac_addr[3];
6879 __le16 udp_src_port;
6882 struct regpair qp_handle_for_cqe;
6883 struct regpair qp_handle_for_async;
6884 __le16 low_latency_phy_queue;
6887 __le16 regular_latency_phy_queue;
6891 struct roce_destroy_qp_req_output_params {
6892 __le32 num_bound_mw;
6896 struct roce_destroy_qp_req_ramrod_data {
6897 struct regpair output_params_addr;
6900 struct roce_destroy_qp_resp_output_params {
6901 __le32 num_invalidated_mw;
6905 struct roce_destroy_qp_resp_ramrod_data {
6906 struct regpair output_params_addr;
6909 enum roce_event_opcode {
6910 ROCE_EVENT_CREATE_QP = 11,
6911 ROCE_EVENT_MODIFY_QP,
6912 ROCE_EVENT_QUERY_QP,
6913 ROCE_EVENT_DESTROY_QP,
6914 MAX_ROCE_EVENT_OPCODE
6917 struct roce_init_func_ramrod_data {
6918 struct rdma_init_func_ramrod_data rdma;
6921 struct roce_modify_qp_req_ramrod_data {
6923 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
6924 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
6925 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
6926 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
6927 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
6928 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
6929 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
6930 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
6931 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
6932 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
6933 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
6934 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
6935 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
6936 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
6937 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
6938 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
6939 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
6940 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
6941 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
6942 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
6943 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6944 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
6945 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
6946 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
6948 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6949 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
6950 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6951 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
6957 __le32 ack_timeout_val;
6960 __le32 reserved3[3];
6965 struct roce_modify_qp_resp_ramrod_data {
6967 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
6968 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
6969 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6970 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
6971 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6972 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
6973 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6974 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
6975 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
6976 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
6977 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
6978 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
6979 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
6980 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
6981 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
6982 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
6983 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
6984 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
6985 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
6986 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
6987 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
6988 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
6990 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6991 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
6992 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6993 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
7005 struct roce_query_qp_req_output_params {
7008 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7009 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7010 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7011 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7012 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7013 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
7016 struct roce_query_qp_req_ramrod_data {
7017 struct regpair output_params_addr;
7020 struct roce_query_qp_resp_output_params {
7023 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7024 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7025 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7026 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7029 struct roce_query_qp_resp_ramrod_data {
7030 struct regpair output_params_addr;
7033 enum roce_ramrod_cmd_id {
7034 ROCE_RAMROD_CREATE_QP = 11,
7035 ROCE_RAMROD_MODIFY_QP,
7036 ROCE_RAMROD_QUERY_QP,
7037 ROCE_RAMROD_DESTROY_QP,
7038 MAX_ROCE_RAMROD_CMD_ID
7041 struct mstorm_roce_req_conn_ag_ctx {
7045 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7046 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7047 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7048 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7049 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7050 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7051 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7052 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7053 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7054 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7056 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7057 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7058 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7059 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7060 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7061 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7062 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7063 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7064 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7065 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7066 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7067 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7068 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7069 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7070 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7071 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7078 struct mstorm_roce_resp_conn_ag_ctx {
7082 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7083 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7084 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7085 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7086 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7087 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7088 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7089 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7090 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7091 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7093 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7094 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7095 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7096 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7097 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7098 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7099 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7100 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7101 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7102 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7103 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7104 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7105 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7106 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7107 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7108 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
7116 PLAIN_ROCE /* RoCE v1 */ ,
7117 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */ ,
7118 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */ ,
7122 struct tstorm_roce_req_conn_ag_ctx {
7126 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7127 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7128 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1
7129 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
7130 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1
7131 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
7132 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7133 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
7134 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7135 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7136 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7137 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
7138 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7139 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
7141 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7142 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
7143 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7144 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
7145 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7146 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7147 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7148 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7150 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7151 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7152 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7153 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
7154 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7155 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
7156 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7157 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
7159 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7160 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7161 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7162 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
7163 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7164 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
7165 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7166 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
7167 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7168 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
7169 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7170 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7172 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7173 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7174 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7175 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7176 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7177 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
7178 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7179 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
7180 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7181 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
7182 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7183 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
7184 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7185 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
7186 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7187 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7189 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7190 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7191 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7192 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7193 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7194 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7195 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7196 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7197 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7198 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7199 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7200 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
7201 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7202 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7203 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7204 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7214 u8 tx_cqe_error_type;
7216 __le16 snd_sq_cons_th;
7226 struct tstorm_roce_resp_conn_ag_ctx {
7230 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7231 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7232 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7233 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7234 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7235 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
7236 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7237 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
7238 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7239 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7240 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7241 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
7242 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7243 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
7245 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7246 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7247 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7248 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
7249 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7250 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
7251 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7252 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7254 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7255 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7256 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7257 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
7258 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7259 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
7260 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7261 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
7263 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7264 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7265 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7266 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
7267 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7268 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
7269 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7270 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
7271 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7272 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
7273 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7274 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
7276 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7277 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7278 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7279 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7280 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7281 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
7282 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7283 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
7284 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7285 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
7286 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7287 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
7288 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7289 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
7290 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7291 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7293 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7294 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7295 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7296 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7297 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7298 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7299 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7300 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7301 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7302 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7303 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7304 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
7305 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7306 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7307 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7308 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7309 __le32 psn_and_rxmit_id_echo;
7318 u8 tx_async_error_type;
7326 __le32 num_invlidated_mw;
7330 struct ustorm_roce_req_conn_ag_ctx {
7334 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7335 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7336 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7337 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7338 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7339 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7340 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7341 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7342 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7343 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7345 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7346 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
7347 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7348 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
7349 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7350 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
7351 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
7352 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
7354 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7355 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7356 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7357 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7358 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7359 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7360 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7361 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
7362 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7363 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
7364 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7365 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
7366 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7367 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
7368 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7369 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7371 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7372 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7373 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7374 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7375 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7376 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7377 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7378 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7379 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7380 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7381 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7382 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
7383 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7384 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7385 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7386 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7399 struct ustorm_roce_resp_conn_ag_ctx {
7403 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7404 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7405 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7406 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7407 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7408 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7409 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7410 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7411 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7412 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7414 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7415 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
7416 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
7417 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
7418 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
7419 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
7420 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7421 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
7423 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7424 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7425 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7426 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7427 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7428 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7429 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7430 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
7431 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
7432 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
7433 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
7434 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
7435 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7436 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
7437 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7438 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7440 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7441 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7442 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7443 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7444 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7445 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7446 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7447 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7448 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7449 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7450 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
7451 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
7452 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7453 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7454 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7455 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7468 struct xstorm_roce_req_conn_ag_ctx {
7472 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7473 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7474 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
7475 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
7476 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
7477 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
7478 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7479 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7480 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
7481 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
7482 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
7483 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
7484 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
7485 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
7486 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
7487 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
7489 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
7490 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
7491 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
7492 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
7493 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
7494 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
7495 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
7496 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
7497 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
7498 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
7499 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
7500 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
7501 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
7502 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
7503 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7504 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7506 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7507 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
7508 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7509 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
7510 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7511 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
7512 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7513 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
7515 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
7516 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
7517 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7518 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
7519 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
7520 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
7521 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7522 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7524 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
7525 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
7526 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
7527 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
7528 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
7529 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
7530 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
7531 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
7533 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
7534 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
7535 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
7536 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
7537 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
7538 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
7539 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
7540 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
7542 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
7543 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
7544 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
7545 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
7546 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
7547 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
7548 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
7549 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
7551 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
7552 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
7553 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
7554 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
7555 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7556 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7557 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7558 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
7559 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7560 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
7562 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7563 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
7564 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7565 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
7566 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
7567 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
7568 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7569 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
7570 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
7571 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
7572 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7573 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7574 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
7575 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
7576 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
7577 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
7579 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
7580 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
7581 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
7582 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
7583 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
7584 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
7585 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
7586 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
7587 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
7588 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
7589 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
7590 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
7591 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
7592 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
7593 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
7594 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
7596 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
7597 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
7598 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
7599 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
7600 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
7601 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
7602 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
7603 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
7604 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7605 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7606 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
7607 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
7608 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7609 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
7610 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7611 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
7613 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7614 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
7615 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7616 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
7617 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7618 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
7619 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7620 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
7621 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7622 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
7623 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
7624 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
7625 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7626 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7627 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
7628 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
7630 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
7631 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
7632 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
7633 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
7634 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7635 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7636 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7637 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7638 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
7639 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
7640 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
7641 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
7642 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
7643 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
7644 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
7645 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
7647 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
7648 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
7649 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
7650 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
7651 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7652 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7653 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7654 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7655 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7656 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7657 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7658 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7659 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7660 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7661 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7662 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7664 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
7665 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
7666 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
7667 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
7668 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7669 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7670 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
7671 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
7672 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7673 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7674 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
7675 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
7697 struct xstorm_roce_resp_conn_ag_ctx {
7701 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7702 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7703 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
7704 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
7705 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
7706 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
7707 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7708 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7709 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
7710 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
7711 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
7712 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
7713 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
7714 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
7715 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
7716 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
7718 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
7719 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
7720 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
7721 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
7722 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
7723 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
7724 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
7725 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
7726 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
7727 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
7728 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
7729 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
7730 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
7731 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
7732 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7733 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7735 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7736 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
7737 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7738 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
7739 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7740 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
7741 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7742 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
7744 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
7745 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
7746 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7747 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
7748 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
7749 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
7750 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7751 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7753 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7754 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
7755 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7756 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
7757 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7758 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
7759 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
7760 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
7762 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
7763 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
7764 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
7765 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
7766 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
7767 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
7768 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
7769 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
7771 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
7772 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
7773 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
7774 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
7775 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
7776 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
7777 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
7778 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
7780 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
7781 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
7782 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
7783 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
7784 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7785 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7786 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7787 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
7788 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7789 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
7791 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7792 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
7793 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7794 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
7795 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
7796 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
7797 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7798 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
7799 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
7800 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
7801 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7802 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7803 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7804 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
7805 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7806 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
7808 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7809 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
7810 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
7811 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
7812 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
7813 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
7814 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
7815 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
7816 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
7817 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
7818 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
7819 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
7820 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
7821 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
7822 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
7823 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
7825 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
7826 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
7827 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
7828 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
7829 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
7830 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
7831 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
7832 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
7833 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7834 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7835 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
7836 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
7837 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7838 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
7839 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7840 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
7842 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7843 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
7844 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7845 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
7846 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7847 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
7848 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7849 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
7850 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
7851 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
7852 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7853 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
7854 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7855 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7856 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
7857 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
7859 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1
7860 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
7861 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
7862 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
7863 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7864 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7865 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7866 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7867 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
7868 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
7869 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
7870 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
7871 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
7872 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
7873 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
7874 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
7876 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
7877 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
7878 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
7879 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
7880 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7881 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7882 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7883 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7884 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7885 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7886 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7887 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7888 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7889 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7890 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7891 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7893 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
7894 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
7895 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
7896 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
7897 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
7898 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
7899 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
7900 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
7901 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
7902 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
7903 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
7904 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
7905 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
7906 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
7919 __le32 rxmit_psn_and_id;
7920 __le32 rxmit_bytes_length;
7925 __le32 msn_and_syndrome;
7928 struct ystorm_roce_req_conn_ag_ctx {
7932 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7933 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7934 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7935 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7936 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7937 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7938 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7939 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7940 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7941 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7943 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7944 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7945 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7946 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7947 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7948 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7949 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7950 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7951 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7952 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7953 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7954 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7955 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7956 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7957 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7958 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7972 struct ystorm_roce_resp_conn_ag_ctx {
7976 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7977 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7978 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7979 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7980 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7981 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7982 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7983 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7984 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7985 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7987 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7988 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7989 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7990 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7991 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7992 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7993 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7994 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7995 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7996 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7997 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7998 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7999 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8000 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8001 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8002 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8016 struct ystorm_fcoe_conn_st_ctx {
8021 __le16 stat_ram_addr;
8023 __le16 max_fc_payload_len;
8024 __le16 tx_max_fc_pay_len;
8028 struct regpair reserved;
8029 __le16 min_frame_size;
8030 u8 protection_info_flags;
8031 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
8032 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
8033 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
8034 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
8035 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
8036 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
8037 u8 dst_protection_per_mss;
8038 u8 src_protection_per_mss;
8039 u8 ptu_log_page_size;
8041 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
8042 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
8043 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
8044 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
8045 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
8046 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
8050 struct fcoe_vlan_fields {
8052 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
8053 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
8054 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
8055 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
8056 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
8057 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
8060 union fcoe_vlan_field_union {
8061 struct fcoe_vlan_fields fields;
8065 union fcoe_vlan_vif_field_union {
8066 union fcoe_vlan_field_union vlan;
8070 struct pstorm_fcoe_eth_context_section {
8083 union fcoe_vlan_vif_field_union vif_outer_vlan;
8084 __le16 vif_outer_eth_type;
8085 union fcoe_vlan_vif_field_union inner_vlan;
8086 __le16 inner_eth_type;
8089 struct pstorm_fcoe_conn_st_ctx {
8094 __le16 stat_ram_addr;
8096 struct regpair abts_cleanup_addr;
8097 struct pstorm_fcoe_eth_context_section eth;
8102 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
8103 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
8104 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
8105 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
8106 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
8107 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
8108 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
8109 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
8110 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
8111 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
8116 __le16 rec_rr_tov_val;
8117 u8 q_relative_offset;
8121 struct xstorm_fcoe_conn_st_ctx {
8125 u8 cached_wqes_avail;
8126 __le16 stat_ram_addr;
8128 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
8129 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
8130 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
8131 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
8132 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
8133 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
8134 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
8135 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
8136 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
8137 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
8138 u8 cached_wqes_offset;
8143 __le16 num_pages_in_pbl;
8145 struct regpair sq_pbl_addr;
8146 struct regpair sq_curr_page_addr;
8147 struct regpair sq_next_page_addr;
8148 struct regpair xferq_pbl_addr;
8149 struct regpair xferq_curr_page_addr;
8150 struct regpair xferq_next_page_addr;
8151 struct regpair respq_pbl_addr;
8152 struct regpair respq_curr_page_addr;
8153 struct regpair respq_next_page_addr;
8155 __le16 tx_max_fc_pay_len;
8156 __le16 max_fc_payload_len;
8157 __le16 min_frame_size;
8158 __le16 sq_pbl_next_index;
8159 __le16 respq_pbl_next_index;
8160 u8 fcp_cmd_byte_credit;
8161 u8 fcp_rsp_byte_credit;
8162 __le16 protection_info;
8163 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
8164 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
8165 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
8166 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
8167 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
8168 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
8169 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
8170 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
8171 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
8172 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
8173 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
8174 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
8175 __le16 xferq_pbl_next_index;
8178 u8 fcp_xfer_byte_credit;
8180 struct fcoe_wqe cached_wqes[16];
8183 struct xstorm_fcoe_conn_ag_ctx {
8187 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8188 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8189 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
8190 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
8191 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
8192 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
8193 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8194 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8195 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
8196 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
8197 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
8198 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
8199 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
8200 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
8201 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
8202 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
8204 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
8205 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
8206 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
8207 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
8208 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
8209 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
8210 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
8211 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
8212 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
8213 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
8214 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
8215 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
8216 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
8217 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
8218 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
8219 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
8221 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8222 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
8223 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8224 #define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
8225 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8226 #define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
8227 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
8228 #define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
8230 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
8231 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
8232 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
8233 #define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
8234 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
8235 #define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
8236 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
8237 #define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
8239 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
8240 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
8241 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
8242 #define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
8243 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
8244 #define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
8245 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
8246 #define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
8248 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
8249 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
8250 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
8251 #define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
8252 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
8253 #define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
8254 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
8255 #define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
8257 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
8258 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
8259 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
8260 #define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
8261 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
8262 #define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
8263 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
8264 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
8266 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8267 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8268 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
8269 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
8270 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8271 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8272 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8273 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
8274 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8275 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
8277 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8278 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
8279 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
8280 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
8281 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
8282 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
8283 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
8284 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
8285 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
8286 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
8287 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
8288 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
8289 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
8290 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
8291 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
8292 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
8294 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
8295 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
8296 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
8297 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
8298 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
8299 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
8300 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
8301 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
8302 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
8303 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
8304 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
8305 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
8306 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
8307 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
8308 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
8309 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
8311 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
8312 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
8313 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
8314 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
8315 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8316 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
8317 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
8318 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
8319 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8320 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8321 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
8322 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
8323 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
8324 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
8325 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
8326 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
8328 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
8329 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
8330 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
8331 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
8332 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
8333 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
8334 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
8335 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
8336 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
8337 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
8338 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
8339 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
8340 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8341 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8342 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
8343 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
8345 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
8346 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
8347 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
8348 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
8349 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8350 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8351 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8352 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8353 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
8354 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
8355 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
8356 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
8357 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
8358 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
8359 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
8360 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
8362 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
8363 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
8364 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
8365 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
8366 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8367 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8368 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8369 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8370 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8371 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8372 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8373 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8374 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8375 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8376 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8377 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8379 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
8380 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
8381 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
8382 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
8383 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
8384 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
8385 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
8386 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
8387 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
8388 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
8389 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
8390 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
8391 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
8392 #define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
8420 struct ustorm_fcoe_conn_st_ctx {
8421 struct regpair respq_pbl_addr;
8422 __le16 num_pages_in_pbl;
8423 u8 ptu_log_page_size;
8429 struct tstorm_fcoe_conn_ag_ctx {
8433 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8434 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8435 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8436 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8437 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
8438 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
8439 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
8440 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
8441 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
8442 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
8443 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
8444 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
8445 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
8446 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
8448 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8449 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
8450 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8451 #define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
8452 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
8453 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
8454 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
8455 #define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
8457 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
8458 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
8459 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
8460 #define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
8461 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
8462 #define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
8463 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
8464 #define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
8466 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
8467 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
8468 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
8469 #define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
8470 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
8471 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
8472 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8473 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8474 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8475 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
8476 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
8477 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
8479 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
8480 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
8481 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
8482 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
8483 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
8484 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
8485 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
8486 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
8487 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
8488 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
8489 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
8490 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
8491 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
8492 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
8493 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8494 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
8496 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8497 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
8498 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8499 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
8500 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8501 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
8502 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8503 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
8504 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
8505 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
8506 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
8507 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
8508 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
8509 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
8510 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
8511 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
8516 struct ustorm_fcoe_conn_ag_ctx {
8520 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
8521 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
8522 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8523 #define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8524 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8525 #define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
8526 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8527 #define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
8528 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8529 #define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
8531 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
8532 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
8533 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
8534 #define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
8535 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
8536 #define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
8537 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
8538 #define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
8540 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8541 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
8542 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8543 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
8544 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8545 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
8546 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
8547 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
8548 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
8549 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
8550 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
8551 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
8552 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
8553 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
8554 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8555 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
8557 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8558 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
8559 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8560 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
8561 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8562 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
8563 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8564 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
8565 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
8566 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
8567 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
8568 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
8569 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
8570 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
8571 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
8572 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
8585 struct tstorm_fcoe_conn_st_ctx {
8586 __le16 stat_ram_addr;
8587 __le16 rx_max_fc_payload_len;
8590 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
8591 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
8592 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
8593 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
8594 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
8595 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
8596 u8 timers_cleanup_invocation_cnt;
8597 __le32 reserved1[2];
8598 __le32 dst_mac_address_bytes0to3;
8599 __le16 dst_mac_address_bytes4to5;
8602 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
8603 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
8604 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
8605 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
8606 u8 q_relative_offset;
8611 struct mstorm_fcoe_conn_ag_ctx {
8615 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
8616 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
8617 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8618 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8619 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8620 #define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
8621 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8622 #define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
8623 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8624 #define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
8626 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8627 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
8628 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8629 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
8630 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8631 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
8632 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8633 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
8634 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8635 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
8636 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8637 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
8638 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8639 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
8640 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8641 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
8648 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
8652 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
8653 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
8654 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
8655 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
8656 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
8657 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
8658 u8 q_relative_offset;
8662 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
8664 __le16 stat_ram_addr;
8665 __le16 num_pages_in_pbl;
8666 u8 ptu_log_page_size;
8668 __le16 unsolicited_cq_count;
8672 struct regpair xferq_pbl_addr;
8673 struct regpair reserved1;
8674 struct regpair reserved2[3];
8677 struct mstorm_fcoe_conn_st_ctx {
8678 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
8679 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
8682 struct fcoe_conn_context {
8683 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
8684 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
8685 struct regpair pstorm_st_padding[2];
8686 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
8687 struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
8688 struct regpair xstorm_ag_padding[6];
8689 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
8690 struct regpair ustorm_st_padding[2];
8691 struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
8692 struct regpair tstorm_ag_padding[2];
8693 struct timers_context timer_context;
8694 struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
8695 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
8696 struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
8697 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
8700 struct fcoe_conn_offload_ramrod_params {
8701 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
8704 struct fcoe_conn_terminate_ramrod_params {
8705 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
8708 enum fcoe_event_type {
8709 FCOE_EVENT_INIT_FUNC,
8710 FCOE_EVENT_DESTROY_FUNC,
8711 FCOE_EVENT_STAT_FUNC,
8712 FCOE_EVENT_OFFLOAD_CONN,
8713 FCOE_EVENT_TERMINATE_CONN,
8718 struct fcoe_init_ramrod_params {
8719 struct fcoe_init_func_ramrod_data init_ramrod_data;
8722 enum fcoe_ramrod_cmd_id {
8723 FCOE_RAMROD_CMD_ID_INIT_FUNC,
8724 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
8725 FCOE_RAMROD_CMD_ID_STAT_FUNC,
8726 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
8727 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
8728 MAX_FCOE_RAMROD_CMD_ID
8731 struct fcoe_stat_ramrod_params {
8732 struct fcoe_stat_ramrod_data stat_ramrod_data;
8735 struct ystorm_fcoe_conn_ag_ctx {
8739 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
8740 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
8741 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8742 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8743 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8744 #define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
8745 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8746 #define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
8747 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8748 #define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
8750 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8751 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
8752 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8753 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
8754 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8755 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
8756 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8757 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
8758 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8759 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
8760 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8761 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
8762 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8763 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
8764 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8765 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
8779 struct ystorm_iscsi_conn_st_ctx {
8783 struct pstorm_iscsi_tcp_conn_st_ctx {
8788 struct xstorm_iscsi_tcp_conn_st_ctx {
8789 __le32 reserved_iscsi[40];
8790 __le32 reserved_tcp[4];
8793 struct xstorm_iscsi_conn_ag_ctx {
8797 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8798 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8799 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8800 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
8801 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
8802 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
8803 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8804 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8805 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
8806 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
8807 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
8808 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
8809 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
8810 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
8811 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
8812 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
8814 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
8815 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
8816 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
8817 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
8818 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
8819 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
8820 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
8821 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
8822 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
8823 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
8824 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
8825 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
8826 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
8827 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
8828 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
8829 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
8831 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
8832 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
8833 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
8834 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
8835 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
8836 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
8837 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8838 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
8840 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
8841 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
8842 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
8843 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
8844 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
8845 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
8846 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
8847 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
8849 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
8850 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
8851 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
8852 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
8853 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
8854 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
8855 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
8856 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
8858 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
8859 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
8860 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
8861 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
8862 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
8863 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
8864 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
8865 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
8867 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
8868 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
8869 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
8870 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
8871 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
8872 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
8873 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8874 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
8876 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
8877 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
8878 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
8879 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
8880 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8881 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8882 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
8883 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
8884 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
8885 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
8887 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
8888 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
8889 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8890 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
8891 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
8892 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
8893 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
8894 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
8895 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
8896 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
8897 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
8898 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
8899 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
8900 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
8901 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
8902 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
8904 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
8905 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
8906 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
8907 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
8908 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
8909 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
8910 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
8911 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
8912 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
8913 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
8914 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
8915 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
8916 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
8917 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
8918 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
8919 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
8921 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
8922 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
8923 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8924 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
8925 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
8926 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
8927 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
8928 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
8929 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8930 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8931 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
8932 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
8933 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
8934 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
8935 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
8936 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
8938 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8939 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
8940 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
8941 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
8942 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
8943 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
8944 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
8945 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
8946 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
8947 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
8948 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
8949 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
8950 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8951 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8952 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
8953 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
8955 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
8956 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
8957 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
8958 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
8959 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8960 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8961 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8962 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8963 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
8964 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
8965 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
8966 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
8967 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
8968 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
8969 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
8970 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
8972 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
8973 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
8974 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
8975 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
8976 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8977 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8978 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8979 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8980 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8981 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8982 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8983 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8984 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8985 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8986 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8987 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8989 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
8990 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
8991 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
8992 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
8993 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
8994 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
8995 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
8996 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
8997 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
8998 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
8999 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
9000 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
9001 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
9002 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
9006 __le16 dummy_dorq_var;
9010 __le16 slow_io_total_data_tx_update;
9018 __le32 more_to_send_seq;
9021 __le32 hq_scan_next_relevant_ack;
9027 __le32 bytes_to_next_pdu;
9043 __le32 ongoing_fast_rxmit_seq;
9050 struct tstorm_iscsi_conn_ag_ctx {
9054 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9055 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9056 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9057 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9058 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
9059 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
9060 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
9061 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
9062 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
9063 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
9064 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
9065 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
9066 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9067 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
9069 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
9070 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
9071 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
9072 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
9073 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9074 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
9075 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
9076 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
9078 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
9079 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
9080 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
9081 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
9082 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
9083 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
9084 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
9085 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
9087 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9088 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9089 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
9090 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
9091 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9092 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
9093 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
9094 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
9095 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
9096 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
9097 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9098 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
9100 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
9101 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
9102 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
9103 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
9104 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
9105 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
9106 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
9107 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
9108 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
9109 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
9110 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9111 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
9112 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
9113 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
9114 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9115 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
9117 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9118 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
9119 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9120 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
9121 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9122 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
9123 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9124 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
9125 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
9126 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
9127 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
9128 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
9129 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
9130 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
9131 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
9132 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
9147 struct ustorm_iscsi_conn_ag_ctx {
9151 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
9152 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
9153 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9154 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9155 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9156 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
9157 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9158 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
9159 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9160 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
9162 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
9163 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
9164 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
9165 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
9166 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
9167 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
9168 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
9169 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
9171 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9172 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
9173 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9174 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
9175 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9176 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
9177 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
9178 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
9179 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
9180 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
9181 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
9182 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
9183 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
9184 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
9185 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9186 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
9188 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9189 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
9190 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9191 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
9192 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9193 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
9194 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9195 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
9196 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
9197 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
9198 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
9199 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
9200 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
9201 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
9202 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
9203 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
9216 struct tstorm_iscsi_conn_st_ctx {
9217 __le32 reserved[40];
9220 struct mstorm_iscsi_conn_ag_ctx {
9224 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
9225 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
9226 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9227 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9228 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9229 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
9230 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9231 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
9232 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9233 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
9235 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9236 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
9237 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9238 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
9239 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9240 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
9241 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9242 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
9243 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9244 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
9245 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9246 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
9247 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9248 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
9249 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9250 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
9257 struct mstorm_iscsi_tcp_conn_st_ctx {
9258 __le32 reserved_tcp[20];
9259 __le32 reserved_iscsi[8];
9262 struct ustorm_iscsi_conn_st_ctx {
9263 __le32 reserved[52];
9266 struct iscsi_conn_context {
9267 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
9268 struct regpair ystorm_st_padding[2];
9269 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
9270 struct regpair pstorm_st_padding[2];
9271 struct pb_context xpb2_context;
9272 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
9273 struct regpair xstorm_st_padding[2];
9274 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
9275 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
9276 struct regpair tstorm_ag_padding[2];
9277 struct timers_context timer_context;
9278 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
9279 struct pb_context upb_context;
9280 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
9281 struct regpair tstorm_st_padding[2];
9282 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
9283 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
9284 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
9287 struct iscsi_init_ramrod_params {
9288 struct iscsi_spe_func_init iscsi_init_spe;
9289 struct tcp_init_params tcp_init;
9292 struct ystorm_iscsi_conn_ag_ctx {
9296 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
9297 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
9298 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9299 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9300 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9301 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
9302 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9303 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
9304 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9305 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
9307 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9308 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
9309 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9310 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
9311 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9312 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
9313 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9314 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
9315 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9316 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
9317 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9318 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
9319 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9320 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
9321 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9322 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
9336 #define MFW_TRACE_SIGNATURE 0x25071946
9338 /* The trace in the buffer */
9339 #define MFW_TRACE_EVENTID_MASK 0x00ffff
9340 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
9341 #define MFW_TRACE_PRM_SIZE_SHIFT 16
9342 #define MFW_TRACE_ENTRY_SIZE 3
9345 u32 signature; /* Help to identify that the trace is valid */
9346 u32 size; /* the size of the trace buffer in bytes */
9347 u32 curr_level; /* 2 - all will be written to the buffer
9348 * 1 - debug trace will not be written
9349 * 0 - just errors will be written to the buffer
9351 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
9355 /* Warning: the following pointers are assumed to be 32bits as they are
9356 * used only in the MFW.
9358 u32 trace_prod; /* The next trace will be written to this offset */
9359 u32 trace_oldest; /* The oldest valid trace starts at this offset
9360 * (usually very close after the current producer).
9364 #define VF_MAX_STATIC 192
9366 #define MCP_GLOB_PATH_MAX 2
9367 #define MCP_PORT_MAX 2
9368 #define MCP_GLOB_PORT_MAX 4
9369 #define MCP_GLOB_FUNC_MAX 16
9371 typedef u32 offsize_t; /* In DWORDS !!! */
9372 /* Offset from the beginning of the MCP scratchpad */
9373 #define OFFSIZE_OFFSET_SHIFT 0
9374 #define OFFSIZE_OFFSET_MASK 0x0000ffff
9375 /* Size of specific element (not the whole array if any) */
9376 #define OFFSIZE_SIZE_SHIFT 16
9377 #define OFFSIZE_SIZE_MASK 0xffff0000
9379 #define SECTION_OFFSET(_offsize) ((((_offsize & \
9380 OFFSIZE_OFFSET_MASK) >> \
9381 OFFSIZE_OFFSET_SHIFT) << 2))
9383 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
9384 OFFSIZE_SIZE_MASK) >> \
9385 OFFSIZE_SIZE_SHIFT) << 2)
9387 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
9388 SECTION_OFFSET(_offsize) + \
9389 (QED_SECTION_SIZE(_offsize) * idx))
9391 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
9392 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
9394 /* PHY configuration */
9395 struct eth_phy_cfg {
9397 #define ETH_SPEED_AUTONEG 0
9398 #define ETH_SPEED_SMARTLINQ 0x8
9401 #define ETH_PAUSE_NONE 0x0
9402 #define ETH_PAUSE_AUTONEG 0x1
9403 #define ETH_PAUSE_RX 0x2
9404 #define ETH_PAUSE_TX 0x4
9408 #define ETH_LOOPBACK_NONE (0)
9409 #define ETH_LOOPBACK_INT_PHY (1)
9410 #define ETH_LOOPBACK_EXT_PHY (2)
9411 #define ETH_LOOPBACK_EXT (3)
9412 #define ETH_LOOPBACK_MAC (4)
9414 u32 feature_config_flags;
9415 #define ETH_EEE_MODE_ADV_LPI (1 << 0)
9418 struct port_mf_cfg {
9420 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
9421 #define PORT_MF_CFG_OV_TAG_SHIFT 0
9422 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
9476 u64 brb_truncate[8];
9481 struct brb_stats brb;
9482 struct eth_stats eth;
9485 struct couple_mode_teaming {
9486 u8 port_cmt[MCP_GLOB_PORT_MAX];
9487 #define PORT_CMT_IN_TEAM (1 << 0)
9489 #define PORT_CMT_PORT_ROLE (1 << 1)
9490 #define PORT_CMT_PORT_INACTIVE (0 << 1)
9491 #define PORT_CMT_PORT_ACTIVE (1 << 1)
9493 #define PORT_CMT_TEAM_MASK (1 << 2)
9494 #define PORT_CMT_TEAM0 (0 << 2)
9495 #define PORT_CMT_TEAM1 (1 << 2)
9498 #define LLDP_CHASSIS_ID_STAT_LEN 4
9499 #define LLDP_PORT_ID_STAT_LEN 4
9500 #define DCBX_MAX_APP_PROTOCOL 32
9501 #define MAX_SYSTEM_LLDP_TLV_DATA 32
9504 LLDP_NEAREST_BRIDGE = 0,
9505 LLDP_NEAREST_NON_TPMR_BRIDGE,
9506 LLDP_NEAREST_CUSTOMER_BRIDGE,
9507 LLDP_MAX_LLDP_AGENTS
9510 struct lldp_config_params_s {
9512 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
9513 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
9514 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
9515 #define LLDP_CONFIG_HOLD_SHIFT 8
9516 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
9517 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
9518 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
9519 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
9520 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
9521 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
9522 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
9523 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
9526 struct lldp_status_params_s {
9529 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
9530 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
9534 struct dcbx_ets_feature {
9536 #define DCBX_ETS_ENABLED_MASK 0x00000001
9537 #define DCBX_ETS_ENABLED_SHIFT 0
9538 #define DCBX_ETS_WILLING_MASK 0x00000002
9539 #define DCBX_ETS_WILLING_SHIFT 1
9540 #define DCBX_ETS_ERROR_MASK 0x00000004
9541 #define DCBX_ETS_ERROR_SHIFT 2
9542 #define DCBX_ETS_CBS_MASK 0x00000008
9543 #define DCBX_ETS_CBS_SHIFT 3
9544 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
9545 #define DCBX_ETS_MAX_TCS_SHIFT 4
9546 #define DCBX_ISCSI_OOO_TC_MASK 0x00000f00
9547 #define DCBX_ISCSI_OOO_TC_SHIFT 8
9549 #define DCBX_ISCSI_OOO_TC (4)
9551 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
9552 #define DCBX_CEE_STRICT_PRIORITY 0xf
9555 #define DCBX_ETS_TSA_STRICT 0
9556 #define DCBX_ETS_TSA_CBS 1
9557 #define DCBX_ETS_TSA_ETS 2
9560 struct dcbx_app_priority_entry {
9562 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
9563 #define DCBX_APP_PRI_MAP_SHIFT 0
9564 #define DCBX_APP_PRI_0 0x01
9565 #define DCBX_APP_PRI_1 0x02
9566 #define DCBX_APP_PRI_2 0x04
9567 #define DCBX_APP_PRI_3 0x08
9568 #define DCBX_APP_PRI_4 0x10
9569 #define DCBX_APP_PRI_5 0x20
9570 #define DCBX_APP_PRI_6 0x40
9571 #define DCBX_APP_PRI_7 0x80
9572 #define DCBX_APP_SF_MASK 0x00000300
9573 #define DCBX_APP_SF_SHIFT 8
9574 #define DCBX_APP_SF_ETHTYPE 0
9575 #define DCBX_APP_SF_PORT 1
9576 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
9577 #define DCBX_APP_SF_IEEE_SHIFT 12
9578 #define DCBX_APP_SF_IEEE_RESERVED 0
9579 #define DCBX_APP_SF_IEEE_ETHTYPE 1
9580 #define DCBX_APP_SF_IEEE_TCP_PORT 2
9581 #define DCBX_APP_SF_IEEE_UDP_PORT 3
9582 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
9584 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
9585 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
9588 struct dcbx_app_priority_feature {
9590 #define DCBX_APP_ENABLED_MASK 0x00000001
9591 #define DCBX_APP_ENABLED_SHIFT 0
9592 #define DCBX_APP_WILLING_MASK 0x00000002
9593 #define DCBX_APP_WILLING_SHIFT 1
9594 #define DCBX_APP_ERROR_MASK 0x00000004
9595 #define DCBX_APP_ERROR_SHIFT 2
9596 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
9597 #define DCBX_APP_MAX_TCS_SHIFT 12
9598 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
9599 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
9600 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
9603 struct dcbx_features {
9604 struct dcbx_ets_feature ets;
9606 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
9607 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
9608 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
9609 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
9610 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
9611 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
9612 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
9613 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
9614 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
9615 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
9617 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
9618 #define DCBX_PFC_FLAGS_SHIFT 8
9619 #define DCBX_PFC_CAPS_MASK 0x00000f00
9620 #define DCBX_PFC_CAPS_SHIFT 8
9621 #define DCBX_PFC_MBC_MASK 0x00004000
9622 #define DCBX_PFC_MBC_SHIFT 14
9623 #define DCBX_PFC_WILLING_MASK 0x00008000
9624 #define DCBX_PFC_WILLING_SHIFT 15
9625 #define DCBX_PFC_ENABLED_MASK 0x00010000
9626 #define DCBX_PFC_ENABLED_SHIFT 16
9627 #define DCBX_PFC_ERROR_MASK 0x00020000
9628 #define DCBX_PFC_ERROR_SHIFT 17
9630 struct dcbx_app_priority_feature app;
9633 struct dcbx_local_params {
9635 #define DCBX_CONFIG_VERSION_MASK 0x00000007
9636 #define DCBX_CONFIG_VERSION_SHIFT 0
9637 #define DCBX_CONFIG_VERSION_DISABLED 0
9638 #define DCBX_CONFIG_VERSION_IEEE 1
9639 #define DCBX_CONFIG_VERSION_CEE 2
9640 #define DCBX_CONFIG_VERSION_STATIC 4
9643 struct dcbx_features features;
9649 struct dcbx_features features;
9653 struct lldp_system_tlvs_buffer_s {
9656 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
9659 struct dcb_dscp_map {
9661 #define DCB_DSCP_ENABLE_MASK 0x1
9662 #define DCB_DSCP_ENABLE_SHIFT 0
9663 #define DCB_DSCP_ENABLE 1
9664 u32 dscp_pri_map[8];
9667 struct public_global {
9674 u32 debug_mb_offset;
9675 u32 phymod_dbg_mb_offset;
9676 struct couple_mode_teaming cmt;
9677 s32 internal_temperature;
9679 u32 running_bundle_id;
9680 s32 external_temperature;
9690 struct public_path {
9691 struct fw_flr_mb flr_mb;
9692 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
9695 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
9696 #define PROCESS_KILL_COUNTER_SHIFT 0
9697 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
9698 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
9699 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
9702 struct public_port {
9706 #define LINK_STATUS_LINK_UP 0x00000001
9707 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
9708 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
9709 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
9710 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
9711 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
9712 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
9713 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
9714 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
9715 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
9717 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
9719 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
9720 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
9722 #define LINK_STATUS_PFC_ENABLED 0x00000100
9723 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
9724 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
9725 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
9726 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
9727 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
9728 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
9729 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
9730 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
9732 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
9733 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
9734 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
9735 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
9736 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
9738 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
9739 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
9740 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
9741 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
9742 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
9743 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
9744 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
9747 u32 ext_phy_fw_version;
9748 u32 drv_phy_cfg_addr;
9754 struct port_mf_cfg port_mf_config;
9755 struct port_stats stats;
9758 #define MEDIA_UNSPECIFIED 0x0
9759 #define MEDIA_SFPP_10G_FIBER 0x1
9760 #define MEDIA_XFP_FIBER 0x2
9761 #define MEDIA_DA_TWINAX 0x3
9762 #define MEDIA_BASE_T 0x4
9763 #define MEDIA_SFP_1G_FIBER 0x5
9764 #define MEDIA_MODULE_FIBER 0x6
9765 #define MEDIA_KR 0xf0
9766 #define MEDIA_NOT_PRESENT 0xff
9769 u32 link_change_count;
9771 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
9772 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
9773 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
9775 /* DCBX related MIB */
9776 struct dcbx_local_params local_admin_dcbx_mib;
9777 struct dcbx_mib remote_dcbx_mib;
9778 struct dcbx_mib operational_dcbx_mib;
9781 u32 transceiver_data;
9782 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
9783 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
9784 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
9785 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
9786 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
9787 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
9791 u32 wol_pkt_details;
9792 struct dcb_dscp_map dcb_dscp_map;
9795 struct public_func {
9803 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
9804 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
9805 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
9807 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
9808 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
9809 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
9810 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
9811 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
9812 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
9813 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
9815 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
9816 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
9817 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
9818 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
9819 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
9820 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
9823 #define FUNC_STATUS_VLINK_DOWN 0x00000001
9826 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
9827 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
9828 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
9830 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
9832 u32 fcoe_wwn_port_name_upper;
9833 u32 fcoe_wwn_port_name_lower;
9835 u32 fcoe_wwn_node_name_upper;
9836 u32 fcoe_wwn_node_name_lower;
9839 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
9840 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
9841 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
9847 u32 driver_last_activity_ts;
9849 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
9852 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
9853 #define DRV_ID_PDA_COMP_VER_SHIFT 0
9855 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
9856 #define DRV_ID_MCP_HSI_VER_SHIFT 16
9857 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT)
9859 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
9860 #define DRV_ID_DRV_TYPE_SHIFT 24
9861 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
9862 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
9864 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
9865 #define DRV_ID_DRV_INIT_HW_SHIFT 31
9866 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
9879 struct mcp_file_att {
9884 struct bist_nvm_image_att {
9891 #define MCP_DRV_VER_STR_SIZE 16
9892 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
9893 #define MCP_DRV_NVM_BUF_LEN 32
9894 struct drv_version_stc {
9896 u8 name[MCP_DRV_VER_STR_SIZE - 4];
9899 struct lan_stats_stc {
9906 struct fcoe_stats_stc {
9913 struct ocbb_data_stc {
9916 u32 ocsd_req_update_interval;
9919 #define MAX_NUM_OF_SENSORS 7
9920 struct temperature_status_stc {
9922 u32 sensor[MAX_NUM_OF_SENSORS];
9925 /* crash dump configuration header */
9926 struct mdump_config_stc {
9934 enum resource_id_enum {
9935 RESOURCE_NUM_SB_E = 0,
9936 RESOURCE_NUM_L2_QUEUE_E = 1,
9937 RESOURCE_NUM_VPORT_E = 2,
9938 RESOURCE_NUM_VMQ_E = 3,
9939 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
9940 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
9941 RESOURCE_NUM_RL_E = 6,
9942 RESOURCE_NUM_PQ_E = 7,
9943 RESOURCE_NUM_VF_E = 8,
9944 RESOURCE_VFC_FILTER_E = 9,
9945 RESOURCE_ILT_E = 10,
9946 RESOURCE_CQS_E = 11,
9947 RESOURCE_GFT_PROFILES_E = 12,
9948 RESOURCE_NUM_TC_E = 13,
9949 RESOURCE_NUM_RSS_ENGINES_E = 14,
9950 RESOURCE_LL2_QUEUE_E = 15,
9951 RESOURCE_RDMA_STATS_QUEUE_E = 16,
9953 RESOURCE_NUM_INVALID = 0xFFFFFFFF
9956 /* Resource ID is to be filled by the driver in the MB request
9957 * Size, offset & flags to be filled by the MFW in the MB response
9959 struct resource_info {
9960 enum resource_id_enum res_id;
9961 u32 size; /* number of allocated resources */
9962 u32 offset; /* Offset of the 1st resource */
9966 #define RESOURCE_ELEMENT_STRICT (1 << 0)
9969 union drv_union_data {
9970 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
9971 struct mcp_mac wol_mac;
9973 struct eth_phy_cfg drv_phy_cfg;
9975 struct mcp_val64 val64;
9977 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
9979 struct mcp_file_att file_att;
9981 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
9983 struct drv_version_stc drv_version;
9985 struct lan_stats_stc lan_stats;
9986 struct fcoe_stats_stc fcoe_stats;
9987 struct ocbb_data_stc ocbb_info;
9988 struct temperature_status_stc temp_info;
9989 struct resource_info resource;
9990 struct bist_nvm_image_att nvm_image_att;
9991 struct mdump_config_stc mdump_config;
9994 struct public_drv_mb {
9996 #define DRV_MSG_CODE_MASK 0xffff0000
9997 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
9998 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
9999 #define DRV_MSG_CODE_INIT_HW 0x12000000
10000 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
10001 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
10002 #define DRV_MSG_CODE_INIT_PHY 0x22000000
10003 #define DRV_MSG_CODE_LINK_RESET 0x23000000
10004 #define DRV_MSG_CODE_SET_DCBX 0x25000000
10005 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
10006 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
10007 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
10008 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
10009 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
10010 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
10011 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
10012 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
10013 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
10015 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
10016 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
10017 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
10018 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
10019 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
10020 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
10021 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
10022 #define DRV_MSG_CODE_MCP_RESET 0x00090000
10023 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
10024 #define DRV_MSG_CODE_MCP_HALT 0x00100000
10025 #define DRV_MSG_CODE_SET_VMAC 0x00110000
10026 #define DRV_MSG_CODE_GET_VMAC 0x00120000
10027 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
10028 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
10029 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
10030 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
10031 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
10033 #define DRV_MSG_CODE_GET_STATS 0x00130000
10034 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
10035 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
10036 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
10037 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
10039 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
10041 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
10042 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
10043 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
10044 #define DRV_MSG_CODE_OS_WOL 0x002e0000
10046 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
10049 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
10050 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
10051 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
10052 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
10053 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
10054 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
10056 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
10058 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
10059 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
10060 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
10061 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
10062 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
10063 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
10065 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
10066 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
10067 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
10068 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
10069 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
10070 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
10072 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
10073 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
10074 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
10075 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
10076 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
10077 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
10079 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
10080 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
10081 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
10082 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
10083 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
10084 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
10085 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
10087 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
10088 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
10090 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
10091 DRV_MB_PARAM_WOL_DISABLED | \
10092 DRV_MB_PARAM_WOL_ENABLED)
10093 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
10094 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
10095 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
10097 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
10098 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
10099 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
10100 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
10101 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
10102 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
10104 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
10105 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
10106 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
10108 /* Resource Allocation params - Driver version support */
10109 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
10110 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
10111 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
10112 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
10114 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
10115 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
10116 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
10117 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
10119 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
10120 #define DRV_MB_PARAM_BIST_RC_PASSED 1
10121 #define DRV_MB_PARAM_BIST_RC_FAILED 2
10122 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
10124 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
10125 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
10126 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
10127 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
10130 #define FW_MSG_CODE_MASK 0xffff0000
10131 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
10132 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
10133 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
10134 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
10135 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
10136 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
10137 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
10138 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
10139 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
10140 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
10141 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
10142 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
10143 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
10144 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
10145 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
10147 #define FW_MSG_CODE_NVM_OK 0x00010000
10148 #define FW_MSG_CODE_OK 0x00160000
10150 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
10151 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
10153 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
10157 /* get pf rdma protocol command responce */
10158 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
10159 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
10160 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
10161 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
10164 #define DRV_PULSE_SEQ_MASK 0x00007fff
10165 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
10166 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
10169 #define MCP_PULSE_SEQ_MASK 0x00007fff
10170 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
10171 #define MCP_EVENT_MASK 0xffff0000
10172 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
10174 union drv_union_data union_data;
10177 enum MFW_DRV_MSG_TYPE {
10178 MFW_DRV_MSG_LINK_CHANGE,
10179 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
10180 MFW_DRV_MSG_VF_DISABLED,
10181 MFW_DRV_MSG_LLDP_DATA_UPDATED,
10182 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
10183 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
10184 MFW_DRV_MSG_RESERVED4,
10185 MFW_DRV_MSG_BW_UPDATE,
10186 MFW_DRV_MSG_BW_UPDATE5,
10187 MFW_DRV_MSG_GET_LAN_STATS,
10188 MFW_DRV_MSG_GET_FCOE_STATS,
10189 MFW_DRV_MSG_GET_ISCSI_STATS,
10190 MFW_DRV_MSG_GET_RDMA_STATS,
10191 MFW_DRV_MSG_BW_UPDATE10,
10192 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
10193 MFW_DRV_MSG_BW_UPDATE11,
10197 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
10198 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
10199 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
10200 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
10202 struct public_mfw_mb {
10204 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
10205 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
10208 enum public_sections {
10215 PUBLIC_MAX_SECTIONS
10218 struct mcp_public_data {
10220 u32 sections[PUBLIC_MAX_SECTIONS];
10221 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
10222 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
10223 struct public_global global;
10224 struct public_path path[MCP_GLOB_PATH_MAX];
10225 struct public_port port[MCP_GLOB_PORT_MAX];
10226 struct public_func func[MCP_GLOB_FUNC_MAX];
10229 struct nvm_cfg_mac_address {
10231 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
10232 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
10236 struct nvm_cfg1_glob {
10238 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
10239 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
10240 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
10241 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
10242 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
10243 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
10244 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
10245 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
10246 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
10247 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
10248 u32 engineering_change[3];
10249 u32 manufacturing_id;
10250 u32 serial_number[4];
10254 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
10255 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
10256 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
10257 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
10258 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
10259 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
10260 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
10261 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
10262 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
10263 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
10264 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
10265 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
10270 u32 mps10_preemphasis;
10271 u32 mps10_driver_current;
10272 u32 mps25_preemphasis;
10273 u32 mps25_driver_current;
10277 u32 mps10_txfir_main;
10278 u32 mps10_txfir_post;
10279 u32 mps25_txfir_main;
10280 u32 mps25_txfir_post;
10281 u32 manufacture_ver;
10282 u32 manufacture_time;
10283 u32 led_global_settings;
10288 u32 device_capabilities;
10289 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
10290 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
10291 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
10292 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
10293 u32 power_dissipated;
10294 u32 power_consumed;
10296 u32 multi_network_modes_capability;
10300 struct nvm_cfg1_path {
10304 struct nvm_cfg1_port {
10305 u32 reserved__m_relocated_to_option_123;
10306 u32 reserved__m_relocated_to_option_124;
10308 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
10309 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
10310 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
10311 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
10312 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
10313 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
10314 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
10315 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
10316 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
10317 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
10318 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
10321 u32 speed_cap_mask;
10322 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
10323 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
10324 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
10325 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
10326 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
10327 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
10328 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
10329 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
10331 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
10332 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
10333 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
10334 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
10335 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
10336 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
10337 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
10338 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
10339 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
10340 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
10341 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
10342 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
10343 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
10344 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
10345 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
10352 struct nvm_cfg_mac_address lldp_mac_address;
10353 u32 led_port_settings;
10354 u32 transceiver_00;
10375 struct nvm_cfg1_func {
10376 struct nvm_cfg_mac_address mac_address;
10382 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
10383 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
10384 u32 preboot_generic_cfg;
10389 struct nvm_cfg1_glob glob;
10390 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
10391 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
10392 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
10395 enum spad_sections {
10396 SPAD_SECTION_TRACE,
10397 SPAD_SECTION_NVM_CFG,
10398 SPAD_SECTION_PUBLIC,
10399 SPAD_SECTION_PRIVATE,
10403 #define MCP_TRACE_SIZE 2048 /* 2kb */
10405 /* This section is located at a fixed location in the beginning of the
10406 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
10407 * All the rest of data has a floating location which differs from version to
10408 * version, and is pointed by the mcp_meta_data below.
10409 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
10410 * with it from nvram in order to clear this portion.
10412 struct static_init {
10414 offsize_t sections[SPAD_SECTION_MAX];
10415 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
10417 struct mcp_trace trace;
10418 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
10419 u8 trace_buffer[MCP_TRACE_SIZE];
10420 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
10421 /* running_mfw has the same definition as in nvm_map.h.
10422 * This bit indicate both the running dir, and the running bundle.
10423 * It is set once when the LIM is loaded.
10426 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
10428 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
10430 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
10431 u32 mfw_secure_mode;
10432 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
10433 u16 pme_status_pf_bitmap;
10434 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
10435 u16 pme_enable_pf_bitmap;
10436 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
10438 u32 mim_start_addr;
10439 u32 ah_pcie_link_params;
10440 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
10441 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
10442 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
10443 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
10444 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
10445 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
10446 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
10447 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
10448 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
10450 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
10453 enum nvm_image_type {
10454 NVM_TYPE_TIM1 = 0x01,
10455 NVM_TYPE_TIM2 = 0x02,
10456 NVM_TYPE_MIM1 = 0x03,
10457 NVM_TYPE_MIM2 = 0x04,
10458 NVM_TYPE_MBA = 0x05,
10459 NVM_TYPE_MODULES_PN = 0x06,
10460 NVM_TYPE_VPD = 0x07,
10461 NVM_TYPE_MFW_TRACE1 = 0x08,
10462 NVM_TYPE_MFW_TRACE2 = 0x09,
10463 NVM_TYPE_NVM_CFG1 = 0x0a,
10464 NVM_TYPE_L2B = 0x0b,
10465 NVM_TYPE_DIR1 = 0x0c,
10466 NVM_TYPE_EAGLE_FW1 = 0x0d,
10467 NVM_TYPE_FALCON_FW1 = 0x0e,
10468 NVM_TYPE_PCIE_FW1 = 0x0f,
10469 NVM_TYPE_HW_SET = 0x10,
10470 NVM_TYPE_LIM = 0x11,
10471 NVM_TYPE_AVS_FW1 = 0x12,
10472 NVM_TYPE_DIR2 = 0x13,
10473 NVM_TYPE_CCM = 0x14,
10474 NVM_TYPE_EAGLE_FW2 = 0x15,
10475 NVM_TYPE_FALCON_FW2 = 0x16,
10476 NVM_TYPE_PCIE_FW2 = 0x17,
10477 NVM_TYPE_AVS_FW2 = 0x18,
10478 NVM_TYPE_INIT_HW = 0x19,
10479 NVM_TYPE_DEFAULT_CFG = 0x1a,
10480 NVM_TYPE_MDUMP = 0x1b,
10481 NVM_TYPE_META = 0x1c,
10482 NVM_TYPE_ISCSI_CFG = 0x1d,
10483 NVM_TYPE_FCOE_CFG = 0x1f,
10484 NVM_TYPE_ETH_PHY_FW1 = 0x20,
10485 NVM_TYPE_ETH_PHY_FW2 = 0x21,
10489 #define DIR_ID_1 (0)