drivers/net/ethernet/qlogic/qed/qed_init_ops.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/io.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/string.h>
  40 #include "qed.h"
  41 #include "qed_hsi.h"
  42 #include "qed_hw.h"
  43 #include "qed_init_ops.h"
  44 #include "qed_reg_addr.h"
  45 #include "qed_sriov.h"
  46
  47 #define QED_INIT_MAX_POLL_COUNT 100
  48 #define QED_INIT_POLL_PERIOD_US 500
  49
  50 static u32 pxp_global_win[] = {
  51         0,
  52         0,
  53         0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
  54         0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
  55         0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
  56         0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
  57         0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */
  58         0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */
  59         0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */
  60         0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */
  61         0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */
  62         0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */
  63         0,
  64         0,
  65         0,
  66         0,
  67         0,
  68         0,
  69         0,
  70 };
  71
  72 void qed_init_iro_array(struct qed_dev *cdev)
  73 {
  74         cdev->iro_arr = iro_arr;
  75 }
  76
  77 /* Runtime configuration helpers */
  78 void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn)
  79 {
  80         int i;
  81
  82         for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
  83                 p_hwfn->rt_data.b_valid[i] = false;
  84 }
  85
  86 void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val)
  87 {
  88         p_hwfn->rt_data.init_val[rt_offset] = val;
  89         p_hwfn->rt_data.b_valid[rt_offset] = true;
  90 }
  91
  92 void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
  93                            u32 rt_offset, u32 *p_val, size_t size)
  94 {
  95         size_t i;
  96
  97         for (i = 0; i < size / sizeof(u32); i++) {
  98                 p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
  99                 p_hwfn->rt_data.b_valid[rt_offset + i]  = true;
 100         }
 101 }
 102
 103 static int qed_init_rt(struct qed_hwfn  *p_hwfn,
 104                        struct qed_ptt *p_ptt,
 105                        u32 addr, u16 rt_offset, u16 size, bool b_must_dmae)
 106 {
 107         u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
 108         bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
 109         u16 i, segment;
 110         int rc = 0;
 111
 112         /* Since not all RT entries are initialized, go over the RT and
 113          * for each segment of initialized values use DMA.
 114          */
 115         for (i = 0; i < size; i++) {
 116                 if (!p_valid[i])
 117                         continue;
 118
 119                 /* In case there isn't any wide-bus configuration here,
 120                  * simply write the data instead of using dmae.
 121                  */
 122                 if (!b_must_dmae) {
 123                         qed_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
 124                         continue;
 125                 }
 126
 127                 /* Start of a new segment */
 128                 for (segment = 1; i + segment < size; segment++)
 129                         if (!p_valid[i + segment])
 130                                 break;
 131
 132                 rc = qed_dmae_host2grc(p_hwfn, p_ptt,
 133                                        (uintptr_t)(p_init_val + i),
 134                                        addr + (i << 2), segment, 0);
 135                 if (rc)
 136                         return rc;
 137
 138                 /* Jump over the entire segment, including invalid entry */
 139                 i += segment;
 140         }
 141
 142         return rc;
 143 }
 144
 145 int qed_init_alloc(struct qed_hwfn *p_hwfn)
 146 {
 147         struct qed_rt_data *rt_data = &p_hwfn->rt_data;
 148
 149         if (IS_VF(p_hwfn->cdev))
 150                 return 0;
 151
 152         rt_data->b_valid = kzalloc(sizeof(bool) * RUNTIME_ARRAY_SIZE,
 153                                    GFP_KERNEL);
 154         if (!rt_data->b_valid)
 155                 return -ENOMEM;
 156
 157         rt_data->init_val = kzalloc(sizeof(u32) * RUNTIME_ARRAY_SIZE,
 158                                     GFP_KERNEL);
 159         if (!rt_data->init_val) {
 160                 kfree(rt_data->b_valid);
 161                 return -ENOMEM;
 162         }
 163
 164         return 0;
 165 }
 166
 167 void qed_init_free(struct qed_hwfn *p_hwfn)
 168 {
 169         kfree(p_hwfn->rt_data.init_val);
 170         kfree(p_hwfn->rt_data.b_valid);
 171 }
 172
 173 static int qed_init_array_dmae(struct qed_hwfn *p_hwfn,
 174                                struct qed_ptt *p_ptt,
 175                                u32 addr,
 176                                u32 dmae_data_offset,
 177                                u32 size,
 178                                const u32 *buf,
 179                                bool b_must_dmae,
 180                                bool b_can_dmae)
 181 {
 182         int rc = 0;
 183
 184         /* Perform DMAE only for lengthy enough sections or for wide-bus */
 185         if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
 186                 const u32 *data = buf + dmae_data_offset;
 187                 u32 i;
 188
 189                 for (i = 0; i < size; i++)
 190                         qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
 191         } else {
 192                 rc = qed_dmae_host2grc(p_hwfn, p_ptt,
 193                                        (uintptr_t)(buf + dmae_data_offset),
 194                                        addr, size, 0);
 195         }
 196
 197         return rc;
 198 }
 199
 200 static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn,
 201                               struct qed_ptt *p_ptt,
 202                               u32 addr, u32 fill, u32 fill_count)
 203 {
 204         static u32 zero_buffer[DMAE_MAX_RW_SIZE];
 205
 206         memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
 207
 208         /* invoke the DMAE virtual/physical buffer API with
 209          * 1. DMAE init channel
 210          * 2. addr,
 211          * 3. p_hwfb->temp_data,
 212          * 4. fill_count
 213          */
 214
 215         return qed_dmae_host2grc(p_hwfn, p_ptt,
 216                                  (uintptr_t)(&zero_buffer[0]),
 217                                  addr, fill_count, QED_DMAE_FLAG_RW_REPL_SRC);
 218 }
 219
 220 static void qed_init_fill(struct qed_hwfn *p_hwfn,
 221                           struct qed_ptt *p_ptt,
 222                           u32 addr, u32 fill, u32 fill_count)
 223 {
 224         u32 i;
 225
 226         for (i = 0; i < fill_count; i++, addr += sizeof(u32))
 227                 qed_wr(p_hwfn, p_ptt, addr, fill);
 228 }
 229
 230 static int qed_init_cmd_array(struct qed_hwfn *p_hwfn,
 231                               struct qed_ptt *p_ptt,
 232                               struct init_write_op *cmd,
 233                               bool b_must_dmae, bool b_can_dmae)
 234 {
 235         u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset);
 236         u32 data = le32_to_cpu(cmd->data);
 237         u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 238
 239         u32 offset, output_len, input_len, max_size;
 240         struct qed_dev *cdev = p_hwfn->cdev;
 241         union init_array_hdr *hdr;
 242         const u32 *array_data;
 243         int rc = 0;
 244         u32 size;
 245
 246         array_data = cdev->fw_data->arr_data;
 247
 248         hdr = (union init_array_hdr *)(array_data + dmae_array_offset);
 249         data = le32_to_cpu(hdr->raw.data);
 250         switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
 251         case INIT_ARR_ZIPPED:
 252                 offset = dmae_array_offset + 1;
 253                 input_len = GET_FIELD(data,
 254                                       INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
 255                 max_size = MAX_ZIPPED_SIZE * 4;
 256                 memset(p_hwfn->unzip_buf, 0, max_size);
 257
 258                 output_len = qed_unzip_data(p_hwfn, input_len,
 259                                             (u8 *)&array_data[offset],
 260                                             max_size, (u8 *)p_hwfn->unzip_buf);
 261                 if (output_len) {
 262                         rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0,
 263                                                  output_len,
 264                                                  p_hwfn->unzip_buf,
 265                                                  b_must_dmae, b_can_dmae);
 266                 } else {
 267                         DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n");
 268                         rc = -EINVAL;
 269                 }
 270                 break;
 271         case INIT_ARR_PATTERN:
 272         {
 273                 u32 repeats = GET_FIELD(data,
 274                                         INIT_ARRAY_PATTERN_HDR_REPETITIONS);
 275                 u32 i;
 276
 277                 size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
 278
 279                 for (i = 0; i < repeats; i++, addr += size << 2) {
 280                         rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
 281                                                  dmae_array_offset + 1,
 282                                                  size, array_data,
 283                                                  b_must_dmae, b_can_dmae);
 284                         if (rc)
 285                                 break;
 286                 }
 287                 break;
 288         }
 289         case INIT_ARR_STANDARD:
 290                 size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
 291                 rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
 292                                          dmae_array_offset + 1,
 293                                          size, array_data,
 294                                          b_must_dmae, b_can_dmae);
 295                 break;
 296         }
 297
 298         return rc;
 299 }
 300
 301 /* init_ops write command */
 302 static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn,
 303                            struct qed_ptt *p_ptt,
 304                            struct init_write_op *p_cmd, bool b_can_dmae)
 305 {
 306         u32 data = le32_to_cpu(p_cmd->data);
 307         bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
 308         u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 309         union init_write_args *arg = &p_cmd->args;
 310         int rc = 0;
 311
 312         /* Sanitize */
 313         if (b_must_dmae && !b_can_dmae) {
 314                 DP_NOTICE(p_hwfn,
 315                           "Need to write to %08x for Wide-bus but DMAE isn't allowed\n",
 316                           addr);
 317                 return -EINVAL;
 318         }
 319
 320         switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
 321         case INIT_SRC_INLINE:
 322                 data = le32_to_cpu(p_cmd->args.inline_val);
 323                 qed_wr(p_hwfn, p_ptt, addr, data);
 324                 break;
 325         case INIT_SRC_ZEROS:
 326                 data = le32_to_cpu(p_cmd->args.zeros_count);
 327                 if (b_must_dmae || (b_can_dmae && (data >= 64)))
 328                         rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
 329                 else
 330                         qed_init_fill(p_hwfn, p_ptt, addr, 0, data);
 331                 break;
 332         case INIT_SRC_ARRAY:
 333                 rc = qed_init_cmd_array(p_hwfn, p_ptt, p_cmd,
 334                                         b_must_dmae, b_can_dmae);
 335                 break;
 336         case INIT_SRC_RUNTIME:
 337                 qed_init_rt(p_hwfn, p_ptt, addr,
 338                             le16_to_cpu(arg->runtime.offset),
 339                             le16_to_cpu(arg->runtime.size),
 340                             b_must_dmae);
 341                 break;
 342         }
 343
 344         return rc;
 345 }
 346
 347 static inline bool comp_eq(u32 val, u32 expected_val)
 348 {
 349         return val == expected_val;
 350 }
 351
 352 static inline bool comp_and(u32 val, u32 expected_val)
 353 {
 354         return (val & expected_val) == expected_val;
 355 }
 356
 357 static inline bool comp_or(u32 val, u32 expected_val)
 358 {
 359         return (val | expected_val) > 0;
 360 }
 361
 362 /* init_ops read/poll commands */
 363 static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
 364                             struct qed_ptt *p_ptt, struct init_read_op *cmd)
 365 {
 366         bool (*comp_check)(u32 val, u32 expected_val);
 367         u32 delay = QED_INIT_POLL_PERIOD_US, val;
 368         u32 data, addr, poll;
 369         int i;
 370
 371         data = le32_to_cpu(cmd->op_data);
 372         addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
 373         poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
 374
 375
 376         val = qed_rd(p_hwfn, p_ptt, addr);
 377
 378         if (poll == INIT_POLL_NONE)
 379                 return;
 380
 381         switch (poll) {
 382         case INIT_POLL_EQ:
 383                 comp_check = comp_eq;
 384                 break;
 385         case INIT_POLL_OR:
 386                 comp_check = comp_or;
 387                 break;
 388         case INIT_POLL_AND:
 389                 comp_check = comp_and;
 390                 break;
 391         default:
 392                 DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
 393                        cmd->op_data);
 394                 return;
 395         }
 396
 397         data = le32_to_cpu(cmd->expected_val);
 398         for (i = 0;
 399              i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data);
 400              i++) {
 401                 udelay(delay);
 402                 val = qed_rd(p_hwfn, p_ptt, addr);
 403         }
 404
 405         if (i == QED_INIT_MAX_POLL_COUNT) {
 406                 DP_ERR(p_hwfn,
 407                        "Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparsion %08x)]\n",
 408                        addr, le32_to_cpu(cmd->expected_val),
 409                        val, le32_to_cpu(cmd->op_data));
 410         }
 411 }
 412
 413 /* init_ops callbacks entry point */
 414 static void qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
 415                             struct qed_ptt *p_ptt,
 416                             struct init_callback_op *p_cmd)
 417 {
 418         DP_NOTICE(p_hwfn, "Currently init values have no need of callbacks\n");
 419 }
 420
 421 static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn,
 422                                   u16 *p_offset, int modes)
 423 {
 424         struct qed_dev *cdev = p_hwfn->cdev;
 425         const u8 *modes_tree_buf;
 426         u8 arg1, arg2, tree_val;
 427
 428         modes_tree_buf = cdev->fw_data->modes_tree_buf;
 429         tree_val = modes_tree_buf[(*p_offset)++];
 430         switch (tree_val) {
 431         case INIT_MODE_OP_NOT:
 432                 return qed_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
 433         case INIT_MODE_OP_OR:
 434                 arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
 435                 arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
 436                 return arg1 | arg2;
 437         case INIT_MODE_OP_AND:
 438                 arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
 439                 arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
 440                 return arg1 & arg2;
 441         default:
 442                 tree_val -= MAX_INIT_MODE_OPS;
 443                 return (modes & BIT(tree_val)) ? 1 : 0;
 444         }
 445 }
 446
 447 static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn,
 448                              struct init_if_mode_op *p_cmd, int modes)
 449 {
 450         u16 offset = le16_to_cpu(p_cmd->modes_buf_offset);
 451
 452         if (qed_init_cmd_mode_match(p_hwfn, &offset, modes))
 453                 return 0;
 454         else
 455                 return GET_FIELD(le32_to_cpu(p_cmd->op_data),
 456                                  INIT_IF_MODE_OP_CMD_OFFSET);
 457 }
 458
 459 static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn,
 460                               struct init_if_phase_op *p_cmd,
 461                               u32 phase, u32 phase_id)
 462 {
 463         u32 data = le32_to_cpu(p_cmd->phase_data);
 464         u32 op_data = le32_to_cpu(p_cmd->op_data);
 465
 466         if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
 467               (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
 468                GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
 469                 return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET);
 470         else
 471                 return 0;
 472 }
 473
 474 int qed_init_run(struct qed_hwfn *p_hwfn,
 475                  struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
 476 {
 477         struct qed_dev *cdev = p_hwfn->cdev;
 478         u32 cmd_num, num_init_ops;
 479         union init_op *init_ops;
 480         bool b_dmae = false;
 481         int rc = 0;
 482
 483         num_init_ops = cdev->fw_data->init_ops_size;
 484         init_ops = cdev->fw_data->init_ops;
 485
 486         p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC);
 487         if (!p_hwfn->unzip_buf)
 488                 return -ENOMEM;
 489
 490         for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
 491                 union init_op *cmd = &init_ops[cmd_num];
 492                 u32 data = le32_to_cpu(cmd->raw.op_data);
 493
 494                 switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
 495                 case INIT_OP_WRITE:
 496                         rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
 497                                              b_dmae);
 498                         break;
 499                 case INIT_OP_READ:
 500                         qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
 501                         break;
 502                 case INIT_OP_IF_MODE:
 503                         cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode,
 504                                                      modes);
 505                         break;
 506                 case INIT_OP_IF_PHASE:
 507                         cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
 508                                                       phase, phase_id);
 509                         b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
 510                         break;
 511                 case INIT_OP_DELAY:
 512                         /* qed_init_run is always invoked from
 513                          * sleep-able context
 514                          */
 515                         udelay(le32_to_cpu(cmd->delay.delay));
 516                         break;
 517
 518                 case INIT_OP_CALLBACK:
 519                         qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
 520                         break;
 521                 }
 522
 523                 if (rc)
 524                         break;
 525         }
 526
 527         kfree(p_hwfn->unzip_buf);
 528         return rc;
 529 }
 530
 531 void qed_gtt_init(struct qed_hwfn *p_hwfn)
 532 {
 533         u32 gtt_base;
 534         u32 i;
 535
 536         /* Set the global windows */
 537         gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
 538
 539         for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++)
 540                 if (pxp_global_win[i])
 541                         REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
 542                                pxp_global_win[i]);
 543 }
 544
 545 int qed_init_fw_data(struct qed_dev *cdev, const u8 *data)
 546 {
 547         struct qed_fw_data *fw = cdev->fw_data;
 548         struct bin_buffer_hdr *buf_hdr;
 549         u32 offset, len;
 550
 551         if (!data) {
 552                 DP_NOTICE(cdev, "Invalid fw data\n");
 553                 return -EINVAL;
 554         }
 555
 556         /* First Dword contains metadata and should be skipped */
 557         buf_hdr = (struct bin_buffer_hdr *)data;
 558
 559         offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
 560         fw->fw_ver_info = (struct fw_ver_info *)(data + offset);
 561
 562         offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
 563         fw->init_ops = (union init_op *)(data + offset);
 564
 565         offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
 566         fw->arr_data = (u32 *)(data + offset);
 567
 568         offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
 569         fw->modes_tree_buf = (u8 *)(data + offset);
 570         len = buf_hdr[BIN_BUF_INIT_CMD].length;
 571         fw->init_ops_size = len / sizeof(struct init_raw_op);
 572
 573         return 0;
 574 }