1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/stddef.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/slab.h>
37 #include <linux/version.h>
38 #include <linux/delay.h>
39 #include <asm/byteorder.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/string.h>
42 #include <linux/module.h>
43 #include <linux/interrupt.h>
44 #include <linux/workqueue.h>
45 #include <linux/ethtool.h>
46 #include <linux/etherdevice.h>
47 #include <linux/vmalloc.h>
48 #include <linux/crash_dump.h>
49 #include <linux/qed/qed_if.h>
50 #include <linux/qed/qed_ll2_if.h>
53 #include "qed_sriov.h"
55 #include "qed_dev_api.h"
58 #include "qed_iscsi.h"
62 #include "qed_selftest.h"
63 #include "qed_debug.h"
65 #define QED_ROCE_QPS (8192)
66 #define QED_ROCE_DPIS (8)
68 static char version[] =
69 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
71 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 #define FW_FILE_VERSION \
76 __stringify(FW_MAJOR_VERSION) "." \
77 __stringify(FW_MINOR_VERSION) "." \
78 __stringify(FW_REVISION_VERSION) "." \
79 __stringify(FW_ENGINEERING_VERSION)
81 #define QED_FW_FILE_NAME \
82 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
84 MODULE_FIRMWARE(QED_FW_FILE_NAME);
86 static int __init qed_init(void)
88 pr_info("%s", version);
93 static void __exit qed_cleanup(void)
95 pr_notice("qed_cleanup called\n");
98 module_init(qed_init);
99 module_exit(qed_cleanup);
101 /* Check if the DMA controller on the machine can properly handle the DMA
102 * addressing required by the device.
104 static int qed_set_coherency_mask(struct qed_dev *cdev)
106 struct device *dev = &cdev->pdev->dev;
108 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
109 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
111 "Can't request 64-bit consistent allocations\n");
114 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
115 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
122 static void qed_free_pci(struct qed_dev *cdev)
124 struct pci_dev *pdev = cdev->pdev;
127 iounmap(cdev->doorbells);
129 iounmap(cdev->regview);
130 if (atomic_read(&pdev->enable_cnt) == 1)
131 pci_release_regions(pdev);
133 pci_disable_device(pdev);
136 #define PCI_REVISION_ID_ERROR_VAL 0xff
138 /* Performs PCI initializations as well as initializing PCI-related parameters
139 * in the device structrue. Returns 0 in case of success.
141 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
148 rc = pci_enable_device(pdev);
150 DP_NOTICE(cdev, "Cannot enable PCI device\n");
154 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
155 DP_NOTICE(cdev, "No memory region found in bar #0\n");
160 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
161 DP_NOTICE(cdev, "No memory region found in bar #2\n");
166 if (atomic_read(&pdev->enable_cnt) == 1) {
167 rc = pci_request_regions(pdev, "qed");
170 "Failed to request PCI memory resources\n");
173 pci_set_master(pdev);
174 pci_save_state(pdev);
177 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
178 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
180 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
185 if (!pci_is_pcie(pdev)) {
186 DP_NOTICE(cdev, "The bus is not PCI Express\n");
191 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
192 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
193 DP_NOTICE(cdev, "Cannot find power management capability\n");
195 rc = qed_set_coherency_mask(cdev);
199 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
200 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
201 cdev->pci_params.irq = pdev->irq;
203 cdev->regview = pci_ioremap_bar(pdev, 0);
204 if (!cdev->regview) {
205 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
211 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
212 cdev->db_size = pci_resource_len(cdev->pdev, 2);
213 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
214 if (!cdev->doorbells) {
215 DP_NOTICE(cdev, "Cannot map doorbell space\n");
223 pci_release_regions(pdev);
225 pci_disable_device(pdev);
230 int qed_fill_dev_info(struct qed_dev *cdev,
231 struct qed_dev_info *dev_info)
233 struct qed_tunnel_info *tun = &cdev->tunnel;
236 memset(dev_info, 0, sizeof(struct qed_dev_info));
238 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
239 tun->vxlan.b_mode_enabled)
240 dev_info->vxlan_enable = true;
242 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
243 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
244 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
245 dev_info->gre_enable = true;
247 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
248 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
249 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
250 dev_info->geneve_enable = true;
252 dev_info->num_hwfns = cdev->num_hwfns;
253 dev_info->pci_mem_start = cdev->pci_params.mem_start;
254 dev_info->pci_mem_end = cdev->pci_params.mem_end;
255 dev_info->pci_irq = cdev->pci_params.irq;
256 dev_info->rdma_supported = (cdev->hwfns[0].hw_info.personality ==
258 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
259 dev_info->dev_type = cdev->type;
260 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
263 dev_info->fw_major = FW_MAJOR_VERSION;
264 dev_info->fw_minor = FW_MINOR_VERSION;
265 dev_info->fw_rev = FW_REVISION_VERSION;
266 dev_info->fw_eng = FW_ENGINEERING_VERSION;
267 dev_info->mf_mode = cdev->mf_mode;
268 dev_info->tx_switching = true;
270 if (QED_LEADING_HWFN(cdev)->hw_info.b_wol_support ==
272 dev_info->wol_support = true;
274 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
275 &dev_info->fw_minor, &dev_info->fw_rev,
280 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
282 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
283 &dev_info->mfw_rev, NULL);
285 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
286 &dev_info->flash_size);
288 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
291 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
292 &dev_info->mfw_rev, NULL);
295 dev_info->mtu = QED_LEADING_HWFN(cdev)->hw_info.mtu;
300 static void qed_free_cdev(struct qed_dev *cdev)
305 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
307 struct qed_dev *cdev;
309 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
313 qed_init_struct(cdev);
318 /* Sets the requested power state */
319 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
324 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
329 static struct qed_dev *qed_probe(struct pci_dev *pdev,
330 struct qed_probe_params *params)
332 struct qed_dev *cdev;
335 cdev = qed_alloc_cdev(pdev);
339 cdev->protocol = params->protocol;
342 cdev->b_is_vf = true;
344 qed_init_dp(cdev, params->dp_module, params->dp_level);
346 rc = qed_init_pci(cdev, pdev);
348 DP_ERR(cdev, "init pci failed\n");
351 DP_INFO(cdev, "PCI init completed successfully\n");
353 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
355 DP_ERR(cdev, "hw prepare failed\n");
359 DP_INFO(cdev, "qed_probe completed successffuly\n");
371 static void qed_remove(struct qed_dev *cdev)
380 qed_set_power_state(cdev, PCI_D3hot);
385 static void qed_disable_msix(struct qed_dev *cdev)
387 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
388 pci_disable_msix(cdev->pdev);
389 kfree(cdev->int_params.msix_table);
390 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
391 pci_disable_msi(cdev->pdev);
394 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
397 static int qed_enable_msix(struct qed_dev *cdev,
398 struct qed_int_params *int_params)
402 cnt = int_params->in.num_vectors;
404 for (i = 0; i < cnt; i++)
405 int_params->msix_table[i].entry = i;
407 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
408 int_params->in.min_msix_cnt, cnt);
409 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
410 (rc % cdev->num_hwfns)) {
411 pci_disable_msix(cdev->pdev);
413 /* If fastpath is initialized, we need at least one interrupt
414 * per hwfn [and the slow path interrupts]. New requested number
415 * should be a multiple of the number of hwfns.
417 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
419 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
420 cnt, int_params->in.num_vectors);
421 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
428 /* MSI-x configuration was achieved */
429 int_params->out.int_mode = QED_INT_MODE_MSIX;
430 int_params->out.num_vectors = rc;
434 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
441 /* This function outputs the int mode and the number of enabled msix vector */
442 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
444 struct qed_int_params *int_params = &cdev->int_params;
445 struct msix_entry *tbl;
448 switch (int_params->in.int_mode) {
449 case QED_INT_MODE_MSIX:
450 /* Allocate MSIX table */
451 cnt = int_params->in.num_vectors;
452 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
453 if (!int_params->msix_table) {
459 rc = qed_enable_msix(cdev, int_params);
463 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
464 kfree(int_params->msix_table);
469 case QED_INT_MODE_MSI:
470 if (cdev->num_hwfns == 1) {
471 rc = pci_enable_msi(cdev->pdev);
473 int_params->out.int_mode = QED_INT_MODE_MSI;
477 DP_NOTICE(cdev, "Failed to enable MSI\n");
483 case QED_INT_MODE_INTA:
484 int_params->out.int_mode = QED_INT_MODE_INTA;
488 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
489 int_params->in.int_mode);
495 DP_INFO(cdev, "Using %s interrupts\n",
496 int_params->out.int_mode == QED_INT_MODE_INTA ?
497 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
499 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
504 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
505 int index, void(*handler)(void *))
507 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
508 int relative_idx = index / cdev->num_hwfns;
510 hwfn->simd_proto_handler[relative_idx].func = handler;
511 hwfn->simd_proto_handler[relative_idx].token = token;
514 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
516 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
517 int relative_idx = index / cdev->num_hwfns;
519 memset(&hwfn->simd_proto_handler[relative_idx], 0,
520 sizeof(struct qed_simd_fp_handler));
523 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
525 tasklet_schedule((struct tasklet_struct *)tasklet);
529 static irqreturn_t qed_single_int(int irq, void *dev_instance)
531 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
532 struct qed_hwfn *hwfn;
533 irqreturn_t rc = IRQ_NONE;
537 for (i = 0; i < cdev->num_hwfns; i++) {
538 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
543 hwfn = &cdev->hwfns[i];
545 /* Slowpath interrupt */
546 if (unlikely(status & 0x1)) {
547 tasklet_schedule(hwfn->sp_dpc);
552 /* Fastpath interrupts */
553 for (j = 0; j < 64; j++) {
554 if ((0x2ULL << j) & status) {
555 hwfn->simd_proto_handler[j].func(
556 hwfn->simd_proto_handler[j].token);
557 status &= ~(0x2ULL << j);
562 if (unlikely(status))
563 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
564 "got an unknown interrupt status 0x%llx\n",
571 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
573 struct qed_dev *cdev = hwfn->cdev;
578 int_mode = cdev->int_params.out.int_mode;
579 if (int_mode == QED_INT_MODE_MSIX) {
581 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
582 id, cdev->pdev->bus->number,
583 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
584 rc = request_irq(cdev->int_params.msix_table[id].vector,
585 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
587 unsigned long flags = 0;
589 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
590 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
591 PCI_FUNC(cdev->pdev->devfn));
593 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
594 flags |= IRQF_SHARED;
596 rc = request_irq(cdev->pdev->irq, qed_single_int,
597 flags, cdev->name, cdev);
601 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
603 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
604 "Requested slowpath %s\n",
605 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
610 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
612 struct qed_dev *cdev = p_hwfn->cdev;
613 u8 id = p_hwfn->my_id;
616 int_mode = cdev->int_params.out.int_mode;
617 if (int_mode == QED_INT_MODE_MSIX)
618 synchronize_irq(cdev->int_params.msix_table[id].vector);
620 synchronize_irq(cdev->pdev->irq);
623 static void qed_slowpath_irq_free(struct qed_dev *cdev)
627 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
628 for_each_hwfn(cdev, i) {
629 if (!cdev->hwfns[i].b_int_requested)
631 synchronize_irq(cdev->int_params.msix_table[i].vector);
632 free_irq(cdev->int_params.msix_table[i].vector,
633 cdev->hwfns[i].sp_dpc);
636 if (QED_LEADING_HWFN(cdev)->b_int_requested)
637 free_irq(cdev->pdev->irq, cdev);
639 qed_int_disable_post_isr_release(cdev);
642 static int qed_nic_stop(struct qed_dev *cdev)
646 rc = qed_hw_stop(cdev);
648 for (i = 0; i < cdev->num_hwfns; i++) {
649 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
651 if (p_hwfn->b_sp_dpc_enabled) {
652 tasklet_disable(p_hwfn->sp_dpc);
653 p_hwfn->b_sp_dpc_enabled = false;
654 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
655 "Disabled sp taskelt [hwfn %d] at %p\n",
660 qed_dbg_pf_exit(cdev);
665 static int qed_nic_setup(struct qed_dev *cdev)
669 /* Determine if interface is going to require LL2 */
670 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
671 for (i = 0; i < cdev->num_hwfns; i++) {
672 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
674 p_hwfn->using_ll2 = true;
678 rc = qed_resc_alloc(cdev);
682 DP_INFO(cdev, "Allocated qed resources\n");
684 qed_resc_setup(cdev);
689 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
693 /* Mark the fastpath as free/used */
694 cdev->int_params.fp_initialized = cnt ? true : false;
696 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
697 limit = cdev->num_hwfns * 63;
698 else if (cdev->int_params.fp_msix_cnt)
699 limit = cdev->int_params.fp_msix_cnt;
704 return min_t(int, cnt, limit);
707 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
709 memset(info, 0, sizeof(struct qed_int_info));
711 if (!cdev->int_params.fp_initialized) {
713 "Protocol driver requested interrupt information, but its support is not yet configured\n");
717 /* Need to expose only MSI-X information; Single IRQ is handled solely
720 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
721 int msix_base = cdev->int_params.fp_msix_base;
723 info->msix_cnt = cdev->int_params.fp_msix_cnt;
724 info->msix = &cdev->int_params.msix_table[msix_base];
730 static int qed_slowpath_setup_int(struct qed_dev *cdev,
731 enum qed_int_mode int_mode)
733 struct qed_sb_cnt_info sb_cnt_info;
734 int num_l2_queues = 0;
738 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
739 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
743 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
744 cdev->int_params.in.int_mode = int_mode;
745 for_each_hwfn(cdev, i) {
746 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
747 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
748 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;
749 cdev->int_params.in.num_vectors++; /* slowpath */
752 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
753 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
755 rc = qed_set_int_mode(cdev, false);
757 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
761 cdev->int_params.fp_msix_base = cdev->num_hwfns;
762 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
765 if (!IS_ENABLED(CONFIG_QED_RDMA) ||
766 QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH_ROCE)
769 for_each_hwfn(cdev, i)
770 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
772 DP_VERBOSE(cdev, QED_MSG_RDMA,
773 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
774 cdev->int_params.fp_msix_cnt, num_l2_queues);
776 if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
777 cdev->int_params.rdma_msix_cnt =
778 (cdev->int_params.fp_msix_cnt - num_l2_queues)
780 cdev->int_params.rdma_msix_base =
781 cdev->int_params.fp_msix_base + num_l2_queues;
782 cdev->int_params.fp_msix_cnt = num_l2_queues;
784 cdev->int_params.rdma_msix_cnt = 0;
787 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
788 cdev->int_params.rdma_msix_cnt,
789 cdev->int_params.rdma_msix_base);
794 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
798 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
799 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
801 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
802 &cdev->int_params.in.num_vectors);
803 if (cdev->num_hwfns > 1) {
806 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
807 cdev->int_params.in.num_vectors += vectors;
810 /* We want a minimum of one fastpath vector per vf hwfn */
811 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
813 rc = qed_set_int_mode(cdev, true);
817 cdev->int_params.fp_msix_base = 0;
818 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
823 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
824 u8 *input_buf, u32 max_size, u8 *unzip_buf)
828 p_hwfn->stream->next_in = input_buf;
829 p_hwfn->stream->avail_in = input_len;
830 p_hwfn->stream->next_out = unzip_buf;
831 p_hwfn->stream->avail_out = max_size;
833 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
836 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
841 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
842 zlib_inflateEnd(p_hwfn->stream);
844 if (rc != Z_OK && rc != Z_STREAM_END) {
845 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
846 p_hwfn->stream->msg, rc);
850 return p_hwfn->stream->total_out / 4;
853 static int qed_alloc_stream_mem(struct qed_dev *cdev)
858 for_each_hwfn(cdev, i) {
859 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
861 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
865 workspace = vzalloc(zlib_inflate_workspacesize());
868 p_hwfn->stream->workspace = workspace;
874 static void qed_free_stream_mem(struct qed_dev *cdev)
878 for_each_hwfn(cdev, i) {
879 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
884 vfree(p_hwfn->stream->workspace);
885 kfree(p_hwfn->stream);
889 static void qed_update_pf_params(struct qed_dev *cdev,
890 struct qed_pf_params *params)
894 if (IS_ENABLED(CONFIG_QED_RDMA)) {
895 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
896 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
897 /* divide by 3 the MRs to avoid MF ILT overflow */
898 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
901 if (cdev->num_hwfns > 1 || IS_VF(cdev))
902 params->eth_pf_params.num_arfs_filters = 0;
904 /* In case we might support RDMA, don't allow qede to be greedy
905 * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn.
907 if (QED_LEADING_HWFN(cdev)->hw_info.personality ==
911 num_cons = ¶ms->eth_pf_params.num_cons;
912 *num_cons = min_t(u16, *num_cons, 192);
915 for (i = 0; i < cdev->num_hwfns; i++) {
916 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
918 p_hwfn->pf_params = *params;
922 static int qed_slowpath_start(struct qed_dev *cdev,
923 struct qed_slowpath_params *params)
925 struct qed_drv_load_params drv_load_params;
926 struct qed_hw_init_params hw_init_params;
927 struct qed_mcp_drv_version drv_version;
928 struct qed_tunnel_info tunn_info;
929 const u8 *data = NULL;
930 struct qed_hwfn *hwfn;
931 #ifdef CONFIG_RFS_ACCEL
932 struct qed_ptt *p_ptt;
936 if (qed_iov_wq_start(cdev))
940 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
944 "Failed to find fw file - /lib/firmware/%s\n",
949 #ifdef CONFIG_RFS_ACCEL
950 if (cdev->num_hwfns == 1) {
951 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
953 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
956 "Failed to acquire PTT for aRFS\n");
963 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
964 rc = qed_nic_setup(cdev);
969 rc = qed_slowpath_setup_int(cdev, params->int_mode);
971 rc = qed_slowpath_vf_setup_int(cdev);
976 /* Allocate stream for unzipping */
977 rc = qed_alloc_stream_mem(cdev);
981 /* First Dword used to diffrentiate between various sources */
982 data = cdev->firmware->data + sizeof(u32);
984 qed_dbg_pf_init(cdev);
987 /* Start the slowpath */
988 memset(&hw_init_params, 0, sizeof(hw_init_params));
989 memset(&tunn_info, 0, sizeof(tunn_info));
990 tunn_info.vxlan.b_mode_enabled = true;
991 tunn_info.l2_gre.b_mode_enabled = true;
992 tunn_info.ip_gre.b_mode_enabled = true;
993 tunn_info.l2_geneve.b_mode_enabled = true;
994 tunn_info.ip_geneve.b_mode_enabled = true;
995 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
996 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
997 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
998 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
999 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1000 hw_init_params.p_tunn = &tunn_info;
1001 hw_init_params.b_hw_start = true;
1002 hw_init_params.int_mode = cdev->int_params.out.int_mode;
1003 hw_init_params.allow_npar_tx_switch = true;
1004 hw_init_params.bin_fw_data = data;
1006 memset(&drv_load_params, 0, sizeof(drv_load_params));
1007 drv_load_params.is_crash_kernel = is_kdump_kernel();
1008 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1009 drv_load_params.avoid_eng_reset = false;
1010 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1011 hw_init_params.p_drv_load_params = &drv_load_params;
1013 rc = qed_hw_init(cdev, &hw_init_params);
1018 "HW initialization and function start completed successfully\n");
1021 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1022 BIT(QED_MODE_L2GENEVE_TUNN) |
1023 BIT(QED_MODE_IPGENEVE_TUNN) |
1024 BIT(QED_MODE_L2GRE_TUNN) |
1025 BIT(QED_MODE_IPGRE_TUNN));
1028 /* Allocate LL2 interface if needed */
1029 if (QED_LEADING_HWFN(cdev)->using_ll2) {
1030 rc = qed_ll2_alloc_if(cdev);
1035 hwfn = QED_LEADING_HWFN(cdev);
1036 drv_version.version = (params->drv_major << 24) |
1037 (params->drv_minor << 16) |
1038 (params->drv_rev << 8) |
1040 strlcpy(drv_version.name, params->name,
1041 MCP_DRV_VER_STR_SIZE - 4);
1042 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1045 DP_NOTICE(cdev, "Failed sending drv version command\n");
1050 qed_reset_vport_stats(cdev);
1057 qed_hw_timers_stop_all(cdev);
1059 qed_slowpath_irq_free(cdev);
1060 qed_free_stream_mem(cdev);
1061 qed_disable_msix(cdev);
1063 qed_resc_free(cdev);
1066 release_firmware(cdev->firmware);
1068 #ifdef CONFIG_RFS_ACCEL
1069 if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1070 QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1071 qed_ptt_release(QED_LEADING_HWFN(cdev),
1072 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1075 qed_iov_wq_stop(cdev, false);
1080 static int qed_slowpath_stop(struct qed_dev *cdev)
1085 qed_ll2_dealloc_if(cdev);
1088 #ifdef CONFIG_RFS_ACCEL
1089 if (cdev->num_hwfns == 1)
1090 qed_ptt_release(QED_LEADING_HWFN(cdev),
1091 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1093 qed_free_stream_mem(cdev);
1094 if (IS_QED_ETH_IF(cdev))
1095 qed_sriov_disable(cdev, true);
1101 qed_slowpath_irq_free(cdev);
1103 qed_disable_msix(cdev);
1105 qed_resc_free(cdev);
1107 qed_iov_wq_stop(cdev, true);
1110 release_firmware(cdev->firmware);
1115 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
1116 char ver_str[VER_SIZE])
1120 memcpy(cdev->name, name, NAME_SIZE);
1121 for_each_hwfn(cdev, i)
1122 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1124 memcpy(cdev->ver_str, ver_str, VER_SIZE);
1125 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
1128 static u32 qed_sb_init(struct qed_dev *cdev,
1129 struct qed_sb_info *sb_info,
1131 dma_addr_t sb_phy_addr, u16 sb_id,
1132 enum qed_sb_type type)
1134 struct qed_hwfn *p_hwfn;
1135 struct qed_ptt *p_ptt;
1141 /* RoCE uses single engine and CMT uses two engines. When using both
1142 * we force only a single engine. Storage uses only engine 0 too.
1144 if (type == QED_SB_TYPE_L2_QUEUE)
1145 n_hwfns = cdev->num_hwfns;
1149 hwfn_index = sb_id % n_hwfns;
1150 p_hwfn = &cdev->hwfns[hwfn_index];
1151 rel_sb_id = sb_id / n_hwfns;
1153 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1154 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1155 hwfn_index, rel_sb_id, sb_id);
1157 if (IS_PF(p_hwfn->cdev)) {
1158 p_ptt = qed_ptt_acquire(p_hwfn);
1162 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1163 sb_phy_addr, rel_sb_id);
1164 qed_ptt_release(p_hwfn, p_ptt);
1166 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1167 sb_phy_addr, rel_sb_id);
1173 static u32 qed_sb_release(struct qed_dev *cdev,
1174 struct qed_sb_info *sb_info, u16 sb_id)
1176 struct qed_hwfn *p_hwfn;
1181 hwfn_index = sb_id % cdev->num_hwfns;
1182 p_hwfn = &cdev->hwfns[hwfn_index];
1183 rel_sb_id = sb_id / cdev->num_hwfns;
1185 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1186 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1187 hwfn_index, rel_sb_id, sb_id);
1189 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1194 static bool qed_can_link_change(struct qed_dev *cdev)
1199 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1201 struct qed_hwfn *hwfn;
1202 struct qed_mcp_link_params *link_params;
1203 struct qed_ptt *ptt;
1209 /* The link should be set only once per PF */
1210 hwfn = &cdev->hwfns[0];
1212 /* When VF wants to set link, force it to read the bulletin instead.
1213 * This mimics the PF behavior, where a noitification [both immediate
1214 * and possible later] would be generated when changing properties.
1217 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1221 ptt = qed_ptt_acquire(hwfn);
1225 link_params = qed_mcp_get_link_params(hwfn);
1226 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1227 link_params->speed.autoneg = params->autoneg;
1228 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1229 link_params->speed.advertised_speeds = 0;
1230 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) ||
1231 (params->adv_speeds & QED_LM_1000baseT_Full_BIT))
1232 link_params->speed.advertised_speeds |=
1233 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1234 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
1235 link_params->speed.advertised_speeds |=
1236 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1237 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
1238 link_params->speed.advertised_speeds |=
1239 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1240 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
1241 link_params->speed.advertised_speeds |=
1242 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1243 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
1244 link_params->speed.advertised_speeds |=
1245 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1246 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
1247 link_params->speed.advertised_speeds |=
1248 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1250 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1251 link_params->speed.forced_speed = params->forced_speed;
1252 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1253 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1254 link_params->pause.autoneg = true;
1256 link_params->pause.autoneg = false;
1257 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1258 link_params->pause.forced_rx = true;
1260 link_params->pause.forced_rx = false;
1261 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1262 link_params->pause.forced_tx = true;
1264 link_params->pause.forced_tx = false;
1266 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1267 switch (params->loopback_mode) {
1268 case QED_LINK_LOOPBACK_INT_PHY:
1269 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1271 case QED_LINK_LOOPBACK_EXT_PHY:
1272 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1274 case QED_LINK_LOOPBACK_EXT:
1275 link_params->loopback_mode = ETH_LOOPBACK_EXT;
1277 case QED_LINK_LOOPBACK_MAC:
1278 link_params->loopback_mode = ETH_LOOPBACK_MAC;
1281 link_params->loopback_mode = ETH_LOOPBACK_NONE;
1286 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1288 qed_ptt_release(hwfn, ptt);
1293 static int qed_get_port_type(u32 media_type)
1297 switch (media_type) {
1298 case MEDIA_SFPP_10G_FIBER:
1299 case MEDIA_SFP_1G_FIBER:
1300 case MEDIA_XFP_FIBER:
1301 case MEDIA_MODULE_FIBER:
1303 port_type = PORT_FIBRE;
1305 case MEDIA_DA_TWINAX:
1306 port_type = PORT_DA;
1309 port_type = PORT_TP;
1311 case MEDIA_NOT_PRESENT:
1312 port_type = PORT_NONE;
1314 case MEDIA_UNSPECIFIED:
1316 port_type = PORT_OTHER;
1322 static int qed_get_link_data(struct qed_hwfn *hwfn,
1323 struct qed_mcp_link_params *params,
1324 struct qed_mcp_link_state *link,
1325 struct qed_mcp_link_capabilities *link_caps)
1329 if (!IS_PF(hwfn->cdev)) {
1330 qed_vf_get_link_params(hwfn, params);
1331 qed_vf_get_link_state(hwfn, link);
1332 qed_vf_get_link_caps(hwfn, link_caps);
1337 p = qed_mcp_get_link_params(hwfn);
1340 memcpy(params, p, sizeof(*params));
1342 p = qed_mcp_get_link_state(hwfn);
1345 memcpy(link, p, sizeof(*link));
1347 p = qed_mcp_get_link_capabilities(hwfn);
1350 memcpy(link_caps, p, sizeof(*link_caps));
1355 static void qed_fill_link(struct qed_hwfn *hwfn,
1356 struct qed_link_output *if_link)
1358 struct qed_mcp_link_params params;
1359 struct qed_mcp_link_state link;
1360 struct qed_mcp_link_capabilities link_caps;
1363 memset(if_link, 0, sizeof(*if_link));
1365 /* Prepare source inputs */
1366 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) {
1367 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1371 /* Set the link parameters to pass to protocol driver */
1373 if_link->link_up = true;
1375 /* TODO - at the moment assume supported and advertised speed equal */
1376 if_link->supported_caps = QED_LM_FIBRE_BIT;
1377 if (link_caps.default_speed_autoneg)
1378 if_link->supported_caps |= QED_LM_Autoneg_BIT;
1379 if (params.pause.autoneg ||
1380 (params.pause.forced_rx && params.pause.forced_tx))
1381 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
1382 if (params.pause.autoneg || params.pause.forced_rx ||
1383 params.pause.forced_tx)
1384 if_link->supported_caps |= QED_LM_Pause_BIT;
1386 if_link->advertised_caps = if_link->supported_caps;
1387 if (params.speed.autoneg)
1388 if_link->advertised_caps |= QED_LM_Autoneg_BIT;
1390 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT;
1391 if (params.speed.advertised_speeds &
1392 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1393 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT |
1394 QED_LM_1000baseT_Full_BIT;
1395 if (params.speed.advertised_speeds &
1396 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1397 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
1398 if (params.speed.advertised_speeds &
1399 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1400 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
1401 if (params.speed.advertised_speeds &
1402 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1403 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT;
1404 if (params.speed.advertised_speeds &
1405 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1406 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT;
1407 if (params.speed.advertised_speeds &
1408 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1409 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT;
1411 if (link_caps.speed_capabilities &
1412 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1413 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT |
1414 QED_LM_1000baseT_Full_BIT;
1415 if (link_caps.speed_capabilities &
1416 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1417 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
1418 if (link_caps.speed_capabilities &
1419 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1420 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
1421 if (link_caps.speed_capabilities &
1422 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1423 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT;
1424 if (link_caps.speed_capabilities &
1425 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1426 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT;
1427 if (link_caps.speed_capabilities &
1428 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1429 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT;
1432 if_link->speed = link.speed;
1434 /* TODO - fill duplex properly */
1435 if_link->duplex = DUPLEX_FULL;
1436 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1437 if_link->port = qed_get_port_type(media_type);
1439 if_link->autoneg = params.speed.autoneg;
1441 if (params.pause.autoneg)
1442 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1443 if (params.pause.forced_rx)
1444 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1445 if (params.pause.forced_tx)
1446 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1448 /* Link partner capabilities */
1449 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD)
1450 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT;
1451 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
1452 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1453 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1454 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1455 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1456 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1457 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1458 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1459 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1460 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1461 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1462 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
1464 if (link.an_complete)
1465 if_link->lp_caps |= QED_LM_Autoneg_BIT;
1467 if (link.partner_adv_pause)
1468 if_link->lp_caps |= QED_LM_Pause_BIT;
1469 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1470 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1471 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
1474 static void qed_get_current_link(struct qed_dev *cdev,
1475 struct qed_link_output *if_link)
1479 qed_fill_link(&cdev->hwfns[0], if_link);
1481 for_each_hwfn(cdev, i)
1482 qed_inform_vf_link_state(&cdev->hwfns[i]);
1485 void qed_link_update(struct qed_hwfn *hwfn)
1487 void *cookie = hwfn->cdev->ops_cookie;
1488 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1489 struct qed_link_output if_link;
1491 qed_fill_link(hwfn, &if_link);
1492 qed_inform_vf_link_state(hwfn);
1494 if (IS_LEAD_HWFN(hwfn) && cookie)
1495 op->link_update(cookie, &if_link);
1498 static int qed_drain(struct qed_dev *cdev)
1500 struct qed_hwfn *hwfn;
1501 struct qed_ptt *ptt;
1507 for_each_hwfn(cdev, i) {
1508 hwfn = &cdev->hwfns[i];
1509 ptt = qed_ptt_acquire(hwfn);
1511 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1514 rc = qed_mcp_drain(hwfn, ptt);
1517 qed_ptt_release(hwfn, ptt);
1523 static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal)
1525 *rx_coal = cdev->rx_coalesce_usecs;
1526 *tx_coal = cdev->tx_coalesce_usecs;
1529 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
1532 struct qed_hwfn *hwfn;
1533 struct qed_ptt *ptt;
1537 hwfn_index = qid % cdev->num_hwfns;
1538 hwfn = &cdev->hwfns[hwfn_index];
1539 ptt = qed_ptt_acquire(hwfn);
1543 status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal,
1544 qid / cdev->num_hwfns, sb_id);
1547 status = qed_set_txq_coalesce(hwfn, ptt, tx_coal,
1548 qid / cdev->num_hwfns, sb_id);
1550 qed_ptt_release(hwfn, ptt);
1555 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1557 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1558 struct qed_ptt *ptt;
1561 ptt = qed_ptt_acquire(hwfn);
1565 status = qed_mcp_set_led(hwfn, ptt, mode);
1567 qed_ptt_release(hwfn, ptt);
1572 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
1574 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1575 struct qed_ptt *ptt;
1581 ptt = qed_ptt_acquire(hwfn);
1585 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
1586 : QED_OV_WOL_DISABLED);
1589 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1592 qed_ptt_release(hwfn, ptt);
1596 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
1598 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1599 struct qed_ptt *ptt;
1605 ptt = qed_ptt_acquire(hwfn);
1609 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
1610 QED_OV_DRIVER_STATE_ACTIVE :
1611 QED_OV_DRIVER_STATE_DISABLED);
1613 qed_ptt_release(hwfn, ptt);
1618 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
1620 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1621 struct qed_ptt *ptt;
1627 ptt = qed_ptt_acquire(hwfn);
1631 status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
1635 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1638 qed_ptt_release(hwfn, ptt);
1642 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
1644 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1645 struct qed_ptt *ptt;
1651 ptt = qed_ptt_acquire(hwfn);
1655 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
1659 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1662 qed_ptt_release(hwfn, ptt);
1666 static struct qed_selftest_ops qed_selftest_ops_pass = {
1667 .selftest_memory = &qed_selftest_memory,
1668 .selftest_interrupt = &qed_selftest_interrupt,
1669 .selftest_register = &qed_selftest_register,
1670 .selftest_clock = &qed_selftest_clock,
1671 .selftest_nvram = &qed_selftest_nvram,
1674 const struct qed_common_ops qed_common_ops_pass = {
1675 .selftest = &qed_selftest_ops_pass,
1676 .probe = &qed_probe,
1677 .remove = &qed_remove,
1678 .set_power_state = &qed_set_power_state,
1679 .set_id = &qed_set_id,
1680 .update_pf_params = &qed_update_pf_params,
1681 .slowpath_start = &qed_slowpath_start,
1682 .slowpath_stop = &qed_slowpath_stop,
1683 .set_fp_int = &qed_set_int_fp,
1684 .get_fp_int = &qed_get_int_fp,
1685 .sb_init = &qed_sb_init,
1686 .sb_release = &qed_sb_release,
1687 .simd_handler_config = &qed_simd_handler_config,
1688 .simd_handler_clean = &qed_simd_handler_clean,
1689 .dbg_grc = &qed_dbg_grc,
1690 .dbg_grc_size = &qed_dbg_grc_size,
1691 .can_link_change = &qed_can_link_change,
1692 .set_link = &qed_set_link,
1693 .get_link = &qed_get_current_link,
1694 .drain = &qed_drain,
1695 .update_msglvl = &qed_init_dp,
1696 .dbg_all_data = &qed_dbg_all_data,
1697 .dbg_all_data_size = &qed_dbg_all_data_size,
1698 .chain_alloc = &qed_chain_alloc,
1699 .chain_free = &qed_chain_free,
1700 .get_coalesce = &qed_get_coalesce,
1701 .set_coalesce = &qed_set_coalesce,
1702 .set_led = &qed_set_led,
1703 .update_drv_state = &qed_update_drv_state,
1704 .update_mac = &qed_update_mac,
1705 .update_mtu = &qed_update_mtu,
1706 .update_wol = &qed_update_wol,
1709 void qed_get_protocol_stats(struct qed_dev *cdev,
1710 enum qed_mcp_protocol_type type,
1711 union qed_mcp_protocol_stats *stats)
1713 struct qed_eth_stats eth_stats;
1715 memset(stats, 0, sizeof(*stats));
1718 case QED_MCP_LAN_STATS:
1719 qed_get_vport_stats(cdev, ð_stats);
1720 stats->lan_stats.ucast_rx_pkts =
1721 eth_stats.common.rx_ucast_pkts;
1722 stats->lan_stats.ucast_tx_pkts =
1723 eth_stats.common.tx_ucast_pkts;
1724 stats->lan_stats.fcs_err = -1;
1726 case QED_MCP_FCOE_STATS:
1727 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
1729 case QED_MCP_ISCSI_STATS:
1730 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
1733 DP_ERR(cdev, "Invalid protocol type = %d\n", type);