drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/string.h>
  41 #include <linux/etherdevice.h>
  42 #include "qed.h"
  43 #include "qed_dcbx.h"
  44 #include "qed_hsi.h"
  45 #include "qed_hw.h"
  46 #include "qed_mcp.h"
  47 #include "qed_reg_addr.h"
  48 #include "qed_sriov.h"
  49
  50 #define CHIP_MCP_RESP_ITER_US 10
  51
  52 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  53 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  54
  55 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  56         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  57                _val)
  58
  59 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  60         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  61
  62 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  63         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  64                      offsetof(struct public_drv_mb, _field), _val)
  65
  66 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  67         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  68                      offsetof(struct public_drv_mb, _field))
  69
  70 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  71                   DRV_ID_PDA_COMP_VER_SHIFT)
  72
  73 #define MCP_BYTES_PER_MBIT_SHIFT 17
  74
  75 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  76 {
  77         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  78                 return false;
  79         return true;
  80 }
  81
  82 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  83 {
  84         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  85                                         PUBLIC_PORT);
  86         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  87
  88         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  89                                                    MFW_PORT(p_hwfn));
  90         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  91                    "port_addr = 0x%x, port_id 0x%02x\n",
  92                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  93 }
  94
  95 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  96 {
  97         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  98         u32 tmp, i;
  99
 100         if (!p_hwfn->mcp_info->public_base)
 101                 return;
 102
 103         for (i = 0; i < length; i++) {
 104                 tmp = qed_rd(p_hwfn, p_ptt,
 105                              p_hwfn->mcp_info->mfw_mb_addr +
 106                              (i << 2) + sizeof(u32));
 107
 108                 /* The MB data is actually BE; Need to force it to cpu */
 109                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
 110                         be32_to_cpu((__force __be32)tmp);
 111         }
 112 }
 113
 114 struct qed_mcp_cmd_elem {
 115         struct list_head list;
 116         struct qed_mcp_mb_params *p_mb_params;
 117         u16 expected_seq_num;
 118         bool b_is_completed;
 119 };
 120
 121 /* Must be called while cmd_lock is acquired */
 122 static struct qed_mcp_cmd_elem *
 123 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 124                      struct qed_mcp_mb_params *p_mb_params,
 125                      u16 expected_seq_num)
 126 {
 127         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 128
 129         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 130         if (!p_cmd_elem)
 131                 goto out;
 132
 133         p_cmd_elem->p_mb_params = p_mb_params;
 134         p_cmd_elem->expected_seq_num = expected_seq_num;
 135         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 136 out:
 137         return p_cmd_elem;
 138 }
 139
 140 /* Must be called while cmd_lock is acquired */
 141 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 142                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 143 {
 144         list_del(&p_cmd_elem->list);
 145         kfree(p_cmd_elem);
 146 }
 147
 148 /* Must be called while cmd_lock is acquired */
 149 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 150                                                      u16 seq_num)
 151 {
 152         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 153
 154         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 155                 if (p_cmd_elem->expected_seq_num == seq_num)
 156                         return p_cmd_elem;
 157         }
 158
 159         return NULL;
 160 }
 161
 162 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 163 {
 164         if (p_hwfn->mcp_info) {
 165                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 166
 167                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 168                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 169
 170                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 171                 list_for_each_entry_safe(p_cmd_elem,
 172                                          p_tmp,
 173                                          &p_hwfn->mcp_info->cmd_list, list) {
 174                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 175                 }
 176                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 177         }
 178
 179         kfree(p_hwfn->mcp_info);
 180
 181         return 0;
 182 }
 183
 184 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 185 {
 186         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 187         u32 drv_mb_offsize, mfw_mb_offsize;
 188         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 189
 190         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 191         if (!p_info->public_base)
 192                 return 0;
 193
 194         p_info->public_base |= GRCBASE_MCP;
 195
 196         /* Calculate the driver and MFW mailbox address */
 197         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 198                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 199                                                      PUBLIC_DRV_MB));
 200         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 201         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 202                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 203                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 204
 205         /* Set the MFW MB address */
 206         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 207                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 208                                                      PUBLIC_MFW_MB));
 209         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 210         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
 211
 212         /* Get the current driver mailbox sequence before sending
 213          * the first command
 214          */
 215         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 216                              DRV_MSG_SEQ_NUMBER_MASK;
 217
 218         /* Get current FW pulse sequence */
 219         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 220                                 DRV_PULSE_SEQ_MASK;
 221
 222         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 223
 224         return 0;
 225 }
 226
 227 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 228 {
 229         struct qed_mcp_info *p_info;
 230         u32 size;
 231
 232         /* Allocate mcp_info structure */
 233         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 234         if (!p_hwfn->mcp_info)
 235                 goto err;
 236         p_info = p_hwfn->mcp_info;
 237
 238         /* Initialize the MFW spinlock */
 239         spin_lock_init(&p_info->cmd_lock);
 240         spin_lock_init(&p_info->link_lock);
 241
 242         INIT_LIST_HEAD(&p_info->cmd_list);
 243
 244         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 245                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 246                 /* Do not free mcp_info here, since public_base indicate that
 247                  * the MCP is not initialized
 248                  */
 249                 return 0;
 250         }
 251
 252         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 253         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 254         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 255         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 256                 goto err;
 257
 258         return 0;
 259
 260 err:
 261         qed_mcp_free(p_hwfn);
 262         return -ENOMEM;
 263 }
 264
 265 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 266                                    struct qed_ptt *p_ptt)
 267 {
 268         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 269
 270         /* Use MCP history register to check if MCP reset occurred between init
 271          * time and now.
 272          */
 273         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 274                 DP_VERBOSE(p_hwfn,
 275                            QED_MSG_SP,
 276                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 277                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 278
 279                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 280                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 281         }
 282 }
 283
 284 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 285 {
 286         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 287         int rc = 0;
 288
 289         /* Ensure that only a single thread is accessing the mailbox */
 290         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 291
 292         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 293
 294         /* Set drv command along with the updated sequence */
 295         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 296         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 297         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 298
 299         do {
 300                 /* Wait for MFW response */
 301                 udelay(delay);
 302                 /* Give the FW up to 500 second (50*1000*10usec) */
 303         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 304                                               MISCS_REG_GENERIC_POR_0)) &&
 305                  (cnt++ < QED_MCP_RESET_RETRIES));
 306
 307         if (org_mcp_reset_seq !=
 308             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 309                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 310                            "MCP was reset after %d usec\n", cnt * delay);
 311         } else {
 312                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 313                 rc = -EAGAIN;
 314         }
 315
 316         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 317
 318         return rc;
 319 }
 320
 321 /* Must be called while cmd_lock is acquired */
 322 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 323 {
 324         struct qed_mcp_cmd_elem *p_cmd_elem;
 325
 326         /* There is at most one pending command at a certain time, and if it
 327          * exists - it is placed at the HEAD of the list.
 328          */
 329         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 330                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 331                                               struct qed_mcp_cmd_elem, list);
 332                 return !p_cmd_elem->b_is_completed;
 333         }
 334
 335         return false;
 336 }
 337
 338 /* Must be called while cmd_lock is acquired */
 339 static int
 340 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 341 {
 342         struct qed_mcp_mb_params *p_mb_params;
 343         struct qed_mcp_cmd_elem *p_cmd_elem;
 344         u32 mcp_resp;
 345         u16 seq_num;
 346
 347         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 348         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 349
 350         /* Return if no new non-handled response has been received */
 351         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 352                 return -EAGAIN;
 353
 354         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 355         if (!p_cmd_elem) {
 356                 DP_ERR(p_hwfn,
 357                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 358                        seq_num);
 359                 return -EINVAL;
 360         }
 361
 362         p_mb_params = p_cmd_elem->p_mb_params;
 363
 364         /* Get the MFW response along with the sequence number */
 365         p_mb_params->mcp_resp = mcp_resp;
 366
 367         /* Get the MFW param */
 368         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 369
 370         /* Get the union data */
 371         if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
 372                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 373                                       offsetof(struct public_drv_mb,
 374                                                union_data);
 375                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 376                                 union_data_addr, p_mb_params->data_dst_size);
 377         }
 378
 379         p_cmd_elem->b_is_completed = true;
 380
 381         return 0;
 382 }
 383
 384 /* Must be called while cmd_lock is acquired */
 385 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 386                                     struct qed_ptt *p_ptt,
 387                                     struct qed_mcp_mb_params *p_mb_params,
 388                                     u16 seq_num)
 389 {
 390         union drv_union_data union_data;
 391         u32 union_data_addr;
 392
 393         /* Set the union data */
 394         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 395                           offsetof(struct public_drv_mb, union_data);
 396         memset(&union_data, 0, sizeof(union_data));
 397         if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
 398                 memcpy(&union_data, p_mb_params->p_data_src,
 399                        p_mb_params->data_src_size);
 400         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 401                       sizeof(union_data));
 402
 403         /* Set the drv param */
 404         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 405
 406         /* Set the drv command along with the sequence number */
 407         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 408
 409         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 410                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 411                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 412 }
 413
 414 static int
 415 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 416                        struct qed_ptt *p_ptt,
 417                        struct qed_mcp_mb_params *p_mb_params,
 418                        u32 max_retries, u32 delay)
 419 {
 420         struct qed_mcp_cmd_elem *p_cmd_elem;
 421         u32 cnt = 0;
 422         u16 seq_num;
 423         int rc = 0;
 424
 425         /* Wait until the mailbox is non-occupied */
 426         do {
 427                 /* Exit the loop if there is no pending command, or if the
 428                  * pending command is completed during this iteration.
 429                  * The spinlock stays locked until the command is sent.
 430                  */
 431
 432                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 433
 434                 if (!qed_mcp_has_pending_cmd(p_hwfn))
 435                         break;
 436
 437                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 438                 if (!rc)
 439                         break;
 440                 else if (rc != -EAGAIN)
 441                         goto err;
 442
 443                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 444                 udelay(delay);
 445         } while (++cnt < max_retries);
 446
 447         if (cnt >= max_retries) {
 448                 DP_NOTICE(p_hwfn,
 449                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 450                           p_mb_params->cmd, p_mb_params->param);
 451                 return -EAGAIN;
 452         }
 453
 454         /* Send the mailbox command */
 455         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 456         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 457         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 458         if (!p_cmd_elem)
 459                 goto err;
 460
 461         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 462         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 463
 464         /* Wait for the MFW response */
 465         do {
 466                 /* Exit the loop if the command is already completed, or if the
 467                  * command is completed during this iteration.
 468                  * The spinlock stays locked until the list element is removed.
 469                  */
 470
 471                 udelay(delay);
 472                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 473
 474                 if (p_cmd_elem->b_is_completed)
 475                         break;
 476
 477                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 478                 if (!rc)
 479                         break;
 480                 else if (rc != -EAGAIN)
 481                         goto err;
 482
 483                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 484         } while (++cnt < max_retries);
 485
 486         if (cnt >= max_retries) {
 487                 DP_NOTICE(p_hwfn,
 488                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 489                           p_mb_params->cmd, p_mb_params->param);
 490
 491                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 492                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 493                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 494
 495                 return -EAGAIN;
 496         }
 497
 498         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 499         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 500
 501         DP_VERBOSE(p_hwfn,
 502                    QED_MSG_SP,
 503                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 504                    p_mb_params->mcp_resp,
 505                    p_mb_params->mcp_param,
 506                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 507
 508         /* Clear the sequence number from the MFW response */
 509         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 510
 511         return 0;
 512
 513 err:
 514         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 515         return rc;
 516 }
 517
 518 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 519                                  struct qed_ptt *p_ptt,
 520                                  struct qed_mcp_mb_params *p_mb_params)
 521 {
 522         size_t union_data_size = sizeof(union drv_union_data);
 523         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 524         u32 delay = CHIP_MCP_RESP_ITER_US;
 525
 526         /* MCP not initialized */
 527         if (!qed_mcp_is_init(p_hwfn)) {
 528                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 529                 return -EBUSY;
 530         }
 531
 532         if (p_mb_params->data_src_size > union_data_size ||
 533             p_mb_params->data_dst_size > union_data_size) {
 534                 DP_ERR(p_hwfn,
 535                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 536                        p_mb_params->data_src_size,
 537                        p_mb_params->data_dst_size, union_data_size);
 538                 return -EINVAL;
 539         }
 540
 541         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 542                                       delay);
 543 }
 544
 545 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 546                 struct qed_ptt *p_ptt,
 547                 u32 cmd,
 548                 u32 param,
 549                 u32 *o_mcp_resp,
 550                 u32 *o_mcp_param)
 551 {
 552         struct qed_mcp_mb_params mb_params;
 553         int rc;
 554
 555         memset(&mb_params, 0, sizeof(mb_params));
 556         mb_params.cmd = cmd;
 557         mb_params.param = param;
 558
 559         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 560         if (rc)
 561                 return rc;
 562
 563         *o_mcp_resp = mb_params.mcp_resp;
 564         *o_mcp_param = mb_params.mcp_param;
 565
 566         return 0;
 567 }
 568
 569 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 570                        struct qed_ptt *p_ptt,
 571                        u32 cmd,
 572                        u32 param,
 573                        u32 *o_mcp_resp,
 574                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 575 {
 576         struct qed_mcp_mb_params mb_params;
 577         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 578         int rc;
 579
 580         memset(&mb_params, 0, sizeof(mb_params));
 581         mb_params.cmd = cmd;
 582         mb_params.param = param;
 583         mb_params.p_data_dst = raw_data;
 584
 585         /* Use the maximal value since the actual one is part of the response */
 586         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 587
 588         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 589         if (rc)
 590                 return rc;
 591
 592         *o_mcp_resp = mb_params.mcp_resp;
 593         *o_mcp_param = mb_params.mcp_param;
 594
 595         *o_txn_size = *o_mcp_param;
 596         memcpy(o_buf, raw_data, *o_txn_size);
 597
 598         return 0;
 599 }
 600
 601 static bool
 602 qed_mcp_can_force_load(u8 drv_role,
 603                        u8 exist_drv_role,
 604                        enum qed_override_force_load override_force_load)
 605 {
 606         bool can_force_load = false;
 607
 608         switch (override_force_load) {
 609         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 610                 can_force_load = true;
 611                 break;
 612         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 613                 can_force_load = false;
 614                 break;
 615         default:
 616                 can_force_load = (drv_role == DRV_ROLE_OS &&
 617                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 618                                  (drv_role == DRV_ROLE_KDUMP &&
 619                                   exist_drv_role == DRV_ROLE_OS);
 620                 break;
 621         }
 622
 623         return can_force_load;
 624 }
 625
 626 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 627                                    struct qed_ptt *p_ptt)
 628 {
 629         u32 resp = 0, param = 0;
 630         int rc;
 631
 632         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 633                          &resp, &param);
 634         if (rc)
 635                 DP_NOTICE(p_hwfn,
 636                           "Failed to send cancel load request, rc = %d\n", rc);
 637
 638         return rc;
 639 }
 640
 641 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 642 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 643 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 644 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 645 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 646 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 647
 648 static u32 qed_get_config_bitmap(void)
 649 {
 650         u32 config_bitmap = 0x0;
 651
 652         if (IS_ENABLED(CONFIG_QEDE))
 653                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 654
 655         if (IS_ENABLED(CONFIG_QED_SRIOV))
 656                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 657
 658         if (IS_ENABLED(CONFIG_QED_RDMA))
 659                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 660
 661         if (IS_ENABLED(CONFIG_QED_FCOE))
 662                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 663
 664         if (IS_ENABLED(CONFIG_QED_ISCSI))
 665                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 666
 667         if (IS_ENABLED(CONFIG_QED_LL2))
 668                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 669
 670         return config_bitmap;
 671 }
 672
 673 struct qed_load_req_in_params {
 674         u8 hsi_ver;
 675 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 676 #define QED_LOAD_REQ_HSI_VER_1          1
 677         u32 drv_ver_0;
 678         u32 drv_ver_1;
 679         u32 fw_ver;
 680         u8 drv_role;
 681         u8 timeout_val;
 682         u8 force_cmd;
 683         bool avoid_eng_reset;
 684 };
 685
 686 struct qed_load_req_out_params {
 687         u32 load_code;
 688         u32 exist_drv_ver_0;
 689         u32 exist_drv_ver_1;
 690         u32 exist_fw_ver;
 691         u8 exist_drv_role;
 692         u8 mfw_hsi_ver;
 693         bool drv_exists;
 694 };
 695
 696 static int
 697 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 698                    struct qed_ptt *p_ptt,
 699                    struct qed_load_req_in_params *p_in_params,
 700                    struct qed_load_req_out_params *p_out_params)
 701 {
 702         struct qed_mcp_mb_params mb_params;
 703         struct load_req_stc load_req;
 704         struct load_rsp_stc load_rsp;
 705         u32 hsi_ver;
 706         int rc;
 707
 708         memset(&load_req, 0, sizeof(load_req));
 709         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 710         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 711         load_req.fw_ver = p_in_params->fw_ver;
 712         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 713         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 714                           p_in_params->timeout_val);
 715         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 716                           p_in_params->force_cmd);
 717         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 718                           p_in_params->avoid_eng_reset);
 719
 720         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 721                   DRV_ID_MCP_HSI_VER_CURRENT :
 722                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 723
 724         memset(&mb_params, 0, sizeof(mb_params));
 725         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 726         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 727         mb_params.p_data_src = &load_req;
 728         mb_params.data_src_size = sizeof(load_req);
 729         mb_params.p_data_dst = &load_rsp;
 730         mb_params.data_dst_size = sizeof(load_rsp);
 731
 732         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 733                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 734                    mb_params.param,
 735                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 736                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 737                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 738                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 739
 740         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 741                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 742                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 743                            load_req.drv_ver_0,
 744                            load_req.drv_ver_1,
 745                            load_req.fw_ver,
 746                            load_req.misc0,
 747                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 748                            QED_MFW_GET_FIELD(load_req.misc0,
 749                                              LOAD_REQ_LOCK_TO),
 750                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 751                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 752         }
 753
 754         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 755         if (rc) {
 756                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 757                 return rc;
 758         }
 759
 760         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 761                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 762         p_out_params->load_code = mb_params.mcp_resp;
 763
 764         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 765             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 766                 DP_VERBOSE(p_hwfn,
 767                            QED_MSG_SP,
 768                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 769                            load_rsp.drv_ver_0,
 770                            load_rsp.drv_ver_1,
 771                            load_rsp.fw_ver,
 772                            load_rsp.misc0,
 773                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 774                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 775                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 776
 777                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 778                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 779                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 780                 p_out_params->exist_drv_role =
 781                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 782                 p_out_params->mfw_hsi_ver =
 783                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 784                 p_out_params->drv_exists =
 785                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 786                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 793                                   enum qed_drv_role drv_role,
 794                                   u8 *p_mfw_drv_role)
 795 {
 796         switch (drv_role) {
 797         case QED_DRV_ROLE_OS:
 798                 *p_mfw_drv_role = DRV_ROLE_OS;
 799                 break;
 800         case QED_DRV_ROLE_KDUMP:
 801                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 802                 break;
 803         default:
 804                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 805                 return -EINVAL;
 806         }
 807
 808         return 0;
 809 }
 810
 811 enum qed_load_req_force {
 812         QED_LOAD_REQ_FORCE_NONE,
 813         QED_LOAD_REQ_FORCE_PF,
 814         QED_LOAD_REQ_FORCE_ALL,
 815 };
 816
 817 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 818
 819                                   enum qed_load_req_force force_cmd,
 820                                   u8 *p_mfw_force_cmd)
 821 {
 822         switch (force_cmd) {
 823         case QED_LOAD_REQ_FORCE_NONE:
 824                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 825                 break;
 826         case QED_LOAD_REQ_FORCE_PF:
 827                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 828                 break;
 829         case QED_LOAD_REQ_FORCE_ALL:
 830                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 831                 break;
 832         }
 833 }
 834
 835 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 836                      struct qed_ptt *p_ptt,
 837                      struct qed_load_req_params *p_params)
 838 {
 839         struct qed_load_req_out_params out_params;
 840         struct qed_load_req_in_params in_params;
 841         u8 mfw_drv_role, mfw_force_cmd;
 842         int rc;
 843
 844         memset(&in_params, 0, sizeof(in_params));
 845         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 846         in_params.drv_ver_0 = QED_VERSION;
 847         in_params.drv_ver_1 = qed_get_config_bitmap();
 848         in_params.fw_ver = STORM_FW_VERSION;
 849         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 850         if (rc)
 851                 return rc;
 852
 853         in_params.drv_role = mfw_drv_role;
 854         in_params.timeout_val = p_params->timeout_val;
 855         qed_get_mfw_force_cmd(p_hwfn,
 856                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 857
 858         in_params.force_cmd = mfw_force_cmd;
 859         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 860
 861         memset(&out_params, 0, sizeof(out_params));
 862         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 863         if (rc)
 864                 return rc;
 865
 866         /* First handle cases where another load request should/might be sent:
 867          * - MFW expects the old interface [HSI version = 1]
 868          * - MFW responds that a force load request is required
 869          */
 870         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 871                 DP_INFO(p_hwfn,
 872                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
 873
 874                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
 875                 memset(&out_params, 0, sizeof(out_params));
 876                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 877                 if (rc)
 878                         return rc;
 879         } else if (out_params.load_code ==
 880                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 881                 if (qed_mcp_can_force_load(in_params.drv_role,
 882                                            out_params.exist_drv_role,
 883                                            p_params->override_force_load)) {
 884                         DP_INFO(p_hwfn,
 885                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
 886                                 in_params.drv_role, in_params.fw_ver,
 887                                 in_params.drv_ver_0, in_params.drv_ver_1,
 888                                 out_params.exist_drv_role,
 889                                 out_params.exist_fw_ver,
 890                                 out_params.exist_drv_ver_0,
 891                                 out_params.exist_drv_ver_1);
 892
 893                         qed_get_mfw_force_cmd(p_hwfn,
 894                                               QED_LOAD_REQ_FORCE_ALL,
 895                                               &mfw_force_cmd);
 896
 897                         in_params.force_cmd = mfw_force_cmd;
 898                         memset(&out_params, 0, sizeof(out_params));
 899                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
 900                                                 &out_params);
 901                         if (rc)
 902                                 return rc;
 903                 } else {
 904                         DP_NOTICE(p_hwfn,
 905                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
 906                                   in_params.drv_role, in_params.fw_ver,
 907                                   in_params.drv_ver_0, in_params.drv_ver_1,
 908                                   out_params.exist_drv_role,
 909                                   out_params.exist_fw_ver,
 910                                   out_params.exist_drv_ver_0,
 911                                   out_params.exist_drv_ver_1);
 912                         DP_NOTICE(p_hwfn,
 913                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
 914
 915                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
 916                         return -EBUSY;
 917                 }
 918         }
 919
 920         /* Now handle the other types of responses.
 921          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
 922          * expected here after the additional revised load requests were sent.
 923          */
 924         switch (out_params.load_code) {
 925         case FW_MSG_CODE_DRV_LOAD_ENGINE:
 926         case FW_MSG_CODE_DRV_LOAD_PORT:
 927         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
 928                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 929                     out_params.drv_exists) {
 930                         /* The role and fw/driver version match, but the PF is
 931                          * already loaded and has not been unloaded gracefully.
 932                          */
 933                         DP_NOTICE(p_hwfn,
 934                                   "PF is already loaded\n");
 935                         return -EINVAL;
 936                 }
 937                 break;
 938         default:
 939                 DP_NOTICE(p_hwfn,
 940                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
 941                           out_params.load_code);
 942                 return -EBUSY;
 943         }
 944
 945         p_params->load_code = out_params.load_code;
 946
 947         return 0;
 948 }
 949
 950 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 951 {
 952         u32 wol_param, mcp_resp, mcp_param;
 953
 954         switch (p_hwfn->cdev->wol_config) {
 955         case QED_OV_WOL_DISABLED:
 956                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
 957                 break;
 958         case QED_OV_WOL_ENABLED:
 959                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
 960                 break;
 961         default:
 962                 DP_NOTICE(p_hwfn,
 963                           "Unknown WoL configuration %02x\n",
 964                           p_hwfn->cdev->wol_config);
 965                 /* Fallthrough */
 966         case QED_OV_WOL_DEFAULT:
 967                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
 968         }
 969
 970         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
 971                            &mcp_resp, &mcp_param);
 972 }
 973
 974 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 975 {
 976         struct qed_mcp_mb_params mb_params;
 977         struct mcp_mac wol_mac;
 978
 979         memset(&mb_params, 0, sizeof(mb_params));
 980         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
 981
 982         /* Set the primary MAC if WoL is enabled */
 983         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
 984                 u8 *p_mac = p_hwfn->cdev->wol_mac;
 985
 986                 memset(&wol_mac, 0, sizeof(wol_mac));
 987                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
 988                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
 989                                     p_mac[4] << 8 | p_mac[5];
 990
 991                 DP_VERBOSE(p_hwfn,
 992                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
 993                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
 994                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
 995
 996                 mb_params.p_data_src = &wol_mac;
 997                 mb_params.data_src_size = sizeof(wol_mac);
 998         }
 999
1000         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1001 }
1002
1003 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1004                                   struct qed_ptt *p_ptt)
1005 {
1006         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1007                                         PUBLIC_PATH);
1008         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1009         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1010                                      QED_PATH_ID(p_hwfn));
1011         u32 disabled_vfs[VF_MAX_STATIC / 32];
1012         int i;
1013
1014         DP_VERBOSE(p_hwfn,
1015                    QED_MSG_SP,
1016                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1017                    mfw_path_offsize, path_addr);
1018
1019         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1020                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1021                                          path_addr +
1022                                          offsetof(struct public_path,
1023                                                   mcp_vf_disabled) +
1024                                          sizeof(u32) * i);
1025                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1026                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1027                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1028         }
1029
1030         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1031                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1032 }
1033
1034 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1035                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1036 {
1037         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1038                                         PUBLIC_FUNC);
1039         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1040         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1041                                      MCP_PF_ID(p_hwfn));
1042         struct qed_mcp_mb_params mb_params;
1043         int rc;
1044         int i;
1045
1046         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1047                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1048                            "Acking VFs [%08x,...,%08x] - %08x\n",
1049                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1050
1051         memset(&mb_params, 0, sizeof(mb_params));
1052         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1053         mb_params.p_data_src = vfs_to_ack;
1054         mb_params.data_src_size = VF_MAX_STATIC / 8;
1055         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1056         if (rc) {
1057                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1058                 return -EBUSY;
1059         }
1060
1061         /* Clear the ACK bits */
1062         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1063                 qed_wr(p_hwfn, p_ptt,
1064                        func_addr +
1065                        offsetof(struct public_func, drv_ack_vf_disabled) +
1066                        i * sizeof(u32), 0);
1067
1068         return rc;
1069 }
1070
1071 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1072                                               struct qed_ptt *p_ptt)
1073 {
1074         u32 transceiver_state;
1075
1076         transceiver_state = qed_rd(p_hwfn, p_ptt,
1077                                    p_hwfn->mcp_info->port_addr +
1078                                    offsetof(struct public_port,
1079                                             transceiver_data));
1080
1081         DP_VERBOSE(p_hwfn,
1082                    (NETIF_MSG_HW | QED_MSG_SP),
1083                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1084                    transceiver_state,
1085                    (u32)(p_hwfn->mcp_info->port_addr +
1086                           offsetof(struct public_port, transceiver_data)));
1087
1088         transceiver_state = GET_FIELD(transceiver_state,
1089                                       ETH_TRANSCEIVER_STATE);
1090
1091         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1092                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1093         else
1094                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1095 }
1096
1097 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1098                                        struct qed_ptt *p_ptt, bool b_reset)
1099 {
1100         struct qed_mcp_link_state *p_link;
1101         u8 max_bw, min_bw;
1102         u32 status = 0;
1103
1104         /* Prevent SW/attentions from doing this at the same time */
1105         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1106
1107         p_link = &p_hwfn->mcp_info->link_output;
1108         memset(p_link, 0, sizeof(*p_link));
1109         if (!b_reset) {
1110                 status = qed_rd(p_hwfn, p_ptt,
1111                                 p_hwfn->mcp_info->port_addr +
1112                                 offsetof(struct public_port, link_status));
1113                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1114                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1115                            status,
1116                            (u32)(p_hwfn->mcp_info->port_addr +
1117                                  offsetof(struct public_port, link_status)));
1118         } else {
1119                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1120                            "Resetting link indications\n");
1121                 goto out;
1122         }
1123
1124         if (p_hwfn->b_drv_link_init)
1125                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1126         else
1127                 p_link->link_up = false;
1128
1129         p_link->full_duplex = true;
1130         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1131         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1132                 p_link->speed = 100000;
1133                 break;
1134         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1135                 p_link->speed = 50000;
1136                 break;
1137         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1138                 p_link->speed = 40000;
1139                 break;
1140         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1141                 p_link->speed = 25000;
1142                 break;
1143         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1144                 p_link->speed = 20000;
1145                 break;
1146         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1147                 p_link->speed = 10000;
1148                 break;
1149         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1150                 p_link->full_duplex = false;
1151         /* Fall-through */
1152         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1153                 p_link->speed = 1000;
1154                 break;
1155         default:
1156                 p_link->speed = 0;
1157         }
1158
1159         if (p_link->link_up && p_link->speed)
1160                 p_link->line_speed = p_link->speed;
1161         else
1162                 p_link->line_speed = 0;
1163
1164         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1165         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1166
1167         /* Max bandwidth configuration */
1168         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1169
1170         /* Min bandwidth configuration */
1171         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1172         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1173                                             p_link->min_pf_rate);
1174
1175         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1176         p_link->an_complete = !!(status &
1177                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1178         p_link->parallel_detection = !!(status &
1179                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1180         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1181
1182         p_link->partner_adv_speed |=
1183                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1184                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1185         p_link->partner_adv_speed |=
1186                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1187                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1188         p_link->partner_adv_speed |=
1189                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1190                 QED_LINK_PARTNER_SPEED_10G : 0;
1191         p_link->partner_adv_speed |=
1192                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1193                 QED_LINK_PARTNER_SPEED_20G : 0;
1194         p_link->partner_adv_speed |=
1195                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1196                 QED_LINK_PARTNER_SPEED_25G : 0;
1197         p_link->partner_adv_speed |=
1198                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1199                 QED_LINK_PARTNER_SPEED_40G : 0;
1200         p_link->partner_adv_speed |=
1201                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1202                 QED_LINK_PARTNER_SPEED_50G : 0;
1203         p_link->partner_adv_speed |=
1204                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1205                 QED_LINK_PARTNER_SPEED_100G : 0;
1206
1207         p_link->partner_tx_flow_ctrl_en =
1208                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1209         p_link->partner_rx_flow_ctrl_en =
1210                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1211
1212         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1213         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1214                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1215                 break;
1216         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1217                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1218                 break;
1219         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1220                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1221                 break;
1222         default:
1223                 p_link->partner_adv_pause = 0;
1224         }
1225
1226         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1227
1228         qed_link_update(p_hwfn);
1229 out:
1230         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1231 }
1232
1233 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1234 {
1235         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1236         struct qed_mcp_mb_params mb_params;
1237         struct eth_phy_cfg phy_cfg;
1238         int rc = 0;
1239         u32 cmd;
1240
1241         /* Set the shmem configuration according to params */
1242         memset(&phy_cfg, 0, sizeof(phy_cfg));
1243         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1244         if (!params->speed.autoneg)
1245                 phy_cfg.speed = params->speed.forced_speed;
1246         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1247         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1248         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1249         phy_cfg.adv_speed = params->speed.advertised_speeds;
1250         phy_cfg.loopback_mode = params->loopback_mode;
1251
1252         p_hwfn->b_drv_link_init = b_up;
1253
1254         if (b_up) {
1255                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1256                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1257                            phy_cfg.speed,
1258                            phy_cfg.pause,
1259                            phy_cfg.adv_speed,
1260                            phy_cfg.loopback_mode,
1261                            phy_cfg.feature_config_flags);
1262         } else {
1263                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1264                            "Resetting link\n");
1265         }
1266
1267         memset(&mb_params, 0, sizeof(mb_params));
1268         mb_params.cmd = cmd;
1269         mb_params.p_data_src = &phy_cfg;
1270         mb_params.data_src_size = sizeof(phy_cfg);
1271         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1272
1273         /* if mcp fails to respond we must abort */
1274         if (rc) {
1275                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1276                 return rc;
1277         }
1278
1279         /* Mimic link-change attention, done for several reasons:
1280          *  - On reset, there's no guarantee MFW would trigger
1281          *    an attention.
1282          *  - On initialization, older MFWs might not indicate link change
1283          *    during LFA, so we'll never get an UP indication.
1284          */
1285         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1286
1287         return 0;
1288 }
1289
1290 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1291                                         struct qed_ptt *p_ptt,
1292                                         enum MFW_DRV_MSG_TYPE type)
1293 {
1294         enum qed_mcp_protocol_type stats_type;
1295         union qed_mcp_protocol_stats stats;
1296         struct qed_mcp_mb_params mb_params;
1297         u32 hsi_param;
1298
1299         switch (type) {
1300         case MFW_DRV_MSG_GET_LAN_STATS:
1301                 stats_type = QED_MCP_LAN_STATS;
1302                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1303                 break;
1304         case MFW_DRV_MSG_GET_FCOE_STATS:
1305                 stats_type = QED_MCP_FCOE_STATS;
1306                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1307                 break;
1308         case MFW_DRV_MSG_GET_ISCSI_STATS:
1309                 stats_type = QED_MCP_ISCSI_STATS;
1310                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1311                 break;
1312         case MFW_DRV_MSG_GET_RDMA_STATS:
1313                 stats_type = QED_MCP_RDMA_STATS;
1314                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1315                 break;
1316         default:
1317                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1318                 return;
1319         }
1320
1321         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1322
1323         memset(&mb_params, 0, sizeof(mb_params));
1324         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1325         mb_params.param = hsi_param;
1326         mb_params.p_data_src = &stats;
1327         mb_params.data_src_size = sizeof(stats);
1328         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1329 }
1330
1331 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1332                                   struct public_func *p_shmem_info)
1333 {
1334         struct qed_mcp_function_info *p_info;
1335
1336         p_info = &p_hwfn->mcp_info->func_info;
1337
1338         p_info->bandwidth_min = (p_shmem_info->config &
1339                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1340                                         FUNC_MF_CFG_MIN_BW_SHIFT;
1341         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1342                 DP_INFO(p_hwfn,
1343                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1344                         p_info->bandwidth_min);
1345                 p_info->bandwidth_min = 1;
1346         }
1347
1348         p_info->bandwidth_max = (p_shmem_info->config &
1349                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1350                                         FUNC_MF_CFG_MAX_BW_SHIFT;
1351         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1352                 DP_INFO(p_hwfn,
1353                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1354                         p_info->bandwidth_max);
1355                 p_info->bandwidth_max = 100;
1356         }
1357 }
1358
1359 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1360                                   struct qed_ptt *p_ptt,
1361                                   struct public_func *p_data, int pfid)
1362 {
1363         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1364                                         PUBLIC_FUNC);
1365         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1366         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1367         u32 i, size;
1368
1369         memset(p_data, 0, sizeof(*p_data));
1370
1371         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1372         for (i = 0; i < size / sizeof(u32); i++)
1373                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1374                                             func_addr + (i << 2));
1375         return size;
1376 }
1377
1378 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1379 {
1380         struct qed_mcp_function_info *p_info;
1381         struct public_func shmem_info;
1382         u32 resp = 0, param = 0;
1383
1384         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1385
1386         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1387
1388         p_info = &p_hwfn->mcp_info->func_info;
1389
1390         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1391         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1392
1393         /* Acknowledge the MFW */
1394         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1395                     &param);
1396 }
1397
1398 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1399                           struct qed_ptt *p_ptt)
1400 {
1401         struct qed_mcp_info *info = p_hwfn->mcp_info;
1402         int rc = 0;
1403         bool found = false;
1404         u16 i;
1405
1406         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1407
1408         /* Read Messages from MFW */
1409         qed_mcp_read_mb(p_hwfn, p_ptt);
1410
1411         /* Compare current messages to old ones */
1412         for (i = 0; i < info->mfw_mb_length; i++) {
1413                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1414                         continue;
1415
1416                 found = true;
1417
1418                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1419                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1420                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1421
1422                 switch (i) {
1423                 case MFW_DRV_MSG_LINK_CHANGE:
1424                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1425                         break;
1426                 case MFW_DRV_MSG_VF_DISABLED:
1427                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1428                         break;
1429                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1430                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1431                                                   QED_DCBX_REMOTE_LLDP_MIB);
1432                         break;
1433                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1434                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1435                                                   QED_DCBX_REMOTE_MIB);
1436                         break;
1437                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1438                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1439                                                   QED_DCBX_OPERATIONAL_MIB);
1440                         break;
1441                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1442                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1443                         break;
1444                 case MFW_DRV_MSG_GET_LAN_STATS:
1445                 case MFW_DRV_MSG_GET_FCOE_STATS:
1446                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1447                 case MFW_DRV_MSG_GET_RDMA_STATS:
1448                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1449                         break;
1450                 case MFW_DRV_MSG_BW_UPDATE:
1451                         qed_mcp_update_bw(p_hwfn, p_ptt);
1452                         break;
1453                 default:
1454                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1455                         rc = -EINVAL;
1456                 }
1457         }
1458
1459         /* ACK everything */
1460         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1461                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1462
1463                 /* MFW expect answer in BE, so we force write in that format */
1464                 qed_wr(p_hwfn, p_ptt,
1465                        info->mfw_mb_addr + sizeof(u32) +
1466                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1467                        sizeof(u32) + i * sizeof(u32),
1468                        (__force u32)val);
1469         }
1470
1471         if (!found) {
1472                 DP_NOTICE(p_hwfn,
1473                           "Received an MFW message indication but no new message!\n");
1474                 rc = -EINVAL;
1475         }
1476
1477         /* Copy the new mfw messages into the shadow */
1478         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1479
1480         return rc;
1481 }
1482
1483 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1484                         struct qed_ptt *p_ptt,
1485                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
1486 {
1487         u32 global_offsize;
1488
1489         if (IS_VF(p_hwfn->cdev)) {
1490                 if (p_hwfn->vf_iov_info) {
1491                         struct pfvf_acquire_resp_tlv *p_resp;
1492
1493                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1494                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1495                         return 0;
1496                 } else {
1497                         DP_VERBOSE(p_hwfn,
1498                                    QED_MSG_IOV,
1499                                    "VF requested MFW version prior to ACQUIRE\n");
1500                         return -EINVAL;
1501                 }
1502         }
1503
1504         global_offsize = qed_rd(p_hwfn, p_ptt,
1505                                 SECTION_OFFSIZE_ADDR(p_hwfn->
1506                                                      mcp_info->public_base,
1507                                                      PUBLIC_GLOBAL));
1508         *p_mfw_ver =
1509             qed_rd(p_hwfn, p_ptt,
1510                    SECTION_ADDR(global_offsize,
1511                                 0) + offsetof(struct public_global, mfw_ver));
1512
1513         if (p_running_bundle_id != NULL) {
1514                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1515                                               SECTION_ADDR(global_offsize, 0) +
1516                                               offsetof(struct public_global,
1517                                                        running_bundle_id));
1518         }
1519
1520         return 0;
1521 }
1522
1523 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1524 {
1525         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1526         struct qed_ptt  *p_ptt;
1527
1528         if (IS_VF(cdev))
1529                 return -EINVAL;
1530
1531         if (!qed_mcp_is_init(p_hwfn)) {
1532                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1533                 return -EBUSY;
1534         }
1535
1536         *p_media_type = MEDIA_UNSPECIFIED;
1537
1538         p_ptt = qed_ptt_acquire(p_hwfn);
1539         if (!p_ptt)
1540                 return -EBUSY;
1541
1542         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1543                                offsetof(struct public_port, media_type));
1544
1545         qed_ptt_release(p_hwfn, p_ptt);
1546
1547         return 0;
1548 }
1549
1550 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1551 static void
1552 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1553                                enum qed_pci_personality *p_proto)
1554 {
1555         /* There wasn't ever a legacy MFW that published iwarp.
1556          * So at this point, this is either plain l2 or RoCE.
1557          */
1558         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1559                 *p_proto = QED_PCI_ETH_ROCE;
1560         else
1561                 *p_proto = QED_PCI_ETH;
1562
1563         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1564                    "According to Legacy capabilities, L2 personality is %08x\n",
1565                    (u32) *p_proto);
1566 }
1567
1568 static int
1569 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1570                             struct qed_ptt *p_ptt,
1571                             enum qed_pci_personality *p_proto)
1572 {
1573         u32 resp = 0, param = 0;
1574         int rc;
1575
1576         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1577                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1578         if (rc)
1579                 return rc;
1580         if (resp != FW_MSG_CODE_OK) {
1581                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1582                            "MFW lacks support for command; Returns %08x\n",
1583                            resp);
1584                 return -EINVAL;
1585         }
1586
1587         switch (param) {
1588         case FW_MB_PARAM_GET_PF_RDMA_NONE:
1589                 *p_proto = QED_PCI_ETH;
1590                 break;
1591         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1592                 *p_proto = QED_PCI_ETH_ROCE;
1593                 break;
1594         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1595                 DP_NOTICE(p_hwfn,
1596                           "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n");
1597                 *p_proto = QED_PCI_ETH_ROCE;
1598                 break;
1599         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1600         default:
1601                 DP_NOTICE(p_hwfn,
1602                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1603                           param);
1604                 return -EINVAL;
1605         }
1606
1607         DP_VERBOSE(p_hwfn,
1608                    NETIF_MSG_IFUP,
1609                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1610                    (u32) *p_proto, resp, param);
1611         return 0;
1612 }
1613
1614 static int
1615 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1616                         struct public_func *p_info,
1617                         struct qed_ptt *p_ptt,
1618                         enum qed_pci_personality *p_proto)
1619 {
1620         int rc = 0;
1621
1622         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1623         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1624                 if (!IS_ENABLED(CONFIG_QED_RDMA))
1625                         *p_proto = QED_PCI_ETH;
1626                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1627                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1628                 break;
1629         case FUNC_MF_CFG_PROTOCOL_ISCSI:
1630                 *p_proto = QED_PCI_ISCSI;
1631                 break;
1632         case FUNC_MF_CFG_PROTOCOL_FCOE:
1633                 *p_proto = QED_PCI_FCOE;
1634                 break;
1635         case FUNC_MF_CFG_PROTOCOL_ROCE:
1636                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1637         /* Fallthrough */
1638         default:
1639                 rc = -EINVAL;
1640         }
1641
1642         return rc;
1643 }
1644
1645 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1646                                  struct qed_ptt *p_ptt)
1647 {
1648         struct qed_mcp_function_info *info;
1649         struct public_func shmem_info;
1650
1651         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1652         info = &p_hwfn->mcp_info->func_info;
1653
1654         info->pause_on_host = (shmem_info.config &
1655                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1656
1657         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1658                                     &info->protocol)) {
1659                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1660                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1661                 return -EINVAL;
1662         }
1663
1664         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1665
1666         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1667                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1668                 info->mac[1] = (u8)(shmem_info.mac_upper);
1669                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1670                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1671                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1672                 info->mac[5] = (u8)(shmem_info.mac_lower);
1673
1674                 /* Store primary MAC for later possible WoL */
1675                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
1676         } else {
1677                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1678         }
1679
1680         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1681                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1682         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1683                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1684
1685         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1686
1687         info->mtu = (u16)shmem_info.mtu_size;
1688
1689         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
1690         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
1691         if (qed_mcp_is_init(p_hwfn)) {
1692                 u32 resp = 0, param = 0;
1693                 int rc;
1694
1695                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1696                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
1697                 if (rc)
1698                         return rc;
1699                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
1700                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
1701         }
1702
1703         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1704                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
1705                 info->pause_on_host, info->protocol,
1706                 info->bandwidth_min, info->bandwidth_max,
1707                 info->mac[0], info->mac[1], info->mac[2],
1708                 info->mac[3], info->mac[4], info->mac[5],
1709                 info->wwn_port, info->wwn_node,
1710                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
1711
1712         return 0;
1713 }
1714
1715 struct qed_mcp_link_params
1716 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1717 {
1718         if (!p_hwfn || !p_hwfn->mcp_info)
1719                 return NULL;
1720         return &p_hwfn->mcp_info->link_input;
1721 }
1722
1723 struct qed_mcp_link_state
1724 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1725 {
1726         if (!p_hwfn || !p_hwfn->mcp_info)
1727                 return NULL;
1728         return &p_hwfn->mcp_info->link_output;
1729 }
1730
1731 struct qed_mcp_link_capabilities
1732 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1733 {
1734         if (!p_hwfn || !p_hwfn->mcp_info)
1735                 return NULL;
1736         return &p_hwfn->mcp_info->link_capabilities;
1737 }
1738
1739 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1740 {
1741         u32 resp = 0, param = 0;
1742         int rc;
1743
1744         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1745                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1746
1747         /* Wait for the drain to complete before returning */
1748         msleep(1020);
1749
1750         return rc;
1751 }
1752
1753 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1754                            struct qed_ptt *p_ptt, u32 *p_flash_size)
1755 {
1756         u32 flash_size;
1757
1758         if (IS_VF(p_hwfn->cdev))
1759                 return -EINVAL;
1760
1761         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1762         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1763                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1764         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1765
1766         *p_flash_size = flash_size;
1767
1768         return 0;
1769 }
1770
1771 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
1772                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1773 {
1774         u32 resp = 0, param = 0, rc_param = 0;
1775         int rc;
1776
1777         /* Only Leader can configure MSIX, and need to take CMT into account */
1778         if (!IS_LEAD_HWFN(p_hwfn))
1779                 return 0;
1780         num *= p_hwfn->cdev->num_hwfns;
1781
1782         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1783                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1784         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1785                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1786
1787         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1788                          &resp, &rc_param);
1789
1790         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1791                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1792                 rc = -EINVAL;
1793         } else {
1794                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1795                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1796                            num, vf_id);
1797         }
1798
1799         return rc;
1800 }
1801
1802 int
1803 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1804                          struct qed_ptt *p_ptt,
1805                          struct qed_mcp_drv_version *p_ver)
1806 {
1807         struct qed_mcp_mb_params mb_params;
1808         struct drv_version_stc drv_version;
1809         __be32 val;
1810         u32 i;
1811         int rc;
1812
1813         memset(&drv_version, 0, sizeof(drv_version));
1814         drv_version.version = p_ver->version;
1815         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
1816                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
1817                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
1818         }
1819
1820         memset(&mb_params, 0, sizeof(mb_params));
1821         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1822         mb_params.p_data_src = &drv_version;
1823         mb_params.data_src_size = sizeof(drv_version);
1824         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1825         if (rc)
1826                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1827
1828         return rc;
1829 }
1830
1831 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1832 {
1833         u32 resp = 0, param = 0;
1834         int rc;
1835
1836         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1837                          &param);
1838         if (rc)
1839                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1840
1841         return rc;
1842 }
1843
1844 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1845 {
1846         u32 value, cpu_mode;
1847
1848         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1849
1850         value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1851         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1852         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1853         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1854
1855         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
1856 }
1857
1858 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
1859                                      struct qed_ptt *p_ptt,
1860                                      enum qed_ov_client client)
1861 {
1862         u32 resp = 0, param = 0;
1863         u32 drv_mb_param;
1864         int rc;
1865
1866         switch (client) {
1867         case QED_OV_CLIENT_DRV:
1868                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1869                 break;
1870         case QED_OV_CLIENT_USER:
1871                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1872                 break;
1873         case QED_OV_CLIENT_VENDOR_SPEC:
1874                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
1875                 break;
1876         default:
1877                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
1878                 return -EINVAL;
1879         }
1880
1881         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1882                          drv_mb_param, &resp, &param);
1883         if (rc)
1884                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1885
1886         return rc;
1887 }
1888
1889 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
1890                                    struct qed_ptt *p_ptt,
1891                                    enum qed_ov_driver_state drv_state)
1892 {
1893         u32 resp = 0, param = 0;
1894         u32 drv_mb_param;
1895         int rc;
1896
1897         switch (drv_state) {
1898         case QED_OV_DRIVER_STATE_NOT_LOADED:
1899                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1900                 break;
1901         case QED_OV_DRIVER_STATE_DISABLED:
1902                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1903                 break;
1904         case QED_OV_DRIVER_STATE_ACTIVE:
1905                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1906                 break;
1907         default:
1908                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
1909                 return -EINVAL;
1910         }
1911
1912         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1913                          drv_mb_param, &resp, &param);
1914         if (rc)
1915                 DP_ERR(p_hwfn, "Failed to send driver state\n");
1916
1917         return rc;
1918 }
1919
1920 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
1921                           struct qed_ptt *p_ptt, u16 mtu)
1922 {
1923         u32 resp = 0, param = 0;
1924         u32 drv_mb_param;
1925         int rc;
1926
1927         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
1928         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
1929                          drv_mb_param, &resp, &param);
1930         if (rc)
1931                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
1932
1933         return rc;
1934 }
1935
1936 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
1937                           struct qed_ptt *p_ptt, u8 *mac)
1938 {
1939         struct qed_mcp_mb_params mb_params;
1940         u32 mfw_mac[2];
1941         int rc;
1942
1943         memset(&mb_params, 0, sizeof(mb_params));
1944         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
1945         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
1946                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
1947         mb_params.param |= MCP_PF_ID(p_hwfn);
1948
1949         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
1950          * in 32-bit granularity.
1951          * So the MAC has to be set in native order [and not byte order],
1952          * otherwise it would be read incorrectly by MFW after swap.
1953          */
1954         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
1955         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
1956
1957         mb_params.p_data_src = (u8 *)mfw_mac;
1958         mb_params.data_src_size = 8;
1959         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1960         if (rc)
1961                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
1962
1963         /* Store primary MAC for later possible WoL */
1964         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
1965
1966         return rc;
1967 }
1968
1969 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
1970                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
1971 {
1972         u32 resp = 0, param = 0;
1973         u32 drv_mb_param;
1974         int rc;
1975
1976         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
1977                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1978                            "Can't change WoL configuration when WoL isn't supported\n");
1979                 return -EINVAL;
1980         }
1981
1982         switch (wol) {
1983         case QED_OV_WOL_DEFAULT:
1984                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
1985                 break;
1986         case QED_OV_WOL_DISABLED:
1987                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
1988                 break;
1989         case QED_OV_WOL_ENABLED:
1990                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
1991                 break;
1992         default:
1993                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
1994                 return -EINVAL;
1995         }
1996
1997         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
1998                          drv_mb_param, &resp, &param);
1999         if (rc)
2000                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2001
2002         /* Store the WoL update for a future unload */
2003         p_hwfn->cdev->wol_config = (u8)wol;
2004
2005         return rc;
2006 }
2007
2008 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2009                               struct qed_ptt *p_ptt,
2010                               enum qed_ov_eswitch eswitch)
2011 {
2012         u32 resp = 0, param = 0;
2013         u32 drv_mb_param;
2014         int rc;
2015
2016         switch (eswitch) {
2017         case QED_OV_ESWITCH_NONE:
2018                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2019                 break;
2020         case QED_OV_ESWITCH_VEB:
2021                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2022                 break;
2023         case QED_OV_ESWITCH_VEPA:
2024                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2025                 break;
2026         default:
2027                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2028                 return -EINVAL;
2029         }
2030
2031         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2032                          drv_mb_param, &resp, &param);
2033         if (rc)
2034                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2035
2036         return rc;
2037 }
2038
2039 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2040                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2041 {
2042         u32 resp = 0, param = 0, drv_mb_param;
2043         int rc;
2044
2045         switch (mode) {
2046         case QED_LED_MODE_ON:
2047                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2048                 break;
2049         case QED_LED_MODE_OFF:
2050                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2051                 break;
2052         case QED_LED_MODE_RESTORE:
2053                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2054                 break;
2055         default:
2056                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2057                 return -EINVAL;
2058         }
2059
2060         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2061                          drv_mb_param, &resp, &param);
2062
2063         return rc;
2064 }
2065
2066 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2067                           struct qed_ptt *p_ptt, u32 mask_parities)
2068 {
2069         u32 resp = 0, param = 0;
2070         int rc;
2071
2072         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2073                          mask_parities, &resp, &param);
2074
2075         if (rc) {
2076                 DP_ERR(p_hwfn,
2077                        "MCP response failure for mask parities, aborting\n");
2078         } else if (resp != FW_MSG_CODE_OK) {
2079                 DP_ERR(p_hwfn,
2080                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2081                 rc = -EINVAL;
2082         }
2083
2084         return rc;
2085 }
2086
2087 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2088 {
2089         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2090         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2091         u32 resp = 0, resp_param = 0;
2092         struct qed_ptt *p_ptt;
2093         int rc = 0;
2094
2095         p_ptt = qed_ptt_acquire(p_hwfn);
2096         if (!p_ptt)
2097                 return -EBUSY;
2098
2099         while (bytes_left > 0) {
2100                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2101
2102                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2103                                         DRV_MSG_CODE_NVM_READ_NVRAM,
2104                                         addr + offset +
2105                                         (bytes_to_copy <<
2106                                          DRV_MB_PARAM_NVM_LEN_SHIFT),
2107                                         &resp, &resp_param,
2108                                         &read_len,
2109                                         (u32 *)(p_buf + offset));
2110
2111                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2112                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2113                         break;
2114                 }
2115
2116                 /* This can be a lengthy process, and it's possible scheduler
2117                  * isn't preemptable. Sleep a bit to prevent CPU hogging.
2118                  */
2119                 if (bytes_left % 0x1000 <
2120                     (bytes_left - read_len) % 0x1000)
2121                         usleep_range(1000, 2000);
2122
2123                 offset += read_len;
2124                 bytes_left -= read_len;
2125         }
2126
2127         cdev->mcp_nvm_resp = resp;
2128         qed_ptt_release(p_hwfn, p_ptt);
2129
2130         return rc;
2131 }
2132
2133 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2134 {
2135         u32 drv_mb_param = 0, rsp, param;
2136         int rc = 0;
2137
2138         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2139                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2140
2141         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2142                          drv_mb_param, &rsp, &param);
2143
2144         if (rc)
2145                 return rc;
2146
2147         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2148             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2149                 rc = -EAGAIN;
2150
2151         return rc;
2152 }
2153
2154 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2155 {
2156         u32 drv_mb_param, rsp, param;
2157         int rc = 0;
2158
2159         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2160                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2161
2162         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2163                          drv_mb_param, &rsp, &param);
2164
2165         if (rc)
2166                 return rc;
2167
2168         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2169             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2170                 rc = -EAGAIN;
2171
2172         return rc;
2173 }
2174
2175 int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
2176                                          struct qed_ptt *p_ptt,
2177                                          u32 *num_images)
2178 {
2179         u32 drv_mb_param = 0, rsp;
2180         int rc = 0;
2181
2182         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2183                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2184
2185         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2186                          drv_mb_param, &rsp, num_images);
2187         if (rc)
2188                 return rc;
2189
2190         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2191                 rc = -EINVAL;
2192
2193         return rc;
2194 }
2195
2196 int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn,
2197                                         struct qed_ptt *p_ptt,
2198                                         struct bist_nvm_image_att *p_image_att,
2199                                         u32 image_index)
2200 {
2201         u32 buf_size = 0, param, resp = 0, resp_param = 0;
2202         int rc;
2203
2204         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2205                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2206         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2207
2208         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2209                                 DRV_MSG_CODE_BIST_TEST, param,
2210                                 &resp, &resp_param,
2211                                 &buf_size,
2212                                 (u32 *)p_image_att);
2213         if (rc)
2214                 return rc;
2215
2216         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2217             (p_image_att->return_code != 1))
2218                 rc = -EINVAL;
2219
2220         return rc;
2221 }
2222
2223 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2224 {
2225         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2226
2227         switch (res_id) {
2228         case QED_SB:
2229                 mfw_res_id = RESOURCE_NUM_SB_E;
2230                 break;
2231         case QED_L2_QUEUE:
2232                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2233                 break;
2234         case QED_VPORT:
2235                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2236                 break;
2237         case QED_RSS_ENG:
2238                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2239                 break;
2240         case QED_PQ:
2241                 mfw_res_id = RESOURCE_NUM_PQ_E;
2242                 break;
2243         case QED_RL:
2244                 mfw_res_id = RESOURCE_NUM_RL_E;
2245                 break;
2246         case QED_MAC:
2247         case QED_VLAN:
2248                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2249                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2250                 break;
2251         case QED_ILT:
2252                 mfw_res_id = RESOURCE_ILT_E;
2253                 break;
2254         case QED_LL2_QUEUE:
2255                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2256                 break;
2257         case QED_RDMA_CNQ_RAM:
2258         case QED_CMDQS_CQS:
2259                 /* CNQ/CMDQS are the same resource */
2260                 mfw_res_id = RESOURCE_CQS_E;
2261                 break;
2262         case QED_RDMA_STATS_QUEUE:
2263                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2264                 break;
2265         case QED_BDQ:
2266                 mfw_res_id = RESOURCE_BDQ_E;
2267                 break;
2268         default:
2269                 break;
2270         }
2271
2272         return mfw_res_id;
2273 }
2274
2275 #define QED_RESC_ALLOC_VERSION_MAJOR    2
2276 #define QED_RESC_ALLOC_VERSION_MINOR    0
2277 #define QED_RESC_ALLOC_VERSION                               \
2278         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
2279           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2280          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
2281           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2282
2283 struct qed_resc_alloc_in_params {
2284         u32 cmd;
2285         enum qed_resources res_id;
2286         u32 resc_max_val;
2287 };
2288
2289 struct qed_resc_alloc_out_params {
2290         u32 mcp_resp;
2291         u32 mcp_param;
2292         u32 resc_num;
2293         u32 resc_start;
2294         u32 vf_resc_num;
2295         u32 vf_resc_start;
2296         u32 flags;
2297 };
2298
2299 static int
2300 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
2301                             struct qed_ptt *p_ptt,
2302                             struct qed_resc_alloc_in_params *p_in_params,
2303                             struct qed_resc_alloc_out_params *p_out_params)
2304 {
2305         struct qed_mcp_mb_params mb_params;
2306         struct resource_info mfw_resc_info;
2307         int rc;
2308
2309         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
2310
2311         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
2312         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2313                 DP_ERR(p_hwfn,
2314                        "Failed to match resource %d [%s] with the MFW resources\n",
2315                        p_in_params->res_id,
2316                        qed_hw_get_resc_name(p_in_params->res_id));
2317                 return -EINVAL;
2318         }
2319
2320         switch (p_in_params->cmd) {
2321         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2322                 mfw_resc_info.size = p_in_params->resc_max_val;
2323                 /* Fallthrough */
2324         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2325                 break;
2326         default:
2327                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2328                        p_in_params->cmd);
2329                 return -EINVAL;
2330         }
2331
2332         memset(&mb_params, 0, sizeof(mb_params));
2333         mb_params.cmd = p_in_params->cmd;
2334         mb_params.param = QED_RESC_ALLOC_VERSION;
2335         mb_params.p_data_src = &mfw_resc_info;
2336         mb_params.data_src_size = sizeof(mfw_resc_info);
2337         mb_params.p_data_dst = mb_params.p_data_src;
2338         mb_params.data_dst_size = mb_params.data_src_size;
2339
2340         DP_VERBOSE(p_hwfn,
2341                    QED_MSG_SP,
2342                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2343                    p_in_params->cmd,
2344                    p_in_params->res_id,
2345                    qed_hw_get_resc_name(p_in_params->res_id),
2346                    QED_MFW_GET_FIELD(mb_params.param,
2347                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2348                    QED_MFW_GET_FIELD(mb_params.param,
2349                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2350                    p_in_params->resc_max_val);
2351
2352         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2353         if (rc)
2354                 return rc;
2355
2356         p_out_params->mcp_resp = mb_params.mcp_resp;
2357         p_out_params->mcp_param = mb_params.mcp_param;
2358         p_out_params->resc_num = mfw_resc_info.size;
2359         p_out_params->resc_start = mfw_resc_info.offset;
2360         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
2361         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
2362         p_out_params->flags = mfw_resc_info.flags;
2363
2364         DP_VERBOSE(p_hwfn,
2365                    QED_MSG_SP,
2366                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
2367                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
2368                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2369                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
2370                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2371                    p_out_params->resc_num,
2372                    p_out_params->resc_start,
2373                    p_out_params->vf_resc_num,
2374                    p_out_params->vf_resc_start, p_out_params->flags);
2375
2376         return 0;
2377 }
2378
2379 int
2380 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
2381                          struct qed_ptt *p_ptt,
2382                          enum qed_resources res_id,
2383                          u32 resc_max_val, u32 *p_mcp_resp)
2384 {
2385         struct qed_resc_alloc_out_params out_params;
2386         struct qed_resc_alloc_in_params in_params;
2387         int rc;
2388
2389         memset(&in_params, 0, sizeof(in_params));
2390         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
2391         in_params.res_id = res_id;
2392         in_params.resc_max_val = resc_max_val;
2393         memset(&out_params, 0, sizeof(out_params));
2394         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2395                                          &out_params);
2396         if (rc)
2397                 return rc;
2398
2399         *p_mcp_resp = out_params.mcp_resp;
2400
2401         return 0;
2402 }
2403
2404 int
2405 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
2406                       struct qed_ptt *p_ptt,
2407                       enum qed_resources res_id,
2408                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
2409 {
2410         struct qed_resc_alloc_out_params out_params;
2411         struct qed_resc_alloc_in_params in_params;
2412         int rc;
2413
2414         memset(&in_params, 0, sizeof(in_params));
2415         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2416         in_params.res_id = res_id;
2417         memset(&out_params, 0, sizeof(out_params));
2418         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2419                                          &out_params);
2420         if (rc)
2421                 return rc;
2422
2423         *p_mcp_resp = out_params.mcp_resp;
2424
2425         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2426                 *p_resc_num = out_params.resc_num;
2427                 *p_resc_start = out_params.resc_start;
2428         }
2429
2430         return 0;
2431 }
2432
2433 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2434 {
2435         u32 mcp_resp, mcp_param;
2436
2437         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2438                            &mcp_resp, &mcp_param);
2439 }
2440
2441 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
2442                                 struct qed_ptt *p_ptt,
2443                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
2444 {
2445         int rc;
2446
2447         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
2448                          p_mcp_resp, p_mcp_param);
2449         if (rc)
2450                 return rc;
2451
2452         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
2453                 DP_INFO(p_hwfn,
2454                         "The resource command is unsupported by the MFW\n");
2455                 return -EINVAL;
2456         }
2457
2458         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
2459                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
2460
2461                 DP_NOTICE(p_hwfn,
2462                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
2463                           param, opcode);
2464                 return -EINVAL;
2465         }
2466
2467         return rc;
2468 }
2469
2470 int
2471 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2472                     struct qed_ptt *p_ptt,
2473                     struct qed_resc_lock_params *p_params)
2474 {
2475         u32 param = 0, mcp_resp, mcp_param;
2476         u8 opcode;
2477         int rc;
2478
2479         switch (p_params->timeout) {
2480         case QED_MCP_RESC_LOCK_TO_DEFAULT:
2481                 opcode = RESOURCE_OPCODE_REQ;
2482                 p_params->timeout = 0;
2483                 break;
2484         case QED_MCP_RESC_LOCK_TO_NONE:
2485                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
2486                 p_params->timeout = 0;
2487                 break;
2488         default:
2489                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
2490                 break;
2491         }
2492
2493         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2494         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2495         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
2496
2497         DP_VERBOSE(p_hwfn,
2498                    QED_MSG_SP,
2499                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
2500                    param, p_params->timeout, opcode, p_params->resource);
2501
2502         /* Attempt to acquire the resource */
2503         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2504         if (rc)
2505                 return rc;
2506
2507         /* Analyze the response */
2508         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
2509         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2510
2511         DP_VERBOSE(p_hwfn,
2512                    QED_MSG_SP,
2513                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
2514                    mcp_param, opcode, p_params->owner);
2515
2516         switch (opcode) {
2517         case RESOURCE_OPCODE_GNT:
2518                 p_params->b_granted = true;
2519                 break;
2520         case RESOURCE_OPCODE_BUSY:
2521                 p_params->b_granted = false;
2522                 break;
2523         default:
2524                 DP_NOTICE(p_hwfn,
2525                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
2526                           mcp_param, opcode);
2527                 return -EINVAL;
2528         }
2529
2530         return 0;
2531 }
2532
2533 int
2534 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2535                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
2536 {
2537         u32 retry_cnt = 0;
2538         int rc;
2539
2540         do {
2541                 /* No need for an interval before the first iteration */
2542                 if (retry_cnt) {
2543                         if (p_params->sleep_b4_retry) {
2544                                 u16 retry_interval_in_ms =
2545                                     DIV_ROUND_UP(p_params->retry_interval,
2546                                                  1000);
2547
2548                                 msleep(retry_interval_in_ms);
2549                         } else {
2550                                 udelay(p_params->retry_interval);
2551                         }
2552                 }
2553
2554                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
2555                 if (rc)
2556                         return rc;
2557
2558                 if (p_params->b_granted)
2559                         break;
2560         } while (retry_cnt++ < p_params->retry_num);
2561
2562         return 0;
2563 }
2564
2565 int
2566 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
2567                     struct qed_ptt *p_ptt,
2568                     struct qed_resc_unlock_params *p_params)
2569 {
2570         u32 param = 0, mcp_resp, mcp_param;
2571         u8 opcode;
2572         int rc;
2573
2574         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
2575                                    : RESOURCE_OPCODE_RELEASE;
2576         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2577         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2578
2579         DP_VERBOSE(p_hwfn, QED_MSG_SP,
2580                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
2581                    param, opcode, p_params->resource);
2582
2583         /* Attempt to release the resource */
2584         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2585         if (rc)
2586                 return rc;
2587
2588         /* Analyze the response */
2589         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2590
2591         DP_VERBOSE(p_hwfn, QED_MSG_SP,
2592                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
2593                    mcp_param, opcode);
2594
2595         switch (opcode) {
2596         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
2597                 DP_INFO(p_hwfn,
2598                         "Resource unlock request for an already released resource [%d]\n",
2599                         p_params->resource);
2600                 /* Fallthrough */
2601         case RESOURCE_OPCODE_RELEASED:
2602                 p_params->b_released = true;
2603                 break;
2604         case RESOURCE_OPCODE_WRONG_OWNER:
2605                 p_params->b_released = false;
2606                 break;
2607         default:
2608                 DP_NOTICE(p_hwfn,
2609                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
2610                           mcp_param, opcode);
2611                 return -EINVAL;
2612         }
2613
2614         return 0;
2615 }