1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
39 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
42 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
45 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
48 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
51 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
54 #define CDU_REG_SEGMENT0_PARAMS \
56 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
58 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
60 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
62 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
64 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
66 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
68 #define CDU_REG_SEGMENT1_PARAMS \
70 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
72 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
74 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
76 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
78 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
80 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
83 #define XSDM_REG_OPERATION_GEN \
85 #define NIG_REG_RX_BRB_OUT_EN \
87 #define NIG_REG_STORM_OUT_EN \
89 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
91 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
93 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
95 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
97 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
99 #define BAR0_MAP_REG_MSDM_RAM \
101 #define BAR0_MAP_REG_USDM_RAM \
103 #define BAR0_MAP_REG_PSDM_RAM \
105 #define BAR0_MAP_REG_TSDM_RAM \
107 #define BAR0_MAP_REG_XSDM_RAM \
109 #define BAR0_MAP_REG_YSDM_RAM \
111 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
113 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \
115 #define PRS_REG_SEARCH_TCP \
117 #define PRS_REG_SEARCH_UDP \
119 #define PRS_REG_SEARCH_FCOE \
121 #define PRS_REG_SEARCH_ROCE \
123 #define PRS_REG_SEARCH_OPENFLOW \
125 #define PRS_REG_SEARCH_TAG1 \
127 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \
129 #define PRS_REG_SEARCH_TCP_FIRST_FRAG \
131 #define TM_REG_PF_ENABLE_CONN \
133 #define TM_REG_PF_ENABLE_TASK \
135 #define TM_REG_PF_SCAN_ACTIVE_CONN \
137 #define TM_REG_PF_SCAN_ACTIVE_TASK \
139 #define IGU_REG_LEADING_EDGE_LATCH \
141 #define IGU_REG_TRAILING_EDGE_LATCH \
143 #define QM_REG_USG_CNT_PF_TX \
145 #define QM_REG_USG_CNT_PF_OTHER \
147 #define DORQ_REG_PF_DB_ENABLE \
149 #define DORQ_REG_VF_USAGE_CNT \
151 #define QM_REG_PF_EN \
153 #define TCFC_REG_WEAK_ENABLE_VF \
155 #define TCFC_REG_STRONG_ENABLE_PF \
157 #define TCFC_REG_STRONG_ENABLE_VF \
159 #define CCFC_REG_WEAK_ENABLE_VF \
161 #define CCFC_REG_STRONG_ENABLE_PF \
163 #define PGLUE_B_REG_PGL_ADDR_88_F0_BB \
165 #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \
167 #define PGLUE_B_REG_PGL_ADDR_90_F0_BB \
169 #define PGLUE_B_REG_PGL_ADDR_94_F0_BB \
171 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
173 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
175 #define MISC_REG_GEN_PURP_CR0 \
177 #define MCP_REG_SCRATCH \
179 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
181 #define MISCS_REG_CHIP_NUM \
183 #define MISCS_REG_CHIP_REV \
185 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
187 #define MISCS_REG_CHIP_TEST_REG \
189 #define MISCS_REG_CHIP_METAL \
191 #define MISCS_REG_FUNCTION_HIDE \
193 #define BRB_REG_HEADER_SIZE \
195 #define BTB_REG_HEADER_SIZE \
197 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
199 #define CCFC_REG_ACTIVITY_COUNTER \
201 #define CCFC_REG_STRONG_ENABLE_VF \
203 #define CDU_REG_CID_ADDR_PARAMS \
205 #define DBG_REG_CLIENT_ENABLE \
207 #define DMAE_REG_INIT \
209 #define DORQ_REG_IFEN \
211 #define DORQ_REG_DB_DROP_REASON \
213 #define DORQ_REG_DB_DROP_DETAILS \
215 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
217 #define GRC_REG_TIMEOUT_EN \
219 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
221 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
223 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
225 #define IGU_REG_BLOCK_CONFIGURATION \
227 #define MCM_REG_INIT \
229 #define MCP2_REG_DBG_DWORD_ENABLE \
231 #define MISC_REG_PORT_MODE \
233 #define MISCS_REG_CLK_100G_MODE \
235 #define MSDM_REG_ENABLE_IN1 \
237 #define MSEM_REG_ENABLE_IN \
239 #define NIG_REG_CM_HDR \
241 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
243 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
245 #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL
246 #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL
247 #define NIG_REG_LLH_FUNC_FILTER_VALUE \
249 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
251 #define NIG_REG_LLH_FUNC_FILTER_EN \
253 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
255 #define NIG_REG_LLH_FUNC_FILTER_MODE \
257 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
259 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
261 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
263 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
265 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
267 #define NCSI_REG_CONFIG \
269 #define PBF_REG_INIT \
271 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
273 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
275 #define PTU_REG_ATC_INIT_ARRAY \
277 #define PCM_REG_INIT \
279 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
281 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
283 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
285 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
287 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
289 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
291 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
293 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
295 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
297 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
299 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
301 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
303 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
305 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
307 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
309 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
311 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
313 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
315 #define PRM_REG_DISABLE_PRM \
317 #define PRS_REG_SOFT_RST \
319 #define PRS_REG_MSG_INFO \
321 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
323 #define PRS_REG_USE_LIGHT_L2 \
325 #define PSDM_REG_ENABLE_IN1 \
327 #define PSEM_REG_ENABLE_IN \
329 #define PSWRQ_REG_DBG_SELECT \
331 #define PSWRQ2_REG_CDUT_P_SIZE \
333 #define PSWRQ2_REG_ILT_MEMORY \
335 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
337 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
339 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
341 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
343 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
345 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
347 #define PSWRD_REG_DBG_SELECT \
349 #define PSWRD2_REG_CONF11 \
351 #define PSWWR_REG_USDM_FULL_TH \
353 #define PSWWR2_REG_CDU_FULL_TH2 \
355 #define QM_REG_MAXPQSIZE_0 \
357 #define RSS_REG_RSS_INIT_EN \
359 #define RDIF_REG_STOP_ON_ERROR \
361 #define RDIF_REG_DEBUG_ERROR_INFO \
363 #define RDIF_REG_DEBUG_ERROR_INFO_SIZE \
365 #define SRC_REG_SOFT_RST \
367 #define TCFC_REG_ACTIVITY_COUNTER \
369 #define TCM_REG_INIT \
371 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
373 #define TSDM_REG_ENABLE_IN1 \
375 #define TSEM_REG_ENABLE_IN \
377 #define TDIF_REG_STOP_ON_ERROR \
379 #define TDIF_REG_DEBUG_ERROR_INFO \
381 #define TDIF_REG_DEBUG_ERROR_INFO_SIZE \
383 #define UCM_REG_INIT \
385 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
387 #define USDM_REG_ENABLE_IN1 \
389 #define USEM_REG_ENABLE_IN \
391 #define XCM_REG_INIT \
393 #define XSDM_REG_ENABLE_IN1 \
395 #define XSEM_REG_ENABLE_IN \
397 #define YCM_REG_INIT \
399 #define YSDM_REG_ENABLE_IN1 \
401 #define YSEM_REG_ENABLE_IN \
403 #define XYLD_REG_SCBD_STRICT_PRIO \
405 #define TMLD_REG_SCBD_STRICT_PRIO \
407 #define MULD_REG_SCBD_STRICT_PRIO \
409 #define YULD_REG_SCBD_STRICT_PRIO \
411 #define MISC_REG_SHARED_MEM_ADDR \
413 #define DMAE_REG_GO_C0 \
415 #define DMAE_REG_GO_C1 \
417 #define DMAE_REG_GO_C2 \
419 #define DMAE_REG_GO_C3 \
421 #define DMAE_REG_GO_C4 \
423 #define DMAE_REG_GO_C5 \
425 #define DMAE_REG_GO_C6 \
427 #define DMAE_REG_GO_C7 \
429 #define DMAE_REG_GO_C8 \
431 #define DMAE_REG_GO_C9 \
433 #define DMAE_REG_GO_C10 \
435 #define DMAE_REG_GO_C11 \
437 #define DMAE_REG_GO_C12 \
439 #define DMAE_REG_GO_C13 \
441 #define DMAE_REG_GO_C14 \
443 #define DMAE_REG_GO_C15 \
445 #define DMAE_REG_GO_C16 \
447 #define DMAE_REG_GO_C17 \
449 #define DMAE_REG_GO_C18 \
451 #define DMAE_REG_GO_C19 \
453 #define DMAE_REG_GO_C20 \
455 #define DMAE_REG_GO_C21 \
457 #define DMAE_REG_GO_C22 \
459 #define DMAE_REG_GO_C23 \
461 #define DMAE_REG_GO_C24 \
463 #define DMAE_REG_GO_C25 \
465 #define DMAE_REG_GO_C26 \
467 #define DMAE_REG_GO_C27 \
469 #define DMAE_REG_GO_C28 \
471 #define DMAE_REG_GO_C29 \
473 #define DMAE_REG_GO_C30 \
475 #define DMAE_REG_GO_C31 \
477 #define DMAE_REG_CMD_MEM \
479 #define QM_REG_MAXPQSIZETXSEL_0 \
481 #define QM_REG_SDMCMDREADY \
483 #define QM_REG_SDMCMDADDR \
485 #define QM_REG_SDMCMDDATALSB \
487 #define QM_REG_SDMCMDDATAMSB \
489 #define QM_REG_SDMCMDGO \
491 #define QM_REG_RLPFCRD \
493 #define QM_REG_RLPFINCVAL \
495 #define QM_REG_RLGLBLCRD \
497 #define QM_REG_RLGLBLINCVAL \
499 #define IGU_REG_ATTENTION_ENABLE \
501 #define IGU_REG_ATTN_MSG_ADDR_L \
503 #define IGU_REG_ATTN_MSG_ADDR_H \
505 #define MISC_REG_AEU_GENERAL_ATTN_0 \
507 #define CAU_REG_SB_ADDR_MEMORY \
509 #define CAU_REG_SB_VAR_MEMORY \
511 #define CAU_REG_PI_MEMORY \
513 #define IGU_REG_PF_CONFIGURATION \
515 #define IGU_REG_VF_CONFIGURATION \
517 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
519 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
521 #define MISC_REG_AEU_MASK_ATTN_IGU \
523 #define IGU_REG_CLEANUP_STATUS_0 \
525 #define IGU_REG_CLEANUP_STATUS_1 \
527 #define IGU_REG_CLEANUP_STATUS_2 \
529 #define IGU_REG_CLEANUP_STATUS_3 \
531 #define IGU_REG_CLEANUP_STATUS_4 \
533 #define IGU_REG_COMMAND_REG_32LSB_DATA \
535 #define IGU_REG_COMMAND_REG_CTRL \
537 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
539 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
541 #define IGU_REG_MAPPING_MEMORY \
543 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
545 #define IGU_REG_WRITE_DONE_PENDING \
547 #define MISCS_REG_GENERIC_POR_0 \
549 #define MCP_REG_NVM_CFG4 \
551 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
553 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
555 #define MCP_REG_CPU_STATE \
557 #define MCP_REG_CPU_EVENT_MASK \
559 #define PGLUE_B_REG_PF_BAR0_SIZE \
561 #define PGLUE_B_REG_PF_BAR1_SIZE \
563 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
564 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
565 #define PRS_REG_VXLAN_PORT 0x1f0738UL
566 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
567 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
569 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
570 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
571 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
572 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
573 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
574 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
576 #define NIG_REG_VXLAN_CTRL 0x50105cUL
577 #define PBF_REG_VXLAN_PORT 0xd80518UL
578 #define PBF_REG_NGE_PORT 0xd8051cUL
579 #define PRS_REG_NGE_PORT 0x1f086cUL
580 #define NIG_REG_NGE_PORT 0x508b38UL
582 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
583 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
584 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
585 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
586 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
588 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
589 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
590 #define NIG_REG_NGE_COMP_VER 0x508b30UL
591 #define PBF_REG_NGE_COMP_VER 0xd80524UL
592 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
594 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
595 #define QM_REG_WFQVPWEIGHT 0x2fa000UL
597 #define PGLCS_REG_DBG_SELECT_K2 \
599 #define PGLCS_REG_DBG_DWORD_ENABLE_K2 \
601 #define PGLCS_REG_DBG_SHIFT_K2 \
603 #define PGLCS_REG_DBG_FORCE_VALID_K2 \
605 #define PGLCS_REG_DBG_FORCE_FRAME_K2 \
607 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \
609 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \
611 #define MISC_REG_RESET_PL_PDA_VAUX \
613 #define MISCS_REG_RESET_PL_UA \
615 #define MISCS_REG_RESET_PL_HV \
617 #define MISCS_REG_RESET_PL_HV_2_K2 \
619 #define DMAE_REG_DBG_SELECT \
621 #define DMAE_REG_DBG_DWORD_ENABLE \
623 #define DMAE_REG_DBG_SHIFT \
625 #define DMAE_REG_DBG_FORCE_VALID \
627 #define DMAE_REG_DBG_FORCE_FRAME \
629 #define NCSI_REG_DBG_SELECT \
631 #define NCSI_REG_DBG_DWORD_ENABLE \
633 #define NCSI_REG_DBG_SHIFT \
635 #define NCSI_REG_DBG_FORCE_VALID \
637 #define NCSI_REG_DBG_FORCE_FRAME \
639 #define GRC_REG_DBG_SELECT \
641 #define GRC_REG_DBG_DWORD_ENABLE \
643 #define GRC_REG_DBG_SHIFT \
645 #define GRC_REG_DBG_FORCE_VALID \
647 #define GRC_REG_DBG_FORCE_FRAME \
649 #define UMAC_REG_DBG_SELECT_K2 \
651 #define UMAC_REG_DBG_DWORD_ENABLE_K2 \
653 #define UMAC_REG_DBG_SHIFT_K2 \
655 #define UMAC_REG_DBG_FORCE_VALID_K2 \
657 #define UMAC_REG_DBG_FORCE_FRAME_K2 \
659 #define MCP2_REG_DBG_SELECT \
661 #define MCP2_REG_DBG_DWORD_ENABLE \
663 #define MCP2_REG_DBG_SHIFT \
665 #define MCP2_REG_DBG_FORCE_VALID \
667 #define MCP2_REG_DBG_FORCE_FRAME \
669 #define PCIE_REG_DBG_SELECT \
671 #define PCIE_REG_DBG_DWORD_ENABLE \
673 #define PCIE_REG_DBG_SHIFT \
675 #define PCIE_REG_DBG_FORCE_VALID \
677 #define PCIE_REG_DBG_FORCE_FRAME \
679 #define DORQ_REG_DBG_SELECT \
681 #define DORQ_REG_DBG_DWORD_ENABLE \
683 #define DORQ_REG_DBG_SHIFT \
685 #define DORQ_REG_DBG_FORCE_VALID \
687 #define DORQ_REG_DBG_FORCE_FRAME \
689 #define IGU_REG_DBG_SELECT \
691 #define IGU_REG_DBG_DWORD_ENABLE \
693 #define IGU_REG_DBG_SHIFT \
695 #define IGU_REG_DBG_FORCE_VALID \
697 #define IGU_REG_DBG_FORCE_FRAME \
699 #define CAU_REG_DBG_SELECT \
701 #define CAU_REG_DBG_DWORD_ENABLE \
703 #define CAU_REG_DBG_SHIFT \
705 #define CAU_REG_DBG_FORCE_VALID \
707 #define CAU_REG_DBG_FORCE_FRAME \
709 #define PRS_REG_DBG_SELECT \
711 #define PRS_REG_DBG_DWORD_ENABLE \
713 #define PRS_REG_DBG_SHIFT \
715 #define PRS_REG_DBG_FORCE_VALID \
717 #define PRS_REG_DBG_FORCE_FRAME \
719 #define CNIG_REG_DBG_SELECT_K2 \
721 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \
723 #define CNIG_REG_DBG_SHIFT_K2 \
725 #define CNIG_REG_DBG_FORCE_VALID_K2 \
727 #define CNIG_REG_DBG_FORCE_FRAME_K2 \
729 #define PRM_REG_DBG_SELECT \
731 #define PRM_REG_DBG_DWORD_ENABLE \
733 #define PRM_REG_DBG_SHIFT \
735 #define PRM_REG_DBG_FORCE_VALID \
737 #define PRM_REG_DBG_FORCE_FRAME \
739 #define SRC_REG_DBG_SELECT \
741 #define SRC_REG_DBG_DWORD_ENABLE \
743 #define SRC_REG_DBG_SHIFT \
745 #define SRC_REG_DBG_FORCE_VALID \
747 #define SRC_REG_DBG_FORCE_FRAME \
749 #define RSS_REG_DBG_SELECT \
751 #define RSS_REG_DBG_DWORD_ENABLE \
753 #define RSS_REG_DBG_SHIFT \
755 #define RSS_REG_DBG_FORCE_VALID \
757 #define RSS_REG_DBG_FORCE_FRAME \
759 #define RPB_REG_DBG_SELECT \
761 #define RPB_REG_DBG_DWORD_ENABLE \
763 #define RPB_REG_DBG_SHIFT \
765 #define RPB_REG_DBG_FORCE_VALID \
767 #define RPB_REG_DBG_FORCE_FRAME \
769 #define PSWRQ2_REG_DBG_SELECT \
771 #define PSWRQ2_REG_DBG_DWORD_ENABLE \
773 #define PSWRQ2_REG_DBG_SHIFT \
775 #define PSWRQ2_REG_DBG_FORCE_VALID \
777 #define PSWRQ2_REG_DBG_FORCE_FRAME \
779 #define PSWRQ_REG_DBG_SELECT \
781 #define PSWRQ_REG_DBG_DWORD_ENABLE \
783 #define PSWRQ_REG_DBG_SHIFT \
785 #define PSWRQ_REG_DBG_FORCE_VALID \
787 #define PSWRQ_REG_DBG_FORCE_FRAME \
789 #define PSWWR_REG_DBG_SELECT \
791 #define PSWWR_REG_DBG_DWORD_ENABLE \
793 #define PSWWR_REG_DBG_SHIFT \
795 #define PSWWR_REG_DBG_FORCE_VALID \
797 #define PSWWR_REG_DBG_FORCE_FRAME \
799 #define PSWRD_REG_DBG_SELECT \
801 #define PSWRD_REG_DBG_DWORD_ENABLE \
803 #define PSWRD_REG_DBG_SHIFT \
805 #define PSWRD_REG_DBG_FORCE_VALID \
807 #define PSWRD_REG_DBG_FORCE_FRAME \
809 #define PSWRD2_REG_DBG_SELECT \
811 #define PSWRD2_REG_DBG_DWORD_ENABLE \
813 #define PSWRD2_REG_DBG_SHIFT \
815 #define PSWRD2_REG_DBG_FORCE_VALID \
817 #define PSWRD2_REG_DBG_FORCE_FRAME \
819 #define PSWHST2_REG_DBG_SELECT \
821 #define PSWHST2_REG_DBG_DWORD_ENABLE \
823 #define PSWHST2_REG_DBG_SHIFT \
825 #define PSWHST2_REG_DBG_FORCE_VALID \
827 #define PSWHST2_REG_DBG_FORCE_FRAME \
829 #define PSWHST_REG_DBG_SELECT \
831 #define PSWHST_REG_DBG_DWORD_ENABLE \
833 #define PSWHST_REG_DBG_SHIFT \
835 #define PSWHST_REG_DBG_FORCE_VALID \
837 #define PSWHST_REG_DBG_FORCE_FRAME \
839 #define PGLUE_B_REG_DBG_SELECT \
841 #define PGLUE_B_REG_DBG_DWORD_ENABLE \
843 #define PGLUE_B_REG_DBG_SHIFT \
845 #define PGLUE_B_REG_DBG_FORCE_VALID \
847 #define PGLUE_B_REG_DBG_FORCE_FRAME \
849 #define TM_REG_DBG_SELECT \
851 #define TM_REG_DBG_DWORD_ENABLE \
853 #define TM_REG_DBG_SHIFT \
855 #define TM_REG_DBG_FORCE_VALID \
857 #define TM_REG_DBG_FORCE_FRAME \
859 #define TCFC_REG_DBG_SELECT \
861 #define TCFC_REG_DBG_DWORD_ENABLE \
863 #define TCFC_REG_DBG_SHIFT \
865 #define TCFC_REG_DBG_FORCE_VALID \
867 #define TCFC_REG_DBG_FORCE_FRAME \
869 #define CCFC_REG_DBG_SELECT \
871 #define CCFC_REG_DBG_DWORD_ENABLE \
873 #define CCFC_REG_DBG_SHIFT \
875 #define CCFC_REG_DBG_FORCE_VALID \
877 #define CCFC_REG_DBG_FORCE_FRAME \
879 #define QM_REG_DBG_SELECT \
881 #define QM_REG_DBG_DWORD_ENABLE \
883 #define QM_REG_DBG_SHIFT \
885 #define QM_REG_DBG_FORCE_VALID \
887 #define QM_REG_DBG_FORCE_FRAME \
889 #define RDIF_REG_DBG_SELECT \
891 #define RDIF_REG_DBG_DWORD_ENABLE \
893 #define RDIF_REG_DBG_SHIFT \
895 #define RDIF_REG_DBG_FORCE_VALID \
897 #define RDIF_REG_DBG_FORCE_FRAME \
899 #define TDIF_REG_DBG_SELECT \
901 #define TDIF_REG_DBG_DWORD_ENABLE \
903 #define TDIF_REG_DBG_SHIFT \
905 #define TDIF_REG_DBG_FORCE_VALID \
907 #define TDIF_REG_DBG_FORCE_FRAME \
909 #define BRB_REG_DBG_SELECT \
911 #define BRB_REG_DBG_DWORD_ENABLE \
913 #define BRB_REG_DBG_SHIFT \
915 #define BRB_REG_DBG_FORCE_VALID \
917 #define BRB_REG_DBG_FORCE_FRAME \
919 #define XYLD_REG_DBG_SELECT \
921 #define XYLD_REG_DBG_DWORD_ENABLE \
923 #define XYLD_REG_DBG_SHIFT \
925 #define XYLD_REG_DBG_FORCE_VALID \
927 #define XYLD_REG_DBG_FORCE_FRAME \
929 #define YULD_REG_DBG_SELECT_BB_K2 \
931 #define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \
933 #define YULD_REG_DBG_SHIFT_BB_K2 \
935 #define YULD_REG_DBG_FORCE_VALID_BB_K2 \
937 #define YULD_REG_DBG_FORCE_FRAME_BB_K2 \
939 #define TMLD_REG_DBG_SELECT \
941 #define TMLD_REG_DBG_DWORD_ENABLE \
943 #define TMLD_REG_DBG_SHIFT \
945 #define TMLD_REG_DBG_FORCE_VALID \
947 #define TMLD_REG_DBG_FORCE_FRAME \
949 #define MULD_REG_DBG_SELECT \
951 #define MULD_REG_DBG_DWORD_ENABLE \
953 #define MULD_REG_DBG_SHIFT \
955 #define MULD_REG_DBG_FORCE_VALID \
957 #define MULD_REG_DBG_FORCE_FRAME \
959 #define NIG_REG_DBG_SELECT \
961 #define NIG_REG_DBG_DWORD_ENABLE \
963 #define NIG_REG_DBG_SHIFT \
965 #define NIG_REG_DBG_FORCE_VALID \
967 #define NIG_REG_DBG_FORCE_FRAME \
969 #define BMB_REG_DBG_SELECT \
971 #define BMB_REG_DBG_DWORD_ENABLE \
973 #define BMB_REG_DBG_SHIFT \
975 #define BMB_REG_DBG_FORCE_VALID \
977 #define BMB_REG_DBG_FORCE_FRAME \
979 #define PTU_REG_DBG_SELECT \
981 #define PTU_REG_DBG_DWORD_ENABLE \
983 #define PTU_REG_DBG_SHIFT \
985 #define PTU_REG_DBG_FORCE_VALID \
987 #define PTU_REG_DBG_FORCE_FRAME \
989 #define CDU_REG_DBG_SELECT \
991 #define CDU_REG_DBG_DWORD_ENABLE \
993 #define CDU_REG_DBG_SHIFT \
995 #define CDU_REG_DBG_FORCE_VALID \
997 #define CDU_REG_DBG_FORCE_FRAME \
999 #define WOL_REG_DBG_SELECT_K2 \
1001 #define WOL_REG_DBG_DWORD_ENABLE_K2 \
1003 #define WOL_REG_DBG_SHIFT_K2 \
1005 #define WOL_REG_DBG_FORCE_VALID_K2 \
1007 #define WOL_REG_DBG_FORCE_FRAME_K2 \
1009 #define BMBN_REG_DBG_SELECT_K2 \
1011 #define BMBN_REG_DBG_DWORD_ENABLE_K2 \
1013 #define BMBN_REG_DBG_SHIFT_K2 \
1015 #define BMBN_REG_DBG_FORCE_VALID_K2 \
1017 #define BMBN_REG_DBG_FORCE_FRAME_K2 \
1019 #define NWM_REG_DBG_SELECT_K2 \
1021 #define NWM_REG_DBG_DWORD_ENABLE_K2 \
1023 #define NWM_REG_DBG_SHIFT_K2 \
1025 #define NWM_REG_DBG_FORCE_VALID_K2 \
1027 #define NWM_REG_DBG_FORCE_FRAME_K2\
1029 #define PBF_REG_DBG_SELECT \
1031 #define PBF_REG_DBG_DWORD_ENABLE \
1033 #define PBF_REG_DBG_SHIFT \
1035 #define PBF_REG_DBG_FORCE_VALID \
1037 #define PBF_REG_DBG_FORCE_FRAME \
1039 #define PBF_PB1_REG_DBG_SELECT \
1041 #define PBF_PB1_REG_DBG_DWORD_ENABLE \
1043 #define PBF_PB1_REG_DBG_SHIFT \
1045 #define PBF_PB1_REG_DBG_FORCE_VALID \
1047 #define PBF_PB1_REG_DBG_FORCE_FRAME \
1049 #define PBF_PB2_REG_DBG_SELECT \
1051 #define PBF_PB2_REG_DBG_DWORD_ENABLE \
1053 #define PBF_PB2_REG_DBG_SHIFT \
1055 #define PBF_PB2_REG_DBG_FORCE_VALID \
1057 #define PBF_PB2_REG_DBG_FORCE_FRAME \
1059 #define BTB_REG_DBG_SELECT \
1061 #define BTB_REG_DBG_DWORD_ENABLE \
1063 #define BTB_REG_DBG_SHIFT \
1065 #define BTB_REG_DBG_FORCE_VALID \
1067 #define BTB_REG_DBG_FORCE_FRAME \
1069 #define XSDM_REG_DBG_SELECT \
1071 #define XSDM_REG_DBG_DWORD_ENABLE \
1073 #define XSDM_REG_DBG_SHIFT \
1075 #define XSDM_REG_DBG_FORCE_VALID \
1077 #define XSDM_REG_DBG_FORCE_FRAME \
1079 #define YSDM_REG_DBG_SELECT \
1081 #define YSDM_REG_DBG_DWORD_ENABLE \
1083 #define YSDM_REG_DBG_SHIFT \
1085 #define YSDM_REG_DBG_FORCE_VALID \
1087 #define YSDM_REG_DBG_FORCE_FRAME \
1089 #define PSDM_REG_DBG_SELECT \
1091 #define PSDM_REG_DBG_DWORD_ENABLE \
1093 #define PSDM_REG_DBG_SHIFT \
1095 #define PSDM_REG_DBG_FORCE_VALID \
1097 #define PSDM_REG_DBG_FORCE_FRAME \
1099 #define TSDM_REG_DBG_SELECT \
1101 #define TSDM_REG_DBG_DWORD_ENABLE \
1103 #define TSDM_REG_DBG_SHIFT \
1105 #define TSDM_REG_DBG_FORCE_VALID \
1107 #define TSDM_REG_DBG_FORCE_FRAME \
1109 #define MSDM_REG_DBG_SELECT \
1111 #define MSDM_REG_DBG_DWORD_ENABLE \
1113 #define MSDM_REG_DBG_SHIFT \
1115 #define MSDM_REG_DBG_FORCE_VALID \
1117 #define MSDM_REG_DBG_FORCE_FRAME \
1119 #define USDM_REG_DBG_SELECT \
1121 #define USDM_REG_DBG_DWORD_ENABLE \
1123 #define USDM_REG_DBG_SHIFT \
1125 #define USDM_REG_DBG_FORCE_VALID \
1127 #define USDM_REG_DBG_FORCE_FRAME \
1129 #define XCM_REG_DBG_SELECT \
1131 #define XCM_REG_DBG_DWORD_ENABLE \
1133 #define XCM_REG_DBG_SHIFT \
1135 #define XCM_REG_DBG_FORCE_VALID \
1137 #define XCM_REG_DBG_FORCE_FRAME \
1139 #define YCM_REG_DBG_SELECT \
1141 #define YCM_REG_DBG_DWORD_ENABLE \
1143 #define YCM_REG_DBG_SHIFT \
1145 #define YCM_REG_DBG_FORCE_VALID \
1147 #define YCM_REG_DBG_FORCE_FRAME \
1149 #define PCM_REG_DBG_SELECT \
1151 #define PCM_REG_DBG_DWORD_ENABLE \
1153 #define PCM_REG_DBG_SHIFT \
1155 #define PCM_REG_DBG_FORCE_VALID \
1157 #define PCM_REG_DBG_FORCE_FRAME \
1159 #define TCM_REG_DBG_SELECT \
1161 #define TCM_REG_DBG_DWORD_ENABLE \
1163 #define TCM_REG_DBG_SHIFT \
1165 #define TCM_REG_DBG_FORCE_VALID \
1167 #define TCM_REG_DBG_FORCE_FRAME \
1169 #define MCM_REG_DBG_SELECT \
1171 #define MCM_REG_DBG_DWORD_ENABLE \
1173 #define MCM_REG_DBG_SHIFT \
1175 #define MCM_REG_DBG_FORCE_VALID \
1177 #define MCM_REG_DBG_FORCE_FRAME \
1179 #define UCM_REG_DBG_SELECT \
1181 #define UCM_REG_DBG_DWORD_ENABLE \
1183 #define UCM_REG_DBG_SHIFT \
1185 #define UCM_REG_DBG_FORCE_VALID \
1187 #define UCM_REG_DBG_FORCE_FRAME \
1189 #define XSEM_REG_DBG_SELECT \
1191 #define XSEM_REG_DBG_DWORD_ENABLE \
1193 #define XSEM_REG_DBG_SHIFT \
1195 #define XSEM_REG_DBG_FORCE_VALID \
1197 #define XSEM_REG_DBG_FORCE_FRAME \
1199 #define YSEM_REG_DBG_SELECT \
1201 #define YSEM_REG_DBG_DWORD_ENABLE \
1203 #define YSEM_REG_DBG_SHIFT \
1205 #define YSEM_REG_DBG_FORCE_VALID \
1207 #define YSEM_REG_DBG_FORCE_FRAME \
1209 #define PSEM_REG_DBG_SELECT \
1211 #define PSEM_REG_DBG_DWORD_ENABLE \
1213 #define PSEM_REG_DBG_SHIFT \
1215 #define PSEM_REG_DBG_FORCE_VALID \
1217 #define PSEM_REG_DBG_FORCE_FRAME \
1219 #define TSEM_REG_DBG_SELECT \
1221 #define TSEM_REG_DBG_DWORD_ENABLE \
1223 #define TSEM_REG_DBG_SHIFT \
1225 #define TSEM_REG_DBG_FORCE_VALID \
1227 #define TSEM_REG_DBG_FORCE_FRAME \
1229 #define MSEM_REG_DBG_SELECT \
1231 #define MSEM_REG_DBG_DWORD_ENABLE \
1233 #define MSEM_REG_DBG_SHIFT \
1235 #define MSEM_REG_DBG_FORCE_VALID \
1237 #define MSEM_REG_DBG_FORCE_FRAME \
1239 #define USEM_REG_DBG_SELECT \
1241 #define USEM_REG_DBG_DWORD_ENABLE \
1243 #define USEM_REG_DBG_SHIFT \
1245 #define USEM_REG_DBG_FORCE_VALID \
1247 #define USEM_REG_DBG_FORCE_FRAME \
1249 #define NWS_REG_DBG_SELECT_K2 \
1251 #define NWS_REG_DBG_DWORD_ENABLE_K2 \
1253 #define NWS_REG_DBG_SHIFT_K2 \
1255 #define NWS_REG_DBG_FORCE_VALID_K2 \
1257 #define NWS_REG_DBG_FORCE_FRAME_K2 \
1259 #define MS_REG_DBG_SELECT_K2 \
1261 #define MS_REG_DBG_DWORD_ENABLE_K2 \
1263 #define MS_REG_DBG_SHIFT_K2 \
1265 #define MS_REG_DBG_FORCE_VALID_K2 \
1267 #define MS_REG_DBG_FORCE_FRAME_K2 \
1269 #define PCIE_REG_DBG_COMMON_SELECT_K2 \
1271 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2 \
1273 #define PCIE_REG_DBG_COMMON_SHIFT_K2 \
1275 #define PCIE_REG_DBG_COMMON_FORCE_VALID_K2 \
1277 #define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2 \
1279 #define MISC_REG_RESET_PL_UA \
1281 #define MISC_REG_RESET_PL_HV \
1283 #define XCM_REG_CTX_RBC_ACCS \
1285 #define XCM_REG_AGG_CON_CTX \
1287 #define XCM_REG_SM_CON_CTX \
1289 #define YCM_REG_CTX_RBC_ACCS \
1291 #define YCM_REG_AGG_CON_CTX \
1293 #define YCM_REG_AGG_TASK_CTX \
1295 #define YCM_REG_SM_CON_CTX \
1297 #define YCM_REG_SM_TASK_CTX \
1299 #define PCM_REG_CTX_RBC_ACCS \
1301 #define PCM_REG_SM_CON_CTX \
1303 #define TCM_REG_CTX_RBC_ACCS \
1305 #define TCM_REG_AGG_CON_CTX \
1307 #define TCM_REG_AGG_TASK_CTX \
1309 #define TCM_REG_SM_CON_CTX \
1311 #define TCM_REG_SM_TASK_CTX \
1313 #define MCM_REG_CTX_RBC_ACCS \
1315 #define MCM_REG_AGG_CON_CTX \
1317 #define MCM_REG_AGG_TASK_CTX \
1319 #define MCM_REG_SM_CON_CTX \
1321 #define MCM_REG_SM_TASK_CTX \
1323 #define UCM_REG_CTX_RBC_ACCS \
1325 #define UCM_REG_AGG_CON_CTX \
1327 #define UCM_REG_AGG_TASK_CTX \
1329 #define UCM_REG_SM_CON_CTX \
1331 #define UCM_REG_SM_TASK_CTX \
1333 #define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1335 #define XSEM_REG_SYNC_DBG_EMPTY \
1337 #define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1339 #define XSEM_REG_SLOW_DBG_MODE_BB_K2 \
1341 #define XSEM_REG_DBG_FRAME_MODE_BB_K2 \
1343 #define XSEM_REG_DBG_MODE1_CFG_BB_K2 \
1345 #define XSEM_REG_FAST_MEMORY \
1347 #define YSEM_REG_SYNC_DBG_EMPTY \
1349 #define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1351 #define YSEM_REG_SLOW_DBG_MODE_BB_K2 \
1353 #define YSEM_REG_DBG_FRAME_MODE_BB_K2 \
1355 #define YSEM_REG_DBG_MODE1_CFG_BB_K2 \
1357 #define YSEM_REG_FAST_MEMORY \
1359 #define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1361 #define PSEM_REG_SYNC_DBG_EMPTY \
1363 #define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1365 #define PSEM_REG_SLOW_DBG_MODE_BB_K2 \
1367 #define PSEM_REG_DBG_FRAME_MODE_BB_K2 \
1369 #define PSEM_REG_DBG_MODE1_CFG_BB_K2 \
1371 #define PSEM_REG_FAST_MEMORY \
1373 #define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1375 #define TSEM_REG_SYNC_DBG_EMPTY \
1377 #define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1379 #define TSEM_REG_SLOW_DBG_MODE_BB_K2 \
1381 #define TSEM_REG_DBG_FRAME_MODE_BB_K2 \
1383 #define TSEM_REG_DBG_MODE1_CFG_BB_K2 \
1385 #define TSEM_REG_FAST_MEMORY \
1387 #define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1389 #define MSEM_REG_SYNC_DBG_EMPTY \
1391 #define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1393 #define MSEM_REG_SLOW_DBG_MODE_BB_K2 \
1395 #define MSEM_REG_DBG_FRAME_MODE_BB_K2 \
1397 #define MSEM_REG_DBG_MODE1_CFG_BB_K2 \
1399 #define MSEM_REG_FAST_MEMORY \
1401 #define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1403 #define USEM_REG_SYNC_DBG_EMPTY \
1405 #define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1407 #define USEM_REG_SLOW_DBG_MODE_BB_K2 \
1409 #define USEM_REG_DBG_FRAME_MODE_BB_K2 \
1411 #define USEM_REG_DBG_MODE1_CFG_BB_K2 \
1413 #define USEM_REG_FAST_MEMORY \
1415 #define SEM_FAST_REG_INT_RAM \
1417 #define SEM_FAST_REG_INT_RAM_SIZE \
1419 #define GRC_REG_TRACE_FIFO_VALID_DATA \
1421 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1423 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1425 #define IGU_REG_ERROR_HANDLING_MEMORY \
1427 #define MCP_REG_CPU_MODE \
1429 #define MCP_REG_CPU_MODE_SOFT_HALT \
1431 #define BRB_REG_BIG_RAM_ADDRESS \
1433 #define BRB_REG_BIG_RAM_DATA \
1435 #define SEM_FAST_REG_STALL_0_BB_K2 \
1437 #define SEM_FAST_REG_STALLED \
1439 #define BTB_REG_BIG_RAM_ADDRESS \
1441 #define BTB_REG_BIG_RAM_DATA \
1443 #define BMB_REG_BIG_RAM_ADDRESS \
1445 #define BMB_REG_BIG_RAM_DATA \
1447 #define SEM_FAST_REG_STORM_REG_FILE \
1449 #define RSS_REG_RSS_RAM_ADDR \
1451 #define MISCS_REG_BLOCK_256B_EN \
1453 #define MCP_REG_SCRATCH_SIZE \
1455 #define MCP_REG_CPU_REG_FILE \
1457 #define MCP_REG_CPU_REG_FILE_SIZE \
1459 #define DBG_REG_DEBUG_TARGET \
1461 #define DBG_REG_FULL_MODE \
1463 #define DBG_REG_CALENDAR_OUT_DATA \
1465 #define GRC_REG_TRACE_FIFO \
1467 #define IGU_REG_ERROR_HANDLING_DATA_VALID \
1469 #define DBG_REG_DBG_BLOCK_ON \
1471 #define DBG_REG_FRAMING_MODE \
1473 #define SEM_FAST_REG_VFC_DATA_WR \
1475 #define SEM_FAST_REG_VFC_ADDR \
1477 #define SEM_FAST_REG_VFC_DATA_RD \
1479 #define RSS_REG_RSS_RAM_DATA \
1481 #define RSS_REG_RSS_RAM_DATA_SIZE \
1483 #define MISC_REG_BLOCK_256B_EN \
1485 #define NWS_REG_NWS_CMU_K2 \
1487 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \
1489 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \
1491 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \
1493 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \
1495 #define MS_REG_MS_CMU_K2 \
1497 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \
1499 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \
1501 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \
1503 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \
1505 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \
1507 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \
1509 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \
1511 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \
1513 #define PHY_PCIE_REG_PHY0_K2 \
1515 #define PHY_PCIE_REG_PHY1_K2 \
1517 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1518 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1519 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1520 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1521 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1522 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1523 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
1524 #define NIG_REG_RX_PTP_EN 0x501900UL
1525 #define NIG_REG_TX_PTP_EN 0x501904UL
1526 #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL
1527 #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL
1528 #define NIG_REG_PTP_SW_TXTSEN 0x501910UL
1529 #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL
1530 #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL
1531 #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL
1532 #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL
1533 #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL
1534 #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL
1535 #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL
1536 #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL
1537 #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL
1538 #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL
1539 #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL
1540 #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL
1541 #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL
1542 #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL
1543 #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL
1544 #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL
1545 #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL
1546 #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL
1547 #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL
1548 #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL
1549 #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL
1550 #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL
1551 #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL
1552 #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL
1553 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL
1554 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL
1555 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL
1556 #define PSWRQ2_REG_WR_MBS0 0x240400UL
1558 #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL
1559 #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL
1560 #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL
1561 #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL
1562 #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL
1563 #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL
1564 #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
1566 #define PRS_REG_SEARCH_GFT 0x1f11bcUL
1567 #define PRS_REG_CM_HDR_GFT 0x1f11c8UL
1568 #define PRS_REG_GFT_CAM 0x1f1100UL
1569 #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
1570 #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
1571 #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
1572 #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL