1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
30 #define CDU_REG_SEGMENT0_PARAMS \
32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
34 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
42 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
44 #define CDU_REG_SEGMENT1_PARAMS \
46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
48 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
56 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
59 #define XSDM_REG_OPERATION_GEN \
61 #define NIG_REG_RX_BRB_OUT_EN \
63 #define NIG_REG_STORM_OUT_EN \
65 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
67 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
69 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
71 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
73 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
75 #define BAR0_MAP_REG_MSDM_RAM \
77 #define BAR0_MAP_REG_USDM_RAM \
79 #define BAR0_MAP_REG_PSDM_RAM \
81 #define BAR0_MAP_REG_TSDM_RAM \
83 #define BAR0_MAP_REG_XSDM_RAM \
85 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
87 #define PRS_REG_SEARCH_TCP \
89 #define PRS_REG_SEARCH_UDP \
91 #define PRS_REG_SEARCH_FCOE \
93 #define PRS_REG_SEARCH_ROCE \
95 #define PRS_REG_SEARCH_OPENFLOW \
97 #define TM_REG_PF_ENABLE_CONN \
99 #define TM_REG_PF_ENABLE_TASK \
101 #define TM_REG_PF_SCAN_ACTIVE_CONN \
103 #define TM_REG_PF_SCAN_ACTIVE_TASK \
105 #define IGU_REG_LEADING_EDGE_LATCH \
107 #define IGU_REG_TRAILING_EDGE_LATCH \
109 #define QM_REG_USG_CNT_PF_TX \
111 #define QM_REG_USG_CNT_PF_OTHER \
113 #define DORQ_REG_PF_DB_ENABLE \
115 #define DORQ_REG_VF_USAGE_CNT \
117 #define QM_REG_PF_EN \
119 #define TCFC_REG_WEAK_ENABLE_VF \
121 #define TCFC_REG_STRONG_ENABLE_PF \
123 #define TCFC_REG_STRONG_ENABLE_VF \
125 #define CCFC_REG_WEAK_ENABLE_VF \
127 #define CCFC_REG_STRONG_ENABLE_PF \
129 #define PGLUE_B_REG_PGL_ADDR_88_F0 \
131 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \
133 #define PGLUE_B_REG_PGL_ADDR_90_F0 \
135 #define PGLUE_B_REG_PGL_ADDR_94_F0 \
137 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
139 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
141 #define MISC_REG_GEN_PURP_CR0 \
143 #define MCP_REG_SCRATCH \
145 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
147 #define MISCS_REG_CHIP_NUM \
149 #define MISCS_REG_CHIP_REV \
151 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
153 #define MISCS_REG_CHIP_TEST_REG \
155 #define MISCS_REG_CHIP_METAL \
157 #define MISCS_REG_FUNCTION_HIDE \
159 #define BRB_REG_HEADER_SIZE \
161 #define BTB_REG_HEADER_SIZE \
163 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
165 #define CCFC_REG_ACTIVITY_COUNTER \
167 #define CCFC_REG_STRONG_ENABLE_VF \
169 #define CDU_REG_CID_ADDR_PARAMS \
171 #define DBG_REG_CLIENT_ENABLE \
173 #define DMAE_REG_INIT \
175 #define DORQ_REG_IFEN \
177 #define DORQ_REG_DB_DROP_REASON \
179 #define DORQ_REG_DB_DROP_DETAILS \
181 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
183 #define GRC_REG_TIMEOUT_EN \
185 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
187 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
189 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
191 #define IGU_REG_BLOCK_CONFIGURATION \
193 #define MCM_REG_INIT \
195 #define MCP2_REG_DBG_DWORD_ENABLE \
197 #define MISC_REG_PORT_MODE \
199 #define MISCS_REG_CLK_100G_MODE \
201 #define MSDM_REG_ENABLE_IN1 \
203 #define MSEM_REG_ENABLE_IN \
205 #define NIG_REG_CM_HDR \
207 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
209 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
211 #define NIG_REG_LLH_FUNC_FILTER_VALUE \
213 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
215 #define NIG_REG_LLH_FUNC_FILTER_EN \
217 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
219 #define NIG_REG_LLH_FUNC_FILTER_MODE \
221 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
223 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
225 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
227 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
229 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
231 #define NCSI_REG_CONFIG \
233 #define PBF_REG_INIT \
235 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
237 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
239 #define PTU_REG_ATC_INIT_ARRAY \
241 #define PCM_REG_INIT \
243 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
245 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
247 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
249 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
251 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
253 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
255 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
257 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
259 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
261 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
263 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
265 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
267 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
269 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
271 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
273 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
275 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
277 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
279 #define PRM_REG_DISABLE_PRM \
281 #define PRS_REG_SOFT_RST \
283 #define PRS_REG_MSG_INFO \
285 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
287 #define PRS_REG_USE_LIGHT_L2 \
289 #define PSDM_REG_ENABLE_IN1 \
291 #define PSEM_REG_ENABLE_IN \
293 #define PSWRQ_REG_DBG_SELECT \
295 #define PSWRQ2_REG_CDUT_P_SIZE \
297 #define PSWRQ2_REG_ILT_MEMORY \
299 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
301 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
303 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
305 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
307 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
309 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
311 #define PSWRD_REG_DBG_SELECT \
313 #define PSWRD2_REG_CONF11 \
315 #define PSWWR_REG_USDM_FULL_TH \
317 #define PSWWR2_REG_CDU_FULL_TH2 \
319 #define QM_REG_MAXPQSIZE_0 \
321 #define RSS_REG_RSS_INIT_EN \
323 #define RDIF_REG_STOP_ON_ERROR \
325 #define SRC_REG_SOFT_RST \
327 #define TCFC_REG_ACTIVITY_COUNTER \
329 #define TCM_REG_INIT \
331 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
333 #define TSDM_REG_ENABLE_IN1 \
335 #define TSEM_REG_ENABLE_IN \
337 #define TDIF_REG_STOP_ON_ERROR \
339 #define UCM_REG_INIT \
341 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
343 #define USDM_REG_ENABLE_IN1 \
345 #define USEM_REG_ENABLE_IN \
347 #define XCM_REG_INIT \
349 #define XSDM_REG_ENABLE_IN1 \
351 #define XSEM_REG_ENABLE_IN \
353 #define YCM_REG_INIT \
355 #define YSDM_REG_ENABLE_IN1 \
357 #define YSEM_REG_ENABLE_IN \
359 #define XYLD_REG_SCBD_STRICT_PRIO \
361 #define TMLD_REG_SCBD_STRICT_PRIO \
363 #define MULD_REG_SCBD_STRICT_PRIO \
365 #define YULD_REG_SCBD_STRICT_PRIO \
367 #define MISC_REG_SHARED_MEM_ADDR \
369 #define DMAE_REG_GO_C0 \
371 #define DMAE_REG_GO_C1 \
373 #define DMAE_REG_GO_C2 \
375 #define DMAE_REG_GO_C3 \
377 #define DMAE_REG_GO_C4 \
379 #define DMAE_REG_GO_C5 \
381 #define DMAE_REG_GO_C6 \
383 #define DMAE_REG_GO_C7 \
385 #define DMAE_REG_GO_C8 \
387 #define DMAE_REG_GO_C9 \
389 #define DMAE_REG_GO_C10 \
391 #define DMAE_REG_GO_C11 \
393 #define DMAE_REG_GO_C12 \
395 #define DMAE_REG_GO_C13 \
397 #define DMAE_REG_GO_C14 \
399 #define DMAE_REG_GO_C15 \
401 #define DMAE_REG_GO_C16 \
403 #define DMAE_REG_GO_C17 \
405 #define DMAE_REG_GO_C18 \
407 #define DMAE_REG_GO_C19 \
409 #define DMAE_REG_GO_C20 \
411 #define DMAE_REG_GO_C21 \
413 #define DMAE_REG_GO_C22 \
415 #define DMAE_REG_GO_C23 \
417 #define DMAE_REG_GO_C24 \
419 #define DMAE_REG_GO_C25 \
421 #define DMAE_REG_GO_C26 \
423 #define DMAE_REG_GO_C27 \
425 #define DMAE_REG_GO_C28 \
427 #define DMAE_REG_GO_C29 \
429 #define DMAE_REG_GO_C30 \
431 #define DMAE_REG_GO_C31 \
433 #define DMAE_REG_CMD_MEM \
435 #define QM_REG_MAXPQSIZETXSEL_0 \
437 #define QM_REG_SDMCMDREADY \
439 #define QM_REG_SDMCMDADDR \
441 #define QM_REG_SDMCMDDATALSB \
443 #define QM_REG_SDMCMDDATAMSB \
445 #define QM_REG_SDMCMDGO \
447 #define QM_REG_RLPFCRD \
449 #define QM_REG_RLPFINCVAL \
451 #define QM_REG_RLGLBLCRD \
453 #define QM_REG_RLGLBLINCVAL \
455 #define IGU_REG_ATTENTION_ENABLE \
457 #define IGU_REG_ATTN_MSG_ADDR_L \
459 #define IGU_REG_ATTN_MSG_ADDR_H \
461 #define MISC_REG_AEU_GENERAL_ATTN_0 \
463 #define CAU_REG_SB_ADDR_MEMORY \
465 #define CAU_REG_SB_VAR_MEMORY \
467 #define CAU_REG_PI_MEMORY \
469 #define IGU_REG_PF_CONFIGURATION \
471 #define IGU_REG_VF_CONFIGURATION \
473 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
475 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
477 #define MISC_REG_AEU_MASK_ATTN_IGU \
479 #define IGU_REG_CLEANUP_STATUS_0 \
481 #define IGU_REG_CLEANUP_STATUS_1 \
483 #define IGU_REG_CLEANUP_STATUS_2 \
485 #define IGU_REG_CLEANUP_STATUS_3 \
487 #define IGU_REG_CLEANUP_STATUS_4 \
489 #define IGU_REG_COMMAND_REG_32LSB_DATA \
491 #define IGU_REG_COMMAND_REG_CTRL \
493 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
495 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
497 #define IGU_REG_MAPPING_MEMORY \
499 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
501 #define IGU_REG_WRITE_DONE_PENDING \
503 #define MISCS_REG_GENERIC_POR_0 \
505 #define MCP_REG_NVM_CFG4 \
507 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
509 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
511 #define MCP_REG_CPU_STATE \
513 #define MCP_REG_CPU_EVENT_MASK \
515 #define PGLUE_B_REG_PF_BAR0_SIZE \
517 #define PGLUE_B_REG_PF_BAR1_SIZE \
519 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
520 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
521 #define PRS_REG_VXLAN_PORT 0x1f0738UL
522 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
523 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
525 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
526 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
527 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
528 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
529 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
530 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
532 #define NIG_REG_VXLAN_CTRL 0x50105cUL
533 #define PBF_REG_VXLAN_PORT 0xd80518UL
534 #define PBF_REG_NGE_PORT 0xd8051cUL
535 #define PRS_REG_NGE_PORT 0x1f086cUL
536 #define NIG_REG_NGE_PORT 0x508b38UL
538 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
539 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
540 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
541 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
542 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
544 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
545 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
546 #define NIG_REG_NGE_COMP_VER 0x508b30UL
547 #define PBF_REG_NGE_COMP_VER 0xd80524UL
548 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
550 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
551 #define QM_REG_WFQVPWEIGHT 0x2fa000UL
553 #define PGLCS_REG_DBG_SELECT \
555 #define PGLCS_REG_DBG_DWORD_ENABLE \
557 #define PGLCS_REG_DBG_SHIFT \
559 #define PGLCS_REG_DBG_FORCE_VALID \
561 #define PGLCS_REG_DBG_FORCE_FRAME \
563 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \
565 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \
567 #define MISC_REG_RESET_PL_PDA_VAUX \
569 #define MISCS_REG_RESET_PL_UA \
571 #define MISCS_REG_RESET_PL_HV \
573 #define MISCS_REG_RESET_PL_HV_2 \
575 #define DMAE_REG_DBG_SELECT \
577 #define DMAE_REG_DBG_DWORD_ENABLE \
579 #define DMAE_REG_DBG_SHIFT \
581 #define DMAE_REG_DBG_FORCE_VALID \
583 #define DMAE_REG_DBG_FORCE_FRAME \
585 #define NCSI_REG_DBG_SELECT \
587 #define NCSI_REG_DBG_DWORD_ENABLE \
589 #define NCSI_REG_DBG_SHIFT \
591 #define NCSI_REG_DBG_FORCE_VALID \
593 #define NCSI_REG_DBG_FORCE_FRAME \
595 #define GRC_REG_DBG_SELECT \
597 #define GRC_REG_DBG_DWORD_ENABLE \
599 #define GRC_REG_DBG_SHIFT \
601 #define GRC_REG_DBG_FORCE_VALID \
603 #define GRC_REG_DBG_FORCE_FRAME \
605 #define UMAC_REG_DBG_SELECT \
607 #define UMAC_REG_DBG_DWORD_ENABLE \
609 #define UMAC_REG_DBG_SHIFT \
611 #define UMAC_REG_DBG_FORCE_VALID \
613 #define UMAC_REG_DBG_FORCE_FRAME \
615 #define MCP2_REG_DBG_SELECT \
617 #define MCP2_REG_DBG_DWORD_ENABLE \
619 #define MCP2_REG_DBG_SHIFT \
621 #define MCP2_REG_DBG_FORCE_VALID \
623 #define MCP2_REG_DBG_FORCE_FRAME \
625 #define PCIE_REG_DBG_SELECT \
627 #define PCIE_REG_DBG_DWORD_ENABLE \
629 #define PCIE_REG_DBG_SHIFT \
631 #define PCIE_REG_DBG_FORCE_VALID \
633 #define PCIE_REG_DBG_FORCE_FRAME \
635 #define DORQ_REG_DBG_SELECT \
637 #define DORQ_REG_DBG_DWORD_ENABLE \
639 #define DORQ_REG_DBG_SHIFT \
641 #define DORQ_REG_DBG_FORCE_VALID \
643 #define DORQ_REG_DBG_FORCE_FRAME \
645 #define IGU_REG_DBG_SELECT \
647 #define IGU_REG_DBG_DWORD_ENABLE \
649 #define IGU_REG_DBG_SHIFT \
651 #define IGU_REG_DBG_FORCE_VALID \
653 #define IGU_REG_DBG_FORCE_FRAME \
655 #define CAU_REG_DBG_SELECT \
657 #define CAU_REG_DBG_DWORD_ENABLE \
659 #define CAU_REG_DBG_SHIFT \
661 #define CAU_REG_DBG_FORCE_VALID \
663 #define CAU_REG_DBG_FORCE_FRAME \
665 #define PRS_REG_DBG_SELECT \
667 #define PRS_REG_DBG_DWORD_ENABLE \
669 #define PRS_REG_DBG_SHIFT \
671 #define PRS_REG_DBG_FORCE_VALID \
673 #define PRS_REG_DBG_FORCE_FRAME \
675 #define CNIG_REG_DBG_SELECT_K2 \
677 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \
679 #define CNIG_REG_DBG_SHIFT_K2 \
681 #define CNIG_REG_DBG_FORCE_VALID_K2 \
683 #define CNIG_REG_DBG_FORCE_FRAME_K2 \
685 #define PRM_REG_DBG_SELECT \
687 #define PRM_REG_DBG_DWORD_ENABLE \
689 #define PRM_REG_DBG_SHIFT \
691 #define PRM_REG_DBG_FORCE_VALID \
693 #define PRM_REG_DBG_FORCE_FRAME \
695 #define SRC_REG_DBG_SELECT \
697 #define SRC_REG_DBG_DWORD_ENABLE \
699 #define SRC_REG_DBG_SHIFT \
701 #define SRC_REG_DBG_FORCE_VALID \
703 #define SRC_REG_DBG_FORCE_FRAME \
705 #define RSS_REG_DBG_SELECT \
707 #define RSS_REG_DBG_DWORD_ENABLE \
709 #define RSS_REG_DBG_SHIFT \
711 #define RSS_REG_DBG_FORCE_VALID \
713 #define RSS_REG_DBG_FORCE_FRAME \
715 #define RPB_REG_DBG_SELECT \
717 #define RPB_REG_DBG_DWORD_ENABLE \
719 #define RPB_REG_DBG_SHIFT \
721 #define RPB_REG_DBG_FORCE_VALID \
723 #define RPB_REG_DBG_FORCE_FRAME \
725 #define PSWRQ2_REG_DBG_SELECT \
727 #define PSWRQ2_REG_DBG_DWORD_ENABLE \
729 #define PSWRQ2_REG_DBG_SHIFT \
731 #define PSWRQ2_REG_DBG_FORCE_VALID \
733 #define PSWRQ2_REG_DBG_FORCE_FRAME \
735 #define PSWRQ_REG_DBG_SELECT \
737 #define PSWRQ_REG_DBG_DWORD_ENABLE \
739 #define PSWRQ_REG_DBG_SHIFT \
741 #define PSWRQ_REG_DBG_FORCE_VALID \
743 #define PSWRQ_REG_DBG_FORCE_FRAME \
745 #define PSWWR_REG_DBG_SELECT \
747 #define PSWWR_REG_DBG_DWORD_ENABLE \
749 #define PSWWR_REG_DBG_SHIFT \
751 #define PSWWR_REG_DBG_FORCE_VALID \
753 #define PSWWR_REG_DBG_FORCE_FRAME \
755 #define PSWRD_REG_DBG_SELECT \
757 #define PSWRD_REG_DBG_DWORD_ENABLE \
759 #define PSWRD_REG_DBG_SHIFT \
761 #define PSWRD_REG_DBG_FORCE_VALID \
763 #define PSWRD_REG_DBG_FORCE_FRAME \
765 #define PSWRD2_REG_DBG_SELECT \
767 #define PSWRD2_REG_DBG_DWORD_ENABLE \
769 #define PSWRD2_REG_DBG_SHIFT \
771 #define PSWRD2_REG_DBG_FORCE_VALID \
773 #define PSWRD2_REG_DBG_FORCE_FRAME \
775 #define PSWHST2_REG_DBG_SELECT \
777 #define PSWHST2_REG_DBG_DWORD_ENABLE \
779 #define PSWHST2_REG_DBG_SHIFT \
781 #define PSWHST2_REG_DBG_FORCE_VALID \
783 #define PSWHST2_REG_DBG_FORCE_FRAME \
785 #define PSWHST_REG_DBG_SELECT \
787 #define PSWHST_REG_DBG_DWORD_ENABLE \
789 #define PSWHST_REG_DBG_SHIFT \
791 #define PSWHST_REG_DBG_FORCE_VALID \
793 #define PSWHST_REG_DBG_FORCE_FRAME \
795 #define PGLUE_B_REG_DBG_SELECT \
797 #define PGLUE_B_REG_DBG_DWORD_ENABLE \
799 #define PGLUE_B_REG_DBG_SHIFT \
801 #define PGLUE_B_REG_DBG_FORCE_VALID \
803 #define PGLUE_B_REG_DBG_FORCE_FRAME \
805 #define TM_REG_DBG_SELECT \
807 #define TM_REG_DBG_DWORD_ENABLE \
809 #define TM_REG_DBG_SHIFT \
811 #define TM_REG_DBG_FORCE_VALID \
813 #define TM_REG_DBG_FORCE_FRAME \
815 #define TCFC_REG_DBG_SELECT \
817 #define TCFC_REG_DBG_DWORD_ENABLE \
819 #define TCFC_REG_DBG_SHIFT \
821 #define TCFC_REG_DBG_FORCE_VALID \
823 #define TCFC_REG_DBG_FORCE_FRAME \
825 #define CCFC_REG_DBG_SELECT \
827 #define CCFC_REG_DBG_DWORD_ENABLE \
829 #define CCFC_REG_DBG_SHIFT \
831 #define CCFC_REG_DBG_FORCE_VALID \
833 #define CCFC_REG_DBG_FORCE_FRAME \
835 #define QM_REG_DBG_SELECT \
837 #define QM_REG_DBG_DWORD_ENABLE \
839 #define QM_REG_DBG_SHIFT \
841 #define QM_REG_DBG_FORCE_VALID \
843 #define QM_REG_DBG_FORCE_FRAME \
845 #define RDIF_REG_DBG_SELECT \
847 #define RDIF_REG_DBG_DWORD_ENABLE \
849 #define RDIF_REG_DBG_SHIFT \
851 #define RDIF_REG_DBG_FORCE_VALID \
853 #define RDIF_REG_DBG_FORCE_FRAME \
855 #define TDIF_REG_DBG_SELECT \
857 #define TDIF_REG_DBG_DWORD_ENABLE \
859 #define TDIF_REG_DBG_SHIFT \
861 #define TDIF_REG_DBG_FORCE_VALID \
863 #define TDIF_REG_DBG_FORCE_FRAME \
865 #define BRB_REG_DBG_SELECT \
867 #define BRB_REG_DBG_DWORD_ENABLE \
869 #define BRB_REG_DBG_SHIFT \
871 #define BRB_REG_DBG_FORCE_VALID \
873 #define BRB_REG_DBG_FORCE_FRAME \
875 #define XYLD_REG_DBG_SELECT \
877 #define XYLD_REG_DBG_DWORD_ENABLE \
879 #define XYLD_REG_DBG_SHIFT \
881 #define XYLD_REG_DBG_FORCE_VALID \
883 #define XYLD_REG_DBG_FORCE_FRAME \
885 #define YULD_REG_DBG_SELECT \
887 #define YULD_REG_DBG_DWORD_ENABLE \
889 #define YULD_REG_DBG_SHIFT \
891 #define YULD_REG_DBG_FORCE_VALID \
893 #define YULD_REG_DBG_FORCE_FRAME \
895 #define TMLD_REG_DBG_SELECT \
897 #define TMLD_REG_DBG_DWORD_ENABLE \
899 #define TMLD_REG_DBG_SHIFT \
901 #define TMLD_REG_DBG_FORCE_VALID \
903 #define TMLD_REG_DBG_FORCE_FRAME \
905 #define MULD_REG_DBG_SELECT \
907 #define MULD_REG_DBG_DWORD_ENABLE \
909 #define MULD_REG_DBG_SHIFT \
911 #define MULD_REG_DBG_FORCE_VALID \
913 #define MULD_REG_DBG_FORCE_FRAME \
915 #define NIG_REG_DBG_SELECT \
917 #define NIG_REG_DBG_DWORD_ENABLE \
919 #define NIG_REG_DBG_SHIFT \
921 #define NIG_REG_DBG_FORCE_VALID \
923 #define NIG_REG_DBG_FORCE_FRAME \
925 #define BMB_REG_DBG_SELECT \
927 #define BMB_REG_DBG_DWORD_ENABLE \
929 #define BMB_REG_DBG_SHIFT \
931 #define BMB_REG_DBG_FORCE_VALID \
933 #define BMB_REG_DBG_FORCE_FRAME \
935 #define PTU_REG_DBG_SELECT \
937 #define PTU_REG_DBG_DWORD_ENABLE \
939 #define PTU_REG_DBG_SHIFT \
941 #define PTU_REG_DBG_FORCE_VALID \
943 #define PTU_REG_DBG_FORCE_FRAME \
945 #define CDU_REG_DBG_SELECT \
947 #define CDU_REG_DBG_DWORD_ENABLE \
949 #define CDU_REG_DBG_SHIFT \
951 #define CDU_REG_DBG_FORCE_VALID \
953 #define CDU_REG_DBG_FORCE_FRAME \
955 #define WOL_REG_DBG_SELECT \
957 #define WOL_REG_DBG_DWORD_ENABLE \
959 #define WOL_REG_DBG_SHIFT \
961 #define WOL_REG_DBG_FORCE_VALID \
963 #define WOL_REG_DBG_FORCE_FRAME \
965 #define BMBN_REG_DBG_SELECT \
967 #define BMBN_REG_DBG_DWORD_ENABLE \
969 #define BMBN_REG_DBG_SHIFT \
971 #define BMBN_REG_DBG_FORCE_VALID \
973 #define BMBN_REG_DBG_FORCE_FRAME \
975 #define NWM_REG_DBG_SELECT \
977 #define NWM_REG_DBG_DWORD_ENABLE \
979 #define NWM_REG_DBG_SHIFT \
981 #define NWM_REG_DBG_FORCE_VALID \
983 #define NWM_REG_DBG_FORCE_FRAME \
985 #define PBF_REG_DBG_SELECT \
987 #define PBF_REG_DBG_DWORD_ENABLE \
989 #define PBF_REG_DBG_SHIFT \
991 #define PBF_REG_DBG_FORCE_VALID \
993 #define PBF_REG_DBG_FORCE_FRAME \
995 #define PBF_PB1_REG_DBG_SELECT \
997 #define PBF_PB1_REG_DBG_DWORD_ENABLE \
999 #define PBF_PB1_REG_DBG_SHIFT \
1001 #define PBF_PB1_REG_DBG_FORCE_VALID \
1003 #define PBF_PB1_REG_DBG_FORCE_FRAME \
1005 #define PBF_PB2_REG_DBG_SELECT \
1007 #define PBF_PB2_REG_DBG_DWORD_ENABLE \
1009 #define PBF_PB2_REG_DBG_SHIFT \
1011 #define PBF_PB2_REG_DBG_FORCE_VALID \
1013 #define PBF_PB2_REG_DBG_FORCE_FRAME \
1015 #define BTB_REG_DBG_SELECT \
1017 #define BTB_REG_DBG_DWORD_ENABLE \
1019 #define BTB_REG_DBG_SHIFT \
1021 #define BTB_REG_DBG_FORCE_VALID \
1023 #define BTB_REG_DBG_FORCE_FRAME \
1025 #define XSDM_REG_DBG_SELECT \
1027 #define XSDM_REG_DBG_DWORD_ENABLE \
1029 #define XSDM_REG_DBG_SHIFT \
1031 #define XSDM_REG_DBG_FORCE_VALID \
1033 #define XSDM_REG_DBG_FORCE_FRAME \
1035 #define YSDM_REG_DBG_SELECT \
1037 #define YSDM_REG_DBG_DWORD_ENABLE \
1039 #define YSDM_REG_DBG_SHIFT \
1041 #define YSDM_REG_DBG_FORCE_VALID \
1043 #define YSDM_REG_DBG_FORCE_FRAME \
1045 #define PSDM_REG_DBG_SELECT \
1047 #define PSDM_REG_DBG_DWORD_ENABLE \
1049 #define PSDM_REG_DBG_SHIFT \
1051 #define PSDM_REG_DBG_FORCE_VALID \
1053 #define PSDM_REG_DBG_FORCE_FRAME \
1055 #define TSDM_REG_DBG_SELECT \
1057 #define TSDM_REG_DBG_DWORD_ENABLE \
1059 #define TSDM_REG_DBG_SHIFT \
1061 #define TSDM_REG_DBG_FORCE_VALID \
1063 #define TSDM_REG_DBG_FORCE_FRAME \
1065 #define MSDM_REG_DBG_SELECT \
1067 #define MSDM_REG_DBG_DWORD_ENABLE \
1069 #define MSDM_REG_DBG_SHIFT \
1071 #define MSDM_REG_DBG_FORCE_VALID \
1073 #define MSDM_REG_DBG_FORCE_FRAME \
1075 #define USDM_REG_DBG_SELECT \
1077 #define USDM_REG_DBG_DWORD_ENABLE \
1079 #define USDM_REG_DBG_SHIFT \
1081 #define USDM_REG_DBG_FORCE_VALID \
1083 #define USDM_REG_DBG_FORCE_FRAME \
1085 #define XCM_REG_DBG_SELECT \
1087 #define XCM_REG_DBG_DWORD_ENABLE \
1089 #define XCM_REG_DBG_SHIFT \
1091 #define XCM_REG_DBG_FORCE_VALID \
1093 #define XCM_REG_DBG_FORCE_FRAME \
1095 #define YCM_REG_DBG_SELECT \
1097 #define YCM_REG_DBG_DWORD_ENABLE \
1099 #define YCM_REG_DBG_SHIFT \
1101 #define YCM_REG_DBG_FORCE_VALID \
1103 #define YCM_REG_DBG_FORCE_FRAME \
1105 #define PCM_REG_DBG_SELECT \
1107 #define PCM_REG_DBG_DWORD_ENABLE \
1109 #define PCM_REG_DBG_SHIFT \
1111 #define PCM_REG_DBG_FORCE_VALID \
1113 #define PCM_REG_DBG_FORCE_FRAME \
1115 #define TCM_REG_DBG_SELECT \
1117 #define TCM_REG_DBG_DWORD_ENABLE \
1119 #define TCM_REG_DBG_SHIFT \
1121 #define TCM_REG_DBG_FORCE_VALID \
1123 #define TCM_REG_DBG_FORCE_FRAME \
1125 #define MCM_REG_DBG_SELECT \
1127 #define MCM_REG_DBG_DWORD_ENABLE \
1129 #define MCM_REG_DBG_SHIFT \
1131 #define MCM_REG_DBG_FORCE_VALID \
1133 #define MCM_REG_DBG_FORCE_FRAME \
1135 #define UCM_REG_DBG_SELECT \
1137 #define UCM_REG_DBG_DWORD_ENABLE \
1139 #define UCM_REG_DBG_SHIFT \
1141 #define UCM_REG_DBG_FORCE_VALID \
1143 #define UCM_REG_DBG_FORCE_FRAME \
1145 #define XSEM_REG_DBG_SELECT \
1147 #define XSEM_REG_DBG_DWORD_ENABLE \
1149 #define XSEM_REG_DBG_SHIFT \
1151 #define XSEM_REG_DBG_FORCE_VALID \
1153 #define XSEM_REG_DBG_FORCE_FRAME \
1155 #define YSEM_REG_DBG_SELECT \
1157 #define YSEM_REG_DBG_DWORD_ENABLE \
1159 #define YSEM_REG_DBG_SHIFT \
1161 #define YSEM_REG_DBG_FORCE_VALID \
1163 #define YSEM_REG_DBG_FORCE_FRAME \
1165 #define PSEM_REG_DBG_SELECT \
1167 #define PSEM_REG_DBG_DWORD_ENABLE \
1169 #define PSEM_REG_DBG_SHIFT \
1171 #define PSEM_REG_DBG_FORCE_VALID \
1173 #define PSEM_REG_DBG_FORCE_FRAME \
1175 #define TSEM_REG_DBG_SELECT \
1177 #define TSEM_REG_DBG_DWORD_ENABLE \
1179 #define TSEM_REG_DBG_SHIFT \
1181 #define TSEM_REG_DBG_FORCE_VALID \
1183 #define TSEM_REG_DBG_FORCE_FRAME \
1185 #define MSEM_REG_DBG_SELECT \
1187 #define MSEM_REG_DBG_DWORD_ENABLE \
1189 #define MSEM_REG_DBG_SHIFT \
1191 #define MSEM_REG_DBG_FORCE_VALID \
1193 #define MSEM_REG_DBG_FORCE_FRAME \
1195 #define USEM_REG_DBG_SELECT \
1197 #define USEM_REG_DBG_DWORD_ENABLE \
1199 #define USEM_REG_DBG_SHIFT \
1201 #define USEM_REG_DBG_FORCE_VALID \
1203 #define USEM_REG_DBG_FORCE_FRAME \
1205 #define PCIE_REG_DBG_COMMON_SELECT \
1207 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
1209 #define PCIE_REG_DBG_COMMON_SHIFT \
1211 #define PCIE_REG_DBG_COMMON_FORCE_VALID \
1213 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \
1215 #define MISC_REG_RESET_PL_UA \
1217 #define MISC_REG_RESET_PL_HV \
1219 #define XCM_REG_CTX_RBC_ACCS \
1221 #define XCM_REG_AGG_CON_CTX \
1223 #define XCM_REG_SM_CON_CTX \
1225 #define YCM_REG_CTX_RBC_ACCS \
1227 #define YCM_REG_AGG_CON_CTX \
1229 #define YCM_REG_AGG_TASK_CTX \
1231 #define YCM_REG_SM_CON_CTX \
1233 #define YCM_REG_SM_TASK_CTX \
1235 #define PCM_REG_CTX_RBC_ACCS \
1237 #define PCM_REG_SM_CON_CTX \
1239 #define TCM_REG_CTX_RBC_ACCS \
1241 #define TCM_REG_AGG_CON_CTX \
1243 #define TCM_REG_AGG_TASK_CTX \
1245 #define TCM_REG_SM_CON_CTX \
1247 #define TCM_REG_SM_TASK_CTX \
1249 #define MCM_REG_CTX_RBC_ACCS \
1251 #define MCM_REG_AGG_CON_CTX \
1253 #define MCM_REG_AGG_TASK_CTX \
1255 #define MCM_REG_SM_CON_CTX \
1257 #define MCM_REG_SM_TASK_CTX \
1259 #define UCM_REG_CTX_RBC_ACCS \
1261 #define UCM_REG_AGG_CON_CTX \
1263 #define UCM_REG_AGG_TASK_CTX \
1265 #define UCM_REG_SM_CON_CTX \
1267 #define UCM_REG_SM_TASK_CTX \
1269 #define XSEM_REG_SLOW_DBG_EMPTY \
1271 #define XSEM_REG_SYNC_DBG_EMPTY \
1273 #define XSEM_REG_SLOW_DBG_ACTIVE \
1275 #define XSEM_REG_SLOW_DBG_MODE \
1277 #define XSEM_REG_DBG_FRAME_MODE \
1279 #define XSEM_REG_DBG_MODE1_CFG \
1281 #define XSEM_REG_FAST_MEMORY \
1283 #define YSEM_REG_SYNC_DBG_EMPTY \
1285 #define YSEM_REG_SLOW_DBG_ACTIVE \
1287 #define YSEM_REG_SLOW_DBG_MODE \
1289 #define YSEM_REG_DBG_FRAME_MODE \
1291 #define YSEM_REG_DBG_MODE1_CFG \
1293 #define YSEM_REG_FAST_MEMORY \
1295 #define PSEM_REG_SLOW_DBG_EMPTY \
1297 #define PSEM_REG_SYNC_DBG_EMPTY \
1299 #define PSEM_REG_SLOW_DBG_ACTIVE \
1301 #define PSEM_REG_SLOW_DBG_MODE \
1303 #define PSEM_REG_DBG_FRAME_MODE \
1305 #define PSEM_REG_DBG_MODE1_CFG \
1307 #define PSEM_REG_FAST_MEMORY \
1309 #define TSEM_REG_SLOW_DBG_EMPTY \
1311 #define TSEM_REG_SYNC_DBG_EMPTY \
1313 #define TSEM_REG_SLOW_DBG_ACTIVE \
1315 #define TSEM_REG_SLOW_DBG_MODE \
1317 #define TSEM_REG_DBG_FRAME_MODE \
1319 #define TSEM_REG_DBG_MODE1_CFG \
1321 #define TSEM_REG_FAST_MEMORY \
1323 #define MSEM_REG_SLOW_DBG_EMPTY \
1325 #define MSEM_REG_SYNC_DBG_EMPTY \
1327 #define MSEM_REG_SLOW_DBG_ACTIVE \
1329 #define MSEM_REG_SLOW_DBG_MODE \
1331 #define MSEM_REG_DBG_FRAME_MODE \
1333 #define MSEM_REG_DBG_MODE1_CFG \
1335 #define MSEM_REG_FAST_MEMORY \
1337 #define USEM_REG_SLOW_DBG_EMPTY \
1339 #define USEM_REG_SYNC_DBG_EMPTY \
1341 #define USEM_REG_SLOW_DBG_ACTIVE \
1343 #define USEM_REG_SLOW_DBG_MODE \
1345 #define USEM_REG_DBG_FRAME_MODE \
1347 #define USEM_REG_DBG_MODE1_CFG \
1349 #define USEM_REG_FAST_MEMORY \
1351 #define SEM_FAST_REG_INT_RAM \
1353 #define SEM_FAST_REG_INT_RAM_SIZE \
1355 #define GRC_REG_TRACE_FIFO_VALID_DATA \
1357 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1359 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1361 #define IGU_REG_ERROR_HANDLING_MEMORY \
1363 #define MCP_REG_CPU_MODE \
1365 #define MCP_REG_CPU_MODE_SOFT_HALT \
1367 #define BRB_REG_BIG_RAM_ADDRESS \
1369 #define BRB_REG_BIG_RAM_DATA \
1371 #define SEM_FAST_REG_STALL_0 \
1373 #define SEM_FAST_REG_STALLED \
1375 #define BTB_REG_BIG_RAM_ADDRESS \
1377 #define BTB_REG_BIG_RAM_DATA \
1379 #define BMB_REG_BIG_RAM_ADDRESS \
1381 #define BMB_REG_BIG_RAM_DATA \
1383 #define SEM_FAST_REG_STORM_REG_FILE \
1385 #define RSS_REG_RSS_RAM_ADDR \
1387 #define MISCS_REG_BLOCK_256B_EN \
1389 #define MCP_REG_SCRATCH_SIZE \
1391 #define MCP_REG_CPU_REG_FILE \
1393 #define MCP_REG_CPU_REG_FILE_SIZE \
1395 #define DBG_REG_DEBUG_TARGET \
1397 #define DBG_REG_FULL_MODE \
1399 #define DBG_REG_CALENDAR_OUT_DATA \
1401 #define GRC_REG_TRACE_FIFO \
1403 #define IGU_REG_ERROR_HANDLING_DATA_VALID \
1405 #define DBG_REG_DBG_BLOCK_ON \
1407 #define DBG_REG_FRAMING_MODE \
1409 #define SEM_FAST_REG_VFC_DATA_WR \
1411 #define SEM_FAST_REG_VFC_ADDR \
1413 #define SEM_FAST_REG_VFC_DATA_RD \
1415 #define RSS_REG_RSS_RAM_DATA \
1417 #define MISC_REG_BLOCK_256B_EN \
1419 #define NWS_REG_NWS_CMU \
1421 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
1423 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
1425 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
1427 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
1429 #define MS_REG_MS_CMU \
1431 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
1433 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
1435 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
1437 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
1439 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
1441 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
1443 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
1445 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
1447 #define PHY_PCIE_REG_PHY0 \
1449 #define PHY_PCIE_REG_PHY1 \
1451 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1452 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1453 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1454 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1455 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1456 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1457 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL