2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
28 #include <linux/vmalloc.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
35 #include "qlcnic_hdr.h"
37 #define _QLCNIC_LINUX_MAJOR 5
38 #define _QLCNIC_LINUX_MINOR 0
39 #define _QLCNIC_LINUX_SUBVERSION 29
40 #define QLCNIC_LINUX_VERSIONID "5.0.29"
41 #define QLCNIC_DRV_IDC_VER 0x01
42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
50 /* version in image has weird encoding:
53 * 31:16 - build (little endian)
55 #define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59 #define QLCNIC_NUM_FLASH_SECTORS (64)
60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
64 #define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66 #define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68 #define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70 #define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72 #define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
75 #define QLCNIC_P3P_A0 0x50
76 #define QLCNIC_P3P_C0 0x58
78 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
80 #define FIRST_PAGE_GROUP_START 0
81 #define FIRST_PAGE_GROUP_END 0x100000
83 #define P3P_MAX_MTU (9600)
84 #define P3P_MIN_MTU (68)
85 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
87 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
88 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
89 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
90 #define QLCNIC_LRO_BUFFER_EXTRA 2048
93 #define QLCNIC_MAX_FRAGS_PER_TX 14
94 #define MAX_TSO_HEADER_DESC 2
95 #define MGMT_CMD_DESC_RESV 4
96 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
98 #define QLCNIC_MAX_TX_TIMEOUTS 2
101 * Following are the states of the Phantom. Phantom will set them and
102 * Host will read to check if the fields are correct.
104 #define PHAN_INITIALIZE_FAILED 0xffff
105 #define PHAN_INITIALIZE_COMPLETE 0xff01
107 /* Host writes the following to notify that it has done the init-handshake */
108 #define PHAN_INITIALIZE_ACK 0xf00f
109 #define PHAN_PEG_RCV_INITIALIZED 0xff01
111 #define NUM_RCV_DESC_RINGS 3
113 #define RCV_RING_NORMAL 0
114 #define RCV_RING_JUMBO 1
116 #define MIN_CMD_DESCRIPTORS 64
117 #define MIN_RCV_DESCRIPTORS 64
118 #define MIN_JUMBO_DESCRIPTORS 32
120 #define MAX_CMD_DESCRIPTORS 1024
121 #define MAX_RCV_DESCRIPTORS_1G 4096
122 #define MAX_RCV_DESCRIPTORS_10G 8192
123 #define MAX_RCV_DESCRIPTORS_VF 2048
124 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
125 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
127 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
128 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
129 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
130 #define MAX_RDS_RINGS 2
132 #define get_next_index(index, length) \
133 (((index) + 1) & ((length) - 1))
136 * Following data structures describe the descriptors that will be used.
137 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
138 * we are doing LSO (above the 1500 size packet) only.
140 struct cmd_desc_type0 {
141 u8 tcp_hdr_offset; /* For LSO only */
142 u8 ip_hdr_offset; /* For LSO only */
143 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
144 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
148 __le16 reference_handle;
150 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
151 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
152 __le16 conn_id; /* IPSec offoad only */
157 __le16 buffer_length[4];
161 u8 eth_addr[ETH_ALEN];
164 } __attribute__ ((aligned(64)));
166 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
168 __le16 reference_handle;
170 __le32 buffer_length; /* allocated buffer length (usually 2K) */
175 __le64 status_desc_data[2];
176 } __attribute__ ((aligned(16)));
178 /* UNIFIED ROMIMAGE */
179 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
180 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
181 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
182 #define QLCNIC_UNI_DIR_SECT_FW 0x7
185 #define QLCNIC_UNI_CHIP_REV_OFF 10
186 #define QLCNIC_UNI_FLAGS_OFF 11
187 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
188 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
189 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
191 struct uni_table_desc{
198 struct uni_data_desc{
204 /* Flash Defines and Structures */
205 #define QLCNIC_FLT_LOCATION 0x3F1000
206 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
207 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
208 #define QLCNIC_BOOTLD_REGION 0X72
209 struct qlcnic_flt_header {
216 struct qlcnic_flt_entry {
226 /* Magic number to let user know flash is programmed */
227 #define QLCNIC_BDINFO_MAGIC 0x12345678
229 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
230 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
231 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
232 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
233 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
234 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
235 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
236 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
237 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
238 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
239 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
240 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
241 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
242 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
244 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
246 /* Flash memory map */
247 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
248 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
249 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
250 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
252 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
253 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
254 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
255 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
257 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
258 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
260 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
261 #define QLCNIC_UNIFIED_ROMIMAGE 0
262 #define QLCNIC_FLASH_ROMIMAGE 1
263 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
265 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
266 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
268 extern char qlcnic_driver_name[];
270 /* Number of status descriptors to handle per interrupt */
271 #define MAX_STATUS_HANDLE (64)
274 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
275 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
277 struct qlcnic_skb_frag {
282 /* Following defines are for the state of the buffers */
283 #define QLCNIC_BUFFER_FREE 0
284 #define QLCNIC_BUFFER_BUSY 1
287 * There will be one qlcnic_buffer per skb packet. These will be
288 * used to save the dma info for pci_unmap_page()
290 struct qlcnic_cmd_buffer {
292 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
296 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
297 struct qlcnic_rx_buffer {
300 struct list_head list;
305 #define QLCNIC_GBE 0x01
306 #define QLCNIC_XGBE 0x02
309 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
310 * adjusted based on configured MTU.
312 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
313 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
315 #define QLCNIC_INTR_DEFAULT 0x04
316 #define QLCNIC_CONFIG_INTR_COALESCE 3
318 struct qlcnic_nic_intr_coalesce {
327 struct qlcnic_dump_template_hdr {
343 struct qlcnic_fw_dump {
344 u8 clr; /* flag to indicate if dump is cleared */
345 u8 enable; /* enable/disable dump */
346 u32 size; /* total size of the dump */
347 void *data; /* dump data area */
348 struct qlcnic_dump_template_hdr *tmpl_hdr;
352 * One hardware_context{} per adapter
353 * contains interrupt info as well shared hardware info.
355 struct qlcnic_hardware_context {
356 void __iomem *pci_base0;
357 void __iomem *ocm_win_crb;
359 unsigned long pci_len0;
362 struct mutex mem_lock;
402 struct qlcnic_hardware_ops *hw_ops;
403 struct qlcnic_nic_intr_coalesce coal;
404 struct qlcnic_fw_dump fw_dump;
407 struct qlcnic_adapter_stats {
421 u64 skb_alloc_failure;
423 u64 rx_dma_map_error;
424 u64 tx_dma_map_error;
428 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
429 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
431 struct qlcnic_host_rds_ring {
432 void __iomem *crb_rcv_producer;
433 struct rcv_desc *desc_head;
434 struct qlcnic_rx_buffer *rx_buf_arr;
440 struct list_head free_list;
442 dma_addr_t phys_addr;
443 } ____cacheline_internodealigned_in_smp;
445 struct qlcnic_host_sds_ring {
448 void __iomem *crb_sts_consumer;
450 struct status_desc *desc_head;
451 struct qlcnic_adapter *adapter;
452 struct napi_struct napi;
453 struct list_head free_list[NUM_RCV_DESC_RINGS];
455 void __iomem *crb_intr_mask;
458 dma_addr_t phys_addr;
459 char name[IFNAMSIZ+4];
460 } ____cacheline_internodealigned_in_smp;
462 struct qlcnic_host_tx_ring {
467 void __iomem *crb_cmd_producer;
468 struct cmd_desc_type0 *desc_head;
469 struct qlcnic_cmd_buffer *cmd_buf_arr;
472 dma_addr_t phys_addr;
473 dma_addr_t hw_cons_phys_addr;
474 struct netdev_queue *txq;
475 } ____cacheline_internodealigned_in_smp;
478 * Receive context. There is one such structure per instance of the
479 * receive processing. Any state information that is relevant to
480 * the receive, and is must be in this structure. The global data may be
483 struct qlcnic_recv_context {
484 struct qlcnic_host_rds_ring *rds_rings;
485 struct qlcnic_host_sds_ring *sds_rings;
492 /* HW context creation */
494 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
495 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
496 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
498 #define QLCNIC_CDRP_CMD_BIT 0x80000000
501 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
502 * in the crb QLCNIC_CDRP_CRB_OFFSET.
504 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
505 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
507 #define QLCNIC_CDRP_RSP_OK 0x00000001
508 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
509 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
512 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
513 * the crb QLCNIC_CDRP_CRB_OFFSET.
515 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
516 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
518 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
519 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
520 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
521 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
522 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
523 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
524 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
525 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
526 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
527 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
528 #define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011
529 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
530 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
531 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
532 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
533 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
534 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
535 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
536 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
537 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
539 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
540 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
541 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
542 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
543 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
544 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
545 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
546 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
547 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
548 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
549 #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E
550 #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f
551 #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030
552 #define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037
554 #define QLCNIC_RCODE_SUCCESS 0
555 #define QLCNIC_RCODE_INVALID_ARGS 6
556 #define QLCNIC_RCODE_NOT_SUPPORTED 9
557 #define QLCNIC_RCODE_NOT_PERMITTED 10
558 #define QLCNIC_RCODE_NOT_IMPL 15
559 #define QLCNIC_RCODE_INVALID 16
560 #define QLCNIC_RCODE_TIMEOUT 17
561 #define QLCNIC_DESTROY_CTX_RESET 0
564 * Capabilities Announced
566 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
567 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
568 #define QLCNIC_CAP0_LSO (1 << 6)
569 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
570 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
571 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
572 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
577 #define QLCNIC_HOST_CTX_STATE_FREED 0
578 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
584 struct qlcnic_hostrq_sds_ring {
585 __le64 host_phys_addr; /* Ring base addr */
586 __le32 ring_size; /* Ring entries */
588 __le16 rsvd; /* Padding */
591 struct qlcnic_hostrq_rds_ring {
592 __le64 host_phys_addr; /* Ring base addr */
593 __le64 buff_size; /* Packet buffer size */
594 __le32 ring_size; /* Ring entries */
595 __le32 ring_kind; /* Class of ring */
598 struct qlcnic_hostrq_rx_ctx {
599 __le64 host_rsp_dma_addr; /* Response dma'd here */
600 __le32 capabilities[4]; /* Flag bit vector */
601 __le32 host_int_crb_mode; /* Interrupt crb usage */
602 __le32 host_rds_crb_mode; /* RDS crb usage */
603 /* These ring offsets are relative to data[0] below */
604 __le32 rds_ring_offset; /* Offset to RDS config */
605 __le32 sds_ring_offset; /* Offset to SDS config */
606 __le16 num_rds_rings; /* Count of RDS rings */
607 __le16 num_sds_rings; /* Count of SDS rings */
608 __le16 valid_field_offset;
611 u8 reserved[128]; /* reserve space for future expansion*/
612 /* MUST BE 64-bit aligned.
613 The following is packed:
615 - N hostrq_sds_rings */
619 struct qlcnic_cardrsp_rds_ring{
620 __le32 host_producer_crb; /* Crb to use */
621 __le32 rsvd1; /* Padding */
624 struct qlcnic_cardrsp_sds_ring {
625 __le32 host_consumer_crb; /* Crb to use */
626 __le32 interrupt_crb; /* Crb to use */
629 struct qlcnic_cardrsp_rx_ctx {
630 /* These ring offsets are relative to data[0] below */
631 __le32 rds_ring_offset; /* Offset to RDS config */
632 __le32 sds_ring_offset; /* Offset to SDS config */
633 __le32 host_ctx_state; /* Starting State */
634 __le32 num_fn_per_port; /* How many PCI fn share the port */
635 __le16 num_rds_rings; /* Count of RDS rings */
636 __le16 num_sds_rings; /* Count of SDS rings */
637 __le16 context_id; /* Handle for context */
638 u8 phys_port; /* Physical id of port */
639 u8 virt_port; /* Virtual/Logical id of port */
640 u8 reserved[128]; /* save space for future expansion */
641 /* MUST BE 64-bit aligned.
642 The following is packed:
643 - N cardrsp_rds_rings
644 - N cardrs_sds_rings */
648 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
649 (sizeof(HOSTRQ_RX) + \
650 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
651 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
653 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
654 (sizeof(CARDRSP_RX) + \
655 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
656 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
662 struct qlcnic_hostrq_cds_ring {
663 __le64 host_phys_addr; /* Ring base addr */
664 __le32 ring_size; /* Ring entries */
665 __le32 rsvd; /* Padding */
668 struct qlcnic_hostrq_tx_ctx {
669 __le64 host_rsp_dma_addr; /* Response dma'd here */
670 __le64 cmd_cons_dma_addr; /* */
671 __le64 dummy_dma_addr; /* */
672 __le32 capabilities[4]; /* Flag bit vector */
673 __le32 host_int_crb_mode; /* Interrupt crb usage */
674 __le32 rsvd1; /* Padding */
675 __le16 rsvd2; /* Padding */
676 __le16 interrupt_ctl;
678 __le16 rsvd3; /* Padding */
679 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
680 u8 reserved[128]; /* future expansion */
683 struct qlcnic_cardrsp_cds_ring {
684 __le32 host_producer_crb; /* Crb to use */
685 __le32 interrupt_crb; /* Crb to use */
688 struct qlcnic_cardrsp_tx_ctx {
689 __le32 host_ctx_state; /* Starting state */
690 __le16 context_id; /* Handle for context */
691 u8 phys_port; /* Physical id of port */
692 u8 virt_port; /* Virtual/Logical id of port */
693 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
694 u8 reserved[128]; /* future expansion */
697 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
698 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
702 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
703 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
704 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
705 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
707 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
708 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
709 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
710 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
711 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
716 #define MC_COUNT_P3P 38
718 #define QLCNIC_MAC_NOOP 0
719 #define QLCNIC_MAC_ADD 1
720 #define QLCNIC_MAC_DEL 2
721 #define QLCNIC_MAC_VLAN_ADD 3
722 #define QLCNIC_MAC_VLAN_DEL 4
724 struct qlcnic_mac_list_s {
725 struct list_head list;
726 uint8_t mac_addr[ETH_ALEN+2];
729 #define QLCNIC_HOST_REQUEST 0x13
730 #define QLCNIC_REQUEST 0x14
732 #define QLCNIC_MAC_EVENT 0x1
734 #define QLCNIC_IP_UP 2
735 #define QLCNIC_IP_DOWN 3
737 #define QLCNIC_ILB_MODE 0x1
738 #define QLCNIC_ELB_MODE 0x2
740 #define QLCNIC_LINKEVENT 0x1
741 #define QLCNIC_LB_RESPONSE 0x2
742 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
743 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
746 * Driver --> Firmware
748 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
749 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
750 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
751 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
752 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
753 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
755 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
756 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
757 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
758 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
761 * Firmware --> Driver
764 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
765 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
767 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
768 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
769 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
771 #define QLCNIC_LRO_REQUEST_CLEANUP 4
773 /* Capabilites received */
774 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
775 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
776 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
777 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
778 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
779 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
781 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
784 #define LINKEVENT_MODULE_NOT_PRESENT 1
785 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
786 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
787 #define LINKEVENT_MODULE_OPTICAL_LRM 4
788 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
789 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
790 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
791 #define LINKEVENT_MODULE_TWINAX 8
793 #define LINKSPEED_10GBPS 10000
794 #define LINKSPEED_1GBPS 1000
795 #define LINKSPEED_100MBPS 100
796 #define LINKSPEED_10MBPS 10
798 #define LINKSPEED_ENCODED_10MBPS 0
799 #define LINKSPEED_ENCODED_100MBPS 1
800 #define LINKSPEED_ENCODED_1GBPS 2
802 #define LINKEVENT_AUTONEG_DISABLED 0
803 #define LINKEVENT_AUTONEG_ENABLED 1
805 #define LINKEVENT_HALF_DUPLEX 0
806 #define LINKEVENT_FULL_DUPLEX 1
808 #define LINKEVENT_LINKSPEED_MBPS 0
809 #define LINKEVENT_LINKSPEED_ENCODED 1
811 /* firmware response header:
812 * 63:58 - message type
816 * 47:40 - completion id
821 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
822 ((msg_hdr >> 32) & 0xFF)
824 struct qlcnic_fw_msg {
834 struct qlcnic_nic_req {
840 struct qlcnic_mac_req {
846 struct qlcnic_vlan_req {
851 struct qlcnic_ipaddr {
856 #define QLCNIC_MSI_ENABLED 0x02
857 #define QLCNIC_MSIX_ENABLED 0x04
858 #define QLCNIC_LRO_ENABLED 0x08
859 #define QLCNIC_LRO_DISABLED 0x00
860 #define QLCNIC_BRIDGE_ENABLED 0X10
861 #define QLCNIC_DIAG_ENABLED 0x20
862 #define QLCNIC_ESWITCH_ENABLED 0x40
863 #define QLCNIC_ADAPTER_INITIALIZED 0x80
864 #define QLCNIC_TAGGING_ENABLED 0x100
865 #define QLCNIC_MACSPOOF 0x200
866 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
867 #define QLCNIC_PROMISC_DISABLED 0x800
868 #define QLCNIC_NEED_FLR 0x1000
869 #define QLCNIC_FW_RESET_OWNER 0x2000
870 #define QLCNIC_FW_HANG 0x4000
871 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
872 #define QLCNIC_IS_MSI_FAMILY(adapter) \
873 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
875 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
876 #define QLCNIC_MSIX_TBL_SPACE 8192
877 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
878 #define QLCNIC_MSIX_TBL_PGSIZE 4096
880 #define QLCNIC_NETDEV_WEIGHT 128
881 #define QLCNIC_ADAPTER_UP_MAGIC 777
883 #define __QLCNIC_FW_ATTACHED 0
884 #define __QLCNIC_DEV_UP 1
885 #define __QLCNIC_RESETTING 2
886 #define __QLCNIC_START_FW 4
887 #define __QLCNIC_AER 5
888 #define __QLCNIC_DIAG_RES_ALLOC 6
889 #define __QLCNIC_LED_ENABLE 7
891 #define QLCNIC_INTERRUPT_TEST 1
892 #define QLCNIC_LOOPBACK_TEST 2
893 #define QLCNIC_LED_TEST 3
895 #define QLCNIC_FILTER_AGE 80
896 #define QLCNIC_READD_AGE 20
897 #define QLCNIC_LB_MAX_FILTERS 64
899 /* QLCNIC Driver Error Code */
900 #define QLCNIC_FW_NOT_RESPOND 51
901 #define QLCNIC_TEST_IN_PROGRESS 52
902 #define QLCNIC_UNDEFINED_ERROR 53
903 #define QLCNIC_LB_CABLE_NOT_CONN 54
905 struct qlcnic_filter {
906 struct hlist_node fnode;
912 struct qlcnic_filter_hash {
913 struct hlist_head *fhead;
918 struct qlcnic_adapter {
919 struct qlcnic_hardware_context *ahw;
920 struct qlcnic_recv_context *recv_ctx;
921 struct qlcnic_host_tx_ring *tx_ring;
922 struct net_device *netdev;
923 struct pci_dev *pdev;
928 int max_drv_tx_rings;
954 u8 mac_addr[ETH_ALEN];
958 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
959 struct qlcnic_npar_info *npars;
960 struct qlcnic_eswitch *eswitch;
961 struct qlcnic_nic_template *nic_ops;
963 struct qlcnic_adapter_stats stats;
964 struct list_head mac_list;
966 void __iomem *tgt_mask_reg;
967 void __iomem *tgt_status_reg;
968 void __iomem *crb_int_state_reg;
969 void __iomem *isr_int_vec;
971 struct msix_entry *msix_entries;
972 struct delayed_work fw_work;
974 struct qlcnic_filter_hash fhash;
976 spinlock_t tx_clean_lock;
977 spinlock_t mac_learn_lock;
978 u32 file_prd_off; /*File fw product offset*/
980 const struct firmware *fw;
983 struct qlcnic_info_le {
985 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
987 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1001 struct qlcnic_info {
1016 struct qlcnic_pci_info_le {
1017 __le16 id; /* pci function id */
1018 __le16 active; /* 1 = Enabled */
1019 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1020 __le16 default_port; /* default port number */
1022 __le16 tx_min_bw; /* Multiple of 100mbpc */
1024 __le16 reserved1[2];
1030 struct qlcnic_pci_info {
1040 struct qlcnic_npar_info {
1057 struct qlcnic_eswitch {
1061 u8 active_ucast_filters;
1062 u8 max_ucast_filters;
1063 u8 max_active_vlans;
1066 #define QLCNIC_SWITCH_ENABLE BIT_1
1067 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1068 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1069 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1073 /* Return codes for Error handling */
1074 #define QL_STATUS_INVALID_PARAM -1
1076 #define MAX_BW 100 /* % of link speed */
1077 #define MAX_VLAN_ID 4095
1078 #define MIN_VLAN_ID 2
1079 #define DEFAULT_MAC_LEARN 1
1081 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1082 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1084 struct qlcnic_pci_func_cfg {
1094 struct qlcnic_npar_func_cfg {
1105 struct qlcnic_pm_func_cfg {
1112 struct qlcnic_esw_func_cfg {
1126 #define QLCNIC_STATS_VERSION 1
1127 #define QLCNIC_STATS_PORT 1
1128 #define QLCNIC_STATS_ESWITCH 2
1129 #define QLCNIC_QUERY_RX_COUNTER 0
1130 #define QLCNIC_QUERY_TX_COUNTER 1
1131 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1132 #define QLCNIC_FILL_STATS(VAL1) \
1133 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1134 #define QLCNIC_MAC_STATS 1
1135 #define QLCNIC_ESW_STATS 2
1137 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1139 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1140 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1142 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1143 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1147 struct qlcnic_mac_statistics_le {
1148 __le64 mac_tx_frames;
1149 __le64 mac_tx_bytes;
1150 __le64 mac_tx_mcast_pkts;
1151 __le64 mac_tx_bcast_pkts;
1152 __le64 mac_tx_pause_cnt;
1153 __le64 mac_tx_ctrl_pkt;
1154 __le64 mac_tx_lt_64b_pkts;
1155 __le64 mac_tx_lt_127b_pkts;
1156 __le64 mac_tx_lt_255b_pkts;
1157 __le64 mac_tx_lt_511b_pkts;
1158 __le64 mac_tx_lt_1023b_pkts;
1159 __le64 mac_tx_lt_1518b_pkts;
1160 __le64 mac_tx_gt_1518b_pkts;
1163 __le64 mac_rx_frames;
1164 __le64 mac_rx_bytes;
1165 __le64 mac_rx_mcast_pkts;
1166 __le64 mac_rx_bcast_pkts;
1167 __le64 mac_rx_pause_cnt;
1168 __le64 mac_rx_ctrl_pkt;
1169 __le64 mac_rx_lt_64b_pkts;
1170 __le64 mac_rx_lt_127b_pkts;
1171 __le64 mac_rx_lt_255b_pkts;
1172 __le64 mac_rx_lt_511b_pkts;
1173 __le64 mac_rx_lt_1023b_pkts;
1174 __le64 mac_rx_lt_1518b_pkts;
1175 __le64 mac_rx_gt_1518b_pkts;
1178 __le64 mac_rx_length_error;
1179 __le64 mac_rx_length_small;
1180 __le64 mac_rx_length_large;
1181 __le64 mac_rx_jabber;
1182 __le64 mac_rx_dropped;
1183 __le64 mac_rx_crc_error;
1184 __le64 mac_align_error;
1187 struct qlcnic_mac_statistics {
1190 u64 mac_tx_mcast_pkts;
1191 u64 mac_tx_bcast_pkts;
1192 u64 mac_tx_pause_cnt;
1193 u64 mac_tx_ctrl_pkt;
1194 u64 mac_tx_lt_64b_pkts;
1195 u64 mac_tx_lt_127b_pkts;
1196 u64 mac_tx_lt_255b_pkts;
1197 u64 mac_tx_lt_511b_pkts;
1198 u64 mac_tx_lt_1023b_pkts;
1199 u64 mac_tx_lt_1518b_pkts;
1200 u64 mac_tx_gt_1518b_pkts;
1204 u64 mac_rx_mcast_pkts;
1205 u64 mac_rx_bcast_pkts;
1206 u64 mac_rx_pause_cnt;
1207 u64 mac_rx_ctrl_pkt;
1208 u64 mac_rx_lt_64b_pkts;
1209 u64 mac_rx_lt_127b_pkts;
1210 u64 mac_rx_lt_255b_pkts;
1211 u64 mac_rx_lt_511b_pkts;
1212 u64 mac_rx_lt_1023b_pkts;
1213 u64 mac_rx_lt_1518b_pkts;
1214 u64 mac_rx_gt_1518b_pkts;
1216 u64 mac_rx_length_error;
1217 u64 mac_rx_length_small;
1218 u64 mac_rx_length_large;
1221 u64 mac_rx_crc_error;
1222 u64 mac_align_error;
1225 struct qlcnic_esw_stats_le {
1230 __le64 unicast_frames;
1231 __le64 multicast_frames;
1232 __le64 broadcast_frames;
1233 __le64 dropped_frames;
1235 __le64 local_frames;
1240 struct __qlcnic_esw_statistics {
1246 u64 multicast_frames;
1247 u64 broadcast_frames;
1255 struct qlcnic_esw_statistics {
1256 struct __qlcnic_esw_statistics rx;
1257 struct __qlcnic_esw_statistics tx;
1260 #define QLCNIC_DUMP_MASK_DEF 0x1f
1261 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1262 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1263 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1264 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1265 #define QLCNIC_SET_QUIESCENT 0xadd00010
1266 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1275 struct qlcnic_cmd_args {
1276 struct _cdrp_cmd req;
1277 struct _cdrp_cmd rsp;
1280 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1281 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1283 int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1284 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1285 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1286 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1287 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1288 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1290 #define ADDR_IN_RANGE(addr, low, high) \
1291 (((addr) < (high)) && ((addr) >= (low)))
1293 #define QLCRD32(adapter, off) \
1294 (qlcnic_hw_read_wx_2M(adapter, off))
1295 #define QLCWR32(adapter, off, val) \
1296 (qlcnic_hw_write_wx_2M(adapter, off, val))
1298 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1299 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1301 #define qlcnic_rom_lock(a) \
1302 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1303 #define qlcnic_rom_unlock(a) \
1304 qlcnic_pcie_sem_unlock((a), 2)
1305 #define qlcnic_phy_lock(a) \
1306 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1307 #define qlcnic_phy_unlock(a) \
1308 qlcnic_pcie_sem_unlock((a), 3)
1309 #define qlcnic_api_lock(a) \
1310 qlcnic_pcie_sem_lock((a), 5, 0)
1311 #define qlcnic_api_unlock(a) \
1312 qlcnic_pcie_sem_unlock((a), 5)
1313 #define qlcnic_sw_lock(a) \
1314 qlcnic_pcie_sem_lock((a), 6, 0)
1315 #define qlcnic_sw_unlock(a) \
1316 qlcnic_pcie_sem_unlock((a), 6)
1317 #define crb_win_lock(a) \
1318 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1319 #define crb_win_unlock(a) \
1320 qlcnic_pcie_sem_unlock((a), 7)
1322 #define __QLCNIC_MAX_LED_RATE 0xf
1323 #define __QLCNIC_MAX_LED_STATE 0x2
1325 #define MAX_CTL_CHECK 1000
1327 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1328 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1329 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1330 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1331 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1332 int qlcnic_dump_fw(struct qlcnic_adapter *);
1334 /* Functions from qlcnic_init.c */
1335 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1336 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1337 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1338 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1339 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1340 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1341 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1343 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1344 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1345 u8 *bytes, size_t size);
1346 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1347 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1349 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1351 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1352 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1354 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1355 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1357 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1358 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1359 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1361 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1362 void qlcnic_watchdog_task(struct work_struct *work);
1363 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1364 struct qlcnic_host_rds_ring *rds_ring);
1365 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1366 void qlcnic_set_multi(struct net_device *netdev);
1367 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1368 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1369 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1370 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1371 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1372 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1373 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1375 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1376 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1377 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1378 netdev_features_t features);
1379 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1380 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1381 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1382 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1383 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1384 void qlcnic_fetch_mac(u32, u32, u8, u8 *);
1385 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1386 void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
1387 int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
1389 /* Functions from qlcnic_ethtool.c */
1390 int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]);
1392 /* Functions from qlcnic_main.c */
1393 int qlcnic_reset_context(struct qlcnic_adapter *);
1394 void qlcnic_issue_cmd(struct qlcnic_adapter *adapter, struct qlcnic_cmd_args *);
1395 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1396 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1397 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1398 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1399 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1400 void qlcnic_dev_request_reset(struct qlcnic_adapter *);
1401 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1403 /* Management functions */
1404 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1405 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1406 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1407 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1409 /* eSwitch management functions */
1410 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1411 struct qlcnic_esw_func_cfg *);
1412 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1413 struct qlcnic_esw_func_cfg *);
1414 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1415 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1416 struct __qlcnic_esw_statistics *);
1417 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1418 struct __qlcnic_esw_statistics *);
1419 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1420 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1421 extern int qlcnic_config_tso;
1423 int qlcnic_napi_add(struct qlcnic_adapter *, struct net_device *);
1424 void qlcnic_napi_del(struct qlcnic_adapter *adapter);
1425 void qlcnic_napi_enable(struct qlcnic_adapter *adapter);
1426 void qlcnic_napi_disable(struct qlcnic_adapter *adapter);
1427 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1428 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1429 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1430 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1432 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1433 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1434 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter);
1435 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter);
1436 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1437 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1438 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1439 struct qlcnic_esw_func_cfg *);
1440 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1441 struct qlcnic_esw_func_cfg *);
1444 * QLOGIC Board information
1447 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1448 struct qlcnic_board_info {
1449 unsigned short vendor;
1450 unsigned short device;
1451 unsigned short sub_vendor;
1452 unsigned short sub_device;
1453 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1456 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1458 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1459 return tx_ring->sw_consumer - tx_ring->producer;
1461 return tx_ring->sw_consumer + tx_ring->num_desc -
1465 static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring)
1467 writel(0, sds_ring->crb_intr_mask);
1470 static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring)
1472 struct qlcnic_adapter *adapter = sds_ring->adapter;
1474 writel(0x1, sds_ring->crb_intr_mask);
1476 if (!QLCNIC_IS_MSI_FAMILY(adapter))
1477 writel(0xfbff, adapter->tgt_mask_reg);
1480 extern const struct ethtool_ops qlcnic_ethtool_ops;
1481 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
1483 struct qlcnic_nic_template {
1484 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1485 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1486 int (*start_firmware) (struct qlcnic_adapter *);
1489 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1490 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
1491 printk(KERN_INFO "%s: %s: " _fmt, \
1492 dev_name(&adapter->pdev->dev), \
1493 __func__, ##_args); \
1496 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
1497 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
1499 unsigned short device = adapter->pdev->device;
1500 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
1503 #endif /* __QLCNIC_H_ */