drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14
  15 #define QLCNIC_MAX_TX_QUEUES            1
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18
  19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  20         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  21         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  22         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  23         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  24         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  25         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  26         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  27         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  28         {QLCNIC_CMD_SET_MTU, 3, 1},
  29         {QLCNIC_CMD_READ_PHY, 4, 2},
  30         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  31         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  32         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  33         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  34         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  35         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  36         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  37         {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
  38         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  39         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  40         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  41         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  42         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  43         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  44         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  45         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  46         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  47         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  48         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  49         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  50         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  51         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  52         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  53         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  54         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  55         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  57         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  58         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  59         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  60         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  61         {QLCNIC_CMD_IDC_ACK, 5, 1},
  62         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  63         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  65         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  66         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  67         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  68         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  69         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  70 };
  71
  72 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  73         0x38CC,         /* Global Reset */
  74         0x38F0,         /* Wildcard */
  75         0x38FC,         /* Informant */
  76         0x3038,         /* Host MBX ctrl */
  77         0x303C,         /* FW MBX ctrl */
  78         0x355C,         /* BOOT LOADER ADDRESS REG */
  79         0x3560,         /* BOOT LOADER SIZE REG */
  80         0x3564,         /* FW IMAGE ADDR REG */
  81         0x1000,         /* MBX intr enable */
  82         0x1200,         /* Default Intr mask */
  83         0x1204,         /* Default Interrupt ID */
  84         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  85         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  86         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  87         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  88         0x3790,         /* QLC_83XX_IDC_CTRL */
  89         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  90         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  91         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  92         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  93         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  94         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  95         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  96         0x37B0,         /* QLC_83XX_IDC_PF_4 */
  97         0x37B4,         /* QLC_83XX_IDC_PF_5 */
  98         0x37B8,         /* QLC_83XX_IDC_PF_6 */
  99         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 100         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 101         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 102         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 103         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 104         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 105         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 106         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 107         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 108         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 109         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 110         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 111         0x37F4,         /* QLC_83XX_VNIC_STATE */
 112         0x3868,         /* QLC_83XX_DRV_LOCK */
 113         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 114         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 115         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 116 };
 117
 118 const u32 qlcnic_83xx_reg_tbl[] = {
 119         0x34A8,         /* PEG_HALT_STAT1 */
 120         0x34AC,         /* PEG_HALT_STAT2 */
 121         0x34B0,         /* FW_HEARTBEAT */
 122         0x3500,         /* FLASH LOCK_ID */
 123         0x3528,         /* FW_CAPABILITIES */
 124         0x3538,         /* Driver active, DRV_REG0 */
 125         0x3540,         /* Device state, DRV_REG1 */
 126         0x3544,         /* Driver state, DRV_REG2 */
 127         0x3548,         /* Driver scratch, DRV_REG3 */
 128         0x354C,         /* Device partiton info, DRV_REG4 */
 129         0x3524,         /* Driver IDC ver, DRV_REG5 */
 130         0x3550,         /* FW_VER_MAJOR */
 131         0x3554,         /* FW_VER_MINOR */
 132         0x3558,         /* FW_VER_SUB */
 133         0x359C,         /* NPAR STATE */
 134         0x35FC,         /* FW_IMG_VALID */
 135         0x3650,         /* CMD_PEG_STATE */
 136         0x373C,         /* RCV_PEG_STATE */
 137         0x37B4,         /* ASIC TEMP */
 138         0x356C,         /* FW API */
 139         0x3570,         /* DRV OP MODE */
 140         0x3850,         /* FLASH LOCK */
 141         0x3854,         /* FLASH UNLOCK */
 142 };
 143
 144 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 145         .read_crb                       = qlcnic_83xx_read_crb,
 146         .write_crb                      = qlcnic_83xx_write_crb,
 147         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 148         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 149         .get_mac_address                = qlcnic_83xx_get_mac_address,
 150         .setup_intr                     = qlcnic_83xx_setup_intr,
 151         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 152         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 153         .get_func_no                    = qlcnic_83xx_get_func_no,
 154         .api_lock                       = qlcnic_83xx_cam_lock,
 155         .api_unlock                     = qlcnic_83xx_cam_unlock,
 156         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 157         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 158         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 159         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 160         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 161         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 162         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 163         .setup_link_event               = qlcnic_83xx_setup_link_event,
 164         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 165         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 166         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 167         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 168         .napi_enable                    = qlcnic_83xx_napi_enable,
 169         .napi_disable                   = qlcnic_83xx_napi_disable,
 170         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 171         .config_rss                     = qlcnic_83xx_config_rss,
 172         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 173         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 174         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 175         .get_board_info                 = qlcnic_83xx_get_port_info,
 176         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 177         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 178 };
 179
 180 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 181         .config_bridged_mode    = qlcnic_config_bridged_mode,
 182         .config_led             = qlcnic_config_led,
 183         .request_reset          = qlcnic_83xx_idc_request_reset,
 184         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 185         .napi_add               = qlcnic_83xx_napi_add,
 186         .napi_del               = qlcnic_83xx_napi_del,
 187         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 188         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 189         .shutdown               = qlcnic_83xx_shutdown,
 190         .resume                 = qlcnic_83xx_resume,
 191 };
 192
 193 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 194 {
 195         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 196         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 197         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 198 }
 199
 200 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 201 {
 202         u32 fw_major, fw_minor, fw_build;
 203         struct pci_dev *pdev = adapter->pdev;
 204
 205         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 206         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 207         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 208         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 209
 210         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 211                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 212
 213         return adapter->fw_version;
 214 }
 215
 216 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 217 {
 218         void __iomem *base;
 219         u32 val;
 220
 221         base = adapter->ahw->pci_base0 +
 222                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 223         writel(addr, base);
 224         val = readl(base);
 225         if (val != addr)
 226                 return -EIO;
 227
 228         return 0;
 229 }
 230
 231 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 232                                 int *err)
 233 {
 234         struct qlcnic_hardware_context *ahw = adapter->ahw;
 235
 236         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 237         if (!*err) {
 238                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 239         } else {
 240                 dev_err(&adapter->pdev->dev,
 241                         "%s failed, addr = 0x%lx\n", __func__, addr);
 242                 return -EIO;
 243         }
 244 }
 245
 246 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 247                                  u32 data)
 248 {
 249         int err;
 250         struct qlcnic_hardware_context *ahw = adapter->ahw;
 251
 252         err = __qlcnic_set_win_base(adapter, (u32) addr);
 253         if (!err) {
 254                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 255                 return 0;
 256         } else {
 257                 dev_err(&adapter->pdev->dev,
 258                         "%s failed, addr = 0x%x data = 0x%x\n",
 259                         __func__, (int)addr, data);
 260                 return err;
 261         }
 262 }
 263
 264 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
 265 {
 266         int err, i, num_msix;
 267         struct qlcnic_hardware_context *ahw = adapter->ahw;
 268
 269         if (!num_intr)
 270                 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
 271         num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
 272                                               num_intr));
 273         /* account for AEN interrupt MSI-X based interrupts */
 274         num_msix += 1;
 275
 276         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 277                 num_msix += adapter->max_drv_tx_rings;
 278
 279         err = qlcnic_enable_msix(adapter, num_msix);
 280         if (err == -ENOMEM)
 281                 return err;
 282         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 283                 num_msix = adapter->ahw->num_msix;
 284         else {
 285                 if (qlcnic_sriov_vf_check(adapter))
 286                         return -EINVAL;
 287                 num_msix = 1;
 288         }
 289         /* setup interrupt mapping table for fw */
 290         ahw->intr_tbl = vzalloc(num_msix *
 291                                 sizeof(struct qlcnic_intrpt_config));
 292         if (!ahw->intr_tbl)
 293                 return -ENOMEM;
 294         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 295                 /* MSI-X enablement failed, use legacy interrupt */
 296                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 297                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 298                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 299                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 300                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 301         }
 302
 303         for (i = 0; i < num_msix; i++) {
 304                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 305                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 306                 else
 307                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 308                 ahw->intr_tbl[i].id = i;
 309                 ahw->intr_tbl[i].src = 0;
 310         }
 311         return 0;
 312 }
 313
 314 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 315 {
 316         writel(0, adapter->tgt_mask_reg);
 317 }
 318
 319 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 320 {
 321         writel(1, adapter->tgt_mask_reg);
 322 }
 323
 324 /* Enable MSI-x and INT-x interrupts */
 325 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 326                              struct qlcnic_host_sds_ring *sds_ring)
 327 {
 328         writel(0, sds_ring->crb_intr_mask);
 329 }
 330
 331 /* Disable MSI-x and INT-x interrupts */
 332 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 333                               struct qlcnic_host_sds_ring *sds_ring)
 334 {
 335         writel(1, sds_ring->crb_intr_mask);
 336 }
 337
 338 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 339                                                     *adapter)
 340 {
 341         u32 mask;
 342
 343         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 344          * source register. We could be here before contexts are created
 345          * and sds_ring->crb_intr_mask has not been initialized, calculate
 346          * BAR offset for Interrupt Source Register
 347          */
 348         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 349         writel(0, adapter->ahw->pci_base0 + mask);
 350 }
 351
 352 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 353 {
 354         u32 mask;
 355
 356         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 357         writel(1, adapter->ahw->pci_base0 + mask);
 358         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 359 }
 360
 361 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 362                                      struct qlcnic_cmd_args *cmd)
 363 {
 364         int i;
 365
 366         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 367                 return;
 368
 369         for (i = 0; i < cmd->rsp.num; i++)
 370                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 371 }
 372
 373 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 374 {
 375         u32 intr_val;
 376         struct qlcnic_hardware_context *ahw = adapter->ahw;
 377         int retries = 0;
 378
 379         intr_val = readl(adapter->tgt_status_reg);
 380
 381         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 382                 return IRQ_NONE;
 383
 384         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 385                 adapter->stats.spurious_intr++;
 386                 return IRQ_NONE;
 387         }
 388         /* The barrier is required to ensure writes to the registers */
 389         wmb();
 390
 391         /* clear the interrupt trigger control register */
 392         writel(0, adapter->isr_int_vec);
 393         intr_val = readl(adapter->isr_int_vec);
 394         do {
 395                 intr_val = readl(adapter->tgt_status_reg);
 396                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 397                         break;
 398                 retries++;
 399         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 400                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 401
 402         return IRQ_HANDLED;
 403 }
 404
 405 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 406 {
 407         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 408         complete(&mbx->completion);
 409 }
 410
 411 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 412 {
 413         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 414         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 415         unsigned long flags;
 416
 417         spin_lock_irqsave(&mbx->aen_lock, flags);
 418         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 419         if (!(resp & QLCNIC_SET_OWNER))
 420                 goto out;
 421
 422         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 423         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 424                 __qlcnic_83xx_process_aen(adapter);
 425         } else {
 426                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 427                         qlcnic_83xx_notify_mbx_response(mbx);
 428         }
 429 out:
 430         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 431         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 432 }
 433
 434 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 435 {
 436         struct qlcnic_adapter *adapter = data;
 437         struct qlcnic_host_sds_ring *sds_ring;
 438         struct qlcnic_hardware_context *ahw = adapter->ahw;
 439
 440         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 441                 return IRQ_NONE;
 442
 443         qlcnic_83xx_poll_process_aen(adapter);
 444
 445         if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
 446                 ahw->diag_cnt++;
 447                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 448                 return IRQ_HANDLED;
 449         }
 450
 451         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 452                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 453         } else {
 454                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 455                 napi_schedule(&sds_ring->napi);
 456         }
 457
 458         return IRQ_HANDLED;
 459 }
 460
 461 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 462 {
 463         struct qlcnic_host_sds_ring *sds_ring = data;
 464         struct qlcnic_adapter *adapter = sds_ring->adapter;
 465
 466         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 467                 goto done;
 468
 469         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 470                 return IRQ_NONE;
 471
 472 done:
 473         adapter->ahw->diag_cnt++;
 474         qlcnic_83xx_enable_intr(adapter, sds_ring);
 475
 476         return IRQ_HANDLED;
 477 }
 478
 479 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 480 {
 481         u32 num_msix;
 482
 483         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 484                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 485
 486         qlcnic_83xx_disable_mbx_intr(adapter);
 487
 488         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 489                 num_msix = adapter->ahw->num_msix - 1;
 490         else
 491                 num_msix = 0;
 492
 493         msleep(20);
 494         synchronize_irq(adapter->msix_entries[num_msix].vector);
 495         free_irq(adapter->msix_entries[num_msix].vector, adapter);
 496 }
 497
 498 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 499 {
 500         irq_handler_t handler;
 501         u32 val;
 502         int err = 0;
 503         unsigned long flags = 0;
 504
 505         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 506             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 507                 flags |= IRQF_SHARED;
 508
 509         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 510                 handler = qlcnic_83xx_handle_aen;
 511                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 512                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 513                 if (err) {
 514                         dev_err(&adapter->pdev->dev,
 515                                 "failed to register MBX interrupt\n");
 516                         return err;
 517                 }
 518         } else {
 519                 handler = qlcnic_83xx_intr;
 520                 val = adapter->msix_entries[0].vector;
 521                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 522                 if (err) {
 523                         dev_err(&adapter->pdev->dev,
 524                                 "failed to register INTx interrupt\n");
 525                         return err;
 526                 }
 527                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 528         }
 529
 530         /* Enable mailbox interrupt */
 531         qlcnic_83xx_enable_mbx_interrupt(adapter);
 532
 533         return err;
 534 }
 535
 536 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 537 {
 538         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 539         adapter->ahw->pci_func = (val >> 24) & 0xff;
 540 }
 541
 542 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 543 {
 544         void __iomem *addr;
 545         u32 val, limit = 0;
 546
 547         struct qlcnic_hardware_context *ahw = adapter->ahw;
 548
 549         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 550         do {
 551                 val = readl(addr);
 552                 if (val) {
 553                         /* write the function number to register */
 554                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 555                                             ahw->pci_func);
 556                         return 0;
 557                 }
 558                 usleep_range(1000, 2000);
 559         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 560
 561         return -EIO;
 562 }
 563
 564 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 565 {
 566         void __iomem *addr;
 567         u32 val;
 568         struct qlcnic_hardware_context *ahw = adapter->ahw;
 569
 570         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 571         val = readl(addr);
 572 }
 573
 574 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 575                           loff_t offset, size_t size)
 576 {
 577         int ret = 0;
 578         u32 data;
 579
 580         if (qlcnic_api_lock(adapter)) {
 581                 dev_err(&adapter->pdev->dev,
 582                         "%s: failed to acquire lock. addr offset 0x%x\n",
 583                         __func__, (u32)offset);
 584                 return;
 585         }
 586
 587         data = QLCRD32(adapter, (u32) offset, &ret);
 588         qlcnic_api_unlock(adapter);
 589
 590         if (ret == -EIO) {
 591                 dev_err(&adapter->pdev->dev,
 592                         "%s: failed. addr offset 0x%x\n",
 593                         __func__, (u32)offset);
 594                 return;
 595         }
 596         memcpy(buf, &data, size);
 597 }
 598
 599 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 600                            loff_t offset, size_t size)
 601 {
 602         u32 data;
 603
 604         memcpy(&data, buf, size);
 605         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 606 }
 607
 608 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 609 {
 610         int status;
 611
 612         status = qlcnic_83xx_get_port_config(adapter);
 613         if (status) {
 614                 dev_err(&adapter->pdev->dev,
 615                         "Get Port Info failed\n");
 616         } else {
 617                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 618                         adapter->ahw->port_type = QLCNIC_XGBE;
 619                 else
 620                         adapter->ahw->port_type = QLCNIC_GBE;
 621
 622                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 623                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 624         }
 625         return status;
 626 }
 627
 628 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 629 {
 630         struct qlcnic_hardware_context *ahw = adapter->ahw;
 631         u16 act_pci_fn = ahw->act_pci_func;
 632         u16 count;
 633
 634         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 635         if (act_pci_fn <= 2)
 636                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 637                          act_pci_fn;
 638         else
 639                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 640                          act_pci_fn;
 641         ahw->max_uc_count = count;
 642 }
 643
 644 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 645 {
 646         u32 val;
 647
 648         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 649                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 650         else
 651                 val = BIT_2;
 652
 653         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 654         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 655 }
 656
 657 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 658                           const struct pci_device_id *ent)
 659 {
 660         u32 op_mode, priv_level;
 661         struct qlcnic_hardware_context *ahw = adapter->ahw;
 662
 663         ahw->fw_hal_version = 2;
 664         qlcnic_get_func_no(adapter);
 665
 666         if (qlcnic_sriov_vf_check(adapter)) {
 667                 qlcnic_sriov_vf_set_ops(adapter);
 668                 return;
 669         }
 670
 671         /* Determine function privilege level */
 672         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 673         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 674                 priv_level = QLCNIC_MGMT_FUNC;
 675         else
 676                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 677                                                          ahw->pci_func);
 678
 679         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 680                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 681                 dev_info(&adapter->pdev->dev,
 682                          "HAL Version: %d Non Privileged function\n",
 683                          ahw->fw_hal_version);
 684                 adapter->nic_ops = &qlcnic_vf_ops;
 685         } else {
 686                 if (pci_find_ext_capability(adapter->pdev,
 687                                             PCI_EXT_CAP_ID_SRIOV))
 688                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 689                 adapter->nic_ops = &qlcnic_83xx_ops;
 690         }
 691 }
 692
 693 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 694                                         u32 data[]);
 695 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 696                                             u32 data[]);
 697
 698 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 699                             struct qlcnic_cmd_args *cmd)
 700 {
 701         int i;
 702
 703         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 704                 return;
 705
 706         dev_info(&adapter->pdev->dev,
 707                  "Host MBX regs(%d)\n", cmd->req.num);
 708         for (i = 0; i < cmd->req.num; i++) {
 709                 if (i && !(i % 8))
 710                         pr_info("\n");
 711                 pr_info("%08x ", cmd->req.arg[i]);
 712         }
 713         pr_info("\n");
 714         dev_info(&adapter->pdev->dev,
 715                  "FW MBX regs(%d)\n", cmd->rsp.num);
 716         for (i = 0; i < cmd->rsp.num; i++) {
 717                 if (i && !(i % 8))
 718                         pr_info("\n");
 719                 pr_info("%08x ", cmd->rsp.arg[i]);
 720         }
 721         pr_info("\n");
 722 }
 723
 724 static inline void
 725 qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 726                                     struct qlcnic_cmd_args *cmd)
 727 {
 728         struct qlcnic_hardware_context *ahw = adapter->ahw;
 729         int opcode = LSW(cmd->req.arg[0]);
 730         unsigned long max_loops;
 731
 732         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 733
 734         for (; max_loops; max_loops--) {
 735                 if (atomic_read(&cmd->rsp_status) ==
 736                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 737                         return;
 738
 739                 udelay(1);
 740         }
 741
 742         dev_err(&adapter->pdev->dev,
 743                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 744                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 745         flush_workqueue(ahw->mailbox->work_q);
 746         return;
 747 }
 748
 749 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 750                           struct qlcnic_cmd_args *cmd)
 751 {
 752         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 753         struct qlcnic_hardware_context *ahw = adapter->ahw;
 754         int cmd_type, err, opcode;
 755         unsigned long timeout;
 756
 757         opcode = LSW(cmd->req.arg[0]);
 758         cmd_type = cmd->type;
 759         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 760         if (err) {
 761                 dev_err(&adapter->pdev->dev,
 762                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 763                         __func__, opcode, cmd->type, ahw->pci_func,
 764                         ahw->op_mode);
 765                 return err;
 766         }
 767
 768         switch (cmd_type) {
 769         case QLC_83XX_MBX_CMD_WAIT:
 770                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 771                         dev_err(&adapter->pdev->dev,
 772                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 773                                 __func__, opcode, cmd_type, ahw->pci_func,
 774                                 ahw->op_mode);
 775                         flush_workqueue(mbx->work_q);
 776                 }
 777                 break;
 778         case QLC_83XX_MBX_CMD_NO_WAIT:
 779                 return 0;
 780         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 781                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 782                 break;
 783         default:
 784                 dev_err(&adapter->pdev->dev,
 785                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 786                         __func__, opcode, cmd_type, ahw->pci_func,
 787                         ahw->op_mode);
 788                 qlcnic_83xx_detach_mailbox_work(adapter);
 789         }
 790
 791         return cmd->rsp_opcode;
 792 }
 793
 794 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 795                                struct qlcnic_adapter *adapter, u32 type)
 796 {
 797         int i, size;
 798         u32 temp;
 799         const struct qlcnic_mailbox_metadata *mbx_tbl;
 800
 801         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 802         mbx_tbl = qlcnic_83xx_mbx_tbl;
 803         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 804         for (i = 0; i < size; i++) {
 805                 if (type == mbx_tbl[i].cmd) {
 806                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 807                         mbx->req.num = mbx_tbl[i].in_args;
 808                         mbx->rsp.num = mbx_tbl[i].out_args;
 809                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 810                                                GFP_ATOMIC);
 811                         if (!mbx->req.arg)
 812                                 return -ENOMEM;
 813                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 814                                                GFP_ATOMIC);
 815                         if (!mbx->rsp.arg) {
 816                                 kfree(mbx->req.arg);
 817                                 mbx->req.arg = NULL;
 818                                 return -ENOMEM;
 819                         }
 820                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 821                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 822                         temp = adapter->ahw->fw_hal_version << 29;
 823                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 824                         mbx->cmd_op = type;
 825                         return 0;
 826                 }
 827         }
 828         return -EINVAL;
 829 }
 830
 831 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 832 {
 833         struct qlcnic_adapter *adapter;
 834         struct qlcnic_cmd_args cmd;
 835         int i, err = 0;
 836
 837         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 838         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 839         if (err)
 840                 return;
 841
 842         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 843                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 844
 845         err = qlcnic_issue_cmd(adapter, &cmd);
 846         if (err)
 847                 dev_info(&adapter->pdev->dev,
 848                          "%s: Mailbox IDC ACK failed.\n", __func__);
 849         qlcnic_free_mbx_args(&cmd);
 850 }
 851
 852 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 853                                             u32 data[])
 854 {
 855         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 856                 QLCNIC_MBX_RSP(data[0]));
 857         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 858         return;
 859 }
 860
 861 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 862 {
 863         u32 event[QLC_83XX_MBX_AEN_CNT];
 864         int i;
 865         struct qlcnic_hardware_context *ahw = adapter->ahw;
 866
 867         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 868                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 869
 870         switch (QLCNIC_MBX_RSP(event[0])) {
 871
 872         case QLCNIC_MBX_LINK_EVENT:
 873                 qlcnic_83xx_handle_link_aen(adapter, event);
 874                 break;
 875         case QLCNIC_MBX_COMP_EVENT:
 876                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 877                 break;
 878         case QLCNIC_MBX_REQUEST_EVENT:
 879                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 880                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 881                 queue_delayed_work(adapter->qlcnic_wq,
 882                                    &adapter->idc_aen_work, 0);
 883                 break;
 884         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 885                 break;
 886         case QLCNIC_MBX_BC_EVENT:
 887                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 888                 break;
 889         case QLCNIC_MBX_SFP_INSERT_EVENT:
 890                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 891                          QLCNIC_MBX_RSP(event[0]));
 892                 break;
 893         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 894                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 895                          QLCNIC_MBX_RSP(event[0]));
 896                 break;
 897         default:
 898                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 899                         QLCNIC_MBX_RSP(event[0]));
 900                 break;
 901         }
 902
 903         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 904 }
 905
 906 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 907 {
 908         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 909         struct qlcnic_hardware_context *ahw = adapter->ahw;
 910         struct qlcnic_mailbox *mbx = ahw->mailbox;
 911         unsigned long flags;
 912
 913         spin_lock_irqsave(&mbx->aen_lock, flags);
 914         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 915         if (resp & QLCNIC_SET_OWNER) {
 916                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 917                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 918                         __qlcnic_83xx_process_aen(adapter);
 919                 } else {
 920                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 921                                 qlcnic_83xx_notify_mbx_response(mbx);
 922                 }
 923         }
 924         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 925 }
 926
 927 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 928 {
 929         struct qlcnic_adapter *adapter;
 930
 931         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 932
 933         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 934                 return;
 935
 936         qlcnic_83xx_process_aen(adapter);
 937         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 938                            (HZ / 10));
 939 }
 940
 941 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 942 {
 943         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 944                 return;
 945
 946         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 947         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 948 }
 949
 950 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 951 {
 952         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 953                 return;
 954         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 955 }
 956
 957 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 958 {
 959         int index, i, err, sds_mbx_size;
 960         u32 *buf, intrpt_id, intr_mask;
 961         u16 context_id;
 962         u8 num_sds;
 963         struct qlcnic_cmd_args cmd;
 964         struct qlcnic_host_sds_ring *sds;
 965         struct qlcnic_sds_mbx sds_mbx;
 966         struct qlcnic_add_rings_mbx_out *mbx_out;
 967         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 968         struct qlcnic_hardware_context *ahw = adapter->ahw;
 969
 970         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 971         context_id = recv_ctx->context_id;
 972         num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
 973         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 974                                     QLCNIC_CMD_ADD_RCV_RINGS);
 975         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 976
 977         /* set up status rings, mbx 2-81 */
 978         index = 2;
 979         for (i = 8; i < adapter->max_sds_rings; i++) {
 980                 memset(&sds_mbx, 0, sds_mbx_size);
 981                 sds = &recv_ctx->sds_rings[i];
 982                 sds->consumer = 0;
 983                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
 984                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
 985                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
 986                 sds_mbx.sds_ring_size = sds->num_desc;
 987
 988                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 989                         intrpt_id = ahw->intr_tbl[i].id;
 990                 else
 991                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
 992
 993                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
 994                         sds_mbx.intrpt_id = intrpt_id;
 995                 else
 996                         sds_mbx.intrpt_id = 0xffff;
 997                 sds_mbx.intrpt_val = 0;
 998                 buf = &cmd.req.arg[index];
 999                 memcpy(buf, &sds_mbx, sds_mbx_size);
1000                 index += sds_mbx_size / sizeof(u32);
1001         }
1002
1003         /* send the mailbox command */
1004         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1005         if (err) {
1006                 dev_err(&adapter->pdev->dev,
1007                         "Failed to add rings %d\n", err);
1008                 goto out;
1009         }
1010
1011         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1012         index = 0;
1013         /* status descriptor ring */
1014         for (i = 8; i < adapter->max_sds_rings; i++) {
1015                 sds = &recv_ctx->sds_rings[i];
1016                 sds->crb_sts_consumer = ahw->pci_base0 +
1017                                         mbx_out->host_csmr[index];
1018                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1019                         intr_mask = ahw->intr_tbl[i].src;
1020                 else
1021                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1022
1023                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1024                 index++;
1025         }
1026 out:
1027         qlcnic_free_mbx_args(&cmd);
1028         return err;
1029 }
1030
1031 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1032 {
1033         int err;
1034         u32 temp = 0;
1035         struct qlcnic_cmd_args cmd;
1036         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1037
1038         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1039                 return;
1040
1041         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1042                 cmd.req.arg[0] |= (0x3 << 29);
1043
1044         if (qlcnic_sriov_pf_check(adapter))
1045                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1046
1047         cmd.req.arg[1] = recv_ctx->context_id | temp;
1048         err = qlcnic_issue_cmd(adapter, &cmd);
1049         if (err)
1050                 dev_err(&adapter->pdev->dev,
1051                         "Failed to destroy rx ctx in firmware\n");
1052
1053         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1054         qlcnic_free_mbx_args(&cmd);
1055 }
1056
1057 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1058 {
1059         int i, err, index, sds_mbx_size, rds_mbx_size;
1060         u8 num_sds, num_rds;
1061         u32 *buf, intrpt_id, intr_mask, cap = 0;
1062         struct qlcnic_host_sds_ring *sds;
1063         struct qlcnic_host_rds_ring *rds;
1064         struct qlcnic_sds_mbx sds_mbx;
1065         struct qlcnic_rds_mbx rds_mbx;
1066         struct qlcnic_cmd_args cmd;
1067         struct qlcnic_rcv_mbx_out *mbx_out;
1068         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1069         struct qlcnic_hardware_context *ahw = adapter->ahw;
1070         num_rds = adapter->max_rds_rings;
1071
1072         if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1073                 num_sds = adapter->max_sds_rings;
1074         else
1075                 num_sds = QLCNIC_MAX_RING_SETS;
1076
1077         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1078         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1079         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1080
1081         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1082                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1083
1084         /* set mailbox hdr and capabilities */
1085         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1086                                     QLCNIC_CMD_CREATE_RX_CTX);
1087         if (err)
1088                 return err;
1089
1090         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1091                 cmd.req.arg[0] |= (0x3 << 29);
1092
1093         cmd.req.arg[1] = cap;
1094         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1095                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1096
1097         if (qlcnic_sriov_pf_check(adapter))
1098                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1099                                                          &cmd.req.arg[6]);
1100         /* set up status rings, mbx 8-57/87 */
1101         index = QLC_83XX_HOST_SDS_MBX_IDX;
1102         for (i = 0; i < num_sds; i++) {
1103                 memset(&sds_mbx, 0, sds_mbx_size);
1104                 sds = &recv_ctx->sds_rings[i];
1105                 sds->consumer = 0;
1106                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1107                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1108                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1109                 sds_mbx.sds_ring_size = sds->num_desc;
1110                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1111                         intrpt_id = ahw->intr_tbl[i].id;
1112                 else
1113                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1114                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1115                         sds_mbx.intrpt_id = intrpt_id;
1116                 else
1117                         sds_mbx.intrpt_id = 0xffff;
1118                 sds_mbx.intrpt_val = 0;
1119                 buf = &cmd.req.arg[index];
1120                 memcpy(buf, &sds_mbx, sds_mbx_size);
1121                 index += sds_mbx_size / sizeof(u32);
1122         }
1123         /* set up receive rings, mbx 88-111/135 */
1124         index = QLCNIC_HOST_RDS_MBX_IDX;
1125         rds = &recv_ctx->rds_rings[0];
1126         rds->producer = 0;
1127         memset(&rds_mbx, 0, rds_mbx_size);
1128         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1129         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1130         rds_mbx.reg_ring_sz = rds->dma_size;
1131         rds_mbx.reg_ring_len = rds->num_desc;
1132         /* Jumbo ring */
1133         rds = &recv_ctx->rds_rings[1];
1134         rds->producer = 0;
1135         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1136         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1137         rds_mbx.jmb_ring_sz = rds->dma_size;
1138         rds_mbx.jmb_ring_len = rds->num_desc;
1139         buf = &cmd.req.arg[index];
1140         memcpy(buf, &rds_mbx, rds_mbx_size);
1141
1142         /* send the mailbox command */
1143         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1144         if (err) {
1145                 dev_err(&adapter->pdev->dev,
1146                         "Failed to create Rx ctx in firmware%d\n", err);
1147                 goto out;
1148         }
1149         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1150         recv_ctx->context_id = mbx_out->ctx_id;
1151         recv_ctx->state = mbx_out->state;
1152         recv_ctx->virt_port = mbx_out->vport_id;
1153         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1154                  recv_ctx->context_id, recv_ctx->state);
1155         /* Receive descriptor ring */
1156         /* Standard ring */
1157         rds = &recv_ctx->rds_rings[0];
1158         rds->crb_rcv_producer = ahw->pci_base0 +
1159                                 mbx_out->host_prod[0].reg_buf;
1160         /* Jumbo ring */
1161         rds = &recv_ctx->rds_rings[1];
1162         rds->crb_rcv_producer = ahw->pci_base0 +
1163                                 mbx_out->host_prod[0].jmb_buf;
1164         /* status descriptor ring */
1165         for (i = 0; i < num_sds; i++) {
1166                 sds = &recv_ctx->sds_rings[i];
1167                 sds->crb_sts_consumer = ahw->pci_base0 +
1168                                         mbx_out->host_csmr[i];
1169                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1170                         intr_mask = ahw->intr_tbl[i].src;
1171                 else
1172                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1173                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1174         }
1175
1176         if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1177                 err = qlcnic_83xx_add_rings(adapter);
1178 out:
1179         qlcnic_free_mbx_args(&cmd);
1180         return err;
1181 }
1182
1183 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1184                             struct qlcnic_host_tx_ring *tx_ring)
1185 {
1186         struct qlcnic_cmd_args cmd;
1187         u32 temp = 0;
1188
1189         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1190                 return;
1191
1192         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1193                 cmd.req.arg[0] |= (0x3 << 29);
1194
1195         if (qlcnic_sriov_pf_check(adapter))
1196                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1197
1198         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1199         if (qlcnic_issue_cmd(adapter, &cmd))
1200                 dev_err(&adapter->pdev->dev,
1201                         "Failed to destroy tx ctx in firmware\n");
1202         qlcnic_free_mbx_args(&cmd);
1203 }
1204
1205 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1206                               struct qlcnic_host_tx_ring *tx, int ring)
1207 {
1208         int err;
1209         u16 msix_id;
1210         u32 *buf, intr_mask, temp = 0;
1211         struct qlcnic_cmd_args cmd;
1212         struct qlcnic_tx_mbx mbx;
1213         struct qlcnic_tx_mbx_out *mbx_out;
1214         struct qlcnic_hardware_context *ahw = adapter->ahw;
1215         u32 msix_vector;
1216
1217         /* Reset host resources */
1218         tx->producer = 0;
1219         tx->sw_consumer = 0;
1220         *(tx->hw_consumer) = 0;
1221
1222         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1223
1224         /* setup mailbox inbox registerss */
1225         mbx.phys_addr_low = LSD(tx->phys_addr);
1226         mbx.phys_addr_high = MSD(tx->phys_addr);
1227         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1228         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1229         mbx.size = tx->num_desc;
1230         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1231                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1232                         msix_vector = adapter->max_sds_rings + ring;
1233                 else
1234                         msix_vector = adapter->max_sds_rings - 1;
1235                 msix_id = ahw->intr_tbl[msix_vector].id;
1236         } else {
1237                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1238         }
1239
1240         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1241                 mbx.intr_id = msix_id;
1242         else
1243                 mbx.intr_id = 0xffff;
1244         mbx.src = 0;
1245
1246         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1247         if (err)
1248                 return err;
1249
1250         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1251                 cmd.req.arg[0] |= (0x3 << 29);
1252
1253         if (qlcnic_sriov_pf_check(adapter))
1254                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1255
1256         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1257         cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1258         buf = &cmd.req.arg[6];
1259         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1260         /* send the mailbox command*/
1261         err = qlcnic_issue_cmd(adapter, &cmd);
1262         if (err) {
1263                 dev_err(&adapter->pdev->dev,
1264                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1265                 goto out;
1266         }
1267         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1268         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1269         tx->ctx_id = mbx_out->ctx_id;
1270         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1271             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1272                 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1273                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1274         }
1275         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1276                  tx->ctx_id, mbx_out->state);
1277 out:
1278         qlcnic_free_mbx_args(&cmd);
1279         return err;
1280 }
1281
1282 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1283                                       int num_sds_ring)
1284 {
1285         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1286         struct qlcnic_host_sds_ring *sds_ring;
1287         struct qlcnic_host_rds_ring *rds_ring;
1288         u16 adapter_state = adapter->is_up;
1289         u8 ring;
1290         int ret;
1291
1292         netif_device_detach(netdev);
1293
1294         if (netif_running(netdev))
1295                 __qlcnic_down(adapter, netdev);
1296
1297         qlcnic_detach(adapter);
1298
1299         adapter->max_sds_rings = 1;
1300         adapter->ahw->diag_test = test;
1301         adapter->ahw->linkup = 0;
1302
1303         ret = qlcnic_attach(adapter);
1304         if (ret) {
1305                 netif_device_attach(netdev);
1306                 return ret;
1307         }
1308
1309         ret = qlcnic_fw_create_ctx(adapter);
1310         if (ret) {
1311                 qlcnic_detach(adapter);
1312                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1313                         adapter->max_sds_rings = num_sds_ring;
1314                         qlcnic_attach(adapter);
1315                 }
1316                 netif_device_attach(netdev);
1317                 return ret;
1318         }
1319
1320         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1321                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1322                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1323         }
1324
1325         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1326                 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1327                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1328                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1329                 }
1330         }
1331
1332         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1333                 /* disable and free mailbox interrupt */
1334                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1335                         qlcnic_83xx_enable_mbx_poll(adapter);
1336                         qlcnic_83xx_free_mbx_intr(adapter);
1337                 }
1338                 adapter->ahw->loopback_state = 0;
1339                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1340         }
1341
1342         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1343         return 0;
1344 }
1345
1346 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1347                                         int max_sds_rings)
1348 {
1349         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1350         struct qlcnic_host_sds_ring *sds_ring;
1351         int ring, err;
1352
1353         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1354         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1355                 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1356                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1357                         qlcnic_83xx_disable_intr(adapter, sds_ring);
1358                         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1359                                 qlcnic_83xx_enable_mbx_poll(adapter);
1360                 }
1361         }
1362
1363         qlcnic_fw_destroy_ctx(adapter);
1364         qlcnic_detach(adapter);
1365
1366         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1367                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1368                         err = qlcnic_83xx_setup_mbx_intr(adapter);
1369                         qlcnic_83xx_disable_mbx_poll(adapter);
1370                         if (err) {
1371                                 dev_err(&adapter->pdev->dev,
1372                                         "%s: failed to setup mbx interrupt\n",
1373                                         __func__);
1374                                 goto out;
1375                         }
1376                 }
1377         }
1378         adapter->ahw->diag_test = 0;
1379         adapter->max_sds_rings = max_sds_rings;
1380
1381         if (qlcnic_attach(adapter))
1382                 goto out;
1383
1384         if (netif_running(netdev))
1385                 __qlcnic_up(adapter, netdev);
1386
1387         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST &&
1388             !(adapter->flags & QLCNIC_MSIX_ENABLED))
1389                 qlcnic_83xx_disable_mbx_poll(adapter);
1390 out:
1391         netif_device_attach(netdev);
1392 }
1393
1394 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1395                            u32 beacon)
1396 {
1397         struct qlcnic_cmd_args cmd;
1398         u32 mbx_in;
1399         int i, status = 0;
1400
1401         if (state) {
1402                 /* Get LED configuration */
1403                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1404                                                QLCNIC_CMD_GET_LED_CONFIG);
1405                 if (status)
1406                         return status;
1407
1408                 status = qlcnic_issue_cmd(adapter, &cmd);
1409                 if (status) {
1410                         dev_err(&adapter->pdev->dev,
1411                                 "Get led config failed.\n");
1412                         goto mbx_err;
1413                 } else {
1414                         for (i = 0; i < 4; i++)
1415                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1416                 }
1417                 qlcnic_free_mbx_args(&cmd);
1418                 /* Set LED Configuration */
1419                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1420                           LSW(QLC_83XX_LED_CONFIG);
1421                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1422                                                QLCNIC_CMD_SET_LED_CONFIG);
1423                 if (status)
1424                         return status;
1425
1426                 cmd.req.arg[1] = mbx_in;
1427                 cmd.req.arg[2] = mbx_in;
1428                 cmd.req.arg[3] = mbx_in;
1429                 if (beacon)
1430                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1431                 status = qlcnic_issue_cmd(adapter, &cmd);
1432                 if (status) {
1433                         dev_err(&adapter->pdev->dev,
1434                                 "Set led config failed.\n");
1435                 }
1436 mbx_err:
1437                 qlcnic_free_mbx_args(&cmd);
1438                 return status;
1439
1440         } else {
1441                 /* Restoring default LED configuration */
1442                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1443                                                QLCNIC_CMD_SET_LED_CONFIG);
1444                 if (status)
1445                         return status;
1446
1447                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1448                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1449                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1450                 if (beacon)
1451                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1452                 status = qlcnic_issue_cmd(adapter, &cmd);
1453                 if (status)
1454                         dev_err(&adapter->pdev->dev,
1455                                 "Restoring led config failed.\n");
1456                 qlcnic_free_mbx_args(&cmd);
1457                 return status;
1458         }
1459 }
1460
1461 int  qlcnic_83xx_set_led(struct net_device *netdev,
1462                          enum ethtool_phys_id_state state)
1463 {
1464         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1465         int err = -EIO, active = 1;
1466
1467         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1468                 netdev_warn(netdev,
1469                             "LED test is not supported in non-privileged mode\n");
1470                 return -EOPNOTSUPP;
1471         }
1472
1473         switch (state) {
1474         case ETHTOOL_ID_ACTIVE:
1475                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1476                         return -EBUSY;
1477
1478                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1479                         break;
1480
1481                 err = qlcnic_83xx_config_led(adapter, active, 0);
1482                 if (err)
1483                         netdev_err(netdev, "Failed to set LED blink state\n");
1484                 break;
1485         case ETHTOOL_ID_INACTIVE:
1486                 active = 0;
1487
1488                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1489                         break;
1490
1491                 err = qlcnic_83xx_config_led(adapter, active, 0);
1492                 if (err)
1493                         netdev_err(netdev, "Failed to reset LED blink state\n");
1494                 break;
1495
1496         default:
1497                 return -EINVAL;
1498         }
1499
1500         if (!active || err)
1501                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1502
1503         return err;
1504 }
1505
1506 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1507                                        int enable)
1508 {
1509         struct qlcnic_cmd_args cmd;
1510         int status;
1511
1512         if (qlcnic_sriov_vf_check(adapter))
1513                 return;
1514
1515         if (enable) {
1516                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1517                                                QLCNIC_CMD_INIT_NIC_FUNC);
1518                 if (status)
1519                         return;
1520
1521                 cmd.req.arg[1] = BIT_0 | BIT_31;
1522         } else {
1523                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1524                                                QLCNIC_CMD_STOP_NIC_FUNC);
1525                 if (status)
1526                         return;
1527
1528                 cmd.req.arg[1] = BIT_0 | BIT_31;
1529         }
1530         status = qlcnic_issue_cmd(adapter, &cmd);
1531         if (status)
1532                 dev_err(&adapter->pdev->dev,
1533                         "Failed to %s in NIC IDC function event.\n",
1534                         (enable ? "register" : "unregister"));
1535
1536         qlcnic_free_mbx_args(&cmd);
1537 }
1538
1539 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1540 {
1541         struct qlcnic_cmd_args cmd;
1542         int err;
1543
1544         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1545         if (err)
1546                 return err;
1547
1548         cmd.req.arg[1] = adapter->ahw->port_config;
1549         err = qlcnic_issue_cmd(adapter, &cmd);
1550         if (err)
1551                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1552         qlcnic_free_mbx_args(&cmd);
1553         return err;
1554 }
1555
1556 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1557 {
1558         struct qlcnic_cmd_args cmd;
1559         int err;
1560
1561         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1562         if (err)
1563                 return err;
1564
1565         err = qlcnic_issue_cmd(adapter, &cmd);
1566         if (err)
1567                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1568         else
1569                 adapter->ahw->port_config = cmd.rsp.arg[1];
1570         qlcnic_free_mbx_args(&cmd);
1571         return err;
1572 }
1573
1574 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1575 {
1576         int err;
1577         u32 temp;
1578         struct qlcnic_cmd_args cmd;
1579
1580         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1581         if (err)
1582                 return err;
1583
1584         temp = adapter->recv_ctx->context_id << 16;
1585         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1586         err = qlcnic_issue_cmd(adapter, &cmd);
1587         if (err)
1588                 dev_info(&adapter->pdev->dev,
1589                          "Setup linkevent mailbox failed\n");
1590         qlcnic_free_mbx_args(&cmd);
1591         return err;
1592 }
1593
1594 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1595                                                  u32 *interface_id)
1596 {
1597         if (qlcnic_sriov_pf_check(adapter)) {
1598                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1599         } else {
1600                 if (!qlcnic_sriov_vf_check(adapter))
1601                         *interface_id = adapter->recv_ctx->context_id << 16;
1602         }
1603 }
1604
1605 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1606 {
1607         struct qlcnic_cmd_args *cmd = NULL;
1608         u32 temp = 0;
1609         int err;
1610
1611         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1612                 return -EIO;
1613
1614         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1615         if (!cmd)
1616                 return -ENOMEM;
1617
1618         err = qlcnic_alloc_mbx_args(cmd, adapter,
1619                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1620         if (err)
1621                 goto out;
1622
1623         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1624         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1625         cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1626         err = qlcnic_issue_cmd(adapter, cmd);
1627         if (!err)
1628                 return err;
1629
1630         qlcnic_free_mbx_args(cmd);
1631
1632 out:
1633         kfree(cmd);
1634         return err;
1635 }
1636
1637 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1638 {
1639         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1640         struct qlcnic_hardware_context *ahw = adapter->ahw;
1641         int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1642
1643         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1644                 netdev_warn(netdev,
1645                             "Loopback test not supported in non privileged mode\n");
1646                 return -ENOTSUPP;
1647         }
1648
1649         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1650                 netdev_info(netdev, "Device is resetting\n");
1651                 return -EBUSY;
1652         }
1653
1654         if (qlcnic_get_diag_lock(adapter)) {
1655                 netdev_info(netdev, "Device is in diagnostics mode\n");
1656                 return -EBUSY;
1657         }
1658
1659         netdev_info(netdev, "%s loopback test in progress\n",
1660                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1661
1662         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1663                                          max_sds_rings);
1664         if (ret)
1665                 goto fail_diag_alloc;
1666
1667         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1668         if (ret)
1669                 goto free_diag_res;
1670
1671         /* Poll for link up event before running traffic */
1672         do {
1673                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1674
1675                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1676                         netdev_info(netdev,
1677                                     "Device is resetting, free LB test resources\n");
1678                         ret = -EBUSY;
1679                         goto free_diag_res;
1680                 }
1681                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1682                         netdev_info(netdev,
1683                                     "Firmware didn't sent link up event to loopback request\n");
1684                         ret = -ETIMEDOUT;
1685                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1686                         goto free_diag_res;
1687                 }
1688         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1689
1690         /* Make sure carrier is off and queue is stopped during loopback */
1691         if (netif_running(netdev)) {
1692                 netif_carrier_off(netdev);
1693                 netif_stop_queue(netdev);
1694         }
1695
1696         ret = qlcnic_do_lb_test(adapter, mode);
1697
1698         qlcnic_83xx_clear_lb_mode(adapter, mode);
1699
1700 free_diag_res:
1701         qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1702
1703 fail_diag_alloc:
1704         adapter->max_sds_rings = max_sds_rings;
1705         qlcnic_release_diag_lock(adapter);
1706         return ret;
1707 }
1708
1709 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1710 {
1711         struct qlcnic_hardware_context *ahw = adapter->ahw;
1712         struct net_device *netdev = adapter->netdev;
1713         int status = 0, loop = 0;
1714         u32 config;
1715
1716         status = qlcnic_83xx_get_port_config(adapter);
1717         if (status)
1718                 return status;
1719
1720         config = ahw->port_config;
1721
1722         /* Check if port is already in loopback mode */
1723         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1724             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1725                 netdev_err(netdev,
1726                            "Port already in Loopback mode.\n");
1727                 return -EINPROGRESS;
1728         }
1729
1730         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1731
1732         if (mode == QLCNIC_ILB_MODE)
1733                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1734         if (mode == QLCNIC_ELB_MODE)
1735                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1736
1737         status = qlcnic_83xx_set_port_config(adapter);
1738         if (status) {
1739                 netdev_err(netdev,
1740                            "Failed to Set Loopback Mode = 0x%x.\n",
1741                            ahw->port_config);
1742                 ahw->port_config = config;
1743                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1744                 return status;
1745         }
1746
1747         /* Wait for Link and IDC Completion AEN */
1748         do {
1749                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1750
1751                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1752                         netdev_info(netdev,
1753                                     "Device is resetting, free LB test resources\n");
1754                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1755                         return -EBUSY;
1756                 }
1757                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1758                         netdev_err(netdev,
1759                                    "Did not receive IDC completion AEN\n");
1760                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1761                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1762                         return -ETIMEDOUT;
1763                 }
1764         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1765
1766         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1767                                   QLCNIC_MAC_ADD);
1768         return status;
1769 }
1770
1771 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1772 {
1773         struct qlcnic_hardware_context *ahw = adapter->ahw;
1774         struct net_device *netdev = adapter->netdev;
1775         int status = 0, loop = 0;
1776         u32 config = ahw->port_config;
1777
1778         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1779         if (mode == QLCNIC_ILB_MODE)
1780                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1781         if (mode == QLCNIC_ELB_MODE)
1782                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1783
1784         status = qlcnic_83xx_set_port_config(adapter);
1785         if (status) {
1786                 netdev_err(netdev,
1787                            "Failed to Clear Loopback Mode = 0x%x.\n",
1788                            ahw->port_config);
1789                 ahw->port_config = config;
1790                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1791                 return status;
1792         }
1793
1794         /* Wait for Link and IDC Completion AEN */
1795         do {
1796                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1797
1798                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1799                         netdev_info(netdev,
1800                                     "Device is resetting, free LB test resources\n");
1801                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1802                         return -EBUSY;
1803                 }
1804
1805                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1806                         netdev_err(netdev,
1807                                    "Did not receive IDC completion AEN\n");
1808                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1809                         return -ETIMEDOUT;
1810                 }
1811         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1812
1813         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1814                                   QLCNIC_MAC_DEL);
1815         return status;
1816 }
1817
1818 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1819                                                 u32 *interface_id)
1820 {
1821         if (qlcnic_sriov_pf_check(adapter)) {
1822                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1823         } else {
1824                 if (!qlcnic_sriov_vf_check(adapter))
1825                         *interface_id = adapter->recv_ctx->context_id << 16;
1826         }
1827 }
1828
1829 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1830                                int mode)
1831 {
1832         int err;
1833         u32 temp = 0, temp_ip;
1834         struct qlcnic_cmd_args cmd;
1835
1836         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1837                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1838         if (err)
1839                 return;
1840
1841         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1842
1843         if (mode == QLCNIC_IP_UP)
1844                 cmd.req.arg[1] = 1 | temp;
1845         else
1846                 cmd.req.arg[1] = 2 | temp;
1847
1848         /*
1849          * Adapter needs IP address in network byte order.
1850          * But hardware mailbox registers go through writel(), hence IP address
1851          * gets swapped on big endian architecture.
1852          * To negate swapping of writel() on big endian architecture
1853          * use swab32(value).
1854          */
1855
1856         temp_ip = swab32(ntohl(ip));
1857         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1858         err = qlcnic_issue_cmd(adapter, &cmd);
1859         if (err != QLCNIC_RCODE_SUCCESS)
1860                 dev_err(&adapter->netdev->dev,
1861                         "could not notify %s IP 0x%x request\n",
1862                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1863
1864         qlcnic_free_mbx_args(&cmd);
1865 }
1866
1867 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1868 {
1869         int err;
1870         u32 temp, arg1;
1871         struct qlcnic_cmd_args cmd;
1872         int lro_bit_mask;
1873
1874         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1875
1876         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1877                 return 0;
1878
1879         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1880         if (err)
1881                 return err;
1882
1883         temp = adapter->recv_ctx->context_id << 16;
1884         arg1 = lro_bit_mask | temp;
1885         cmd.req.arg[1] = arg1;
1886
1887         err = qlcnic_issue_cmd(adapter, &cmd);
1888         if (err)
1889                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1890         qlcnic_free_mbx_args(&cmd);
1891
1892         return err;
1893 }
1894
1895 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1896 {
1897         int err;
1898         u32 word;
1899         struct qlcnic_cmd_args cmd;
1900         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1901                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1902                             0x255b0ec26d5a56daULL };
1903
1904         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1905         if (err)
1906                 return err;
1907         /*
1908          * RSS request:
1909          * bits 3-0: Rsvd
1910          *      5-4: hash_type_ipv4
1911          *      7-6: hash_type_ipv6
1912          *        8: enable
1913          *        9: use indirection table
1914          *    16-31: indirection table mask
1915          */
1916         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1917                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1918                 ((u32)(enable & 0x1) << 8) |
1919                 ((0x7ULL) << 16);
1920         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1921         cmd.req.arg[2] = word;
1922         memcpy(&cmd.req.arg[4], key, sizeof(key));
1923
1924         err = qlcnic_issue_cmd(adapter, &cmd);
1925
1926         if (err)
1927                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1928         qlcnic_free_mbx_args(&cmd);
1929
1930         return err;
1931
1932 }
1933
1934 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1935                                                  u32 *interface_id)
1936 {
1937         if (qlcnic_sriov_pf_check(adapter)) {
1938                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1939         } else {
1940                 if (!qlcnic_sriov_vf_check(adapter))
1941                         *interface_id = adapter->recv_ctx->context_id << 16;
1942         }
1943 }
1944
1945 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1946                                    u16 vlan_id, u8 op)
1947 {
1948         struct qlcnic_cmd_args *cmd = NULL;
1949         struct qlcnic_macvlan_mbx mv;
1950         u32 *buf, temp = 0;
1951         int err;
1952
1953         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1954                 return -EIO;
1955
1956         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1957         if (!cmd)
1958                 return -ENOMEM;
1959
1960         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1961         if (err)
1962                 goto out;
1963
1964         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1965
1966         if (vlan_id)
1967                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1968                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1969
1970         cmd->req.arg[1] = op | (1 << 8);
1971         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1972         cmd->req.arg[1] |= temp;
1973         mv.vlan = vlan_id;
1974         mv.mac_addr0 = addr[0];
1975         mv.mac_addr1 = addr[1];
1976         mv.mac_addr2 = addr[2];
1977         mv.mac_addr3 = addr[3];
1978         mv.mac_addr4 = addr[4];
1979         mv.mac_addr5 = addr[5];
1980         buf = &cmd->req.arg[2];
1981         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1982         err = qlcnic_issue_cmd(adapter, cmd);
1983         if (!err)
1984                 return err;
1985
1986         qlcnic_free_mbx_args(cmd);
1987 out:
1988         kfree(cmd);
1989         return err;
1990 }
1991
1992 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1993                                   u16 vlan_id)
1994 {
1995         u8 mac[ETH_ALEN];
1996         memcpy(&mac, addr, ETH_ALEN);
1997         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1998 }
1999
2000 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2001                                u8 type, struct qlcnic_cmd_args *cmd)
2002 {
2003         switch (type) {
2004         case QLCNIC_SET_STATION_MAC:
2005         case QLCNIC_SET_FAC_DEF_MAC:
2006                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2007                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2008                 break;
2009         }
2010         cmd->req.arg[1] = type;
2011 }
2012
2013 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
2014 {
2015         int err, i;
2016         struct qlcnic_cmd_args cmd;
2017         u32 mac_low, mac_high;
2018
2019         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2020         if (err)
2021                 return err;
2022
2023         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2024         err = qlcnic_issue_cmd(adapter, &cmd);
2025
2026         if (err == QLCNIC_RCODE_SUCCESS) {
2027                 mac_low = cmd.rsp.arg[1];
2028                 mac_high = cmd.rsp.arg[2];
2029
2030                 for (i = 0; i < 2; i++)
2031                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2032                 for (i = 2; i < 6; i++)
2033                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2034         } else {
2035                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2036                         err);
2037                 err = -EIO;
2038         }
2039         qlcnic_free_mbx_args(&cmd);
2040         return err;
2041 }
2042
2043 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2044 {
2045         int err;
2046         u16 temp;
2047         struct qlcnic_cmd_args cmd;
2048         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2049
2050         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2051                 return;
2052
2053         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2054         if (err)
2055                 return;
2056
2057         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2058                 temp = adapter->recv_ctx->context_id;
2059                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2060                 temp = coal->rx_time_us;
2061                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2062         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2063                 temp = adapter->tx_ring->ctx_id;
2064                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2065                 temp = coal->tx_time_us;
2066                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2067         }
2068         cmd.req.arg[3] = coal->flag;
2069         err = qlcnic_issue_cmd(adapter, &cmd);
2070         if (err != QLCNIC_RCODE_SUCCESS)
2071                 dev_info(&adapter->pdev->dev,
2072                          "Failed to send interrupt coalescence parameters\n");
2073         qlcnic_free_mbx_args(&cmd);
2074 }
2075
2076 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2077                                         u32 data[])
2078 {
2079         struct qlcnic_hardware_context *ahw = adapter->ahw;
2080         u8 link_status, duplex;
2081         /* link speed */
2082         link_status = LSB(data[3]) & 1;
2083         if (link_status) {
2084                 ahw->link_speed = MSW(data[2]);
2085                 duplex = LSB(MSW(data[3]));
2086                 if (duplex)
2087                         ahw->link_duplex = DUPLEX_FULL;
2088                 else
2089                         ahw->link_duplex = DUPLEX_HALF;
2090         } else {
2091                 ahw->link_speed = SPEED_UNKNOWN;
2092                 ahw->link_duplex = DUPLEX_UNKNOWN;
2093         }
2094
2095         ahw->link_autoneg = MSB(MSW(data[3]));
2096         ahw->module_type = MSB(LSW(data[3]));
2097         ahw->has_link_events = 1;
2098         qlcnic_advert_link_change(adapter, link_status);
2099 }
2100
2101 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2102 {
2103         struct qlcnic_adapter *adapter = data;
2104         struct qlcnic_mailbox *mbx;
2105         u32 mask, resp, event;
2106         unsigned long flags;
2107
2108         mbx = adapter->ahw->mailbox;
2109         spin_lock_irqsave(&mbx->aen_lock, flags);
2110         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2111         if (!(resp & QLCNIC_SET_OWNER))
2112                 goto out;
2113
2114         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2115         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2116                 __qlcnic_83xx_process_aen(adapter);
2117         else
2118                 qlcnic_83xx_notify_mbx_response(mbx);
2119
2120 out:
2121         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2122         writel(0, adapter->ahw->pci_base0 + mask);
2123         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2124         return IRQ_HANDLED;
2125 }
2126
2127 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2128 {
2129         int err = -EIO;
2130         struct qlcnic_cmd_args cmd;
2131
2132         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2133                 dev_err(&adapter->pdev->dev,
2134                         "%s: Error, invoked by non management func\n",
2135                         __func__);
2136                 return err;
2137         }
2138
2139         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2140         if (err)
2141                 return err;
2142
2143         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2144         err = qlcnic_issue_cmd(adapter, &cmd);
2145
2146         if (err != QLCNIC_RCODE_SUCCESS) {
2147                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2148                         err);
2149                 err = -EIO;
2150         }
2151         qlcnic_free_mbx_args(&cmd);
2152
2153         return err;
2154
2155 }
2156
2157 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2158                              struct qlcnic_info *nic)
2159 {
2160         int i, err = -EIO;
2161         struct qlcnic_cmd_args cmd;
2162
2163         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2164                 dev_err(&adapter->pdev->dev,
2165                         "%s: Error, invoked by non management func\n",
2166                         __func__);
2167                 return err;
2168         }
2169
2170         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2171         if (err)
2172                 return err;
2173
2174         cmd.req.arg[1] = (nic->pci_func << 16);
2175         cmd.req.arg[2] = 0x1 << 16;
2176         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2177         cmd.req.arg[4] = nic->capabilities;
2178         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2179         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2180         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2181         for (i = 8; i < 32; i++)
2182                 cmd.req.arg[i] = 0;
2183
2184         err = qlcnic_issue_cmd(adapter, &cmd);
2185
2186         if (err != QLCNIC_RCODE_SUCCESS) {
2187                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2188                         err);
2189                 err = -EIO;
2190         }
2191
2192         qlcnic_free_mbx_args(&cmd);
2193
2194         return err;
2195 }
2196
2197 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2198                              struct qlcnic_info *npar_info, u8 func_id)
2199 {
2200         int err;
2201         u32 temp;
2202         u8 op = 0;
2203         struct qlcnic_cmd_args cmd;
2204         struct qlcnic_hardware_context *ahw = adapter->ahw;
2205
2206         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2207         if (err)
2208                 return err;
2209
2210         if (func_id != ahw->pci_func) {
2211                 temp = func_id << 16;
2212                 cmd.req.arg[1] = op | BIT_31 | temp;
2213         } else {
2214                 cmd.req.arg[1] = ahw->pci_func << 16;
2215         }
2216         err = qlcnic_issue_cmd(adapter, &cmd);
2217         if (err) {
2218                 dev_info(&adapter->pdev->dev,
2219                          "Failed to get nic info %d\n", err);
2220                 goto out;
2221         }
2222
2223         npar_info->op_type = cmd.rsp.arg[1];
2224         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2225         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2226         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2227         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2228         npar_info->capabilities = cmd.rsp.arg[4];
2229         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2230         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2231         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2232         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2233         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2234         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2235         if (cmd.rsp.arg[8] & 0x1)
2236                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2237         if (cmd.rsp.arg[8] & 0x10000) {
2238                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2239                 npar_info->max_linkspeed_reg_offset = temp;
2240         }
2241         if (npar_info->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS)
2242                 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2243                        sizeof(ahw->extra_capability));
2244
2245 out:
2246         qlcnic_free_mbx_args(&cmd);
2247         return err;
2248 }
2249
2250 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2251                              struct qlcnic_pci_info *pci_info)
2252 {
2253         struct qlcnic_hardware_context *ahw = adapter->ahw;
2254         struct device *dev = &adapter->pdev->dev;
2255         struct qlcnic_cmd_args cmd;
2256         int i, err = 0, j = 0;
2257         u32 temp;
2258
2259         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2260         if (err)
2261                 return err;
2262
2263         err = qlcnic_issue_cmd(adapter, &cmd);
2264
2265         ahw->act_pci_func = 0;
2266         if (err == QLCNIC_RCODE_SUCCESS) {
2267                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2268                 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2269                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2270                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2271                         i++;
2272                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2273                         if (pci_info->type == QLCNIC_TYPE_NIC)
2274                                 ahw->act_pci_func++;
2275                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2276                         pci_info->default_port = temp;
2277                         i++;
2278                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2279                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2280                         pci_info->tx_max_bw = temp;
2281                         i = i + 2;
2282                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2283                         i++;
2284                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2285                         i = i + 3;
2286                         if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2287                                 dev_info(dev, "id = %d active = %d type = %d\n"
2288                                          "\tport = %d min bw = %d max bw = %d\n"
2289                                          "\tmac_addr =  %pM\n", pci_info->id,
2290                                          pci_info->active, pci_info->type,
2291                                          pci_info->default_port,
2292                                          pci_info->tx_min_bw,
2293                                          pci_info->tx_max_bw, pci_info->mac);
2294                 }
2295                 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2296                         dev_info(dev, "Max vNIC functions = %d, active vNIC functions = %d\n",
2297                                  ahw->max_pci_func, ahw->act_pci_func);
2298
2299         } else {
2300                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2301                 err = -EIO;
2302         }
2303
2304         qlcnic_free_mbx_args(&cmd);
2305
2306         return err;
2307 }
2308
2309 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2310 {
2311         int i, index, err;
2312         u8 max_ints;
2313         u32 val, temp, type;
2314         struct qlcnic_cmd_args cmd;
2315
2316         max_ints = adapter->ahw->num_msix - 1;
2317         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2318         if (err)
2319                 return err;
2320
2321         cmd.req.arg[1] = max_ints;
2322
2323         if (qlcnic_sriov_vf_check(adapter))
2324                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2325
2326         for (i = 0, index = 2; i < max_ints; i++) {
2327                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2328                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2329                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2330                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2331                 cmd.req.arg[index++] = val;
2332         }
2333         err = qlcnic_issue_cmd(adapter, &cmd);
2334         if (err) {
2335                 dev_err(&adapter->pdev->dev,
2336                         "Failed to configure interrupts 0x%x\n", err);
2337                 goto out;
2338         }
2339
2340         max_ints = cmd.rsp.arg[1];
2341         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2342                 val = cmd.rsp.arg[index];
2343                 if (LSB(val)) {
2344                         dev_info(&adapter->pdev->dev,
2345                                  "Can't configure interrupt %d\n",
2346                                  adapter->ahw->intr_tbl[i].id);
2347                         continue;
2348                 }
2349                 if (op_type) {
2350                         adapter->ahw->intr_tbl[i].id = MSW(val);
2351                         adapter->ahw->intr_tbl[i].enabled = 1;
2352                         temp = cmd.rsp.arg[index + 1];
2353                         adapter->ahw->intr_tbl[i].src = temp;
2354                 } else {
2355                         adapter->ahw->intr_tbl[i].id = i;
2356                         adapter->ahw->intr_tbl[i].enabled = 0;
2357                         adapter->ahw->intr_tbl[i].src = 0;
2358                 }
2359         }
2360 out:
2361         qlcnic_free_mbx_args(&cmd);
2362         return err;
2363 }
2364
2365 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2366 {
2367         int id, timeout = 0;
2368         u32 status = 0;
2369
2370         while (status == 0) {
2371                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2372                 if (status)
2373                         break;
2374
2375                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2376                         id = QLC_SHARED_REG_RD32(adapter,
2377                                                  QLCNIC_FLASH_LOCK_OWNER);
2378                         dev_err(&adapter->pdev->dev,
2379                                 "%s: failed, lock held by %d\n", __func__, id);
2380                         return -EIO;
2381                 }
2382                 usleep_range(1000, 2000);
2383         }
2384
2385         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2386         return 0;
2387 }
2388
2389 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2390 {
2391         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2392         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2393 }
2394
2395 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2396                                       u32 flash_addr, u8 *p_data,
2397                                       int count)
2398 {
2399         u32 word, range, flash_offset, addr = flash_addr, ret;
2400         ulong indirect_add, direct_window;
2401         int i, err = 0;
2402
2403         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2404         if (addr & 0x3) {
2405                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2406                 return -EIO;
2407         }
2408
2409         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2410                                      (addr));
2411
2412         range = flash_offset + (count * sizeof(u32));
2413         /* Check if data is spread across multiple sectors */
2414         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2415
2416                 /* Multi sector read */
2417                 for (i = 0; i < count; i++) {
2418                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2419                         ret = QLCRD32(adapter, indirect_add, &err);
2420                         if (err == -EIO)
2421                                 return err;
2422
2423                         word = ret;
2424                         *(u32 *)p_data  = word;
2425                         p_data = p_data + 4;
2426                         addr = addr + 4;
2427                         flash_offset = flash_offset + 4;
2428
2429                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2430                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2431                                 /* This write is needed once for each sector */
2432                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2433                                                              direct_window,
2434                                                              (addr));
2435                                 flash_offset = 0;
2436                         }
2437                 }
2438         } else {
2439                 /* Single sector read */
2440                 for (i = 0; i < count; i++) {
2441                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2442                         ret = QLCRD32(adapter, indirect_add, &err);
2443                         if (err == -EIO)
2444                                 return err;
2445
2446                         word = ret;
2447                         *(u32 *)p_data  = word;
2448                         p_data = p_data + 4;
2449                         addr = addr + 4;
2450                 }
2451         }
2452
2453         return 0;
2454 }
2455
2456 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2457 {
2458         u32 status;
2459         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2460         int err = 0;
2461
2462         do {
2463                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2464                 if (err == -EIO)
2465                         return err;
2466
2467                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2468                     QLC_83XX_FLASH_STATUS_READY)
2469                         break;
2470
2471                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2472         } while (--retries);
2473
2474         if (!retries)
2475                 return -EIO;
2476
2477         return 0;
2478 }
2479
2480 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2481 {
2482         int ret;
2483         u32 cmd;
2484         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2485         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2486                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2487         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2488                                      adapter->ahw->fdt.write_enable_bits);
2489         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2490                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2491         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2492         if (ret)
2493                 return -EIO;
2494
2495         return 0;
2496 }
2497
2498 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2499 {
2500         int ret;
2501
2502         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2503                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2504                                      adapter->ahw->fdt.write_statusreg_cmd));
2505         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2506                                      adapter->ahw->fdt.write_disable_bits);
2507         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2508                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2509         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2510         if (ret)
2511                 return -EIO;
2512
2513         return 0;
2514 }
2515
2516 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2517 {
2518         int ret, err = 0;
2519         u32 mfg_id;
2520
2521         if (qlcnic_83xx_lock_flash(adapter))
2522                 return -EIO;
2523
2524         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2525                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2526         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2527                                      QLC_83XX_FLASH_READ_CTRL);
2528         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2529         if (ret) {
2530                 qlcnic_83xx_unlock_flash(adapter);
2531                 return -EIO;
2532         }
2533
2534         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2535         if (err == -EIO) {
2536                 qlcnic_83xx_unlock_flash(adapter);
2537                 return err;
2538         }
2539
2540         adapter->flash_mfg_id = (mfg_id & 0xFF);
2541         qlcnic_83xx_unlock_flash(adapter);
2542
2543         return 0;
2544 }
2545
2546 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2547 {
2548         int count, fdt_size, ret = 0;
2549
2550         fdt_size = sizeof(struct qlcnic_fdt);
2551         count = fdt_size / sizeof(u32);
2552
2553         if (qlcnic_83xx_lock_flash(adapter))
2554                 return -EIO;
2555
2556         memset(&adapter->ahw->fdt, 0, fdt_size);
2557         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2558                                                 (u8 *)&adapter->ahw->fdt,
2559                                                 count);
2560
2561         qlcnic_83xx_unlock_flash(adapter);
2562         return ret;
2563 }
2564
2565 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2566                                    u32 sector_start_addr)
2567 {
2568         u32 reversed_addr, addr1, addr2, cmd;
2569         int ret = -EIO;
2570
2571         if (qlcnic_83xx_lock_flash(adapter) != 0)
2572                 return -EIO;
2573
2574         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2575                 ret = qlcnic_83xx_enable_flash_write(adapter);
2576                 if (ret) {
2577                         qlcnic_83xx_unlock_flash(adapter);
2578                         dev_err(&adapter->pdev->dev,
2579                                 "%s failed at %d\n",
2580                                 __func__, __LINE__);
2581                         return ret;
2582                 }
2583         }
2584
2585         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2586         if (ret) {
2587                 qlcnic_83xx_unlock_flash(adapter);
2588                 dev_err(&adapter->pdev->dev,
2589                         "%s: failed at %d\n", __func__, __LINE__);
2590                 return -EIO;
2591         }
2592
2593         addr1 = (sector_start_addr & 0xFF) << 16;
2594         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2595         reversed_addr = addr1 | addr2;
2596
2597         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2598                                      reversed_addr);
2599         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2600         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2601                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2602         else
2603                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2604                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2605         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2606                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2607
2608         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2609         if (ret) {
2610                 qlcnic_83xx_unlock_flash(adapter);
2611                 dev_err(&adapter->pdev->dev,
2612                         "%s: failed at %d\n", __func__, __LINE__);
2613                 return -EIO;
2614         }
2615
2616         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2617                 ret = qlcnic_83xx_disable_flash_write(adapter);
2618                 if (ret) {
2619                         qlcnic_83xx_unlock_flash(adapter);
2620                         dev_err(&adapter->pdev->dev,
2621                                 "%s: failed at %d\n", __func__, __LINE__);
2622                         return ret;
2623                 }
2624         }
2625
2626         qlcnic_83xx_unlock_flash(adapter);
2627
2628         return 0;
2629 }
2630
2631 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2632                               u32 *p_data)
2633 {
2634         int ret = -EIO;
2635         u32 addr1 = 0x00800000 | (addr >> 2);
2636
2637         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2638         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2639         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2640                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2641         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2642         if (ret) {
2643                 dev_err(&adapter->pdev->dev,
2644                         "%s: failed at %d\n", __func__, __LINE__);
2645                 return -EIO;
2646         }
2647
2648         return 0;
2649 }
2650
2651 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2652                                  u32 *p_data, int count)
2653 {
2654         u32 temp;
2655         int ret = -EIO, err = 0;
2656
2657         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2658             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2659                 dev_err(&adapter->pdev->dev,
2660                         "%s: Invalid word count\n", __func__);
2661                 return -EIO;
2662         }
2663
2664         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2665         if (err == -EIO)
2666                 return err;
2667
2668         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2669                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2670         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2671                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2672
2673         /* First DWORD write */
2674         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2675         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2676                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2677         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2678         if (ret) {
2679                 dev_err(&adapter->pdev->dev,
2680                         "%s: failed at %d\n", __func__, __LINE__);
2681                 return -EIO;
2682         }
2683
2684         count--;
2685         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2686                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2687         /* Second to N-1 DWORD writes */
2688         while (count != 1) {
2689                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2690                                              *p_data++);
2691                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2692                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2693                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2694                 if (ret) {
2695                         dev_err(&adapter->pdev->dev,
2696                                 "%s: failed at %d\n", __func__, __LINE__);
2697                         return -EIO;
2698                 }
2699                 count--;
2700         }
2701
2702         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2703                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2704                                      (addr >> 2));
2705         /* Last DWORD write */
2706         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2707         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2708                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2709         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2710         if (ret) {
2711                 dev_err(&adapter->pdev->dev,
2712                         "%s: failed at %d\n", __func__, __LINE__);
2713                 return -EIO;
2714         }
2715
2716         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2717         if (err == -EIO)
2718                 return err;
2719
2720         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2721                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2722                         __func__, __LINE__);
2723                 /* Operation failed, clear error bit */
2724                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2725                 if (err == -EIO)
2726                         return err;
2727
2728                 qlcnic_83xx_wrt_reg_indirect(adapter,
2729                                              QLC_83XX_FLASH_SPI_CONTROL,
2730                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2731         }
2732
2733         return 0;
2734 }
2735
2736 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2737 {
2738         u32 val, id;
2739
2740         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2741
2742         /* Check if recovery need to be performed by the calling function */
2743         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2744                 val = val & ~0x3F;
2745                 val = val | ((adapter->portnum << 2) |
2746                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2747                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2748                 dev_info(&adapter->pdev->dev,
2749                          "%s: lock recovery initiated\n", __func__);
2750                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2751                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2752                 id = ((val >> 2) & 0xF);
2753                 if (id == adapter->portnum) {
2754                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2755                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2756                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2757                         /* Force release the lock */
2758                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2759                         /* Clear recovery bits */
2760                         val = val & ~0x3F;
2761                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2762                         dev_info(&adapter->pdev->dev,
2763                                  "%s: lock recovery completed\n", __func__);
2764                 } else {
2765                         dev_info(&adapter->pdev->dev,
2766                                  "%s: func %d to resume lock recovery process\n",
2767                                  __func__, id);
2768                 }
2769         } else {
2770                 dev_info(&adapter->pdev->dev,
2771                          "%s: lock recovery initiated by other functions\n",
2772                          __func__);
2773         }
2774 }
2775
2776 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2777 {
2778         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2779         int max_attempt = 0;
2780
2781         while (status == 0) {
2782                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2783                 if (status)
2784                         break;
2785
2786                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2787                 i++;
2788
2789                 if (i == 1)
2790                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2791
2792                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2793                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2794                         if (val == temp) {
2795                                 id = val & 0xFF;
2796                                 dev_info(&adapter->pdev->dev,
2797                                          "%s: lock to be recovered from %d\n",
2798                                          __func__, id);
2799                                 qlcnic_83xx_recover_driver_lock(adapter);
2800                                 i = 0;
2801                                 max_attempt++;
2802                         } else {
2803                                 dev_err(&adapter->pdev->dev,
2804                                         "%s: failed to get lock\n", __func__);
2805                                 return -EIO;
2806                         }
2807                 }
2808
2809                 /* Force exit from while loop after few attempts */
2810                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2811                         dev_err(&adapter->pdev->dev,
2812                                 "%s: failed to get lock\n", __func__);
2813                         return -EIO;
2814                 }
2815         }
2816
2817         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2818         lock_alive_counter = val >> 8;
2819         lock_alive_counter++;
2820         val = lock_alive_counter << 8 | adapter->portnum;
2821         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2822
2823         return 0;
2824 }
2825
2826 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2827 {
2828         u32 val, lock_alive_counter, id;
2829
2830         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2831         id = val & 0xFF;
2832         lock_alive_counter = val >> 8;
2833
2834         if (id != adapter->portnum)
2835                 dev_err(&adapter->pdev->dev,
2836                         "%s:Warning func %d is unlocking lock owned by %d\n",
2837                         __func__, adapter->portnum, id);
2838
2839         val = (lock_alive_counter << 8) | 0xFF;
2840         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2841         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2842 }
2843
2844 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2845                                 u32 *data, u32 count)
2846 {
2847         int i, j, ret = 0;
2848         u32 temp;
2849         int err = 0;
2850
2851         /* Check alignment */
2852         if (addr & 0xF)
2853                 return -EIO;
2854
2855         mutex_lock(&adapter->ahw->mem_lock);
2856         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2857
2858         for (i = 0; i < count; i++, addr += 16) {
2859                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2860                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2861                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2862                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2863                         mutex_unlock(&adapter->ahw->mem_lock);
2864                         return -EIO;
2865                 }
2866
2867                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2868                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2869                                              *data++);
2870                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2871                                              *data++);
2872                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2873                                              *data++);
2874                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2875                                              *data++);
2876                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2877                                              QLCNIC_TA_WRITE_ENABLE);
2878                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2879                                              QLCNIC_TA_WRITE_START);
2880
2881                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2882                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2883                         if (err == -EIO) {
2884                                 mutex_unlock(&adapter->ahw->mem_lock);
2885                                 return err;
2886                         }
2887
2888                         if ((temp & TA_CTL_BUSY) == 0)
2889                                 break;
2890                 }
2891
2892                 /* Status check failure */
2893                 if (j >= MAX_CTL_CHECK) {
2894                         printk_ratelimited(KERN_WARNING
2895                                            "MS memory write failed\n");
2896                         mutex_unlock(&adapter->ahw->mem_lock);
2897                         return -EIO;
2898                 }
2899         }
2900
2901         mutex_unlock(&adapter->ahw->mem_lock);
2902
2903         return ret;
2904 }
2905
2906 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2907                              u8 *p_data, int count)
2908 {
2909         u32 word, addr = flash_addr, ret;
2910         ulong  indirect_addr;
2911         int i, err = 0;
2912
2913         if (qlcnic_83xx_lock_flash(adapter) != 0)
2914                 return -EIO;
2915
2916         if (addr & 0x3) {
2917                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2918                 qlcnic_83xx_unlock_flash(adapter);
2919                 return -EIO;
2920         }
2921
2922         for (i = 0; i < count; i++) {
2923                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2924                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2925                                                  (addr))) {
2926                         qlcnic_83xx_unlock_flash(adapter);
2927                         return -EIO;
2928                 }
2929
2930                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2931                 ret = QLCRD32(adapter, indirect_addr, &err);
2932                 if (err == -EIO)
2933                         return err;
2934
2935                 word = ret;
2936                 *(u32 *)p_data  = word;
2937                 p_data = p_data + 4;
2938                 addr = addr + 4;
2939         }
2940
2941         qlcnic_83xx_unlock_flash(adapter);
2942
2943         return 0;
2944 }
2945
2946 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2947 {
2948         u8 pci_func;
2949         int err;
2950         u32 config = 0, state;
2951         struct qlcnic_cmd_args cmd;
2952         struct qlcnic_hardware_context *ahw = adapter->ahw;
2953
2954         if (qlcnic_sriov_vf_check(adapter))
2955                 pci_func = adapter->portnum;
2956         else
2957                 pci_func = ahw->pci_func;
2958
2959         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2960         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2961                 dev_info(&adapter->pdev->dev, "link state down\n");
2962                 return config;
2963         }
2964
2965         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2966         if (err)
2967                 return err;
2968
2969         err = qlcnic_issue_cmd(adapter, &cmd);
2970         if (err) {
2971                 dev_info(&adapter->pdev->dev,
2972                          "Get Link Status Command failed: 0x%x\n", err);
2973                 goto out;
2974         } else {
2975                 config = cmd.rsp.arg[1];
2976                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2977                 case QLC_83XX_10M_LINK:
2978                         ahw->link_speed = SPEED_10;
2979                         break;
2980                 case QLC_83XX_100M_LINK:
2981                         ahw->link_speed = SPEED_100;
2982                         break;
2983                 case QLC_83XX_1G_LINK:
2984                         ahw->link_speed = SPEED_1000;
2985                         break;
2986                 case QLC_83XX_10G_LINK:
2987                         ahw->link_speed = SPEED_10000;
2988                         break;
2989                 default:
2990                         ahw->link_speed = 0;
2991                         break;
2992                 }
2993                 config = cmd.rsp.arg[3];
2994                 if (QLC_83XX_SFP_PRESENT(config)) {
2995                         switch (ahw->module_type) {
2996                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
2997                         case LINKEVENT_MODULE_OPTICAL_SRLR:
2998                         case LINKEVENT_MODULE_OPTICAL_LRM:
2999                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3000                                 ahw->supported_type = PORT_FIBRE;
3001                                 break;
3002                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3003                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3004                         case LINKEVENT_MODULE_TWINAX:
3005                                 ahw->supported_type = PORT_TP;
3006                                 break;
3007                         default:
3008                                 ahw->supported_type = PORT_OTHER;
3009                         }
3010                 }
3011                 if (config & 1)
3012                         err = 1;
3013         }
3014 out:
3015         qlcnic_free_mbx_args(&cmd);
3016         return config;
3017 }
3018
3019 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3020                              struct ethtool_cmd *ecmd)
3021 {
3022         u32 config = 0;
3023         int status = 0;
3024         struct qlcnic_hardware_context *ahw = adapter->ahw;
3025
3026         /* Get port configuration info */
3027         status = qlcnic_83xx_get_port_info(adapter);
3028         /* Get Link Status related info */
3029         config = qlcnic_83xx_test_link(adapter);
3030         ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3031         /* hard code until there is a way to get it from flash */
3032         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3033
3034         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3035                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3036                 ecmd->duplex = ahw->link_duplex;
3037                 ecmd->autoneg = ahw->link_autoneg;
3038         } else {
3039                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3040                 ecmd->duplex = DUPLEX_UNKNOWN;
3041                 ecmd->autoneg = AUTONEG_DISABLE;
3042         }
3043
3044         if (ahw->port_type == QLCNIC_XGBE) {
3045                 ecmd->supported = SUPPORTED_10000baseT_Full;
3046                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3047         } else {
3048                 ecmd->supported = (SUPPORTED_10baseT_Half |
3049                                    SUPPORTED_10baseT_Full |
3050                                    SUPPORTED_100baseT_Half |
3051                                    SUPPORTED_100baseT_Full |
3052                                    SUPPORTED_1000baseT_Half |
3053                                    SUPPORTED_1000baseT_Full);
3054                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3055                                      ADVERTISED_100baseT_Full |
3056                                      ADVERTISED_1000baseT_Half |
3057                                      ADVERTISED_1000baseT_Full);
3058         }
3059
3060         switch (ahw->supported_type) {
3061         case PORT_FIBRE:
3062                 ecmd->supported |= SUPPORTED_FIBRE;
3063                 ecmd->advertising |= ADVERTISED_FIBRE;
3064                 ecmd->port = PORT_FIBRE;
3065                 ecmd->transceiver = XCVR_EXTERNAL;
3066                 break;
3067         case PORT_TP:
3068                 ecmd->supported |= SUPPORTED_TP;
3069                 ecmd->advertising |= ADVERTISED_TP;
3070                 ecmd->port = PORT_TP;
3071                 ecmd->transceiver = XCVR_INTERNAL;
3072                 break;
3073         default:
3074                 ecmd->supported |= SUPPORTED_FIBRE;
3075                 ecmd->advertising |= ADVERTISED_FIBRE;
3076                 ecmd->port = PORT_OTHER;
3077                 ecmd->transceiver = XCVR_EXTERNAL;
3078                 break;
3079         }
3080         ecmd->phy_address = ahw->physical_port;
3081         return status;
3082 }
3083
3084 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3085                              struct ethtool_cmd *ecmd)
3086 {
3087         int status = 0;
3088         u32 config = adapter->ahw->port_config;
3089
3090         if (ecmd->autoneg)
3091                 adapter->ahw->port_config |= BIT_15;
3092
3093         switch (ethtool_cmd_speed(ecmd)) {
3094         case SPEED_10:
3095                 adapter->ahw->port_config |= BIT_8;
3096                 break;
3097         case SPEED_100:
3098                 adapter->ahw->port_config |= BIT_9;
3099                 break;
3100         case SPEED_1000:
3101                 adapter->ahw->port_config |= BIT_10;
3102                 break;
3103         case SPEED_10000:
3104                 adapter->ahw->port_config |= BIT_11;
3105                 break;
3106         default:
3107                 return -EINVAL;
3108         }
3109
3110         status = qlcnic_83xx_set_port_config(adapter);
3111         if (status) {
3112                 dev_info(&adapter->pdev->dev,
3113                          "Faild to Set Link Speed and autoneg.\n");
3114                 adapter->ahw->port_config = config;
3115         }
3116         return status;
3117 }
3118
3119 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3120                                           u64 *data, int index)
3121 {
3122         u32 low, hi;
3123         u64 val;
3124
3125         low = cmd->rsp.arg[index];
3126         hi = cmd->rsp.arg[index + 1];
3127         val = (((u64) low) | (((u64) hi) << 32));
3128         *data++ = val;
3129         return data;
3130 }
3131
3132 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3133                                    struct qlcnic_cmd_args *cmd, u64 *data,
3134                                    int type, int *ret)
3135 {
3136         int err, k, total_regs;
3137
3138         *ret = 0;
3139         err = qlcnic_issue_cmd(adapter, cmd);
3140         if (err != QLCNIC_RCODE_SUCCESS) {
3141                 dev_info(&adapter->pdev->dev,
3142                          "Error in get statistics mailbox command\n");
3143                 *ret = -EIO;
3144                 return data;
3145         }
3146         total_regs = cmd->rsp.num;
3147         switch (type) {
3148         case QLC_83XX_STAT_MAC:
3149                 /* fill in MAC tx counters */
3150                 for (k = 2; k < 28; k += 2)
3151                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3152                 /* skip 24 bytes of reserved area */
3153                 /* fill in MAC rx counters */
3154                 for (k += 6; k < 60; k += 2)
3155                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3156                 /* skip 24 bytes of reserved area */
3157                 /* fill in MAC rx frame stats */
3158                 for (k += 6; k < 80; k += 2)
3159                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3160                 /* fill in eSwitch stats */
3161                 for (; k < total_regs; k += 2)
3162                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3163                 break;
3164         case QLC_83XX_STAT_RX:
3165                 for (k = 2; k < 8; k += 2)
3166                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3167                 /* skip 8 bytes of reserved data */
3168                 for (k += 2; k < 24; k += 2)
3169                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3170                 /* skip 8 bytes containing RE1FBQ error data */
3171                 for (k += 2; k < total_regs; k += 2)
3172                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3173                 break;
3174         case QLC_83XX_STAT_TX:
3175                 for (k = 2; k < 10; k += 2)
3176                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3177                 /* skip 8 bytes of reserved data */
3178                 for (k += 2; k < total_regs; k += 2)
3179                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3180                 break;
3181         default:
3182                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3183                 *ret = -EIO;
3184         }
3185         return data;
3186 }
3187
3188 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3189 {
3190         struct qlcnic_cmd_args cmd;
3191         struct net_device *netdev = adapter->netdev;
3192         int ret = 0;
3193
3194         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3195         if (ret)
3196                 return;
3197         /* Get Tx stats */
3198         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3199         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3200         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3201                                       QLC_83XX_STAT_TX, &ret);
3202         if (ret) {
3203                 netdev_err(netdev, "Error getting Tx stats\n");
3204                 goto out;
3205         }
3206         /* Get MAC stats */
3207         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3208         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3209         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3210         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3211                                       QLC_83XX_STAT_MAC, &ret);
3212         if (ret) {
3213                 netdev_err(netdev, "Error getting MAC stats\n");
3214                 goto out;
3215         }
3216         /* Get Rx stats */
3217         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3218         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3219         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3220         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3221                                       QLC_83XX_STAT_RX, &ret);
3222         if (ret)
3223                 netdev_err(netdev, "Error getting Rx stats\n");
3224 out:
3225         qlcnic_free_mbx_args(&cmd);
3226 }
3227
3228 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3229 {
3230         u32 major, minor, sub;
3231
3232         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3233         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3234         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3235
3236         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3237                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3238                          __func__);
3239                 return 1;
3240         }
3241         return 0;
3242 }
3243
3244 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3245 {
3246         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3247                 sizeof(adapter->ahw->ext_reg_tbl)) +
3248                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3249                 sizeof(adapter->ahw->reg_tbl));
3250 }
3251
3252 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3253 {
3254         int i, j = 0;
3255
3256         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3257              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3258                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3259
3260         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3261                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3262         return i;
3263 }
3264
3265 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3266 {
3267         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3268         struct qlcnic_hardware_context *ahw = adapter->ahw;
3269         struct qlcnic_cmd_args cmd;
3270         u32 data;
3271         u16 intrpt_id, id;
3272         u8 val;
3273         int ret, max_sds_rings = adapter->max_sds_rings;
3274
3275         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3276                 netdev_info(netdev, "Device is resetting\n");
3277                 return -EBUSY;
3278         }
3279
3280         if (qlcnic_get_diag_lock(adapter)) {
3281                 netdev_info(netdev, "Device in diagnostics mode\n");
3282                 return -EBUSY;
3283         }
3284
3285         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3286                                          max_sds_rings);
3287         if (ret)
3288                 goto fail_diag_irq;
3289
3290         ahw->diag_cnt = 0;
3291         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3292         if (ret)
3293                 goto fail_diag_irq;
3294
3295         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3296                 intrpt_id = ahw->intr_tbl[0].id;
3297         else
3298                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3299
3300         cmd.req.arg[1] = 1;
3301         cmd.req.arg[2] = intrpt_id;
3302         cmd.req.arg[3] = BIT_0;
3303
3304         ret = qlcnic_issue_cmd(adapter, &cmd);
3305         data = cmd.rsp.arg[2];
3306         id = LSW(data);
3307         val = LSB(MSW(data));
3308         if (id != intrpt_id)
3309                 dev_info(&adapter->pdev->dev,
3310                          "Interrupt generated: 0x%x, requested:0x%x\n",
3311                          id, intrpt_id);
3312         if (val)
3313                 dev_err(&adapter->pdev->dev,
3314                          "Interrupt test error: 0x%x\n", val);
3315         if (ret)
3316                 goto done;
3317
3318         msleep(20);
3319         ret = !ahw->diag_cnt;
3320
3321 done:
3322         qlcnic_free_mbx_args(&cmd);
3323         qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3324
3325 fail_diag_irq:
3326         adapter->max_sds_rings = max_sds_rings;
3327         qlcnic_release_diag_lock(adapter);
3328         return ret;
3329 }
3330
3331 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3332                                 struct ethtool_pauseparam *pause)
3333 {
3334         struct qlcnic_hardware_context *ahw = adapter->ahw;
3335         int status = 0;
3336         u32 config;
3337
3338         status = qlcnic_83xx_get_port_config(adapter);
3339         if (status) {
3340                 dev_err(&adapter->pdev->dev,
3341                         "%s: Get Pause Config failed\n", __func__);
3342                 return;
3343         }
3344         config = ahw->port_config;
3345         if (config & QLC_83XX_CFG_STD_PAUSE) {
3346                 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3347                         pause->tx_pause = 1;
3348                 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3349                         pause->rx_pause = 1;
3350         }
3351
3352         if (QLC_83XX_AUTONEG(config))
3353                 pause->autoneg = 1;
3354 }
3355
3356 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3357                                struct ethtool_pauseparam *pause)
3358 {
3359         struct qlcnic_hardware_context *ahw = adapter->ahw;
3360         int status = 0;
3361         u32 config;
3362
3363         status = qlcnic_83xx_get_port_config(adapter);
3364         if (status) {
3365                 dev_err(&adapter->pdev->dev,
3366                         "%s: Get Pause Config failed.\n", __func__);
3367                 return status;
3368         }
3369         config = ahw->port_config;
3370
3371         if (ahw->port_type == QLCNIC_GBE) {
3372                 if (pause->autoneg)
3373                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3374                 if (!pause->autoneg)
3375                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3376         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3377                 return -EOPNOTSUPP;
3378         }
3379
3380         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3381                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3382
3383         if (pause->rx_pause && pause->tx_pause) {
3384                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3385         } else if (pause->rx_pause && !pause->tx_pause) {
3386                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3387                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3388         } else if (pause->tx_pause && !pause->rx_pause) {
3389                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3390                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3391         } else if (!pause->rx_pause && !pause->tx_pause) {
3392                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3393         }
3394         status = qlcnic_83xx_set_port_config(adapter);
3395         if (status) {
3396                 dev_err(&adapter->pdev->dev,
3397                         "%s: Set Pause Config failed.\n", __func__);
3398                 ahw->port_config = config;
3399         }
3400         return status;
3401 }
3402
3403 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3404 {
3405         int ret, err = 0;
3406         u32 temp;
3407
3408         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3409                                      QLC_83XX_FLASH_OEM_READ_SIG);
3410         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3411                                      QLC_83XX_FLASH_READ_CTRL);
3412         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3413         if (ret)
3414                 return -EIO;
3415
3416         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3417         if (err == -EIO)
3418                 return err;
3419
3420         return temp & 0xFF;
3421 }
3422
3423 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3424 {
3425         int status;
3426
3427         status = qlcnic_83xx_read_flash_status_reg(adapter);
3428         if (status == -EIO) {
3429                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3430                          __func__);
3431                 return 1;
3432         }
3433         return 0;
3434 }
3435
3436 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3437 {
3438         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3439         struct net_device *netdev = adapter->netdev;
3440         int retval;
3441
3442         netif_device_detach(netdev);
3443         qlcnic_cancel_idc_work(adapter);
3444
3445         if (netif_running(netdev))
3446                 qlcnic_down(adapter, netdev);
3447
3448         qlcnic_83xx_disable_mbx_intr(adapter);
3449         cancel_delayed_work_sync(&adapter->idc_aen_work);
3450
3451         retval = pci_save_state(pdev);
3452         if (retval)
3453                 return retval;
3454
3455         return 0;
3456 }
3457
3458 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3459 {
3460         struct qlcnic_hardware_context *ahw = adapter->ahw;
3461         struct qlc_83xx_idc *idc = &ahw->idc;
3462         int err = 0;
3463
3464         err = qlcnic_83xx_idc_init(adapter);
3465         if (err)
3466                 return err;
3467
3468         if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) {
3469                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3470                         qlcnic_83xx_set_vnic_opmode(adapter);
3471                 } else {
3472                         err = qlcnic_83xx_check_vnic_state(adapter);
3473                         if (err)
3474                                 return err;
3475                 }
3476         }
3477
3478         err = qlcnic_83xx_idc_reattach_driver(adapter);
3479         if (err)
3480                 return err;
3481
3482         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3483                              idc->delay);
3484         return err;
3485 }
3486
3487 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3488 {
3489         INIT_COMPLETION(mbx->completion);
3490         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3491 }
3492
3493 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3494 {
3495         destroy_workqueue(mbx->work_q);
3496         kfree(mbx);
3497 }
3498
3499 static inline void
3500 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3501                                   struct qlcnic_cmd_args *cmd)
3502 {
3503         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3504
3505         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3506                 qlcnic_free_mbx_args(cmd);
3507                 kfree(cmd);
3508                 return;
3509         }
3510         complete(&cmd->completion);
3511 }
3512
3513 static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3514 {
3515         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3516         struct list_head *head = &mbx->cmd_q;
3517         struct qlcnic_cmd_args *cmd = NULL;
3518
3519         spin_lock(&mbx->queue_lock);
3520
3521         while (!list_empty(head)) {
3522                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3523                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3524                          __func__, cmd->cmd_op);
3525                 list_del(&cmd->list);
3526                 mbx->num_cmds--;
3527                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3528         }
3529
3530         spin_unlock(&mbx->queue_lock);
3531 }
3532
3533 static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3534 {
3535         struct qlcnic_hardware_context *ahw = adapter->ahw;
3536         struct qlcnic_mailbox *mbx = ahw->mailbox;
3537         u32 host_mbx_ctrl;
3538
3539         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3540                 return -EBUSY;
3541
3542         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3543         if (host_mbx_ctrl) {
3544                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3545                 ahw->idc.collect_dump = 1;
3546                 return -EIO;
3547         }
3548
3549         return 0;
3550 }
3551
3552 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3553                                               u8 issue_cmd)
3554 {
3555         if (issue_cmd)
3556                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3557         else
3558                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3559 }
3560
3561 static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3562                                                struct qlcnic_cmd_args *cmd)
3563 {
3564         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3565
3566         spin_lock(&mbx->queue_lock);
3567
3568         list_del(&cmd->list);
3569         mbx->num_cmds--;
3570
3571         spin_unlock(&mbx->queue_lock);
3572
3573         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3574 }
3575
3576 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3577                                        struct qlcnic_cmd_args *cmd)
3578 {
3579         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3580         struct qlcnic_hardware_context *ahw = adapter->ahw;
3581         int i, j;
3582
3583         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3584                 mbx_cmd = cmd->req.arg[0];
3585                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3586                 for (i = 1; i < cmd->req.num; i++)
3587                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3588         } else {
3589                 fw_hal_version = ahw->fw_hal_version;
3590                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3591                 total_size = cmd->pay_size + hdr_size;
3592                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3593                 mbx_cmd = tmp | fw_hal_version << 29;
3594                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3595
3596                 /* Back channel specific operations bits */
3597                 mbx_cmd = 0x1 | 1 << 4;
3598
3599                 if (qlcnic_sriov_pf_check(adapter))
3600                         mbx_cmd |= cmd->func_num << 5;
3601
3602                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3603
3604                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3605                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3606                 for (j = 0; j < cmd->pay_size; j++, i++)
3607                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3608         }
3609 }
3610
3611 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3612 {
3613         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3614
3615         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3616         complete(&mbx->completion);
3617         cancel_work_sync(&mbx->work);
3618         flush_workqueue(mbx->work_q);
3619         qlcnic_83xx_flush_mbx_queue(adapter);
3620 }
3621
3622 static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3623                                               struct qlcnic_cmd_args *cmd,
3624                                               unsigned long *timeout)
3625 {
3626         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3627
3628         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3629                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3630                 init_completion(&cmd->completion);
3631                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3632
3633                 spin_lock(&mbx->queue_lock);
3634
3635                 list_add_tail(&cmd->list, &mbx->cmd_q);
3636                 mbx->num_cmds++;
3637                 cmd->total_cmds = mbx->num_cmds;
3638                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3639                 queue_work(mbx->work_q, &mbx->work);
3640
3641                 spin_unlock(&mbx->queue_lock);
3642
3643                 return 0;
3644         }
3645
3646         return -EBUSY;
3647 }
3648
3649 static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3650                                               struct qlcnic_cmd_args *cmd)
3651 {
3652         u8 mac_cmd_rcode;
3653         u32 fw_data;
3654
3655         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3656                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3657                 mac_cmd_rcode = (u8)fw_data;
3658                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3659                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3660                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3661                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3662                         return QLCNIC_RCODE_SUCCESS;
3663                 }
3664         }
3665
3666         return -EINVAL;
3667 }
3668
3669 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3670                                        struct qlcnic_cmd_args *cmd)
3671 {
3672         struct qlcnic_hardware_context *ahw = adapter->ahw;
3673         struct device *dev = &adapter->pdev->dev;
3674         u8 mbx_err_code;
3675         u32 fw_data;
3676
3677         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3678         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3679         qlcnic_83xx_get_mbx_data(adapter, cmd);
3680
3681         switch (mbx_err_code) {
3682         case QLCNIC_MBX_RSP_OK:
3683         case QLCNIC_MBX_PORT_RSP_OK:
3684                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3685                 break;
3686         default:
3687                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3688                         break;
3689
3690                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3691                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3692                         ahw->op_mode, mbx_err_code);
3693                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3694                 qlcnic_dump_mbx(adapter, cmd);
3695         }
3696
3697         return;
3698 }
3699
3700 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3701 {
3702         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3703                                                   work);
3704         struct qlcnic_adapter *adapter = mbx->adapter;
3705         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3706         struct device *dev = &adapter->pdev->dev;
3707         atomic_t *rsp_status = &mbx->rsp_status;
3708         struct list_head *head = &mbx->cmd_q;
3709         struct qlcnic_hardware_context *ahw;
3710         struct qlcnic_cmd_args *cmd = NULL;
3711
3712         ahw = adapter->ahw;
3713
3714         while (true) {
3715                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3716                         qlcnic_83xx_flush_mbx_queue(adapter);
3717                         return;
3718                 }
3719
3720                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3721
3722                 spin_lock(&mbx->queue_lock);
3723
3724                 if (list_empty(head)) {
3725                         spin_unlock(&mbx->queue_lock);
3726                         return;
3727                 }
3728                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3729
3730                 spin_unlock(&mbx->queue_lock);
3731
3732                 mbx_ops->encode_cmd(adapter, cmd);
3733                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3734
3735                 if (wait_for_completion_timeout(&mbx->completion,
3736                                                 QLC_83XX_MBX_TIMEOUT)) {
3737                         mbx_ops->decode_resp(adapter, cmd);
3738                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3739                 } else {
3740                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3741                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3742                                 ahw->op_mode);
3743                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3744                         qlcnic_dump_mbx(adapter, cmd);
3745                         qlcnic_83xx_idc_request_reset(adapter,
3746                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3747                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3748                 }
3749                 mbx_ops->dequeue_cmd(adapter, cmd);
3750         }
3751 }
3752
3753 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3754         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3755         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3756         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3757         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3758         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3759 };
3760
3761 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3762 {
3763         struct qlcnic_hardware_context *ahw = adapter->ahw;
3764         struct qlcnic_mailbox *mbx;
3765
3766         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3767         if (!ahw->mailbox)
3768                 return -ENOMEM;
3769
3770         mbx = ahw->mailbox;
3771         mbx->ops = &qlcnic_83xx_mbx_ops;
3772         mbx->adapter = adapter;
3773
3774         spin_lock_init(&mbx->queue_lock);
3775         spin_lock_init(&mbx->aen_lock);
3776         INIT_LIST_HEAD(&mbx->cmd_q);
3777         init_completion(&mbx->completion);
3778
3779         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3780         if (mbx->work_q == NULL) {
3781                 kfree(mbx);
3782                 return -ENOMEM;
3783         }
3784
3785         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3786         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3787         return 0;
3788 }