2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
70 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
71 {QLCNIC_CMD_DCB_QUERY_PARAM, 2, 50},
74 const u32 qlcnic_83xx_ext_reg_tbl[] = {
75 0x38CC, /* Global Reset */
76 0x38F0, /* Wildcard */
77 0x38FC, /* Informant */
78 0x3038, /* Host MBX ctrl */
79 0x303C, /* FW MBX ctrl */
80 0x355C, /* BOOT LOADER ADDRESS REG */
81 0x3560, /* BOOT LOADER SIZE REG */
82 0x3564, /* FW IMAGE ADDR REG */
83 0x1000, /* MBX intr enable */
84 0x1200, /* Default Intr mask */
85 0x1204, /* Default Interrupt ID */
86 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
87 0x3784, /* QLC_83XX_IDC_DEV_STATE */
88 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
89 0x378C, /* QLC_83XX_IDC_DRV_ACK */
90 0x3790, /* QLC_83XX_IDC_CTRL */
91 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
92 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
93 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
94 0x37A0, /* QLC_83XX_IDC_PF_0 */
95 0x37A4, /* QLC_83XX_IDC_PF_1 */
96 0x37A8, /* QLC_83XX_IDC_PF_2 */
97 0x37AC, /* QLC_83XX_IDC_PF_3 */
98 0x37B0, /* QLC_83XX_IDC_PF_4 */
99 0x37B4, /* QLC_83XX_IDC_PF_5 */
100 0x37B8, /* QLC_83XX_IDC_PF_6 */
101 0x37BC, /* QLC_83XX_IDC_PF_7 */
102 0x37C0, /* QLC_83XX_IDC_PF_8 */
103 0x37C4, /* QLC_83XX_IDC_PF_9 */
104 0x37C8, /* QLC_83XX_IDC_PF_10 */
105 0x37CC, /* QLC_83XX_IDC_PF_11 */
106 0x37D0, /* QLC_83XX_IDC_PF_12 */
107 0x37D4, /* QLC_83XX_IDC_PF_13 */
108 0x37D8, /* QLC_83XX_IDC_PF_14 */
109 0x37DC, /* QLC_83XX_IDC_PF_15 */
110 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
111 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
112 0x37F0, /* QLC_83XX_DRV_OP_MODE */
113 0x37F4, /* QLC_83XX_VNIC_STATE */
114 0x3868, /* QLC_83XX_DRV_LOCK */
115 0x386C, /* QLC_83XX_DRV_UNLOCK */
116 0x3504, /* QLC_83XX_DRV_LOCK_ID */
117 0x34A4, /* QLC_83XX_ASIC_TEMP */
120 const u32 qlcnic_83xx_reg_tbl[] = {
121 0x34A8, /* PEG_HALT_STAT1 */
122 0x34AC, /* PEG_HALT_STAT2 */
123 0x34B0, /* FW_HEARTBEAT */
124 0x3500, /* FLASH LOCK_ID */
125 0x3528, /* FW_CAPABILITIES */
126 0x3538, /* Driver active, DRV_REG0 */
127 0x3540, /* Device state, DRV_REG1 */
128 0x3544, /* Driver state, DRV_REG2 */
129 0x3548, /* Driver scratch, DRV_REG3 */
130 0x354C, /* Device partiton info, DRV_REG4 */
131 0x3524, /* Driver IDC ver, DRV_REG5 */
132 0x3550, /* FW_VER_MAJOR */
133 0x3554, /* FW_VER_MINOR */
134 0x3558, /* FW_VER_SUB */
135 0x359C, /* NPAR STATE */
136 0x35FC, /* FW_IMG_VALID */
137 0x3650, /* CMD_PEG_STATE */
138 0x373C, /* RCV_PEG_STATE */
139 0x37B4, /* ASIC TEMP */
141 0x3570, /* DRV OP MODE */
142 0x3850, /* FLASH LOCK */
143 0x3854, /* FLASH UNLOCK */
146 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
147 .read_crb = qlcnic_83xx_read_crb,
148 .write_crb = qlcnic_83xx_write_crb,
149 .read_reg = qlcnic_83xx_rd_reg_indirect,
150 .write_reg = qlcnic_83xx_wrt_reg_indirect,
151 .get_mac_address = qlcnic_83xx_get_mac_address,
152 .setup_intr = qlcnic_83xx_setup_intr,
153 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
154 .mbx_cmd = qlcnic_83xx_issue_cmd,
155 .get_func_no = qlcnic_83xx_get_func_no,
156 .api_lock = qlcnic_83xx_cam_lock,
157 .api_unlock = qlcnic_83xx_cam_unlock,
158 .add_sysfs = qlcnic_83xx_add_sysfs,
159 .remove_sysfs = qlcnic_83xx_remove_sysfs,
160 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
161 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
162 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
163 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
164 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
165 .setup_link_event = qlcnic_83xx_setup_link_event,
166 .get_nic_info = qlcnic_83xx_get_nic_info,
167 .get_pci_info = qlcnic_83xx_get_pci_info,
168 .set_nic_info = qlcnic_83xx_set_nic_info,
169 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
170 .napi_enable = qlcnic_83xx_napi_enable,
171 .napi_disable = qlcnic_83xx_napi_disable,
172 .config_intr_coal = qlcnic_83xx_config_intr_coal,
173 .config_rss = qlcnic_83xx_config_rss,
174 .config_hw_lro = qlcnic_83xx_config_hw_lro,
175 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
176 .change_l2_filter = qlcnic_83xx_change_l2_filter,
177 .get_board_info = qlcnic_83xx_get_port_info,
178 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
179 .free_mac_list = qlcnic_82xx_free_mac_list,
180 .io_error_detected = qlcnic_83xx_io_error_detected,
181 .io_slot_reset = qlcnic_83xx_io_slot_reset,
182 .io_resume = qlcnic_83xx_io_resume,
186 static struct qlcnic_nic_template qlcnic_83xx_ops = {
187 .config_bridged_mode = qlcnic_config_bridged_mode,
188 .config_led = qlcnic_config_led,
189 .request_reset = qlcnic_83xx_idc_request_reset,
190 .cancel_idc_work = qlcnic_83xx_idc_exit,
191 .napi_add = qlcnic_83xx_napi_add,
192 .napi_del = qlcnic_83xx_napi_del,
193 .config_ipaddr = qlcnic_83xx_config_ipaddr,
194 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
195 .shutdown = qlcnic_83xx_shutdown,
196 .resume = qlcnic_83xx_resume,
199 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
201 ahw->hw_ops = &qlcnic_83xx_hw_ops;
202 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
203 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
206 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
208 u32 fw_major, fw_minor, fw_build;
209 struct pci_dev *pdev = adapter->pdev;
211 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
212 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
213 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
214 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
216 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
217 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
219 return adapter->fw_version;
222 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
227 base = adapter->ahw->pci_base0 +
228 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
237 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
240 struct qlcnic_hardware_context *ahw = adapter->ahw;
242 *err = __qlcnic_set_win_base(adapter, (u32) addr);
244 return QLCRDX(ahw, QLCNIC_WILDCARD);
246 dev_err(&adapter->pdev->dev,
247 "%s failed, addr = 0x%lx\n", __func__, addr);
252 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
256 struct qlcnic_hardware_context *ahw = adapter->ahw;
258 err = __qlcnic_set_win_base(adapter, (u32) addr);
260 QLCWRX(ahw, QLCNIC_WILDCARD, data);
263 dev_err(&adapter->pdev->dev,
264 "%s failed, addr = 0x%x data = 0x%x\n",
265 __func__, (int)addr, data);
270 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
272 int err, i, num_msix;
273 struct qlcnic_hardware_context *ahw = adapter->ahw;
275 num_msix = adapter->drv_sds_rings;
277 /* account for AEN interrupt MSI-X based interrupts */
280 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
281 num_msix += adapter->drv_tx_rings;
283 err = qlcnic_enable_msix(adapter, num_msix);
286 if (adapter->flags & QLCNIC_MSIX_ENABLED)
287 num_msix = adapter->ahw->num_msix;
289 if (qlcnic_sriov_vf_check(adapter))
293 /* setup interrupt mapping table for fw */
294 ahw->intr_tbl = vzalloc(num_msix *
295 sizeof(struct qlcnic_intrpt_config));
298 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
299 /* MSI-X enablement failed, use legacy interrupt */
300 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
301 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
302 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
303 adapter->msix_entries[0].vector = adapter->pdev->irq;
304 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
307 for (i = 0; i < num_msix; i++) {
308 if (adapter->flags & QLCNIC_MSIX_ENABLED)
309 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
311 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
312 ahw->intr_tbl[i].id = i;
313 ahw->intr_tbl[i].src = 0;
318 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
320 writel(0, adapter->tgt_mask_reg);
323 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
325 if (adapter->tgt_mask_reg)
326 writel(1, adapter->tgt_mask_reg);
329 /* Enable MSI-x and INT-x interrupts */
330 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
331 struct qlcnic_host_sds_ring *sds_ring)
333 writel(0, sds_ring->crb_intr_mask);
336 /* Disable MSI-x and INT-x interrupts */
337 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
338 struct qlcnic_host_sds_ring *sds_ring)
340 writel(1, sds_ring->crb_intr_mask);
343 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
348 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
349 * source register. We could be here before contexts are created
350 * and sds_ring->crb_intr_mask has not been initialized, calculate
351 * BAR offset for Interrupt Source Register
353 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
354 writel(0, adapter->ahw->pci_base0 + mask);
357 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
361 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
362 writel(1, adapter->ahw->pci_base0 + mask);
363 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
366 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
367 struct qlcnic_cmd_args *cmd)
371 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
374 for (i = 0; i < cmd->rsp.num; i++)
375 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
378 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
381 struct qlcnic_hardware_context *ahw = adapter->ahw;
384 intr_val = readl(adapter->tgt_status_reg);
386 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
389 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
390 adapter->stats.spurious_intr++;
393 /* The barrier is required to ensure writes to the registers */
396 /* clear the interrupt trigger control register */
397 writel(0, adapter->isr_int_vec);
398 intr_val = readl(adapter->isr_int_vec);
400 intr_val = readl(adapter->tgt_status_reg);
401 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
404 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
405 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
410 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
412 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
413 complete(&mbx->completion);
416 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
418 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
419 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
422 spin_lock_irqsave(&mbx->aen_lock, flags);
423 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
424 if (!(resp & QLCNIC_SET_OWNER))
427 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
428 if (event & QLCNIC_MBX_ASYNC_EVENT) {
429 __qlcnic_83xx_process_aen(adapter);
431 if (atomic_read(&mbx->rsp_status) != rsp_status)
432 qlcnic_83xx_notify_mbx_response(mbx);
435 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
436 spin_unlock_irqrestore(&mbx->aen_lock, flags);
439 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
441 struct qlcnic_adapter *adapter = data;
442 struct qlcnic_host_sds_ring *sds_ring;
443 struct qlcnic_hardware_context *ahw = adapter->ahw;
445 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
448 qlcnic_83xx_poll_process_aen(adapter);
450 if (ahw->diag_test) {
451 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
453 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
457 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
458 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
460 sds_ring = &adapter->recv_ctx->sds_rings[0];
461 napi_schedule(&sds_ring->napi);
467 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
469 struct qlcnic_host_sds_ring *sds_ring = data;
470 struct qlcnic_adapter *adapter = sds_ring->adapter;
472 if (adapter->flags & QLCNIC_MSIX_ENABLED)
475 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
479 adapter->ahw->diag_cnt++;
480 qlcnic_83xx_enable_intr(adapter, sds_ring);
485 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
489 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
490 qlcnic_83xx_set_legacy_intr_mask(adapter);
492 qlcnic_83xx_disable_mbx_intr(adapter);
494 if (adapter->flags & QLCNIC_MSIX_ENABLED)
495 num_msix = adapter->ahw->num_msix - 1;
501 if (adapter->msix_entries) {
502 synchronize_irq(adapter->msix_entries[num_msix].vector);
503 free_irq(adapter->msix_entries[num_msix].vector, adapter);
507 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
509 irq_handler_t handler;
512 unsigned long flags = 0;
514 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
515 !(adapter->flags & QLCNIC_MSIX_ENABLED))
516 flags |= IRQF_SHARED;
518 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
519 handler = qlcnic_83xx_handle_aen;
520 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
521 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
523 dev_err(&adapter->pdev->dev,
524 "failed to register MBX interrupt\n");
528 handler = qlcnic_83xx_intr;
529 val = adapter->msix_entries[0].vector;
530 err = request_irq(val, handler, flags, "qlcnic", adapter);
532 dev_err(&adapter->pdev->dev,
533 "failed to register INTx interrupt\n");
536 qlcnic_83xx_clear_legacy_intr_mask(adapter);
539 /* Enable mailbox interrupt */
540 qlcnic_83xx_enable_mbx_interrupt(adapter);
545 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
547 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
548 adapter->ahw->pci_func = (val >> 24) & 0xff;
551 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
556 struct qlcnic_hardware_context *ahw = adapter->ahw;
558 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
562 /* write the function number to register */
563 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
567 usleep_range(1000, 2000);
568 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
573 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
577 struct qlcnic_hardware_context *ahw = adapter->ahw;
579 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
583 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
584 loff_t offset, size_t size)
589 if (qlcnic_api_lock(adapter)) {
590 dev_err(&adapter->pdev->dev,
591 "%s: failed to acquire lock. addr offset 0x%x\n",
592 __func__, (u32)offset);
596 data = QLCRD32(adapter, (u32) offset, &ret);
597 qlcnic_api_unlock(adapter);
600 dev_err(&adapter->pdev->dev,
601 "%s: failed. addr offset 0x%x\n",
602 __func__, (u32)offset);
605 memcpy(buf, &data, size);
608 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
609 loff_t offset, size_t size)
613 memcpy(&data, buf, size);
614 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
617 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
621 status = qlcnic_83xx_get_port_config(adapter);
623 dev_err(&adapter->pdev->dev,
624 "Get Port Info failed\n");
626 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
627 adapter->ahw->port_type = QLCNIC_XGBE;
629 adapter->ahw->port_type = QLCNIC_GBE;
631 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
632 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
637 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
639 struct qlcnic_hardware_context *ahw = adapter->ahw;
640 u16 act_pci_fn = ahw->act_pci_func;
643 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
645 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
648 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
650 ahw->max_uc_count = count;
653 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
657 if (adapter->flags & QLCNIC_MSIX_ENABLED)
658 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
662 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
663 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
666 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
667 const struct pci_device_id *ent)
669 u32 op_mode, priv_level;
670 struct qlcnic_hardware_context *ahw = adapter->ahw;
672 ahw->fw_hal_version = 2;
673 qlcnic_get_func_no(adapter);
675 if (qlcnic_sriov_vf_check(adapter)) {
676 qlcnic_sriov_vf_set_ops(adapter);
680 /* Determine function privilege level */
681 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
682 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
683 priv_level = QLCNIC_MGMT_FUNC;
685 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
688 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
689 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
690 dev_info(&adapter->pdev->dev,
691 "HAL Version: %d Non Privileged function\n",
692 ahw->fw_hal_version);
693 adapter->nic_ops = &qlcnic_vf_ops;
695 if (pci_find_ext_capability(adapter->pdev,
696 PCI_EXT_CAP_ID_SRIOV))
697 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
698 adapter->nic_ops = &qlcnic_83xx_ops;
702 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
704 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
707 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
708 struct qlcnic_cmd_args *cmd)
712 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
715 dev_info(&adapter->pdev->dev,
716 "Host MBX regs(%d)\n", cmd->req.num);
717 for (i = 0; i < cmd->req.num; i++) {
720 pr_info("%08x ", cmd->req.arg[i]);
723 dev_info(&adapter->pdev->dev,
724 "FW MBX regs(%d)\n", cmd->rsp.num);
725 for (i = 0; i < cmd->rsp.num; i++) {
728 pr_info("%08x ", cmd->rsp.arg[i]);
733 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
734 struct qlcnic_cmd_args *cmd)
736 struct qlcnic_hardware_context *ahw = adapter->ahw;
737 int opcode = LSW(cmd->req.arg[0]);
738 unsigned long max_loops;
740 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
742 for (; max_loops; max_loops--) {
743 if (atomic_read(&cmd->rsp_status) ==
744 QLC_83XX_MBX_RESPONSE_ARRIVED)
750 dev_err(&adapter->pdev->dev,
751 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
752 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
753 flush_workqueue(ahw->mailbox->work_q);
757 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
758 struct qlcnic_cmd_args *cmd)
760 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
761 struct qlcnic_hardware_context *ahw = adapter->ahw;
762 int cmd_type, err, opcode;
763 unsigned long timeout;
768 opcode = LSW(cmd->req.arg[0]);
769 cmd_type = cmd->type;
770 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
772 dev_err(&adapter->pdev->dev,
773 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
774 __func__, opcode, cmd->type, ahw->pci_func,
780 case QLC_83XX_MBX_CMD_WAIT:
781 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
782 dev_err(&adapter->pdev->dev,
783 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
784 __func__, opcode, cmd_type, ahw->pci_func,
786 flush_workqueue(mbx->work_q);
789 case QLC_83XX_MBX_CMD_NO_WAIT:
791 case QLC_83XX_MBX_CMD_BUSY_WAIT:
792 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
795 dev_err(&adapter->pdev->dev,
796 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
797 __func__, opcode, cmd_type, ahw->pci_func,
799 qlcnic_83xx_detach_mailbox_work(adapter);
802 return cmd->rsp_opcode;
805 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
806 struct qlcnic_adapter *adapter, u32 type)
810 const struct qlcnic_mailbox_metadata *mbx_tbl;
812 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
813 mbx_tbl = qlcnic_83xx_mbx_tbl;
814 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
815 for (i = 0; i < size; i++) {
816 if (type == mbx_tbl[i].cmd) {
817 mbx->op_type = QLC_83XX_FW_MBX_CMD;
818 mbx->req.num = mbx_tbl[i].in_args;
819 mbx->rsp.num = mbx_tbl[i].out_args;
820 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
824 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
831 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
832 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
833 temp = adapter->ahw->fw_hal_version << 29;
834 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
842 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
844 struct qlcnic_adapter *adapter;
845 struct qlcnic_cmd_args cmd;
848 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
849 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
853 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
854 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
856 err = qlcnic_issue_cmd(adapter, &cmd);
858 dev_info(&adapter->pdev->dev,
859 "%s: Mailbox IDC ACK failed.\n", __func__);
860 qlcnic_free_mbx_args(&cmd);
863 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
866 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
867 QLCNIC_MBX_RSP(data[0]));
868 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
872 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
874 struct qlcnic_hardware_context *ahw = adapter->ahw;
875 u32 event[QLC_83XX_MBX_AEN_CNT];
878 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
879 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
881 switch (QLCNIC_MBX_RSP(event[0])) {
883 case QLCNIC_MBX_LINK_EVENT:
884 qlcnic_83xx_handle_link_aen(adapter, event);
886 case QLCNIC_MBX_COMP_EVENT:
887 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
889 case QLCNIC_MBX_REQUEST_EVENT:
890 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
891 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
892 queue_delayed_work(adapter->qlcnic_wq,
893 &adapter->idc_aen_work, 0);
895 case QLCNIC_MBX_TIME_EXTEND_EVENT:
896 ahw->extend_lb_time = event[1] >> 8 & 0xf;
898 case QLCNIC_MBX_BC_EVENT:
899 qlcnic_sriov_handle_bc_event(adapter, event[1]);
901 case QLCNIC_MBX_SFP_INSERT_EVENT:
902 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
903 QLCNIC_MBX_RSP(event[0]));
905 case QLCNIC_MBX_SFP_REMOVE_EVENT:
906 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
907 QLCNIC_MBX_RSP(event[0]));
909 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
910 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
913 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
914 QLCNIC_MBX_RSP(event[0]));
918 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
921 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
923 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
924 struct qlcnic_hardware_context *ahw = adapter->ahw;
925 struct qlcnic_mailbox *mbx = ahw->mailbox;
928 spin_lock_irqsave(&mbx->aen_lock, flags);
929 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
930 if (resp & QLCNIC_SET_OWNER) {
931 event = readl(QLCNIC_MBX_FW(ahw, 0));
932 if (event & QLCNIC_MBX_ASYNC_EVENT) {
933 __qlcnic_83xx_process_aen(adapter);
935 if (atomic_read(&mbx->rsp_status) != rsp_status)
936 qlcnic_83xx_notify_mbx_response(mbx);
939 spin_unlock_irqrestore(&mbx->aen_lock, flags);
942 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
944 struct qlcnic_adapter *adapter;
946 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
948 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
951 qlcnic_83xx_process_aen(adapter);
952 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
956 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
958 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
961 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
962 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
965 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
967 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
969 cancel_delayed_work_sync(&adapter->mbx_poll_work);
972 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
974 int index, i, err, sds_mbx_size;
975 u32 *buf, intrpt_id, intr_mask;
978 struct qlcnic_cmd_args cmd;
979 struct qlcnic_host_sds_ring *sds;
980 struct qlcnic_sds_mbx sds_mbx;
981 struct qlcnic_add_rings_mbx_out *mbx_out;
982 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
983 struct qlcnic_hardware_context *ahw = adapter->ahw;
985 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
986 context_id = recv_ctx->context_id;
987 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
988 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
989 QLCNIC_CMD_ADD_RCV_RINGS);
990 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
992 /* set up status rings, mbx 2-81 */
994 for (i = 8; i < adapter->drv_sds_rings; i++) {
995 memset(&sds_mbx, 0, sds_mbx_size);
996 sds = &recv_ctx->sds_rings[i];
998 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
999 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1000 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1001 sds_mbx.sds_ring_size = sds->num_desc;
1003 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1004 intrpt_id = ahw->intr_tbl[i].id;
1006 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1008 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1009 sds_mbx.intrpt_id = intrpt_id;
1011 sds_mbx.intrpt_id = 0xffff;
1012 sds_mbx.intrpt_val = 0;
1013 buf = &cmd.req.arg[index];
1014 memcpy(buf, &sds_mbx, sds_mbx_size);
1015 index += sds_mbx_size / sizeof(u32);
1018 /* send the mailbox command */
1019 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1021 dev_err(&adapter->pdev->dev,
1022 "Failed to add rings %d\n", err);
1026 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1028 /* status descriptor ring */
1029 for (i = 8; i < adapter->drv_sds_rings; i++) {
1030 sds = &recv_ctx->sds_rings[i];
1031 sds->crb_sts_consumer = ahw->pci_base0 +
1032 mbx_out->host_csmr[index];
1033 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1034 intr_mask = ahw->intr_tbl[i].src;
1036 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1038 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1042 qlcnic_free_mbx_args(&cmd);
1046 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1050 struct qlcnic_cmd_args cmd;
1051 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1053 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1056 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1057 cmd.req.arg[0] |= (0x3 << 29);
1059 if (qlcnic_sriov_pf_check(adapter))
1060 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1062 cmd.req.arg[1] = recv_ctx->context_id | temp;
1063 err = qlcnic_issue_cmd(adapter, &cmd);
1065 dev_err(&adapter->pdev->dev,
1066 "Failed to destroy rx ctx in firmware\n");
1068 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1069 qlcnic_free_mbx_args(&cmd);
1072 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1074 int i, err, index, sds_mbx_size, rds_mbx_size;
1075 u8 num_sds, num_rds;
1076 u32 *buf, intrpt_id, intr_mask, cap = 0;
1077 struct qlcnic_host_sds_ring *sds;
1078 struct qlcnic_host_rds_ring *rds;
1079 struct qlcnic_sds_mbx sds_mbx;
1080 struct qlcnic_rds_mbx rds_mbx;
1081 struct qlcnic_cmd_args cmd;
1082 struct qlcnic_rcv_mbx_out *mbx_out;
1083 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1084 struct qlcnic_hardware_context *ahw = adapter->ahw;
1085 num_rds = adapter->max_rds_rings;
1087 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1088 num_sds = adapter->drv_sds_rings;
1090 num_sds = QLCNIC_MAX_SDS_RINGS;
1092 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1093 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1094 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1096 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1097 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1099 /* set mailbox hdr and capabilities */
1100 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1101 QLCNIC_CMD_CREATE_RX_CTX);
1105 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1106 cmd.req.arg[0] |= (0x3 << 29);
1108 cmd.req.arg[1] = cap;
1109 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1110 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1112 if (qlcnic_sriov_pf_check(adapter))
1113 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1115 /* set up status rings, mbx 8-57/87 */
1116 index = QLC_83XX_HOST_SDS_MBX_IDX;
1117 for (i = 0; i < num_sds; i++) {
1118 memset(&sds_mbx, 0, sds_mbx_size);
1119 sds = &recv_ctx->sds_rings[i];
1121 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1122 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1123 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1124 sds_mbx.sds_ring_size = sds->num_desc;
1125 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1126 intrpt_id = ahw->intr_tbl[i].id;
1128 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1129 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1130 sds_mbx.intrpt_id = intrpt_id;
1132 sds_mbx.intrpt_id = 0xffff;
1133 sds_mbx.intrpt_val = 0;
1134 buf = &cmd.req.arg[index];
1135 memcpy(buf, &sds_mbx, sds_mbx_size);
1136 index += sds_mbx_size / sizeof(u32);
1138 /* set up receive rings, mbx 88-111/135 */
1139 index = QLCNIC_HOST_RDS_MBX_IDX;
1140 rds = &recv_ctx->rds_rings[0];
1142 memset(&rds_mbx, 0, rds_mbx_size);
1143 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1144 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1145 rds_mbx.reg_ring_sz = rds->dma_size;
1146 rds_mbx.reg_ring_len = rds->num_desc;
1148 rds = &recv_ctx->rds_rings[1];
1150 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1151 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1152 rds_mbx.jmb_ring_sz = rds->dma_size;
1153 rds_mbx.jmb_ring_len = rds->num_desc;
1154 buf = &cmd.req.arg[index];
1155 memcpy(buf, &rds_mbx, rds_mbx_size);
1157 /* send the mailbox command */
1158 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1160 dev_err(&adapter->pdev->dev,
1161 "Failed to create Rx ctx in firmware%d\n", err);
1164 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1165 recv_ctx->context_id = mbx_out->ctx_id;
1166 recv_ctx->state = mbx_out->state;
1167 recv_ctx->virt_port = mbx_out->vport_id;
1168 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1169 recv_ctx->context_id, recv_ctx->state);
1170 /* Receive descriptor ring */
1172 rds = &recv_ctx->rds_rings[0];
1173 rds->crb_rcv_producer = ahw->pci_base0 +
1174 mbx_out->host_prod[0].reg_buf;
1176 rds = &recv_ctx->rds_rings[1];
1177 rds->crb_rcv_producer = ahw->pci_base0 +
1178 mbx_out->host_prod[0].jmb_buf;
1179 /* status descriptor ring */
1180 for (i = 0; i < num_sds; i++) {
1181 sds = &recv_ctx->sds_rings[i];
1182 sds->crb_sts_consumer = ahw->pci_base0 +
1183 mbx_out->host_csmr[i];
1184 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1185 intr_mask = ahw->intr_tbl[i].src;
1187 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1188 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1191 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1192 err = qlcnic_83xx_add_rings(adapter);
1194 qlcnic_free_mbx_args(&cmd);
1198 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1199 struct qlcnic_host_tx_ring *tx_ring)
1201 struct qlcnic_cmd_args cmd;
1204 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1207 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1208 cmd.req.arg[0] |= (0x3 << 29);
1210 if (qlcnic_sriov_pf_check(adapter))
1211 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1213 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1214 if (qlcnic_issue_cmd(adapter, &cmd))
1215 dev_err(&adapter->pdev->dev,
1216 "Failed to destroy tx ctx in firmware\n");
1217 qlcnic_free_mbx_args(&cmd);
1220 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1221 struct qlcnic_host_tx_ring *tx, int ring)
1225 u32 *buf, intr_mask, temp = 0;
1226 struct qlcnic_cmd_args cmd;
1227 struct qlcnic_tx_mbx mbx;
1228 struct qlcnic_tx_mbx_out *mbx_out;
1229 struct qlcnic_hardware_context *ahw = adapter->ahw;
1232 /* Reset host resources */
1234 tx->sw_consumer = 0;
1235 *(tx->hw_consumer) = 0;
1237 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1239 /* setup mailbox inbox registerss */
1240 mbx.phys_addr_low = LSD(tx->phys_addr);
1241 mbx.phys_addr_high = MSD(tx->phys_addr);
1242 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1243 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1244 mbx.size = tx->num_desc;
1245 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1246 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1247 msix_vector = adapter->drv_sds_rings + ring;
1249 msix_vector = adapter->drv_sds_rings - 1;
1250 msix_id = ahw->intr_tbl[msix_vector].id;
1252 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1255 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1256 mbx.intr_id = msix_id;
1258 mbx.intr_id = 0xffff;
1261 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1265 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1266 cmd.req.arg[0] |= (0x3 << 29);
1268 if (qlcnic_sriov_pf_check(adapter))
1269 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1271 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1272 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1274 buf = &cmd.req.arg[6];
1275 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1276 /* send the mailbox command*/
1277 err = qlcnic_issue_cmd(adapter, &cmd);
1279 dev_err(&adapter->pdev->dev,
1280 "Failed to create Tx ctx in firmware 0x%x\n", err);
1283 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1284 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1285 tx->ctx_id = mbx_out->ctx_id;
1286 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1287 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1288 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1289 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1291 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1292 tx->ctx_id, mbx_out->state);
1294 qlcnic_free_mbx_args(&cmd);
1298 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1301 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1302 struct qlcnic_host_sds_ring *sds_ring;
1303 struct qlcnic_host_rds_ring *rds_ring;
1304 u16 adapter_state = adapter->is_up;
1308 netif_device_detach(netdev);
1310 if (netif_running(netdev))
1311 __qlcnic_down(adapter, netdev);
1313 qlcnic_detach(adapter);
1315 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1316 adapter->ahw->diag_test = test;
1317 adapter->ahw->linkup = 0;
1319 ret = qlcnic_attach(adapter);
1321 netif_device_attach(netdev);
1325 ret = qlcnic_fw_create_ctx(adapter);
1327 qlcnic_detach(adapter);
1328 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1329 adapter->drv_sds_rings = num_sds_ring;
1330 qlcnic_attach(adapter);
1332 netif_device_attach(netdev);
1336 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1337 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1338 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1341 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1342 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1343 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1344 qlcnic_83xx_enable_intr(adapter, sds_ring);
1348 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1349 adapter->ahw->loopback_state = 0;
1350 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1353 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1357 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1360 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1361 struct qlcnic_host_sds_ring *sds_ring;
1364 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1365 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1366 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1367 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1368 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1369 qlcnic_83xx_disable_intr(adapter, sds_ring);
1373 qlcnic_fw_destroy_ctx(adapter);
1374 qlcnic_detach(adapter);
1376 adapter->ahw->diag_test = 0;
1377 adapter->drv_sds_rings = drv_sds_rings;
1379 if (qlcnic_attach(adapter))
1382 if (netif_running(netdev))
1383 __qlcnic_up(adapter, netdev);
1386 netif_device_attach(netdev);
1389 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1392 struct qlcnic_cmd_args cmd;
1397 /* Get LED configuration */
1398 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1399 QLCNIC_CMD_GET_LED_CONFIG);
1403 status = qlcnic_issue_cmd(adapter, &cmd);
1405 dev_err(&adapter->pdev->dev,
1406 "Get led config failed.\n");
1409 for (i = 0; i < 4; i++)
1410 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1412 qlcnic_free_mbx_args(&cmd);
1413 /* Set LED Configuration */
1414 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1415 LSW(QLC_83XX_LED_CONFIG);
1416 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1417 QLCNIC_CMD_SET_LED_CONFIG);
1421 cmd.req.arg[1] = mbx_in;
1422 cmd.req.arg[2] = mbx_in;
1423 cmd.req.arg[3] = mbx_in;
1425 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1426 status = qlcnic_issue_cmd(adapter, &cmd);
1428 dev_err(&adapter->pdev->dev,
1429 "Set led config failed.\n");
1432 qlcnic_free_mbx_args(&cmd);
1436 /* Restoring default LED configuration */
1437 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1438 QLCNIC_CMD_SET_LED_CONFIG);
1442 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1443 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1444 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1446 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1447 status = qlcnic_issue_cmd(adapter, &cmd);
1449 dev_err(&adapter->pdev->dev,
1450 "Restoring led config failed.\n");
1451 qlcnic_free_mbx_args(&cmd);
1456 int qlcnic_83xx_set_led(struct net_device *netdev,
1457 enum ethtool_phys_id_state state)
1459 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1460 int err = -EIO, active = 1;
1462 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1464 "LED test is not supported in non-privileged mode\n");
1469 case ETHTOOL_ID_ACTIVE:
1470 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1473 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1476 err = qlcnic_83xx_config_led(adapter, active, 0);
1478 netdev_err(netdev, "Failed to set LED blink state\n");
1480 case ETHTOOL_ID_INACTIVE:
1483 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1486 err = qlcnic_83xx_config_led(adapter, active, 0);
1488 netdev_err(netdev, "Failed to reset LED blink state\n");
1496 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1501 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1504 struct qlcnic_cmd_args cmd;
1507 if (qlcnic_sriov_vf_check(adapter))
1511 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1512 QLCNIC_CMD_INIT_NIC_FUNC);
1516 cmd.req.arg[1] = BIT_0 | BIT_31;
1518 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1519 QLCNIC_CMD_STOP_NIC_FUNC);
1523 cmd.req.arg[1] = BIT_0 | BIT_31;
1525 status = qlcnic_issue_cmd(adapter, &cmd);
1527 dev_err(&adapter->pdev->dev,
1528 "Failed to %s in NIC IDC function event.\n",
1529 (enable ? "register" : "unregister"));
1531 qlcnic_free_mbx_args(&cmd);
1534 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1536 struct qlcnic_cmd_args cmd;
1539 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1543 cmd.req.arg[1] = adapter->ahw->port_config;
1544 err = qlcnic_issue_cmd(adapter, &cmd);
1546 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1547 qlcnic_free_mbx_args(&cmd);
1551 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1553 struct qlcnic_cmd_args cmd;
1556 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1560 err = qlcnic_issue_cmd(adapter, &cmd);
1562 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1564 adapter->ahw->port_config = cmd.rsp.arg[1];
1565 qlcnic_free_mbx_args(&cmd);
1569 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1573 struct qlcnic_cmd_args cmd;
1575 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1579 temp = adapter->recv_ctx->context_id << 16;
1580 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1581 err = qlcnic_issue_cmd(adapter, &cmd);
1583 dev_info(&adapter->pdev->dev,
1584 "Setup linkevent mailbox failed\n");
1585 qlcnic_free_mbx_args(&cmd);
1589 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1592 if (qlcnic_sriov_pf_check(adapter)) {
1593 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1595 if (!qlcnic_sriov_vf_check(adapter))
1596 *interface_id = adapter->recv_ctx->context_id << 16;
1600 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1602 struct qlcnic_cmd_args *cmd = NULL;
1606 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1609 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1613 err = qlcnic_alloc_mbx_args(cmd, adapter,
1614 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1618 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1619 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1620 cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1621 err = qlcnic_issue_cmd(adapter, cmd);
1625 qlcnic_free_mbx_args(cmd);
1632 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1634 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1635 struct qlcnic_hardware_context *ahw = adapter->ahw;
1636 u8 drv_sds_rings = adapter->drv_sds_rings;
1637 u8 drv_tx_rings = adapter->drv_tx_rings;
1638 int ret = 0, loop = 0;
1640 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1642 "Loopback test not supported in non privileged mode\n");
1646 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1647 netdev_info(netdev, "Device is resetting\n");
1651 if (qlcnic_get_diag_lock(adapter)) {
1652 netdev_info(netdev, "Device is in diagnostics mode\n");
1656 netdev_info(netdev, "%s loopback test in progress\n",
1657 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1659 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1662 goto fail_diag_alloc;
1664 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1668 /* Poll for link up event before running traffic */
1670 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1672 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1674 "Device is resetting, free LB test resources\n");
1678 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1680 "Firmware didn't sent link up event to loopback request\n");
1682 qlcnic_83xx_clear_lb_mode(adapter, mode);
1685 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1687 /* Make sure carrier is off and queue is stopped during loopback */
1688 if (netif_running(netdev)) {
1689 netif_carrier_off(netdev);
1690 netif_tx_stop_all_queues(netdev);
1693 ret = qlcnic_do_lb_test(adapter, mode);
1695 qlcnic_83xx_clear_lb_mode(adapter, mode);
1698 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1701 adapter->drv_sds_rings = drv_sds_rings;
1702 adapter->drv_tx_rings = drv_tx_rings;
1703 qlcnic_release_diag_lock(adapter);
1707 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1708 u32 *max_wait_count)
1710 struct qlcnic_hardware_context *ahw = adapter->ahw;
1713 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1714 ahw->extend_lb_time);
1715 temp = ahw->extend_lb_time * 1000;
1716 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1717 ahw->extend_lb_time = 0;
1720 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1722 struct qlcnic_hardware_context *ahw = adapter->ahw;
1723 struct net_device *netdev = adapter->netdev;
1724 u32 config, max_wait_count;
1725 int status = 0, loop = 0;
1727 ahw->extend_lb_time = 0;
1728 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1729 status = qlcnic_83xx_get_port_config(adapter);
1733 config = ahw->port_config;
1735 /* Check if port is already in loopback mode */
1736 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1737 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1739 "Port already in Loopback mode.\n");
1740 return -EINPROGRESS;
1743 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1745 if (mode == QLCNIC_ILB_MODE)
1746 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1747 if (mode == QLCNIC_ELB_MODE)
1748 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1750 status = qlcnic_83xx_set_port_config(adapter);
1753 "Failed to Set Loopback Mode = 0x%x.\n",
1755 ahw->port_config = config;
1756 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1760 /* Wait for Link and IDC Completion AEN */
1762 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1764 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1766 "Device is resetting, free LB test resources\n");
1767 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1771 if (ahw->extend_lb_time)
1772 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1775 if (loop++ > max_wait_count) {
1776 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1778 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1779 qlcnic_83xx_clear_lb_mode(adapter, mode);
1782 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1784 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1789 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1791 struct qlcnic_hardware_context *ahw = adapter->ahw;
1792 u32 config = ahw->port_config, max_wait_count;
1793 struct net_device *netdev = adapter->netdev;
1794 int status = 0, loop = 0;
1796 ahw->extend_lb_time = 0;
1797 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1798 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1799 if (mode == QLCNIC_ILB_MODE)
1800 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1801 if (mode == QLCNIC_ELB_MODE)
1802 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1804 status = qlcnic_83xx_set_port_config(adapter);
1807 "Failed to Clear Loopback Mode = 0x%x.\n",
1809 ahw->port_config = config;
1810 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1814 /* Wait for Link and IDC Completion AEN */
1816 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1818 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1820 "Device is resetting, free LB test resources\n");
1821 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1825 if (ahw->extend_lb_time)
1826 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1829 if (loop++ > max_wait_count) {
1830 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1832 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1835 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1837 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1842 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1845 if (qlcnic_sriov_pf_check(adapter)) {
1846 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1848 if (!qlcnic_sriov_vf_check(adapter))
1849 *interface_id = adapter->recv_ctx->context_id << 16;
1853 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1857 u32 temp = 0, temp_ip;
1858 struct qlcnic_cmd_args cmd;
1860 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1861 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1865 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1867 if (mode == QLCNIC_IP_UP)
1868 cmd.req.arg[1] = 1 | temp;
1870 cmd.req.arg[1] = 2 | temp;
1873 * Adapter needs IP address in network byte order.
1874 * But hardware mailbox registers go through writel(), hence IP address
1875 * gets swapped on big endian architecture.
1876 * To negate swapping of writel() on big endian architecture
1877 * use swab32(value).
1880 temp_ip = swab32(ntohl(ip));
1881 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1882 err = qlcnic_issue_cmd(adapter, &cmd);
1883 if (err != QLCNIC_RCODE_SUCCESS)
1884 dev_err(&adapter->netdev->dev,
1885 "could not notify %s IP 0x%x request\n",
1886 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1888 qlcnic_free_mbx_args(&cmd);
1891 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1895 struct qlcnic_cmd_args cmd;
1898 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1900 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1903 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1907 temp = adapter->recv_ctx->context_id << 16;
1908 arg1 = lro_bit_mask | temp;
1909 cmd.req.arg[1] = arg1;
1911 err = qlcnic_issue_cmd(adapter, &cmd);
1913 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1914 qlcnic_free_mbx_args(&cmd);
1919 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1923 struct qlcnic_cmd_args cmd;
1924 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1925 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1926 0x255b0ec26d5a56daULL };
1928 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1934 * 5-4: hash_type_ipv4
1935 * 7-6: hash_type_ipv6
1937 * 9: use indirection table
1938 * 16-31: indirection table mask
1940 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1941 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1942 ((u32)(enable & 0x1) << 8) |
1944 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1945 cmd.req.arg[2] = word;
1946 memcpy(&cmd.req.arg[4], key, sizeof(key));
1948 err = qlcnic_issue_cmd(adapter, &cmd);
1951 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1952 qlcnic_free_mbx_args(&cmd);
1958 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1961 if (qlcnic_sriov_pf_check(adapter)) {
1962 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1964 if (!qlcnic_sriov_vf_check(adapter))
1965 *interface_id = adapter->recv_ctx->context_id << 16;
1969 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1972 struct qlcnic_cmd_args *cmd = NULL;
1973 struct qlcnic_macvlan_mbx mv;
1977 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1980 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1984 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1988 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1991 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1992 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1994 cmd->req.arg[1] = op | (1 << 8);
1995 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1996 cmd->req.arg[1] |= temp;
1998 mv.mac_addr0 = addr[0];
1999 mv.mac_addr1 = addr[1];
2000 mv.mac_addr2 = addr[2];
2001 mv.mac_addr3 = addr[3];
2002 mv.mac_addr4 = addr[4];
2003 mv.mac_addr5 = addr[5];
2004 buf = &cmd->req.arg[2];
2005 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2006 err = qlcnic_issue_cmd(adapter, cmd);
2010 qlcnic_free_mbx_args(cmd);
2016 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2020 memcpy(&mac, addr, ETH_ALEN);
2021 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2024 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2025 u8 type, struct qlcnic_cmd_args *cmd)
2028 case QLCNIC_SET_STATION_MAC:
2029 case QLCNIC_SET_FAC_DEF_MAC:
2030 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2031 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2034 cmd->req.arg[1] = type;
2037 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2041 struct qlcnic_cmd_args cmd;
2042 u32 mac_low, mac_high;
2045 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2049 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2050 err = qlcnic_issue_cmd(adapter, &cmd);
2052 if (err == QLCNIC_RCODE_SUCCESS) {
2053 mac_low = cmd.rsp.arg[1];
2054 mac_high = cmd.rsp.arg[2];
2056 for (i = 0; i < 2; i++)
2057 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2058 for (i = 2; i < 6; i++)
2059 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2061 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2065 qlcnic_free_mbx_args(&cmd);
2069 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2073 struct qlcnic_cmd_args cmd;
2074 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2076 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2079 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2083 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2084 temp = adapter->recv_ctx->context_id;
2085 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2086 temp = coal->rx_time_us;
2087 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2088 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2089 temp = adapter->tx_ring->ctx_id;
2090 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2091 temp = coal->tx_time_us;
2092 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2094 cmd.req.arg[3] = coal->flag;
2095 err = qlcnic_issue_cmd(adapter, &cmd);
2096 if (err != QLCNIC_RCODE_SUCCESS)
2097 dev_info(&adapter->pdev->dev,
2098 "Failed to send interrupt coalescence parameters\n");
2099 qlcnic_free_mbx_args(&cmd);
2102 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2105 struct qlcnic_hardware_context *ahw = adapter->ahw;
2106 u8 link_status, duplex;
2108 link_status = LSB(data[3]) & 1;
2110 ahw->link_speed = MSW(data[2]);
2111 duplex = LSB(MSW(data[3]));
2113 ahw->link_duplex = DUPLEX_FULL;
2115 ahw->link_duplex = DUPLEX_HALF;
2117 ahw->link_speed = SPEED_UNKNOWN;
2118 ahw->link_duplex = DUPLEX_UNKNOWN;
2121 ahw->link_autoneg = MSB(MSW(data[3]));
2122 ahw->module_type = MSB(LSW(data[3]));
2123 ahw->has_link_events = 1;
2124 qlcnic_advert_link_change(adapter, link_status);
2127 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2129 struct qlcnic_adapter *adapter = data;
2130 struct qlcnic_mailbox *mbx;
2131 u32 mask, resp, event;
2132 unsigned long flags;
2134 mbx = adapter->ahw->mailbox;
2135 spin_lock_irqsave(&mbx->aen_lock, flags);
2136 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2137 if (!(resp & QLCNIC_SET_OWNER))
2140 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2141 if (event & QLCNIC_MBX_ASYNC_EVENT)
2142 __qlcnic_83xx_process_aen(adapter);
2144 qlcnic_83xx_notify_mbx_response(mbx);
2147 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2148 writel(0, adapter->ahw->pci_base0 + mask);
2149 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2153 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2156 struct qlcnic_cmd_args cmd;
2158 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2159 dev_err(&adapter->pdev->dev,
2160 "%s: Error, invoked by non management func\n",
2165 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2169 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2170 err = qlcnic_issue_cmd(adapter, &cmd);
2172 if (err != QLCNIC_RCODE_SUCCESS) {
2173 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2177 qlcnic_free_mbx_args(&cmd);
2183 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2184 struct qlcnic_info *nic)
2187 struct qlcnic_cmd_args cmd;
2189 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2190 dev_err(&adapter->pdev->dev,
2191 "%s: Error, invoked by non management func\n",
2196 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2200 cmd.req.arg[1] = (nic->pci_func << 16);
2201 cmd.req.arg[2] = 0x1 << 16;
2202 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2203 cmd.req.arg[4] = nic->capabilities;
2204 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2205 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2206 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2207 for (i = 8; i < 32; i++)
2210 err = qlcnic_issue_cmd(adapter, &cmd);
2212 if (err != QLCNIC_RCODE_SUCCESS) {
2213 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2218 qlcnic_free_mbx_args(&cmd);
2223 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2224 struct qlcnic_info *npar_info, u8 func_id)
2229 struct qlcnic_cmd_args cmd;
2230 struct qlcnic_hardware_context *ahw = adapter->ahw;
2232 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2236 if (func_id != ahw->pci_func) {
2237 temp = func_id << 16;
2238 cmd.req.arg[1] = op | BIT_31 | temp;
2240 cmd.req.arg[1] = ahw->pci_func << 16;
2242 err = qlcnic_issue_cmd(adapter, &cmd);
2244 dev_info(&adapter->pdev->dev,
2245 "Failed to get nic info %d\n", err);
2249 npar_info->op_type = cmd.rsp.arg[1];
2250 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2251 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2252 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2253 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2254 npar_info->capabilities = cmd.rsp.arg[4];
2255 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2256 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2257 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2258 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2259 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2260 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2261 if (cmd.rsp.arg[8] & 0x1)
2262 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2263 if (cmd.rsp.arg[8] & 0x10000) {
2264 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2265 npar_info->max_linkspeed_reg_offset = temp;
2268 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2269 sizeof(ahw->extra_capability));
2272 qlcnic_free_mbx_args(&cmd);
2276 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2277 struct qlcnic_pci_info *pci_info)
2279 struct qlcnic_hardware_context *ahw = adapter->ahw;
2280 struct device *dev = &adapter->pdev->dev;
2281 struct qlcnic_cmd_args cmd;
2282 int i, err = 0, j = 0;
2285 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2289 err = qlcnic_issue_cmd(adapter, &cmd);
2291 ahw->act_pci_func = 0;
2292 if (err == QLCNIC_RCODE_SUCCESS) {
2293 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2294 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2295 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2296 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2298 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2299 if (pci_info->type == QLCNIC_TYPE_NIC)
2300 ahw->act_pci_func++;
2301 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2302 pci_info->default_port = temp;
2304 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2305 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2306 pci_info->tx_max_bw = temp;
2308 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2310 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2314 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2318 qlcnic_free_mbx_args(&cmd);
2323 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2327 u32 val, temp, type;
2328 struct qlcnic_cmd_args cmd;
2330 max_ints = adapter->ahw->num_msix - 1;
2331 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2335 cmd.req.arg[1] = max_ints;
2337 if (qlcnic_sriov_vf_check(adapter))
2338 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2340 for (i = 0, index = 2; i < max_ints; i++) {
2341 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2342 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2343 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2344 val |= (adapter->ahw->intr_tbl[i].id << 16);
2345 cmd.req.arg[index++] = val;
2347 err = qlcnic_issue_cmd(adapter, &cmd);
2349 dev_err(&adapter->pdev->dev,
2350 "Failed to configure interrupts 0x%x\n", err);
2354 max_ints = cmd.rsp.arg[1];
2355 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2356 val = cmd.rsp.arg[index];
2358 dev_info(&adapter->pdev->dev,
2359 "Can't configure interrupt %d\n",
2360 adapter->ahw->intr_tbl[i].id);
2364 adapter->ahw->intr_tbl[i].id = MSW(val);
2365 adapter->ahw->intr_tbl[i].enabled = 1;
2366 temp = cmd.rsp.arg[index + 1];
2367 adapter->ahw->intr_tbl[i].src = temp;
2369 adapter->ahw->intr_tbl[i].id = i;
2370 adapter->ahw->intr_tbl[i].enabled = 0;
2371 adapter->ahw->intr_tbl[i].src = 0;
2375 qlcnic_free_mbx_args(&cmd);
2379 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2381 int id, timeout = 0;
2384 while (status == 0) {
2385 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2389 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2390 id = QLC_SHARED_REG_RD32(adapter,
2391 QLCNIC_FLASH_LOCK_OWNER);
2392 dev_err(&adapter->pdev->dev,
2393 "%s: failed, lock held by %d\n", __func__, id);
2396 usleep_range(1000, 2000);
2399 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2403 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2405 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2406 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2409 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2410 u32 flash_addr, u8 *p_data,
2413 u32 word, range, flash_offset, addr = flash_addr, ret;
2414 ulong indirect_add, direct_window;
2417 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2419 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2423 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2426 range = flash_offset + (count * sizeof(u32));
2427 /* Check if data is spread across multiple sectors */
2428 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2430 /* Multi sector read */
2431 for (i = 0; i < count; i++) {
2432 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2433 ret = QLCRD32(adapter, indirect_add, &err);
2438 *(u32 *)p_data = word;
2439 p_data = p_data + 4;
2441 flash_offset = flash_offset + 4;
2443 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2444 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2445 /* This write is needed once for each sector */
2446 qlcnic_83xx_wrt_reg_indirect(adapter,
2453 /* Single sector read */
2454 for (i = 0; i < count; i++) {
2455 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2456 ret = QLCRD32(adapter, indirect_add, &err);
2461 *(u32 *)p_data = word;
2462 p_data = p_data + 4;
2470 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2473 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2477 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2481 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2482 QLC_83XX_FLASH_STATUS_READY)
2485 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2486 } while (--retries);
2494 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2498 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2499 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2500 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2501 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2502 adapter->ahw->fdt.write_enable_bits);
2503 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2504 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2505 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2512 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2516 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2517 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2518 adapter->ahw->fdt.write_statusreg_cmd));
2519 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2520 adapter->ahw->fdt.write_disable_bits);
2521 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2522 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2523 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2530 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2535 if (qlcnic_83xx_lock_flash(adapter))
2538 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2539 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2540 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2541 QLC_83XX_FLASH_READ_CTRL);
2542 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2544 qlcnic_83xx_unlock_flash(adapter);
2548 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2550 qlcnic_83xx_unlock_flash(adapter);
2554 adapter->flash_mfg_id = (mfg_id & 0xFF);
2555 qlcnic_83xx_unlock_flash(adapter);
2560 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2562 int count, fdt_size, ret = 0;
2564 fdt_size = sizeof(struct qlcnic_fdt);
2565 count = fdt_size / sizeof(u32);
2567 if (qlcnic_83xx_lock_flash(adapter))
2570 memset(&adapter->ahw->fdt, 0, fdt_size);
2571 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2572 (u8 *)&adapter->ahw->fdt,
2575 qlcnic_83xx_unlock_flash(adapter);
2579 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2580 u32 sector_start_addr)
2582 u32 reversed_addr, addr1, addr2, cmd;
2585 if (qlcnic_83xx_lock_flash(adapter) != 0)
2588 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2589 ret = qlcnic_83xx_enable_flash_write(adapter);
2591 qlcnic_83xx_unlock_flash(adapter);
2592 dev_err(&adapter->pdev->dev,
2593 "%s failed at %d\n",
2594 __func__, __LINE__);
2599 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2601 qlcnic_83xx_unlock_flash(adapter);
2602 dev_err(&adapter->pdev->dev,
2603 "%s: failed at %d\n", __func__, __LINE__);
2607 addr1 = (sector_start_addr & 0xFF) << 16;
2608 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2609 reversed_addr = addr1 | addr2;
2611 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2613 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2614 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2615 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2617 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2618 QLC_83XX_FLASH_OEM_ERASE_SIG);
2619 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2620 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2622 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2624 qlcnic_83xx_unlock_flash(adapter);
2625 dev_err(&adapter->pdev->dev,
2626 "%s: failed at %d\n", __func__, __LINE__);
2630 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2631 ret = qlcnic_83xx_disable_flash_write(adapter);
2633 qlcnic_83xx_unlock_flash(adapter);
2634 dev_err(&adapter->pdev->dev,
2635 "%s: failed at %d\n", __func__, __LINE__);
2640 qlcnic_83xx_unlock_flash(adapter);
2645 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2649 u32 addr1 = 0x00800000 | (addr >> 2);
2651 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2652 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2653 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2654 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2655 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2657 dev_err(&adapter->pdev->dev,
2658 "%s: failed at %d\n", __func__, __LINE__);
2665 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2666 u32 *p_data, int count)
2669 int ret = -EIO, err = 0;
2671 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2672 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2673 dev_err(&adapter->pdev->dev,
2674 "%s: Invalid word count\n", __func__);
2678 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2682 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2683 (temp | QLC_83XX_FLASH_SPI_CTRL));
2684 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2685 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2687 /* First DWORD write */
2688 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2689 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2690 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2691 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2693 dev_err(&adapter->pdev->dev,
2694 "%s: failed at %d\n", __func__, __LINE__);
2699 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2700 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2701 /* Second to N-1 DWORD writes */
2702 while (count != 1) {
2703 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2705 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2706 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2707 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2709 dev_err(&adapter->pdev->dev,
2710 "%s: failed at %d\n", __func__, __LINE__);
2716 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2717 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2719 /* Last DWORD write */
2720 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2721 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2722 QLC_83XX_FLASH_LAST_MS_PATTERN);
2723 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2725 dev_err(&adapter->pdev->dev,
2726 "%s: failed at %d\n", __func__, __LINE__);
2730 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2734 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2735 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2736 __func__, __LINE__);
2737 /* Operation failed, clear error bit */
2738 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2742 qlcnic_83xx_wrt_reg_indirect(adapter,
2743 QLC_83XX_FLASH_SPI_CONTROL,
2744 (temp | QLC_83XX_FLASH_SPI_CTRL));
2750 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2754 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2756 /* Check if recovery need to be performed by the calling function */
2757 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2759 val = val | ((adapter->portnum << 2) |
2760 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2761 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2762 dev_info(&adapter->pdev->dev,
2763 "%s: lock recovery initiated\n", __func__);
2764 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2765 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2766 id = ((val >> 2) & 0xF);
2767 if (id == adapter->portnum) {
2768 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2769 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2770 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2771 /* Force release the lock */
2772 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2773 /* Clear recovery bits */
2775 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2776 dev_info(&adapter->pdev->dev,
2777 "%s: lock recovery completed\n", __func__);
2779 dev_info(&adapter->pdev->dev,
2780 "%s: func %d to resume lock recovery process\n",
2784 dev_info(&adapter->pdev->dev,
2785 "%s: lock recovery initiated by other functions\n",
2790 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2792 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2793 int max_attempt = 0;
2795 while (status == 0) {
2796 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2800 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2804 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2806 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2807 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2810 dev_info(&adapter->pdev->dev,
2811 "%s: lock to be recovered from %d\n",
2813 qlcnic_83xx_recover_driver_lock(adapter);
2817 dev_err(&adapter->pdev->dev,
2818 "%s: failed to get lock\n", __func__);
2823 /* Force exit from while loop after few attempts */
2824 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2825 dev_err(&adapter->pdev->dev,
2826 "%s: failed to get lock\n", __func__);
2831 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2832 lock_alive_counter = val >> 8;
2833 lock_alive_counter++;
2834 val = lock_alive_counter << 8 | adapter->portnum;
2835 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2840 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2842 u32 val, lock_alive_counter, id;
2844 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2846 lock_alive_counter = val >> 8;
2848 if (id != adapter->portnum)
2849 dev_err(&adapter->pdev->dev,
2850 "%s:Warning func %d is unlocking lock owned by %d\n",
2851 __func__, adapter->portnum, id);
2853 val = (lock_alive_counter << 8) | 0xFF;
2854 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2855 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2858 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2859 u32 *data, u32 count)
2865 /* Check alignment */
2869 mutex_lock(&adapter->ahw->mem_lock);
2870 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2872 for (i = 0; i < count; i++, addr += 16) {
2873 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2874 QLCNIC_ADDR_QDR_NET_MAX)) ||
2875 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2876 QLCNIC_ADDR_DDR_NET_MAX)))) {
2877 mutex_unlock(&adapter->ahw->mem_lock);
2881 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2882 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2884 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2886 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2888 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2890 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2891 QLCNIC_TA_WRITE_ENABLE);
2892 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2893 QLCNIC_TA_WRITE_START);
2895 for (j = 0; j < MAX_CTL_CHECK; j++) {
2896 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2898 mutex_unlock(&adapter->ahw->mem_lock);
2902 if ((temp & TA_CTL_BUSY) == 0)
2906 /* Status check failure */
2907 if (j >= MAX_CTL_CHECK) {
2908 printk_ratelimited(KERN_WARNING
2909 "MS memory write failed\n");
2910 mutex_unlock(&adapter->ahw->mem_lock);
2915 mutex_unlock(&adapter->ahw->mem_lock);
2920 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2921 u8 *p_data, int count)
2923 u32 word, addr = flash_addr, ret;
2924 ulong indirect_addr;
2927 if (qlcnic_83xx_lock_flash(adapter) != 0)
2931 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2932 qlcnic_83xx_unlock_flash(adapter);
2936 for (i = 0; i < count; i++) {
2937 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2938 QLC_83XX_FLASH_DIRECT_WINDOW,
2940 qlcnic_83xx_unlock_flash(adapter);
2944 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2945 ret = QLCRD32(adapter, indirect_addr, &err);
2950 *(u32 *)p_data = word;
2951 p_data = p_data + 4;
2955 qlcnic_83xx_unlock_flash(adapter);
2960 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2964 u32 config = 0, state;
2965 struct qlcnic_cmd_args cmd;
2966 struct qlcnic_hardware_context *ahw = adapter->ahw;
2968 if (qlcnic_sriov_vf_check(adapter))
2969 pci_func = adapter->portnum;
2971 pci_func = ahw->pci_func;
2973 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2974 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2975 dev_info(&adapter->pdev->dev, "link state down\n");
2979 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2983 err = qlcnic_issue_cmd(adapter, &cmd);
2985 dev_info(&adapter->pdev->dev,
2986 "Get Link Status Command failed: 0x%x\n", err);
2989 config = cmd.rsp.arg[1];
2990 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2991 case QLC_83XX_10M_LINK:
2992 ahw->link_speed = SPEED_10;
2994 case QLC_83XX_100M_LINK:
2995 ahw->link_speed = SPEED_100;
2997 case QLC_83XX_1G_LINK:
2998 ahw->link_speed = SPEED_1000;
3000 case QLC_83XX_10G_LINK:
3001 ahw->link_speed = SPEED_10000;
3004 ahw->link_speed = 0;
3007 config = cmd.rsp.arg[3];
3008 if (QLC_83XX_SFP_PRESENT(config)) {
3009 switch (ahw->module_type) {
3010 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3011 case LINKEVENT_MODULE_OPTICAL_SRLR:
3012 case LINKEVENT_MODULE_OPTICAL_LRM:
3013 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3014 ahw->supported_type = PORT_FIBRE;
3016 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3017 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3018 case LINKEVENT_MODULE_TWINAX:
3019 ahw->supported_type = PORT_TP;
3022 ahw->supported_type = PORT_OTHER;
3029 qlcnic_free_mbx_args(&cmd);
3033 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3034 struct ethtool_cmd *ecmd)
3038 struct qlcnic_hardware_context *ahw = adapter->ahw;
3040 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3041 /* Get port configuration info */
3042 status = qlcnic_83xx_get_port_info(adapter);
3043 /* Get Link Status related info */
3044 config = qlcnic_83xx_test_link(adapter);
3045 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3048 /* hard code until there is a way to get it from flash */
3049 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3051 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3052 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3053 ecmd->duplex = ahw->link_duplex;
3054 ecmd->autoneg = ahw->link_autoneg;
3056 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3057 ecmd->duplex = DUPLEX_UNKNOWN;
3058 ecmd->autoneg = AUTONEG_DISABLE;
3061 if (ahw->port_type == QLCNIC_XGBE) {
3062 ecmd->supported = SUPPORTED_10000baseT_Full;
3063 ecmd->advertising = ADVERTISED_10000baseT_Full;
3065 ecmd->supported = (SUPPORTED_10baseT_Half |
3066 SUPPORTED_10baseT_Full |
3067 SUPPORTED_100baseT_Half |
3068 SUPPORTED_100baseT_Full |
3069 SUPPORTED_1000baseT_Half |
3070 SUPPORTED_1000baseT_Full);
3071 ecmd->advertising = (ADVERTISED_100baseT_Half |
3072 ADVERTISED_100baseT_Full |
3073 ADVERTISED_1000baseT_Half |
3074 ADVERTISED_1000baseT_Full);
3077 switch (ahw->supported_type) {
3079 ecmd->supported |= SUPPORTED_FIBRE;
3080 ecmd->advertising |= ADVERTISED_FIBRE;
3081 ecmd->port = PORT_FIBRE;
3082 ecmd->transceiver = XCVR_EXTERNAL;
3085 ecmd->supported |= SUPPORTED_TP;
3086 ecmd->advertising |= ADVERTISED_TP;
3087 ecmd->port = PORT_TP;
3088 ecmd->transceiver = XCVR_INTERNAL;
3091 ecmd->supported |= SUPPORTED_FIBRE;
3092 ecmd->advertising |= ADVERTISED_FIBRE;
3093 ecmd->port = PORT_OTHER;
3094 ecmd->transceiver = XCVR_EXTERNAL;
3097 ecmd->phy_address = ahw->physical_port;
3101 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3102 struct ethtool_cmd *ecmd)
3105 u32 config = adapter->ahw->port_config;
3108 adapter->ahw->port_config |= BIT_15;
3110 switch (ethtool_cmd_speed(ecmd)) {
3112 adapter->ahw->port_config |= BIT_8;
3115 adapter->ahw->port_config |= BIT_9;
3118 adapter->ahw->port_config |= BIT_10;
3121 adapter->ahw->port_config |= BIT_11;
3127 status = qlcnic_83xx_set_port_config(adapter);
3129 dev_info(&adapter->pdev->dev,
3130 "Failed to Set Link Speed and autoneg.\n");
3131 adapter->ahw->port_config = config;
3136 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3137 u64 *data, int index)
3142 low = cmd->rsp.arg[index];
3143 hi = cmd->rsp.arg[index + 1];
3144 val = (((u64) low) | (((u64) hi) << 32));
3149 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3150 struct qlcnic_cmd_args *cmd, u64 *data,
3153 int err, k, total_regs;
3156 err = qlcnic_issue_cmd(adapter, cmd);
3157 if (err != QLCNIC_RCODE_SUCCESS) {
3158 dev_info(&adapter->pdev->dev,
3159 "Error in get statistics mailbox command\n");
3163 total_regs = cmd->rsp.num;
3165 case QLC_83XX_STAT_MAC:
3166 /* fill in MAC tx counters */
3167 for (k = 2; k < 28; k += 2)
3168 data = qlcnic_83xx_copy_stats(cmd, data, k);
3169 /* skip 24 bytes of reserved area */
3170 /* fill in MAC rx counters */
3171 for (k += 6; k < 60; k += 2)
3172 data = qlcnic_83xx_copy_stats(cmd, data, k);
3173 /* skip 24 bytes of reserved area */
3174 /* fill in MAC rx frame stats */
3175 for (k += 6; k < 80; k += 2)
3176 data = qlcnic_83xx_copy_stats(cmd, data, k);
3177 /* fill in eSwitch stats */
3178 for (; k < total_regs; k += 2)
3179 data = qlcnic_83xx_copy_stats(cmd, data, k);
3181 case QLC_83XX_STAT_RX:
3182 for (k = 2; k < 8; k += 2)
3183 data = qlcnic_83xx_copy_stats(cmd, data, k);
3184 /* skip 8 bytes of reserved data */
3185 for (k += 2; k < 24; k += 2)
3186 data = qlcnic_83xx_copy_stats(cmd, data, k);
3187 /* skip 8 bytes containing RE1FBQ error data */
3188 for (k += 2; k < total_regs; k += 2)
3189 data = qlcnic_83xx_copy_stats(cmd, data, k);
3191 case QLC_83XX_STAT_TX:
3192 for (k = 2; k < 10; k += 2)
3193 data = qlcnic_83xx_copy_stats(cmd, data, k);
3194 /* skip 8 bytes of reserved data */
3195 for (k += 2; k < total_regs; k += 2)
3196 data = qlcnic_83xx_copy_stats(cmd, data, k);
3199 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3205 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3207 struct qlcnic_cmd_args cmd;
3208 struct net_device *netdev = adapter->netdev;
3211 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3215 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3216 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3217 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3218 QLC_83XX_STAT_TX, &ret);
3220 netdev_err(netdev, "Error getting Tx stats\n");
3224 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3225 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3226 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3227 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3228 QLC_83XX_STAT_MAC, &ret);
3230 netdev_err(netdev, "Error getting MAC stats\n");
3234 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3235 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3236 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3237 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3238 QLC_83XX_STAT_RX, &ret);
3240 netdev_err(netdev, "Error getting Rx stats\n");
3242 qlcnic_free_mbx_args(&cmd);
3245 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3247 u32 major, minor, sub;
3249 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3250 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3251 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3253 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3254 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3261 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3263 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3264 sizeof(*adapter->ahw->ext_reg_tbl)) +
3265 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3266 sizeof(*adapter->ahw->reg_tbl));
3269 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3273 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3274 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3275 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3277 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3278 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3282 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3284 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3285 struct qlcnic_hardware_context *ahw = adapter->ahw;
3286 struct qlcnic_cmd_args cmd;
3287 u8 val, drv_sds_rings = adapter->drv_sds_rings;
3288 u8 drv_tx_rings = adapter->drv_tx_rings;
3293 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3294 netdev_info(netdev, "Device is resetting\n");
3298 if (qlcnic_get_diag_lock(adapter)) {
3299 netdev_info(netdev, "Device in diagnostics mode\n");
3303 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3309 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3313 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3314 intrpt_id = ahw->intr_tbl[0].id;
3316 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3319 cmd.req.arg[2] = intrpt_id;
3320 cmd.req.arg[3] = BIT_0;
3322 ret = qlcnic_issue_cmd(adapter, &cmd);
3323 data = cmd.rsp.arg[2];
3325 val = LSB(MSW(data));
3326 if (id != intrpt_id)
3327 dev_info(&adapter->pdev->dev,
3328 "Interrupt generated: 0x%x, requested:0x%x\n",
3331 dev_err(&adapter->pdev->dev,
3332 "Interrupt test error: 0x%x\n", val);
3337 ret = !ahw->diag_cnt;
3340 qlcnic_free_mbx_args(&cmd);
3341 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3344 adapter->drv_sds_rings = drv_sds_rings;
3345 adapter->drv_tx_rings = drv_tx_rings;
3346 qlcnic_release_diag_lock(adapter);
3350 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3351 struct ethtool_pauseparam *pause)
3353 struct qlcnic_hardware_context *ahw = adapter->ahw;
3357 status = qlcnic_83xx_get_port_config(adapter);
3359 dev_err(&adapter->pdev->dev,
3360 "%s: Get Pause Config failed\n", __func__);
3363 config = ahw->port_config;
3364 if (config & QLC_83XX_CFG_STD_PAUSE) {
3365 switch (MSW(config)) {
3366 case QLC_83XX_TX_PAUSE:
3367 pause->tx_pause = 1;
3369 case QLC_83XX_RX_PAUSE:
3370 pause->rx_pause = 1;
3372 case QLC_83XX_TX_RX_PAUSE:
3374 /* Backward compatibility for existing
3377 pause->tx_pause = 1;
3378 pause->rx_pause = 1;
3382 if (QLC_83XX_AUTONEG(config))
3386 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3387 struct ethtool_pauseparam *pause)
3389 struct qlcnic_hardware_context *ahw = adapter->ahw;
3393 status = qlcnic_83xx_get_port_config(adapter);
3395 dev_err(&adapter->pdev->dev,
3396 "%s: Get Pause Config failed.\n", __func__);
3399 config = ahw->port_config;
3401 if (ahw->port_type == QLCNIC_GBE) {
3403 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3404 if (!pause->autoneg)
3405 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3406 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3410 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3411 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3413 if (pause->rx_pause && pause->tx_pause) {
3414 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3415 } else if (pause->rx_pause && !pause->tx_pause) {
3416 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3417 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3418 } else if (pause->tx_pause && !pause->rx_pause) {
3419 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3420 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3421 } else if (!pause->rx_pause && !pause->tx_pause) {
3422 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3423 QLC_83XX_CFG_STD_PAUSE);
3425 status = qlcnic_83xx_set_port_config(adapter);
3427 dev_err(&adapter->pdev->dev,
3428 "%s: Set Pause Config failed.\n", __func__);
3429 ahw->port_config = config;
3434 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3439 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3440 QLC_83XX_FLASH_OEM_READ_SIG);
3441 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3442 QLC_83XX_FLASH_READ_CTRL);
3443 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3447 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3454 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3458 status = qlcnic_83xx_read_flash_status_reg(adapter);
3459 if (status == -EIO) {
3460 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3467 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3469 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3470 struct net_device *netdev = adapter->netdev;
3473 netif_device_detach(netdev);
3474 qlcnic_cancel_idc_work(adapter);
3476 if (netif_running(netdev))
3477 qlcnic_down(adapter, netdev);
3479 qlcnic_83xx_disable_mbx_intr(adapter);
3480 cancel_delayed_work_sync(&adapter->idc_aen_work);
3482 retval = pci_save_state(pdev);
3489 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3491 struct qlcnic_hardware_context *ahw = adapter->ahw;
3492 struct qlc_83xx_idc *idc = &ahw->idc;
3495 err = qlcnic_83xx_idc_init(adapter);
3499 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3500 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3501 qlcnic_83xx_set_vnic_opmode(adapter);
3503 err = qlcnic_83xx_check_vnic_state(adapter);
3509 err = qlcnic_83xx_idc_reattach_driver(adapter);
3513 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3518 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3520 reinit_completion(&mbx->completion);
3521 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3524 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3529 destroy_workqueue(mbx->work_q);
3534 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3535 struct qlcnic_cmd_args *cmd)
3537 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3539 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3540 qlcnic_free_mbx_args(cmd);
3544 complete(&cmd->completion);
3547 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3549 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3550 struct list_head *head = &mbx->cmd_q;
3551 struct qlcnic_cmd_args *cmd = NULL;
3553 spin_lock(&mbx->queue_lock);
3555 while (!list_empty(head)) {
3556 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3557 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3558 __func__, cmd->cmd_op);
3559 list_del(&cmd->list);
3561 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3564 spin_unlock(&mbx->queue_lock);
3567 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3569 struct qlcnic_hardware_context *ahw = adapter->ahw;
3570 struct qlcnic_mailbox *mbx = ahw->mailbox;
3573 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3576 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3577 if (host_mbx_ctrl) {
3578 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3579 ahw->idc.collect_dump = 1;
3586 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3590 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3592 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3595 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3596 struct qlcnic_cmd_args *cmd)
3598 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3600 spin_lock(&mbx->queue_lock);
3602 list_del(&cmd->list);
3605 spin_unlock(&mbx->queue_lock);
3607 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3610 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3611 struct qlcnic_cmd_args *cmd)
3613 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3614 struct qlcnic_hardware_context *ahw = adapter->ahw;
3617 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3618 mbx_cmd = cmd->req.arg[0];
3619 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3620 for (i = 1; i < cmd->req.num; i++)
3621 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3623 fw_hal_version = ahw->fw_hal_version;
3624 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3625 total_size = cmd->pay_size + hdr_size;
3626 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3627 mbx_cmd = tmp | fw_hal_version << 29;
3628 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3630 /* Back channel specific operations bits */
3631 mbx_cmd = 0x1 | 1 << 4;
3633 if (qlcnic_sriov_pf_check(adapter))
3634 mbx_cmd |= cmd->func_num << 5;
3636 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3638 for (i = 2, j = 0; j < hdr_size; i++, j++)
3639 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3640 for (j = 0; j < cmd->pay_size; j++, i++)
3641 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3645 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3647 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3652 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3653 complete(&mbx->completion);
3654 cancel_work_sync(&mbx->work);
3655 flush_workqueue(mbx->work_q);
3656 qlcnic_83xx_flush_mbx_queue(adapter);
3659 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3660 struct qlcnic_cmd_args *cmd,
3661 unsigned long *timeout)
3663 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3665 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3666 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3667 init_completion(&cmd->completion);
3668 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3670 spin_lock(&mbx->queue_lock);
3672 list_add_tail(&cmd->list, &mbx->cmd_q);
3674 cmd->total_cmds = mbx->num_cmds;
3675 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3676 queue_work(mbx->work_q, &mbx->work);
3678 spin_unlock(&mbx->queue_lock);
3686 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3687 struct qlcnic_cmd_args *cmd)
3692 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3693 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3694 mac_cmd_rcode = (u8)fw_data;
3695 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3696 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3697 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3698 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3699 return QLCNIC_RCODE_SUCCESS;
3706 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3707 struct qlcnic_cmd_args *cmd)
3709 struct qlcnic_hardware_context *ahw = adapter->ahw;
3710 struct device *dev = &adapter->pdev->dev;
3714 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3715 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3716 qlcnic_83xx_get_mbx_data(adapter, cmd);
3718 switch (mbx_err_code) {
3719 case QLCNIC_MBX_RSP_OK:
3720 case QLCNIC_MBX_PORT_RSP_OK:
3721 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3724 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3727 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3728 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3729 ahw->op_mode, mbx_err_code);
3730 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3731 qlcnic_dump_mbx(adapter, cmd);
3737 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3739 struct qlcnic_hardware_context *ahw = adapter->ahw;
3742 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3743 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3744 readl(ahw->pci_base0 + offset),
3745 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3746 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3747 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3750 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3752 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3754 struct qlcnic_adapter *adapter = mbx->adapter;
3755 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3756 struct device *dev = &adapter->pdev->dev;
3757 atomic_t *rsp_status = &mbx->rsp_status;
3758 struct list_head *head = &mbx->cmd_q;
3759 struct qlcnic_hardware_context *ahw;
3760 struct qlcnic_cmd_args *cmd = NULL;
3765 if (qlcnic_83xx_check_mbx_status(adapter)) {
3766 qlcnic_83xx_flush_mbx_queue(adapter);
3770 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3772 spin_lock(&mbx->queue_lock);
3774 if (list_empty(head)) {
3775 spin_unlock(&mbx->queue_lock);
3778 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3780 spin_unlock(&mbx->queue_lock);
3782 mbx_ops->encode_cmd(adapter, cmd);
3783 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3785 if (wait_for_completion_timeout(&mbx->completion,
3786 QLC_83XX_MBX_TIMEOUT)) {
3787 mbx_ops->decode_resp(adapter, cmd);
3788 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3790 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3791 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3793 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3794 qlcnic_dump_mailbox_registers(adapter);
3795 qlcnic_83xx_get_mbx_data(adapter, cmd);
3796 qlcnic_dump_mbx(adapter, cmd);
3797 qlcnic_83xx_idc_request_reset(adapter,
3798 QLCNIC_FORCE_FW_DUMP_KEY);
3799 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3801 mbx_ops->dequeue_cmd(adapter, cmd);
3805 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3806 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3807 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3808 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3809 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3810 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3813 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3815 struct qlcnic_hardware_context *ahw = adapter->ahw;
3816 struct qlcnic_mailbox *mbx;
3818 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3823 mbx->ops = &qlcnic_83xx_mbx_ops;
3824 mbx->adapter = adapter;
3826 spin_lock_init(&mbx->queue_lock);
3827 spin_lock_init(&mbx->aen_lock);
3828 INIT_LIST_HEAD(&mbx->cmd_q);
3829 init_completion(&mbx->completion);
3831 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3832 if (mbx->work_q == NULL) {
3837 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3838 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3842 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3843 pci_channel_state_t state)
3845 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3847 if (state == pci_channel_io_perm_failure)
3848 return PCI_ERS_RESULT_DISCONNECT;
3850 if (state == pci_channel_io_normal)
3851 return PCI_ERS_RESULT_RECOVERED;
3853 set_bit(__QLCNIC_AER, &adapter->state);
3854 set_bit(__QLCNIC_RESETTING, &adapter->state);
3856 qlcnic_83xx_aer_stop_poll_work(adapter);
3858 pci_save_state(pdev);
3859 pci_disable_device(pdev);
3861 return PCI_ERS_RESULT_NEED_RESET;
3864 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3866 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3869 pdev->error_state = pci_channel_io_normal;
3870 err = pci_enable_device(pdev);
3874 pci_set_power_state(pdev, PCI_D0);
3875 pci_set_master(pdev);
3876 pci_restore_state(pdev);
3878 err = qlcnic_83xx_aer_reset(adapter);
3880 return PCI_ERS_RESULT_RECOVERED;
3882 clear_bit(__QLCNIC_AER, &adapter->state);
3883 clear_bit(__QLCNIC_RESETTING, &adapter->state);
3884 return PCI_ERS_RESULT_DISCONNECT;
3887 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3889 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3891 pci_cleanup_aer_uncorrect_error_status(pdev);
3892 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3893 qlcnic_83xx_aer_start_poll_work(adapter);