drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/aer.h>
  15
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  19
  20 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  21         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  22         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  23         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  24         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  25         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  26         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  27         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  28         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  29         {QLCNIC_CMD_SET_MTU, 3, 1},
  30         {QLCNIC_CMD_READ_PHY, 4, 2},
  31         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  32         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  33         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  34         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  35         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  36         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  37         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  38         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  39         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  40         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  41         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  42         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  43         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  44         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  45         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  46         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  47         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  48         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  49         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  50         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  51         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  52         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  53         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  54         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  55         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  57         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  58         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  59         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  60         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  61         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  62         {QLCNIC_CMD_IDC_ACK, 5, 1},
  63         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  65         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  66         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  67         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  68         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  69         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  70         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  71         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  72         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
  73 };
  74
  75 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  76         0x38CC,         /* Global Reset */
  77         0x38F0,         /* Wildcard */
  78         0x38FC,         /* Informant */
  79         0x3038,         /* Host MBX ctrl */
  80         0x303C,         /* FW MBX ctrl */
  81         0x355C,         /* BOOT LOADER ADDRESS REG */
  82         0x3560,         /* BOOT LOADER SIZE REG */
  83         0x3564,         /* FW IMAGE ADDR REG */
  84         0x1000,         /* MBX intr enable */
  85         0x1200,         /* Default Intr mask */
  86         0x1204,         /* Default Interrupt ID */
  87         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  88         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  89         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  90         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  91         0x3790,         /* QLC_83XX_IDC_CTRL */
  92         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  93         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  94         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  95         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  96         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  97         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  98         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  99         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 100         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 101         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 102         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 103         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 104         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 105         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 106         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 107         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 108         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 109         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 110         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 111         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 112         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 113         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 114         0x37F4,         /* QLC_83XX_VNIC_STATE */
 115         0x3868,         /* QLC_83XX_DRV_LOCK */
 116         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 117         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 118         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 119 };
 120
 121 const u32 qlcnic_83xx_reg_tbl[] = {
 122         0x34A8,         /* PEG_HALT_STAT1 */
 123         0x34AC,         /* PEG_HALT_STAT2 */
 124         0x34B0,         /* FW_HEARTBEAT */
 125         0x3500,         /* FLASH LOCK_ID */
 126         0x3528,         /* FW_CAPABILITIES */
 127         0x3538,         /* Driver active, DRV_REG0 */
 128         0x3540,         /* Device state, DRV_REG1 */
 129         0x3544,         /* Driver state, DRV_REG2 */
 130         0x3548,         /* Driver scratch, DRV_REG3 */
 131         0x354C,         /* Device partiton info, DRV_REG4 */
 132         0x3524,         /* Driver IDC ver, DRV_REG5 */
 133         0x3550,         /* FW_VER_MAJOR */
 134         0x3554,         /* FW_VER_MINOR */
 135         0x3558,         /* FW_VER_SUB */
 136         0x359C,         /* NPAR STATE */
 137         0x35FC,         /* FW_IMG_VALID */
 138         0x3650,         /* CMD_PEG_STATE */
 139         0x373C,         /* RCV_PEG_STATE */
 140         0x37B4,         /* ASIC TEMP */
 141         0x356C,         /* FW API */
 142         0x3570,         /* DRV OP MODE */
 143         0x3850,         /* FLASH LOCK */
 144         0x3854,         /* FLASH UNLOCK */
 145 };
 146
 147 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 148         .read_crb                       = qlcnic_83xx_read_crb,
 149         .write_crb                      = qlcnic_83xx_write_crb,
 150         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 151         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 152         .get_mac_address                = qlcnic_83xx_get_mac_address,
 153         .setup_intr                     = qlcnic_83xx_setup_intr,
 154         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 155         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 156         .get_func_no                    = qlcnic_83xx_get_func_no,
 157         .api_lock                       = qlcnic_83xx_cam_lock,
 158         .api_unlock                     = qlcnic_83xx_cam_unlock,
 159         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 160         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 161         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 162         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 163         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 164         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 165         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 166         .setup_link_event               = qlcnic_83xx_setup_link_event,
 167         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 168         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 169         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 170         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 171         .napi_enable                    = qlcnic_83xx_napi_enable,
 172         .napi_disable                   = qlcnic_83xx_napi_disable,
 173         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 174         .config_rss                     = qlcnic_83xx_config_rss,
 175         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 176         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 177         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 178         .get_board_info                 = qlcnic_83xx_get_port_info,
 179         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 180         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 181         .io_error_detected              = qlcnic_83xx_io_error_detected,
 182         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 183         .io_resume                      = qlcnic_83xx_io_resume,
 184         .get_beacon_state               = qlcnic_83xx_get_beacon_state,
 185 };
 186
 187 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 188         .config_bridged_mode    = qlcnic_config_bridged_mode,
 189         .config_led             = qlcnic_config_led,
 190         .request_reset          = qlcnic_83xx_idc_request_reset,
 191         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 192         .napi_add               = qlcnic_83xx_napi_add,
 193         .napi_del               = qlcnic_83xx_napi_del,
 194         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 195         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 196         .shutdown               = qlcnic_83xx_shutdown,
 197         .resume                 = qlcnic_83xx_resume,
 198 };
 199
 200 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 201 {
 202         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 203         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 204         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 205 }
 206
 207 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 208 {
 209         u32 fw_major, fw_minor, fw_build;
 210         struct pci_dev *pdev = adapter->pdev;
 211
 212         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 213         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 214         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 215         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 216
 217         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 218                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 219
 220         return adapter->fw_version;
 221 }
 222
 223 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 224 {
 225         void __iomem *base;
 226         u32 val;
 227
 228         base = adapter->ahw->pci_base0 +
 229                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 230         writel(addr, base);
 231         val = readl(base);
 232         if (val != addr)
 233                 return -EIO;
 234
 235         return 0;
 236 }
 237
 238 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 239                                 int *err)
 240 {
 241         struct qlcnic_hardware_context *ahw = adapter->ahw;
 242
 243         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 244         if (!*err) {
 245                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 246         } else {
 247                 dev_err(&adapter->pdev->dev,
 248                         "%s failed, addr = 0x%lx\n", __func__, addr);
 249                 return -EIO;
 250         }
 251 }
 252
 253 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 254                                  u32 data)
 255 {
 256         int err;
 257         struct qlcnic_hardware_context *ahw = adapter->ahw;
 258
 259         err = __qlcnic_set_win_base(adapter, (u32) addr);
 260         if (!err) {
 261                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 262                 return 0;
 263         } else {
 264                 dev_err(&adapter->pdev->dev,
 265                         "%s failed, addr = 0x%x data = 0x%x\n",
 266                         __func__, (int)addr, data);
 267                 return err;
 268         }
 269 }
 270
 271 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 272 {
 273         int err, i, num_msix;
 274         struct qlcnic_hardware_context *ahw = adapter->ahw;
 275
 276         num_msix = adapter->drv_sds_rings;
 277
 278         /* account for AEN interrupt MSI-X based interrupts */
 279         num_msix += 1;
 280
 281         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 282                 num_msix += adapter->drv_tx_rings;
 283
 284         err = qlcnic_enable_msix(adapter, num_msix);
 285         if (err == -ENOMEM)
 286                 return err;
 287         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 288                 num_msix = adapter->ahw->num_msix;
 289         else {
 290                 if (qlcnic_sriov_vf_check(adapter))
 291                         return -EINVAL;
 292                 num_msix = 1;
 293                 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 294         }
 295         /* setup interrupt mapping table for fw */
 296         ahw->intr_tbl = vzalloc(num_msix *
 297                                 sizeof(struct qlcnic_intrpt_config));
 298         if (!ahw->intr_tbl)
 299                 return -ENOMEM;
 300         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 301                 /* MSI-X enablement failed, use legacy interrupt */
 302                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 303                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 304                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 305                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 306                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 307         }
 308
 309         for (i = 0; i < num_msix; i++) {
 310                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 311                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 312                 else
 313                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 314                 ahw->intr_tbl[i].id = i;
 315                 ahw->intr_tbl[i].src = 0;
 316         }
 317         return 0;
 318 }
 319
 320 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 321 {
 322         writel(0, adapter->tgt_mask_reg);
 323 }
 324
 325 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 326 {
 327         if (adapter->tgt_mask_reg)
 328                 writel(1, adapter->tgt_mask_reg);
 329 }
 330
 331 /* Enable MSI-x and INT-x interrupts */
 332 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 333                              struct qlcnic_host_sds_ring *sds_ring)
 334 {
 335         writel(0, sds_ring->crb_intr_mask);
 336 }
 337
 338 /* Disable MSI-x and INT-x interrupts */
 339 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 340                               struct qlcnic_host_sds_ring *sds_ring)
 341 {
 342         writel(1, sds_ring->crb_intr_mask);
 343 }
 344
 345 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 346                                                     *adapter)
 347 {
 348         u32 mask;
 349
 350         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 351          * source register. We could be here before contexts are created
 352          * and sds_ring->crb_intr_mask has not been initialized, calculate
 353          * BAR offset for Interrupt Source Register
 354          */
 355         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 356         writel(0, adapter->ahw->pci_base0 + mask);
 357 }
 358
 359 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 360 {
 361         u32 mask;
 362
 363         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 364         writel(1, adapter->ahw->pci_base0 + mask);
 365         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 366 }
 367
 368 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 369                                      struct qlcnic_cmd_args *cmd)
 370 {
 371         int i;
 372
 373         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 374                 return;
 375
 376         for (i = 0; i < cmd->rsp.num; i++)
 377                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 378 }
 379
 380 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 381 {
 382         u32 intr_val;
 383         struct qlcnic_hardware_context *ahw = adapter->ahw;
 384         int retries = 0;
 385
 386         intr_val = readl(adapter->tgt_status_reg);
 387
 388         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 389                 return IRQ_NONE;
 390
 391         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 392                 adapter->stats.spurious_intr++;
 393                 return IRQ_NONE;
 394         }
 395         /* The barrier is required to ensure writes to the registers */
 396         wmb();
 397
 398         /* clear the interrupt trigger control register */
 399         writel(0, adapter->isr_int_vec);
 400         intr_val = readl(adapter->isr_int_vec);
 401         do {
 402                 intr_val = readl(adapter->tgt_status_reg);
 403                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 404                         break;
 405                 retries++;
 406         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 407                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 408
 409         return IRQ_HANDLED;
 410 }
 411
 412 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 413 {
 414         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 415         complete(&mbx->completion);
 416 }
 417
 418 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 419 {
 420         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 421         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 422         unsigned long flags;
 423
 424         spin_lock_irqsave(&mbx->aen_lock, flags);
 425         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 426         if (!(resp & QLCNIC_SET_OWNER))
 427                 goto out;
 428
 429         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 430         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 431                 __qlcnic_83xx_process_aen(adapter);
 432         } else {
 433                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 434                         qlcnic_83xx_notify_mbx_response(mbx);
 435         }
 436 out:
 437         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 438         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 439 }
 440
 441 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 442 {
 443         struct qlcnic_adapter *adapter = data;
 444         struct qlcnic_host_sds_ring *sds_ring;
 445         struct qlcnic_hardware_context *ahw = adapter->ahw;
 446
 447         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 448                 return IRQ_NONE;
 449
 450         qlcnic_83xx_poll_process_aen(adapter);
 451
 452         if (ahw->diag_test) {
 453                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 454                         ahw->diag_cnt++;
 455                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 456                 return IRQ_HANDLED;
 457         }
 458
 459         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 460                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 461         } else {
 462                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 463                 napi_schedule(&sds_ring->napi);
 464         }
 465
 466         return IRQ_HANDLED;
 467 }
 468
 469 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 470 {
 471         struct qlcnic_host_sds_ring *sds_ring = data;
 472         struct qlcnic_adapter *adapter = sds_ring->adapter;
 473
 474         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 475                 goto done;
 476
 477         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 478                 return IRQ_NONE;
 479
 480 done:
 481         adapter->ahw->diag_cnt++;
 482         qlcnic_83xx_enable_intr(adapter, sds_ring);
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 488 {
 489         u32 num_msix;
 490
 491         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 492                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 493
 494         qlcnic_83xx_disable_mbx_intr(adapter);
 495
 496         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 497                 num_msix = adapter->ahw->num_msix - 1;
 498         else
 499                 num_msix = 0;
 500
 501         msleep(20);
 502
 503         if (adapter->msix_entries) {
 504                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 505                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 506         }
 507 }
 508
 509 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 510 {
 511         irq_handler_t handler;
 512         u32 val;
 513         int err = 0;
 514         unsigned long flags = 0;
 515
 516         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 517             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 518                 flags |= IRQF_SHARED;
 519
 520         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 521                 handler = qlcnic_83xx_handle_aen;
 522                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 523                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 524                 if (err) {
 525                         dev_err(&adapter->pdev->dev,
 526                                 "failed to register MBX interrupt\n");
 527                         return err;
 528                 }
 529         } else {
 530                 handler = qlcnic_83xx_intr;
 531                 val = adapter->msix_entries[0].vector;
 532                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 533                 if (err) {
 534                         dev_err(&adapter->pdev->dev,
 535                                 "failed to register INTx interrupt\n");
 536                         return err;
 537                 }
 538                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 539         }
 540
 541         /* Enable mailbox interrupt */
 542         qlcnic_83xx_enable_mbx_interrupt(adapter);
 543
 544         return err;
 545 }
 546
 547 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 548 {
 549         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 550         adapter->ahw->pci_func = (val >> 24) & 0xff;
 551 }
 552
 553 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 554 {
 555         void __iomem *addr;
 556         u32 val, limit = 0;
 557
 558         struct qlcnic_hardware_context *ahw = adapter->ahw;
 559
 560         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 561         do {
 562                 val = readl(addr);
 563                 if (val) {
 564                         /* write the function number to register */
 565                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 566                                             ahw->pci_func);
 567                         return 0;
 568                 }
 569                 usleep_range(1000, 2000);
 570         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 571
 572         return -EIO;
 573 }
 574
 575 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 576 {
 577         void __iomem *addr;
 578         u32 val;
 579         struct qlcnic_hardware_context *ahw = adapter->ahw;
 580
 581         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 582         val = readl(addr);
 583 }
 584
 585 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 586                           loff_t offset, size_t size)
 587 {
 588         int ret = 0;
 589         u32 data;
 590
 591         if (qlcnic_api_lock(adapter)) {
 592                 dev_err(&adapter->pdev->dev,
 593                         "%s: failed to acquire lock. addr offset 0x%x\n",
 594                         __func__, (u32)offset);
 595                 return;
 596         }
 597
 598         data = QLCRD32(adapter, (u32) offset, &ret);
 599         qlcnic_api_unlock(adapter);
 600
 601         if (ret == -EIO) {
 602                 dev_err(&adapter->pdev->dev,
 603                         "%s: failed. addr offset 0x%x\n",
 604                         __func__, (u32)offset);
 605                 return;
 606         }
 607         memcpy(buf, &data, size);
 608 }
 609
 610 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 611                            loff_t offset, size_t size)
 612 {
 613         u32 data;
 614
 615         memcpy(&data, buf, size);
 616         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 617 }
 618
 619 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 620 {
 621         int status;
 622
 623         status = qlcnic_83xx_get_port_config(adapter);
 624         if (status) {
 625                 dev_err(&adapter->pdev->dev,
 626                         "Get Port Info failed\n");
 627         } else {
 628                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 629                         adapter->ahw->port_type = QLCNIC_XGBE;
 630                 else
 631                         adapter->ahw->port_type = QLCNIC_GBE;
 632
 633                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 634                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 635         }
 636         return status;
 637 }
 638
 639 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 640 {
 641         struct qlcnic_hardware_context *ahw = adapter->ahw;
 642         u16 act_pci_fn = ahw->total_nic_func;
 643         u16 count;
 644
 645         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 646         if (act_pci_fn <= 2)
 647                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 648                          act_pci_fn;
 649         else
 650                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 651                          act_pci_fn;
 652         ahw->max_uc_count = count;
 653 }
 654
 655 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 656 {
 657         u32 val;
 658
 659         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 660                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 661         else
 662                 val = BIT_2;
 663
 664         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 665         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 666 }
 667
 668 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 669                           const struct pci_device_id *ent)
 670 {
 671         u32 op_mode, priv_level;
 672         struct qlcnic_hardware_context *ahw = adapter->ahw;
 673
 674         ahw->fw_hal_version = 2;
 675         qlcnic_get_func_no(adapter);
 676
 677         if (qlcnic_sriov_vf_check(adapter)) {
 678                 qlcnic_sriov_vf_set_ops(adapter);
 679                 return;
 680         }
 681
 682         /* Determine function privilege level */
 683         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 684         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 685                 priv_level = QLCNIC_MGMT_FUNC;
 686         else
 687                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 688                                                          ahw->pci_func);
 689
 690         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 691                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 692                 dev_info(&adapter->pdev->dev,
 693                          "HAL Version: %d Non Privileged function\n",
 694                          ahw->fw_hal_version);
 695                 adapter->nic_ops = &qlcnic_vf_ops;
 696         } else {
 697                 if (pci_find_ext_capability(adapter->pdev,
 698                                             PCI_EXT_CAP_ID_SRIOV))
 699                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 700                 adapter->nic_ops = &qlcnic_83xx_ops;
 701         }
 702 }
 703
 704 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 705                                         u32 data[]);
 706 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 707                                             u32 data[]);
 708
 709 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 710                      struct qlcnic_cmd_args *cmd)
 711 {
 712         int i;
 713
 714         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 715                 return;
 716
 717         dev_info(&adapter->pdev->dev,
 718                  "Host MBX regs(%d)\n", cmd->req.num);
 719         for (i = 0; i < cmd->req.num; i++) {
 720                 if (i && !(i % 8))
 721                         pr_info("\n");
 722                 pr_info("%08x ", cmd->req.arg[i]);
 723         }
 724         pr_info("\n");
 725         dev_info(&adapter->pdev->dev,
 726                  "FW MBX regs(%d)\n", cmd->rsp.num);
 727         for (i = 0; i < cmd->rsp.num; i++) {
 728                 if (i && !(i % 8))
 729                         pr_info("\n");
 730                 pr_info("%08x ", cmd->rsp.arg[i]);
 731         }
 732         pr_info("\n");
 733 }
 734
 735 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 736                                                 struct qlcnic_cmd_args *cmd)
 737 {
 738         struct qlcnic_hardware_context *ahw = adapter->ahw;
 739         int opcode = LSW(cmd->req.arg[0]);
 740         unsigned long max_loops;
 741
 742         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 743
 744         for (; max_loops; max_loops--) {
 745                 if (atomic_read(&cmd->rsp_status) ==
 746                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 747                         return;
 748
 749                 udelay(1);
 750         }
 751
 752         dev_err(&adapter->pdev->dev,
 753                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 754                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 755         flush_workqueue(ahw->mailbox->work_q);
 756         return;
 757 }
 758
 759 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 760                           struct qlcnic_cmd_args *cmd)
 761 {
 762         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 763         struct qlcnic_hardware_context *ahw = adapter->ahw;
 764         int cmd_type, err, opcode;
 765         unsigned long timeout;
 766
 767         if (!mbx)
 768                 return -EIO;
 769
 770         opcode = LSW(cmd->req.arg[0]);
 771         cmd_type = cmd->type;
 772         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 773         if (err) {
 774                 dev_err(&adapter->pdev->dev,
 775                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 776                         __func__, opcode, cmd->type, ahw->pci_func,
 777                         ahw->op_mode);
 778                 return err;
 779         }
 780
 781         switch (cmd_type) {
 782         case QLC_83XX_MBX_CMD_WAIT:
 783                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 784                         dev_err(&adapter->pdev->dev,
 785                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 786                                 __func__, opcode, cmd_type, ahw->pci_func,
 787                                 ahw->op_mode);
 788                         flush_workqueue(mbx->work_q);
 789                 }
 790                 break;
 791         case QLC_83XX_MBX_CMD_NO_WAIT:
 792                 return 0;
 793         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 794                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 795                 break;
 796         default:
 797                 dev_err(&adapter->pdev->dev,
 798                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 799                         __func__, opcode, cmd_type, ahw->pci_func,
 800                         ahw->op_mode);
 801                 qlcnic_83xx_detach_mailbox_work(adapter);
 802         }
 803
 804         return cmd->rsp_opcode;
 805 }
 806
 807 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 808                                struct qlcnic_adapter *adapter, u32 type)
 809 {
 810         int i, size;
 811         u32 temp;
 812         const struct qlcnic_mailbox_metadata *mbx_tbl;
 813
 814         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 815         mbx_tbl = qlcnic_83xx_mbx_tbl;
 816         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 817         for (i = 0; i < size; i++) {
 818                 if (type == mbx_tbl[i].cmd) {
 819                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 820                         mbx->req.num = mbx_tbl[i].in_args;
 821                         mbx->rsp.num = mbx_tbl[i].out_args;
 822                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 823                                                GFP_ATOMIC);
 824                         if (!mbx->req.arg)
 825                                 return -ENOMEM;
 826                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 827                                                GFP_ATOMIC);
 828                         if (!mbx->rsp.arg) {
 829                                 kfree(mbx->req.arg);
 830                                 mbx->req.arg = NULL;
 831                                 return -ENOMEM;
 832                         }
 833                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 834                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 835                         temp = adapter->ahw->fw_hal_version << 29;
 836                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 837                         mbx->cmd_op = type;
 838                         return 0;
 839                 }
 840         }
 841         return -EINVAL;
 842 }
 843
 844 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 845 {
 846         struct qlcnic_adapter *adapter;
 847         struct qlcnic_cmd_args cmd;
 848         int i, err = 0;
 849
 850         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 851         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 852         if (err)
 853                 return;
 854
 855         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 856                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 857
 858         err = qlcnic_issue_cmd(adapter, &cmd);
 859         if (err)
 860                 dev_info(&adapter->pdev->dev,
 861                          "%s: Mailbox IDC ACK failed.\n", __func__);
 862         qlcnic_free_mbx_args(&cmd);
 863 }
 864
 865 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 866                                             u32 data[])
 867 {
 868         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 869                 QLCNIC_MBX_RSP(data[0]));
 870         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 871         return;
 872 }
 873
 874 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 875 {
 876         struct qlcnic_hardware_context *ahw = adapter->ahw;
 877         u32 event[QLC_83XX_MBX_AEN_CNT];
 878         int i;
 879
 880         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 881                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 882
 883         switch (QLCNIC_MBX_RSP(event[0])) {
 884
 885         case QLCNIC_MBX_LINK_EVENT:
 886                 qlcnic_83xx_handle_link_aen(adapter, event);
 887                 break;
 888         case QLCNIC_MBX_COMP_EVENT:
 889                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 890                 break;
 891         case QLCNIC_MBX_REQUEST_EVENT:
 892                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 893                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 894                 queue_delayed_work(adapter->qlcnic_wq,
 895                                    &adapter->idc_aen_work, 0);
 896                 break;
 897         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 898                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 899                 break;
 900         case QLCNIC_MBX_BC_EVENT:
 901                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 902                 break;
 903         case QLCNIC_MBX_SFP_INSERT_EVENT:
 904                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 905                          QLCNIC_MBX_RSP(event[0]));
 906                 break;
 907         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 908                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 909                          QLCNIC_MBX_RSP(event[0]));
 910                 break;
 911         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
 912                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
 913                 break;
 914         default:
 915                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 916                         QLCNIC_MBX_RSP(event[0]));
 917                 break;
 918         }
 919
 920         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 921 }
 922
 923 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 924 {
 925         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 926         struct qlcnic_hardware_context *ahw = adapter->ahw;
 927         struct qlcnic_mailbox *mbx = ahw->mailbox;
 928         unsigned long flags;
 929
 930         spin_lock_irqsave(&mbx->aen_lock, flags);
 931         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 932         if (resp & QLCNIC_SET_OWNER) {
 933                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 934                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 935                         __qlcnic_83xx_process_aen(adapter);
 936                 } else {
 937                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 938                                 qlcnic_83xx_notify_mbx_response(mbx);
 939                 }
 940         }
 941         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 942 }
 943
 944 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 945 {
 946         struct qlcnic_adapter *adapter;
 947
 948         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 949
 950         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 951                 return;
 952
 953         qlcnic_83xx_process_aen(adapter);
 954         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 955                            (HZ / 10));
 956 }
 957
 958 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 959 {
 960         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 961                 return;
 962
 963         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 964         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 965 }
 966
 967 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 968 {
 969         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 970                 return;
 971         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 972 }
 973
 974 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 975 {
 976         int index, i, err, sds_mbx_size;
 977         u32 *buf, intrpt_id, intr_mask;
 978         u16 context_id;
 979         u8 num_sds;
 980         struct qlcnic_cmd_args cmd;
 981         struct qlcnic_host_sds_ring *sds;
 982         struct qlcnic_sds_mbx sds_mbx;
 983         struct qlcnic_add_rings_mbx_out *mbx_out;
 984         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 985         struct qlcnic_hardware_context *ahw = adapter->ahw;
 986
 987         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 988         context_id = recv_ctx->context_id;
 989         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
 990         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 991                                     QLCNIC_CMD_ADD_RCV_RINGS);
 992         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 993
 994         /* set up status rings, mbx 2-81 */
 995         index = 2;
 996         for (i = 8; i < adapter->drv_sds_rings; i++) {
 997                 memset(&sds_mbx, 0, sds_mbx_size);
 998                 sds = &recv_ctx->sds_rings[i];
 999                 sds->consumer = 0;
1000                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1001                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1002                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1003                 sds_mbx.sds_ring_size = sds->num_desc;
1004
1005                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1006                         intrpt_id = ahw->intr_tbl[i].id;
1007                 else
1008                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1009
1010                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1011                         sds_mbx.intrpt_id = intrpt_id;
1012                 else
1013                         sds_mbx.intrpt_id = 0xffff;
1014                 sds_mbx.intrpt_val = 0;
1015                 buf = &cmd.req.arg[index];
1016                 memcpy(buf, &sds_mbx, sds_mbx_size);
1017                 index += sds_mbx_size / sizeof(u32);
1018         }
1019
1020         /* send the mailbox command */
1021         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1022         if (err) {
1023                 dev_err(&adapter->pdev->dev,
1024                         "Failed to add rings %d\n", err);
1025                 goto out;
1026         }
1027
1028         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1029         index = 0;
1030         /* status descriptor ring */
1031         for (i = 8; i < adapter->drv_sds_rings; i++) {
1032                 sds = &recv_ctx->sds_rings[i];
1033                 sds->crb_sts_consumer = ahw->pci_base0 +
1034                                         mbx_out->host_csmr[index];
1035                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1036                         intr_mask = ahw->intr_tbl[i].src;
1037                 else
1038                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1039
1040                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1041                 index++;
1042         }
1043 out:
1044         qlcnic_free_mbx_args(&cmd);
1045         return err;
1046 }
1047
1048 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1049 {
1050         int err;
1051         u32 temp = 0;
1052         struct qlcnic_cmd_args cmd;
1053         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1054
1055         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1056                 return;
1057
1058         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1059                 cmd.req.arg[0] |= (0x3 << 29);
1060
1061         if (qlcnic_sriov_pf_check(adapter))
1062                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1063
1064         cmd.req.arg[1] = recv_ctx->context_id | temp;
1065         err = qlcnic_issue_cmd(adapter, &cmd);
1066         if (err)
1067                 dev_err(&adapter->pdev->dev,
1068                         "Failed to destroy rx ctx in firmware\n");
1069
1070         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1071         qlcnic_free_mbx_args(&cmd);
1072 }
1073
1074 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1075 {
1076         int i, err, index, sds_mbx_size, rds_mbx_size;
1077         u8 num_sds, num_rds;
1078         u32 *buf, intrpt_id, intr_mask, cap = 0;
1079         struct qlcnic_host_sds_ring *sds;
1080         struct qlcnic_host_rds_ring *rds;
1081         struct qlcnic_sds_mbx sds_mbx;
1082         struct qlcnic_rds_mbx rds_mbx;
1083         struct qlcnic_cmd_args cmd;
1084         struct qlcnic_rcv_mbx_out *mbx_out;
1085         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1086         struct qlcnic_hardware_context *ahw = adapter->ahw;
1087         num_rds = adapter->max_rds_rings;
1088
1089         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1090                 num_sds = adapter->drv_sds_rings;
1091         else
1092                 num_sds = QLCNIC_MAX_SDS_RINGS;
1093
1094         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1095         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1096         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1097
1098         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1099                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1100
1101         /* set mailbox hdr and capabilities */
1102         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1103                                     QLCNIC_CMD_CREATE_RX_CTX);
1104         if (err)
1105                 return err;
1106
1107         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1108                 cmd.req.arg[0] |= (0x3 << 29);
1109
1110         cmd.req.arg[1] = cap;
1111         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1112                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1113
1114         if (qlcnic_sriov_pf_check(adapter))
1115                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1116                                                          &cmd.req.arg[6]);
1117         /* set up status rings, mbx 8-57/87 */
1118         index = QLC_83XX_HOST_SDS_MBX_IDX;
1119         for (i = 0; i < num_sds; i++) {
1120                 memset(&sds_mbx, 0, sds_mbx_size);
1121                 sds = &recv_ctx->sds_rings[i];
1122                 sds->consumer = 0;
1123                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1124                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1125                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1126                 sds_mbx.sds_ring_size = sds->num_desc;
1127                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1128                         intrpt_id = ahw->intr_tbl[i].id;
1129                 else
1130                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1131                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1132                         sds_mbx.intrpt_id = intrpt_id;
1133                 else
1134                         sds_mbx.intrpt_id = 0xffff;
1135                 sds_mbx.intrpt_val = 0;
1136                 buf = &cmd.req.arg[index];
1137                 memcpy(buf, &sds_mbx, sds_mbx_size);
1138                 index += sds_mbx_size / sizeof(u32);
1139         }
1140         /* set up receive rings, mbx 88-111/135 */
1141         index = QLCNIC_HOST_RDS_MBX_IDX;
1142         rds = &recv_ctx->rds_rings[0];
1143         rds->producer = 0;
1144         memset(&rds_mbx, 0, rds_mbx_size);
1145         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1146         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1147         rds_mbx.reg_ring_sz = rds->dma_size;
1148         rds_mbx.reg_ring_len = rds->num_desc;
1149         /* Jumbo ring */
1150         rds = &recv_ctx->rds_rings[1];
1151         rds->producer = 0;
1152         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1153         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1154         rds_mbx.jmb_ring_sz = rds->dma_size;
1155         rds_mbx.jmb_ring_len = rds->num_desc;
1156         buf = &cmd.req.arg[index];
1157         memcpy(buf, &rds_mbx, rds_mbx_size);
1158
1159         /* send the mailbox command */
1160         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1161         if (err) {
1162                 dev_err(&adapter->pdev->dev,
1163                         "Failed to create Rx ctx in firmware%d\n", err);
1164                 goto out;
1165         }
1166         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1167         recv_ctx->context_id = mbx_out->ctx_id;
1168         recv_ctx->state = mbx_out->state;
1169         recv_ctx->virt_port = mbx_out->vport_id;
1170         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1171                  recv_ctx->context_id, recv_ctx->state);
1172         /* Receive descriptor ring */
1173         /* Standard ring */
1174         rds = &recv_ctx->rds_rings[0];
1175         rds->crb_rcv_producer = ahw->pci_base0 +
1176                                 mbx_out->host_prod[0].reg_buf;
1177         /* Jumbo ring */
1178         rds = &recv_ctx->rds_rings[1];
1179         rds->crb_rcv_producer = ahw->pci_base0 +
1180                                 mbx_out->host_prod[0].jmb_buf;
1181         /* status descriptor ring */
1182         for (i = 0; i < num_sds; i++) {
1183                 sds = &recv_ctx->sds_rings[i];
1184                 sds->crb_sts_consumer = ahw->pci_base0 +
1185                                         mbx_out->host_csmr[i];
1186                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1187                         intr_mask = ahw->intr_tbl[i].src;
1188                 else
1189                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1190                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1191         }
1192
1193         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1194                 err = qlcnic_83xx_add_rings(adapter);
1195 out:
1196         qlcnic_free_mbx_args(&cmd);
1197         return err;
1198 }
1199
1200 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1201                             struct qlcnic_host_tx_ring *tx_ring)
1202 {
1203         struct qlcnic_cmd_args cmd;
1204         u32 temp = 0;
1205
1206         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1207                 return;
1208
1209         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1210                 cmd.req.arg[0] |= (0x3 << 29);
1211
1212         if (qlcnic_sriov_pf_check(adapter))
1213                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1214
1215         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1216         if (qlcnic_issue_cmd(adapter, &cmd))
1217                 dev_err(&adapter->pdev->dev,
1218                         "Failed to destroy tx ctx in firmware\n");
1219         qlcnic_free_mbx_args(&cmd);
1220 }
1221
1222 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1223                               struct qlcnic_host_tx_ring *tx, int ring)
1224 {
1225         int err;
1226         u16 msix_id;
1227         u32 *buf, intr_mask, temp = 0;
1228         struct qlcnic_cmd_args cmd;
1229         struct qlcnic_tx_mbx mbx;
1230         struct qlcnic_tx_mbx_out *mbx_out;
1231         struct qlcnic_hardware_context *ahw = adapter->ahw;
1232         u32 msix_vector;
1233
1234         /* Reset host resources */
1235         tx->producer = 0;
1236         tx->sw_consumer = 0;
1237         *(tx->hw_consumer) = 0;
1238
1239         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1240
1241         /* setup mailbox inbox registerss */
1242         mbx.phys_addr_low = LSD(tx->phys_addr);
1243         mbx.phys_addr_high = MSD(tx->phys_addr);
1244         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1245         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1246         mbx.size = tx->num_desc;
1247         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1248                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1249                         msix_vector = adapter->drv_sds_rings + ring;
1250                 else
1251                         msix_vector = adapter->drv_sds_rings - 1;
1252                 msix_id = ahw->intr_tbl[msix_vector].id;
1253         } else {
1254                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1255         }
1256
1257         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1258                 mbx.intr_id = msix_id;
1259         else
1260                 mbx.intr_id = 0xffff;
1261         mbx.src = 0;
1262
1263         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1264         if (err)
1265                 return err;
1266
1267         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1268                 cmd.req.arg[0] |= (0x3 << 29);
1269
1270         if (qlcnic_sriov_pf_check(adapter))
1271                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1272
1273         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1274         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1275
1276         buf = &cmd.req.arg[6];
1277         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1278         /* send the mailbox command*/
1279         err = qlcnic_issue_cmd(adapter, &cmd);
1280         if (err) {
1281                 dev_err(&adapter->pdev->dev,
1282                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1283                 goto out;
1284         }
1285         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1286         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1287         tx->ctx_id = mbx_out->ctx_id;
1288         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1289             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1290                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1291                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1292         }
1293         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1294                  tx->ctx_id, mbx_out->state);
1295 out:
1296         qlcnic_free_mbx_args(&cmd);
1297         return err;
1298 }
1299
1300 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1301                                       u8 num_sds_ring)
1302 {
1303         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1304         struct qlcnic_host_sds_ring *sds_ring;
1305         struct qlcnic_host_rds_ring *rds_ring;
1306         u16 adapter_state = adapter->is_up;
1307         u8 ring;
1308         int ret;
1309
1310         netif_device_detach(netdev);
1311
1312         if (netif_running(netdev))
1313                 __qlcnic_down(adapter, netdev);
1314
1315         qlcnic_detach(adapter);
1316
1317         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1318         adapter->ahw->diag_test = test;
1319         adapter->ahw->linkup = 0;
1320
1321         ret = qlcnic_attach(adapter);
1322         if (ret) {
1323                 netif_device_attach(netdev);
1324                 return ret;
1325         }
1326
1327         ret = qlcnic_fw_create_ctx(adapter);
1328         if (ret) {
1329                 qlcnic_detach(adapter);
1330                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1331                         adapter->drv_sds_rings = num_sds_ring;
1332                         qlcnic_attach(adapter);
1333                 }
1334                 netif_device_attach(netdev);
1335                 return ret;
1336         }
1337
1338         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1339                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1340                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1341         }
1342
1343         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1344                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1345                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1346                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1347                 }
1348         }
1349
1350         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1351                 adapter->ahw->loopback_state = 0;
1352                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1353         }
1354
1355         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1356         return 0;
1357 }
1358
1359 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1360                                       u8 drv_sds_rings)
1361 {
1362         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1363         struct qlcnic_host_sds_ring *sds_ring;
1364         int ring;
1365
1366         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1367         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1368                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1369                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1370                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1371                                 qlcnic_83xx_disable_intr(adapter, sds_ring);
1372                 }
1373         }
1374
1375         qlcnic_fw_destroy_ctx(adapter);
1376         qlcnic_detach(adapter);
1377
1378         adapter->ahw->diag_test = 0;
1379         adapter->drv_sds_rings = drv_sds_rings;
1380
1381         if (qlcnic_attach(adapter))
1382                 goto out;
1383
1384         if (netif_running(netdev))
1385                 __qlcnic_up(adapter, netdev);
1386
1387 out:
1388         netif_device_attach(netdev);
1389 }
1390
1391 void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1392 {
1393         struct qlcnic_hardware_context *ahw = adapter->ahw;
1394         struct qlcnic_cmd_args cmd;
1395         u8 beacon_state;
1396         int err = 0;
1397
1398         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1399         if (!err) {
1400                 err = qlcnic_issue_cmd(adapter, &cmd);
1401                 if (!err) {
1402                         beacon_state = cmd.rsp.arg[4];
1403                         if (beacon_state == QLCNIC_BEACON_DISABLE)
1404                                 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1405                         else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1406                                 ahw->beacon_state = QLC_83XX_BEACON_ON;
1407                 }
1408         } else {
1409                 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1410                            err);
1411         }
1412
1413         qlcnic_free_mbx_args(&cmd);
1414
1415         return;
1416 }
1417
1418 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1419                            u32 beacon)
1420 {
1421         struct qlcnic_cmd_args cmd;
1422         u32 mbx_in;
1423         int i, status = 0;
1424
1425         if (state) {
1426                 /* Get LED configuration */
1427                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1428                                                QLCNIC_CMD_GET_LED_CONFIG);
1429                 if (status)
1430                         return status;
1431
1432                 status = qlcnic_issue_cmd(adapter, &cmd);
1433                 if (status) {
1434                         dev_err(&adapter->pdev->dev,
1435                                 "Get led config failed.\n");
1436                         goto mbx_err;
1437                 } else {
1438                         for (i = 0; i < 4; i++)
1439                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1440                 }
1441                 qlcnic_free_mbx_args(&cmd);
1442                 /* Set LED Configuration */
1443                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1444                           LSW(QLC_83XX_LED_CONFIG);
1445                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1446                                                QLCNIC_CMD_SET_LED_CONFIG);
1447                 if (status)
1448                         return status;
1449
1450                 cmd.req.arg[1] = mbx_in;
1451                 cmd.req.arg[2] = mbx_in;
1452                 cmd.req.arg[3] = mbx_in;
1453                 if (beacon)
1454                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1455                 status = qlcnic_issue_cmd(adapter, &cmd);
1456                 if (status) {
1457                         dev_err(&adapter->pdev->dev,
1458                                 "Set led config failed.\n");
1459                 }
1460 mbx_err:
1461                 qlcnic_free_mbx_args(&cmd);
1462                 return status;
1463
1464         } else {
1465                 /* Restoring default LED configuration */
1466                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1467                                                QLCNIC_CMD_SET_LED_CONFIG);
1468                 if (status)
1469                         return status;
1470
1471                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1472                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1473                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1474                 if (beacon)
1475                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1476                 status = qlcnic_issue_cmd(adapter, &cmd);
1477                 if (status)
1478                         dev_err(&adapter->pdev->dev,
1479                                 "Restoring led config failed.\n");
1480                 qlcnic_free_mbx_args(&cmd);
1481                 return status;
1482         }
1483 }
1484
1485 int  qlcnic_83xx_set_led(struct net_device *netdev,
1486                          enum ethtool_phys_id_state state)
1487 {
1488         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1489         int err = -EIO, active = 1;
1490
1491         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1492                 netdev_warn(netdev,
1493                             "LED test is not supported in non-privileged mode\n");
1494                 return -EOPNOTSUPP;
1495         }
1496
1497         switch (state) {
1498         case ETHTOOL_ID_ACTIVE:
1499                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1500                         return -EBUSY;
1501
1502                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1503                         break;
1504
1505                 err = qlcnic_83xx_config_led(adapter, active, 0);
1506                 if (err)
1507                         netdev_err(netdev, "Failed to set LED blink state\n");
1508                 break;
1509         case ETHTOOL_ID_INACTIVE:
1510                 active = 0;
1511
1512                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1513                         break;
1514
1515                 err = qlcnic_83xx_config_led(adapter, active, 0);
1516                 if (err)
1517                         netdev_err(netdev, "Failed to reset LED blink state\n");
1518                 break;
1519
1520         default:
1521                 return -EINVAL;
1522         }
1523
1524         if (!active || err)
1525                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1526
1527         return err;
1528 }
1529
1530 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1531 {
1532         struct qlcnic_cmd_args cmd;
1533         int status;
1534
1535         if (qlcnic_sriov_vf_check(adapter))
1536                 return;
1537
1538         if (enable)
1539                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1540                                                QLCNIC_CMD_INIT_NIC_FUNC);
1541         else
1542                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1543                                                QLCNIC_CMD_STOP_NIC_FUNC);
1544
1545         if (status)
1546                 return;
1547
1548         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1549
1550         if (adapter->dcb)
1551                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1552
1553         status = qlcnic_issue_cmd(adapter, &cmd);
1554         if (status)
1555                 dev_err(&adapter->pdev->dev,
1556                         "Failed to %s in NIC IDC function event.\n",
1557                         (enable ? "register" : "unregister"));
1558
1559         qlcnic_free_mbx_args(&cmd);
1560 }
1561
1562 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1563 {
1564         struct qlcnic_cmd_args cmd;
1565         int err;
1566
1567         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1568         if (err)
1569                 return err;
1570
1571         cmd.req.arg[1] = adapter->ahw->port_config;
1572         err = qlcnic_issue_cmd(adapter, &cmd);
1573         if (err)
1574                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1575         qlcnic_free_mbx_args(&cmd);
1576         return err;
1577 }
1578
1579 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1580 {
1581         struct qlcnic_cmd_args cmd;
1582         int err;
1583
1584         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1585         if (err)
1586                 return err;
1587
1588         err = qlcnic_issue_cmd(adapter, &cmd);
1589         if (err)
1590                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1591         else
1592                 adapter->ahw->port_config = cmd.rsp.arg[1];
1593         qlcnic_free_mbx_args(&cmd);
1594         return err;
1595 }
1596
1597 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1598 {
1599         int err;
1600         u32 temp;
1601         struct qlcnic_cmd_args cmd;
1602
1603         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1604         if (err)
1605                 return err;
1606
1607         temp = adapter->recv_ctx->context_id << 16;
1608         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1609         err = qlcnic_issue_cmd(adapter, &cmd);
1610         if (err)
1611                 dev_info(&adapter->pdev->dev,
1612                          "Setup linkevent mailbox failed\n");
1613         qlcnic_free_mbx_args(&cmd);
1614         return err;
1615 }
1616
1617 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1618                                                  u32 *interface_id)
1619 {
1620         if (qlcnic_sriov_pf_check(adapter)) {
1621                 qlcnic_alloc_lb_filters_mem(adapter);
1622                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1623                 adapter->rx_mac_learn = 1;
1624         } else {
1625                 if (!qlcnic_sriov_vf_check(adapter))
1626                         *interface_id = adapter->recv_ctx->context_id << 16;
1627         }
1628 }
1629
1630 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1631 {
1632         struct qlcnic_cmd_args *cmd = NULL;
1633         u32 temp = 0;
1634         int err;
1635
1636         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1637                 return -EIO;
1638
1639         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1640         if (!cmd)
1641                 return -ENOMEM;
1642
1643         err = qlcnic_alloc_mbx_args(cmd, adapter,
1644                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1645         if (err)
1646                 goto out;
1647
1648         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1649         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1650
1651         if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1652                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1653
1654         cmd->req.arg[1] = mode | temp;
1655         err = qlcnic_issue_cmd(adapter, cmd);
1656         if (!err)
1657                 return err;
1658
1659         qlcnic_free_mbx_args(cmd);
1660
1661 out:
1662         kfree(cmd);
1663         return err;
1664 }
1665
1666 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1667 {
1668         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1669         struct qlcnic_hardware_context *ahw = adapter->ahw;
1670         u8 drv_sds_rings = adapter->drv_sds_rings;
1671         u8 drv_tx_rings = adapter->drv_tx_rings;
1672         int ret = 0, loop = 0;
1673
1674         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1675                 netdev_warn(netdev,
1676                             "Loopback test not supported in non privileged mode\n");
1677                 return -ENOTSUPP;
1678         }
1679
1680         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1681                 netdev_info(netdev, "Device is resetting\n");
1682                 return -EBUSY;
1683         }
1684
1685         if (qlcnic_get_diag_lock(adapter)) {
1686                 netdev_info(netdev, "Device is in diagnostics mode\n");
1687                 return -EBUSY;
1688         }
1689
1690         netdev_info(netdev, "%s loopback test in progress\n",
1691                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1692
1693         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1694                                          drv_sds_rings);
1695         if (ret)
1696                 goto fail_diag_alloc;
1697
1698         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1699         if (ret)
1700                 goto free_diag_res;
1701
1702         /* Poll for link up event before running traffic */
1703         do {
1704                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1705
1706                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1707                         netdev_info(netdev,
1708                                     "Device is resetting, free LB test resources\n");
1709                         ret = -EBUSY;
1710                         goto free_diag_res;
1711                 }
1712                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1713                         netdev_info(netdev,
1714                                     "Firmware didn't sent link up event to loopback request\n");
1715                         ret = -ETIMEDOUT;
1716                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1717                         goto free_diag_res;
1718                 }
1719         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1720
1721         ret = qlcnic_do_lb_test(adapter, mode);
1722
1723         qlcnic_83xx_clear_lb_mode(adapter, mode);
1724
1725 free_diag_res:
1726         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1727
1728 fail_diag_alloc:
1729         adapter->drv_sds_rings = drv_sds_rings;
1730         adapter->drv_tx_rings = drv_tx_rings;
1731         qlcnic_release_diag_lock(adapter);
1732         return ret;
1733 }
1734
1735 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1736                                              u32 *max_wait_count)
1737 {
1738         struct qlcnic_hardware_context *ahw = adapter->ahw;
1739         int temp;
1740
1741         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1742                     ahw->extend_lb_time);
1743         temp = ahw->extend_lb_time * 1000;
1744         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1745         ahw->extend_lb_time = 0;
1746 }
1747
1748 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1749 {
1750         struct qlcnic_hardware_context *ahw = adapter->ahw;
1751         struct net_device *netdev = adapter->netdev;
1752         u32 config, max_wait_count;
1753         int status = 0, loop = 0;
1754
1755         ahw->extend_lb_time = 0;
1756         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1757         status = qlcnic_83xx_get_port_config(adapter);
1758         if (status)
1759                 return status;
1760
1761         config = ahw->port_config;
1762
1763         /* Check if port is already in loopback mode */
1764         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1765             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1766                 netdev_err(netdev,
1767                            "Port already in Loopback mode.\n");
1768                 return -EINPROGRESS;
1769         }
1770
1771         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1772
1773         if (mode == QLCNIC_ILB_MODE)
1774                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1775         if (mode == QLCNIC_ELB_MODE)
1776                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1777
1778         status = qlcnic_83xx_set_port_config(adapter);
1779         if (status) {
1780                 netdev_err(netdev,
1781                            "Failed to Set Loopback Mode = 0x%x.\n",
1782                            ahw->port_config);
1783                 ahw->port_config = config;
1784                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1785                 return status;
1786         }
1787
1788         /* Wait for Link and IDC Completion AEN */
1789         do {
1790                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1791
1792                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1793                         netdev_info(netdev,
1794                                     "Device is resetting, free LB test resources\n");
1795                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1796                         return -EBUSY;
1797                 }
1798
1799                 if (ahw->extend_lb_time)
1800                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1801                                                          &max_wait_count);
1802
1803                 if (loop++ > max_wait_count) {
1804                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1805                                    __func__);
1806                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1807                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1808                         return -ETIMEDOUT;
1809                 }
1810         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1811
1812         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1813                                   QLCNIC_MAC_ADD);
1814         return status;
1815 }
1816
1817 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1818 {
1819         struct qlcnic_hardware_context *ahw = adapter->ahw;
1820         u32 config = ahw->port_config, max_wait_count;
1821         struct net_device *netdev = adapter->netdev;
1822         int status = 0, loop = 0;
1823
1824         ahw->extend_lb_time = 0;
1825         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1826         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1827         if (mode == QLCNIC_ILB_MODE)
1828                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1829         if (mode == QLCNIC_ELB_MODE)
1830                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1831
1832         status = qlcnic_83xx_set_port_config(adapter);
1833         if (status) {
1834                 netdev_err(netdev,
1835                            "Failed to Clear Loopback Mode = 0x%x.\n",
1836                            ahw->port_config);
1837                 ahw->port_config = config;
1838                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1839                 return status;
1840         }
1841
1842         /* Wait for Link and IDC Completion AEN */
1843         do {
1844                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1845
1846                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1847                         netdev_info(netdev,
1848                                     "Device is resetting, free LB test resources\n");
1849                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1850                         return -EBUSY;
1851                 }
1852
1853                 if (ahw->extend_lb_time)
1854                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1855                                                          &max_wait_count);
1856
1857                 if (loop++ > max_wait_count) {
1858                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1859                                    __func__);
1860                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1861                         return -ETIMEDOUT;
1862                 }
1863         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1864
1865         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1866                                   QLCNIC_MAC_DEL);
1867         return status;
1868 }
1869
1870 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1871                                                 u32 *interface_id)
1872 {
1873         if (qlcnic_sriov_pf_check(adapter)) {
1874                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1875         } else {
1876                 if (!qlcnic_sriov_vf_check(adapter))
1877                         *interface_id = adapter->recv_ctx->context_id << 16;
1878         }
1879 }
1880
1881 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1882                                int mode)
1883 {
1884         int err;
1885         u32 temp = 0, temp_ip;
1886         struct qlcnic_cmd_args cmd;
1887
1888         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1889                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1890         if (err)
1891                 return;
1892
1893         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1894
1895         if (mode == QLCNIC_IP_UP)
1896                 cmd.req.arg[1] = 1 | temp;
1897         else
1898                 cmd.req.arg[1] = 2 | temp;
1899
1900         /*
1901          * Adapter needs IP address in network byte order.
1902          * But hardware mailbox registers go through writel(), hence IP address
1903          * gets swapped on big endian architecture.
1904          * To negate swapping of writel() on big endian architecture
1905          * use swab32(value).
1906          */
1907
1908         temp_ip = swab32(ntohl(ip));
1909         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1910         err = qlcnic_issue_cmd(adapter, &cmd);
1911         if (err != QLCNIC_RCODE_SUCCESS)
1912                 dev_err(&adapter->netdev->dev,
1913                         "could not notify %s IP 0x%x request\n",
1914                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1915
1916         qlcnic_free_mbx_args(&cmd);
1917 }
1918
1919 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1920 {
1921         int err;
1922         u32 temp, arg1;
1923         struct qlcnic_cmd_args cmd;
1924         int lro_bit_mask;
1925
1926         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1927
1928         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1929                 return 0;
1930
1931         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1932         if (err)
1933                 return err;
1934
1935         temp = adapter->recv_ctx->context_id << 16;
1936         arg1 = lro_bit_mask | temp;
1937         cmd.req.arg[1] = arg1;
1938
1939         err = qlcnic_issue_cmd(adapter, &cmd);
1940         if (err)
1941                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1942         qlcnic_free_mbx_args(&cmd);
1943
1944         return err;
1945 }
1946
1947 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1948 {
1949         int err;
1950         u32 word;
1951         struct qlcnic_cmd_args cmd;
1952         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1953                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1954                             0x255b0ec26d5a56daULL };
1955
1956         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1957         if (err)
1958                 return err;
1959         /*
1960          * RSS request:
1961          * bits 3-0: Rsvd
1962          *      5-4: hash_type_ipv4
1963          *      7-6: hash_type_ipv6
1964          *        8: enable
1965          *        9: use indirection table
1966          *    16-31: indirection table mask
1967          */
1968         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1969                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1970                 ((u32)(enable & 0x1) << 8) |
1971                 ((0x7ULL) << 16);
1972         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1973         cmd.req.arg[2] = word;
1974         memcpy(&cmd.req.arg[4], key, sizeof(key));
1975
1976         err = qlcnic_issue_cmd(adapter, &cmd);
1977
1978         if (err)
1979                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1980         qlcnic_free_mbx_args(&cmd);
1981
1982         return err;
1983
1984 }
1985
1986 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1987                                                  u32 *interface_id)
1988 {
1989         if (qlcnic_sriov_pf_check(adapter)) {
1990                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1991         } else {
1992                 if (!qlcnic_sriov_vf_check(adapter))
1993                         *interface_id = adapter->recv_ctx->context_id << 16;
1994         }
1995 }
1996
1997 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1998                                    u16 vlan_id, u8 op)
1999 {
2000         struct qlcnic_cmd_args *cmd = NULL;
2001         struct qlcnic_macvlan_mbx mv;
2002         u32 *buf, temp = 0;
2003         int err;
2004
2005         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2006                 return -EIO;
2007
2008         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2009         if (!cmd)
2010                 return -ENOMEM;
2011
2012         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2013         if (err)
2014                 goto out;
2015
2016         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2017
2018         if (vlan_id)
2019                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2020                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2021
2022         cmd->req.arg[1] = op | (1 << 8);
2023         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2024         cmd->req.arg[1] |= temp;
2025         mv.vlan = vlan_id;
2026         mv.mac_addr0 = addr[0];
2027         mv.mac_addr1 = addr[1];
2028         mv.mac_addr2 = addr[2];
2029         mv.mac_addr3 = addr[3];
2030         mv.mac_addr4 = addr[4];
2031         mv.mac_addr5 = addr[5];
2032         buf = &cmd->req.arg[2];
2033         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2034         err = qlcnic_issue_cmd(adapter, cmd);
2035         if (!err)
2036                 return err;
2037
2038         qlcnic_free_mbx_args(cmd);
2039 out:
2040         kfree(cmd);
2041         return err;
2042 }
2043
2044 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2045                                   u16 vlan_id)
2046 {
2047         u8 mac[ETH_ALEN];
2048         memcpy(&mac, addr, ETH_ALEN);
2049         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2050 }
2051
2052 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2053                                u8 type, struct qlcnic_cmd_args *cmd)
2054 {
2055         switch (type) {
2056         case QLCNIC_SET_STATION_MAC:
2057         case QLCNIC_SET_FAC_DEF_MAC:
2058                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2059                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2060                 break;
2061         }
2062         cmd->req.arg[1] = type;
2063 }
2064
2065 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2066                                 u8 function)
2067 {
2068         int err, i;
2069         struct qlcnic_cmd_args cmd;
2070         u32 mac_low, mac_high;
2071
2072         function = 0;
2073         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2074         if (err)
2075                 return err;
2076
2077         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2078         err = qlcnic_issue_cmd(adapter, &cmd);
2079
2080         if (err == QLCNIC_RCODE_SUCCESS) {
2081                 mac_low = cmd.rsp.arg[1];
2082                 mac_high = cmd.rsp.arg[2];
2083
2084                 for (i = 0; i < 2; i++)
2085                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2086                 for (i = 2; i < 6; i++)
2087                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2088         } else {
2089                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2090                         err);
2091                 err = -EIO;
2092         }
2093         qlcnic_free_mbx_args(&cmd);
2094         return err;
2095 }
2096
2097 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2098 {
2099         int err;
2100         u16 temp;
2101         struct qlcnic_cmd_args cmd;
2102         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2103
2104         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2105                 return;
2106
2107         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2108         if (err)
2109                 return;
2110
2111         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2112                 temp = adapter->recv_ctx->context_id;
2113                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2114                 temp = coal->rx_time_us;
2115                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2116         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2117                 temp = adapter->tx_ring->ctx_id;
2118                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2119                 temp = coal->tx_time_us;
2120                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2121         }
2122         cmd.req.arg[3] = coal->flag;
2123         err = qlcnic_issue_cmd(adapter, &cmd);
2124         if (err != QLCNIC_RCODE_SUCCESS)
2125                 dev_info(&adapter->pdev->dev,
2126                          "Failed to send interrupt coalescence parameters\n");
2127         qlcnic_free_mbx_args(&cmd);
2128 }
2129
2130 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2131                                         u32 data[])
2132 {
2133         struct qlcnic_hardware_context *ahw = adapter->ahw;
2134         u8 link_status, duplex;
2135         /* link speed */
2136         link_status = LSB(data[3]) & 1;
2137         if (link_status) {
2138                 ahw->link_speed = MSW(data[2]);
2139                 duplex = LSB(MSW(data[3]));
2140                 if (duplex)
2141                         ahw->link_duplex = DUPLEX_FULL;
2142                 else
2143                         ahw->link_duplex = DUPLEX_HALF;
2144         } else {
2145                 ahw->link_speed = SPEED_UNKNOWN;
2146                 ahw->link_duplex = DUPLEX_UNKNOWN;
2147         }
2148
2149         ahw->link_autoneg = MSB(MSW(data[3]));
2150         ahw->module_type = MSB(LSW(data[3]));
2151         ahw->has_link_events = 1;
2152         ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2153         qlcnic_advert_link_change(adapter, link_status);
2154 }
2155
2156 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2157 {
2158         struct qlcnic_adapter *adapter = data;
2159         struct qlcnic_mailbox *mbx;
2160         u32 mask, resp, event;
2161         unsigned long flags;
2162
2163         mbx = adapter->ahw->mailbox;
2164         spin_lock_irqsave(&mbx->aen_lock, flags);
2165         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2166         if (!(resp & QLCNIC_SET_OWNER))
2167                 goto out;
2168
2169         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2170         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2171                 __qlcnic_83xx_process_aen(adapter);
2172         else
2173                 qlcnic_83xx_notify_mbx_response(mbx);
2174
2175 out:
2176         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2177         writel(0, adapter->ahw->pci_base0 + mask);
2178         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2179         return IRQ_HANDLED;
2180 }
2181
2182 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2183 {
2184         int err = -EIO;
2185         struct qlcnic_cmd_args cmd;
2186
2187         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2188                 dev_err(&adapter->pdev->dev,
2189                         "%s: Error, invoked by non management func\n",
2190                         __func__);
2191                 return err;
2192         }
2193
2194         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2195         if (err)
2196                 return err;
2197
2198         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2199         err = qlcnic_issue_cmd(adapter, &cmd);
2200
2201         if (err != QLCNIC_RCODE_SUCCESS) {
2202                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2203                         err);
2204                 err = -EIO;
2205         }
2206         qlcnic_free_mbx_args(&cmd);
2207
2208         return err;
2209
2210 }
2211
2212 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2213                              struct qlcnic_info *nic)
2214 {
2215         int i, err = -EIO;
2216         struct qlcnic_cmd_args cmd;
2217
2218         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2219                 dev_err(&adapter->pdev->dev,
2220                         "%s: Error, invoked by non management func\n",
2221                         __func__);
2222                 return err;
2223         }
2224
2225         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2226         if (err)
2227                 return err;
2228
2229         cmd.req.arg[1] = (nic->pci_func << 16);
2230         cmd.req.arg[2] = 0x1 << 16;
2231         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2232         cmd.req.arg[4] = nic->capabilities;
2233         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2234         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2235         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2236         for (i = 8; i < 32; i++)
2237                 cmd.req.arg[i] = 0;
2238
2239         err = qlcnic_issue_cmd(adapter, &cmd);
2240
2241         if (err != QLCNIC_RCODE_SUCCESS) {
2242                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2243                         err);
2244                 err = -EIO;
2245         }
2246
2247         qlcnic_free_mbx_args(&cmd);
2248
2249         return err;
2250 }
2251
2252 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2253                              struct qlcnic_info *npar_info, u8 func_id)
2254 {
2255         int err;
2256         u32 temp;
2257         u8 op = 0;
2258         struct qlcnic_cmd_args cmd;
2259         struct qlcnic_hardware_context *ahw = adapter->ahw;
2260
2261         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2262         if (err)
2263                 return err;
2264
2265         if (func_id != ahw->pci_func) {
2266                 temp = func_id << 16;
2267                 cmd.req.arg[1] = op | BIT_31 | temp;
2268         } else {
2269                 cmd.req.arg[1] = ahw->pci_func << 16;
2270         }
2271         err = qlcnic_issue_cmd(adapter, &cmd);
2272         if (err) {
2273                 dev_info(&adapter->pdev->dev,
2274                          "Failed to get nic info %d\n", err);
2275                 goto out;
2276         }
2277
2278         npar_info->op_type = cmd.rsp.arg[1];
2279         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2280         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2281         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2282         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2283         npar_info->capabilities = cmd.rsp.arg[4];
2284         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2285         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2286         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2287         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2288         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2289         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2290         if (cmd.rsp.arg[8] & 0x1)
2291                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2292         if (cmd.rsp.arg[8] & 0x10000) {
2293                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2294                 npar_info->max_linkspeed_reg_offset = temp;
2295         }
2296
2297         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2298                sizeof(ahw->extra_capability));
2299
2300 out:
2301         qlcnic_free_mbx_args(&cmd);
2302         return err;
2303 }
2304
2305 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2306                              u16 *nic, u16 *fcoe, u16 *iscsi)
2307 {
2308         struct device *dev = &adapter->pdev->dev;
2309         int err = 0;
2310
2311         switch (type) {
2312         case QLCNIC_TYPE_NIC:
2313                 (*nic)++;
2314                 break;
2315         case QLCNIC_TYPE_FCOE:
2316                 (*fcoe)++;
2317                 break;
2318         case QLCNIC_TYPE_ISCSI:
2319                 (*iscsi)++;
2320                 break;
2321         default:
2322                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2323                         __func__, type);
2324                 err = -EIO;
2325         }
2326
2327         return err;
2328 }
2329
2330 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2331                              struct qlcnic_pci_info *pci_info)
2332 {
2333         struct qlcnic_hardware_context *ahw = adapter->ahw;
2334         struct device *dev = &adapter->pdev->dev;
2335         u16 nic = 0, fcoe = 0, iscsi = 0;
2336         struct qlcnic_cmd_args cmd;
2337         int i, err = 0, j = 0;
2338         u32 temp;
2339
2340         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2341         if (err)
2342                 return err;
2343
2344         err = qlcnic_issue_cmd(adapter, &cmd);
2345
2346         ahw->total_nic_func = 0;
2347         if (err == QLCNIC_RCODE_SUCCESS) {
2348                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2349                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2350                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2351                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2352                         i++;
2353                         if (!pci_info->active) {
2354                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2355                                 continue;
2356                         }
2357                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2358                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2359                                                        &nic, &fcoe, &iscsi);
2360                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2361                         pci_info->default_port = temp;
2362                         i++;
2363                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2364                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2365                         pci_info->tx_max_bw = temp;
2366                         i = i + 2;
2367                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2368                         i++;
2369                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2370                         i = i + 3;
2371                 }
2372         } else {
2373                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2374                 err = -EIO;
2375         }
2376
2377         ahw->total_nic_func = nic;
2378         ahw->total_pci_func = nic + fcoe + iscsi;
2379         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2380                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2381                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2382                 err = -EIO;
2383         }
2384         qlcnic_free_mbx_args(&cmd);
2385
2386         return err;
2387 }
2388
2389 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2390 {
2391         int i, index, err;
2392         u8 max_ints;
2393         u32 val, temp, type;
2394         struct qlcnic_cmd_args cmd;
2395
2396         max_ints = adapter->ahw->num_msix - 1;
2397         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2398         if (err)
2399                 return err;
2400
2401         cmd.req.arg[1] = max_ints;
2402
2403         if (qlcnic_sriov_vf_check(adapter))
2404                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2405
2406         for (i = 0, index = 2; i < max_ints; i++) {
2407                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2408                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2409                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2410                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2411                 cmd.req.arg[index++] = val;
2412         }
2413         err = qlcnic_issue_cmd(adapter, &cmd);
2414         if (err) {
2415                 dev_err(&adapter->pdev->dev,
2416                         "Failed to configure interrupts 0x%x\n", err);
2417                 goto out;
2418         }
2419
2420         max_ints = cmd.rsp.arg[1];
2421         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2422                 val = cmd.rsp.arg[index];
2423                 if (LSB(val)) {
2424                         dev_info(&adapter->pdev->dev,
2425                                  "Can't configure interrupt %d\n",
2426                                  adapter->ahw->intr_tbl[i].id);
2427                         continue;
2428                 }
2429                 if (op_type) {
2430                         adapter->ahw->intr_tbl[i].id = MSW(val);
2431                         adapter->ahw->intr_tbl[i].enabled = 1;
2432                         temp = cmd.rsp.arg[index + 1];
2433                         adapter->ahw->intr_tbl[i].src = temp;
2434                 } else {
2435                         adapter->ahw->intr_tbl[i].id = i;
2436                         adapter->ahw->intr_tbl[i].enabled = 0;
2437                         adapter->ahw->intr_tbl[i].src = 0;
2438                 }
2439         }
2440 out:
2441         qlcnic_free_mbx_args(&cmd);
2442         return err;
2443 }
2444
2445 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2446 {
2447         int id, timeout = 0;
2448         u32 status = 0;
2449
2450         while (status == 0) {
2451                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2452                 if (status)
2453                         break;
2454
2455                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2456                         id = QLC_SHARED_REG_RD32(adapter,
2457                                                  QLCNIC_FLASH_LOCK_OWNER);
2458                         dev_err(&adapter->pdev->dev,
2459                                 "%s: failed, lock held by %d\n", __func__, id);
2460                         return -EIO;
2461                 }
2462                 usleep_range(1000, 2000);
2463         }
2464
2465         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2466         return 0;
2467 }
2468
2469 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2470 {
2471         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2472         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2473 }
2474
2475 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2476                                       u32 flash_addr, u8 *p_data,
2477                                       int count)
2478 {
2479         u32 word, range, flash_offset, addr = flash_addr, ret;
2480         ulong indirect_add, direct_window;
2481         int i, err = 0;
2482
2483         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2484         if (addr & 0x3) {
2485                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2486                 return -EIO;
2487         }
2488
2489         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2490                                      (addr));
2491
2492         range = flash_offset + (count * sizeof(u32));
2493         /* Check if data is spread across multiple sectors */
2494         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2495
2496                 /* Multi sector read */
2497                 for (i = 0; i < count; i++) {
2498                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2499                         ret = QLCRD32(adapter, indirect_add, &err);
2500                         if (err == -EIO)
2501                                 return err;
2502
2503                         word = ret;
2504                         *(u32 *)p_data  = word;
2505                         p_data = p_data + 4;
2506                         addr = addr + 4;
2507                         flash_offset = flash_offset + 4;
2508
2509                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2510                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2511                                 /* This write is needed once for each sector */
2512                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2513                                                              direct_window,
2514                                                              (addr));
2515                                 flash_offset = 0;
2516                         }
2517                 }
2518         } else {
2519                 /* Single sector read */
2520                 for (i = 0; i < count; i++) {
2521                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2522                         ret = QLCRD32(adapter, indirect_add, &err);
2523                         if (err == -EIO)
2524                                 return err;
2525
2526                         word = ret;
2527                         *(u32 *)p_data  = word;
2528                         p_data = p_data + 4;
2529                         addr = addr + 4;
2530                 }
2531         }
2532
2533         return 0;
2534 }
2535
2536 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2537 {
2538         u32 status;
2539         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2540         int err = 0;
2541
2542         do {
2543                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2544                 if (err == -EIO)
2545                         return err;
2546
2547                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2548                     QLC_83XX_FLASH_STATUS_READY)
2549                         break;
2550
2551                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2552         } while (--retries);
2553
2554         if (!retries)
2555                 return -EIO;
2556
2557         return 0;
2558 }
2559
2560 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2561 {
2562         int ret;
2563         u32 cmd;
2564         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2565         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2566                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2567         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2568                                      adapter->ahw->fdt.write_enable_bits);
2569         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2570                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2571         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2572         if (ret)
2573                 return -EIO;
2574
2575         return 0;
2576 }
2577
2578 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2579 {
2580         int ret;
2581
2582         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2583                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2584                                      adapter->ahw->fdt.write_statusreg_cmd));
2585         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2586                                      adapter->ahw->fdt.write_disable_bits);
2587         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2588                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2589         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2590         if (ret)
2591                 return -EIO;
2592
2593         return 0;
2594 }
2595
2596 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2597 {
2598         int ret, err = 0;
2599         u32 mfg_id;
2600
2601         if (qlcnic_83xx_lock_flash(adapter))
2602                 return -EIO;
2603
2604         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2605                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2606         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2607                                      QLC_83XX_FLASH_READ_CTRL);
2608         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2609         if (ret) {
2610                 qlcnic_83xx_unlock_flash(adapter);
2611                 return -EIO;
2612         }
2613
2614         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2615         if (err == -EIO) {
2616                 qlcnic_83xx_unlock_flash(adapter);
2617                 return err;
2618         }
2619
2620         adapter->flash_mfg_id = (mfg_id & 0xFF);
2621         qlcnic_83xx_unlock_flash(adapter);
2622
2623         return 0;
2624 }
2625
2626 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2627 {
2628         int count, fdt_size, ret = 0;
2629
2630         fdt_size = sizeof(struct qlcnic_fdt);
2631         count = fdt_size / sizeof(u32);
2632
2633         if (qlcnic_83xx_lock_flash(adapter))
2634                 return -EIO;
2635
2636         memset(&adapter->ahw->fdt, 0, fdt_size);
2637         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2638                                                 (u8 *)&adapter->ahw->fdt,
2639                                                 count);
2640
2641         qlcnic_83xx_unlock_flash(adapter);
2642         return ret;
2643 }
2644
2645 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2646                                    u32 sector_start_addr)
2647 {
2648         u32 reversed_addr, addr1, addr2, cmd;
2649         int ret = -EIO;
2650
2651         if (qlcnic_83xx_lock_flash(adapter) != 0)
2652                 return -EIO;
2653
2654         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2655                 ret = qlcnic_83xx_enable_flash_write(adapter);
2656                 if (ret) {
2657                         qlcnic_83xx_unlock_flash(adapter);
2658                         dev_err(&adapter->pdev->dev,
2659                                 "%s failed at %d\n",
2660                                 __func__, __LINE__);
2661                         return ret;
2662                 }
2663         }
2664
2665         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2666         if (ret) {
2667                 qlcnic_83xx_unlock_flash(adapter);
2668                 dev_err(&adapter->pdev->dev,
2669                         "%s: failed at %d\n", __func__, __LINE__);
2670                 return -EIO;
2671         }
2672
2673         addr1 = (sector_start_addr & 0xFF) << 16;
2674         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2675         reversed_addr = addr1 | addr2;
2676
2677         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2678                                      reversed_addr);
2679         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2680         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2681                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2682         else
2683                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2684                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2685         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2686                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2687
2688         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2689         if (ret) {
2690                 qlcnic_83xx_unlock_flash(adapter);
2691                 dev_err(&adapter->pdev->dev,
2692                         "%s: failed at %d\n", __func__, __LINE__);
2693                 return -EIO;
2694         }
2695
2696         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2697                 ret = qlcnic_83xx_disable_flash_write(adapter);
2698                 if (ret) {
2699                         qlcnic_83xx_unlock_flash(adapter);
2700                         dev_err(&adapter->pdev->dev,
2701                                 "%s: failed at %d\n", __func__, __LINE__);
2702                         return ret;
2703                 }
2704         }
2705
2706         qlcnic_83xx_unlock_flash(adapter);
2707
2708         return 0;
2709 }
2710
2711 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2712                               u32 *p_data)
2713 {
2714         int ret = -EIO;
2715         u32 addr1 = 0x00800000 | (addr >> 2);
2716
2717         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2718         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2719         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2720                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2721         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2722         if (ret) {
2723                 dev_err(&adapter->pdev->dev,
2724                         "%s: failed at %d\n", __func__, __LINE__);
2725                 return -EIO;
2726         }
2727
2728         return 0;
2729 }
2730
2731 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2732                                  u32 *p_data, int count)
2733 {
2734         u32 temp;
2735         int ret = -EIO, err = 0;
2736
2737         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2738             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2739                 dev_err(&adapter->pdev->dev,
2740                         "%s: Invalid word count\n", __func__);
2741                 return -EIO;
2742         }
2743
2744         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2745         if (err == -EIO)
2746                 return err;
2747
2748         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2749                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2750         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2751                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2752
2753         /* First DWORD write */
2754         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2755         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2756                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2757         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2758         if (ret) {
2759                 dev_err(&adapter->pdev->dev,
2760                         "%s: failed at %d\n", __func__, __LINE__);
2761                 return -EIO;
2762         }
2763
2764         count--;
2765         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2766                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2767         /* Second to N-1 DWORD writes */
2768         while (count != 1) {
2769                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2770                                              *p_data++);
2771                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2772                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2773                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2774                 if (ret) {
2775                         dev_err(&adapter->pdev->dev,
2776                                 "%s: failed at %d\n", __func__, __LINE__);
2777                         return -EIO;
2778                 }
2779                 count--;
2780         }
2781
2782         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2783                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2784                                      (addr >> 2));
2785         /* Last DWORD write */
2786         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2787         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2788                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2789         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2790         if (ret) {
2791                 dev_err(&adapter->pdev->dev,
2792                         "%s: failed at %d\n", __func__, __LINE__);
2793                 return -EIO;
2794         }
2795
2796         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2797         if (err == -EIO)
2798                 return err;
2799
2800         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2801                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2802                         __func__, __LINE__);
2803                 /* Operation failed, clear error bit */
2804                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2805                 if (err == -EIO)
2806                         return err;
2807
2808                 qlcnic_83xx_wrt_reg_indirect(adapter,
2809                                              QLC_83XX_FLASH_SPI_CONTROL,
2810                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2811         }
2812
2813         return 0;
2814 }
2815
2816 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2817 {
2818         u32 val, id;
2819
2820         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2821
2822         /* Check if recovery need to be performed by the calling function */
2823         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2824                 val = val & ~0x3F;
2825                 val = val | ((adapter->portnum << 2) |
2826                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2827                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2828                 dev_info(&adapter->pdev->dev,
2829                          "%s: lock recovery initiated\n", __func__);
2830                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2831                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2832                 id = ((val >> 2) & 0xF);
2833                 if (id == adapter->portnum) {
2834                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2835                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2836                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2837                         /* Force release the lock */
2838                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2839                         /* Clear recovery bits */
2840                         val = val & ~0x3F;
2841                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2842                         dev_info(&adapter->pdev->dev,
2843                                  "%s: lock recovery completed\n", __func__);
2844                 } else {
2845                         dev_info(&adapter->pdev->dev,
2846                                  "%s: func %d to resume lock recovery process\n",
2847                                  __func__, id);
2848                 }
2849         } else {
2850                 dev_info(&adapter->pdev->dev,
2851                          "%s: lock recovery initiated by other functions\n",
2852                          __func__);
2853         }
2854 }
2855
2856 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2857 {
2858         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2859         int max_attempt = 0;
2860
2861         while (status == 0) {
2862                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2863                 if (status)
2864                         break;
2865
2866                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2867                 i++;
2868
2869                 if (i == 1)
2870                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2871
2872                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2873                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2874                         if (val == temp) {
2875                                 id = val & 0xFF;
2876                                 dev_info(&adapter->pdev->dev,
2877                                          "%s: lock to be recovered from %d\n",
2878                                          __func__, id);
2879                                 qlcnic_83xx_recover_driver_lock(adapter);
2880                                 i = 0;
2881                                 max_attempt++;
2882                         } else {
2883                                 dev_err(&adapter->pdev->dev,
2884                                         "%s: failed to get lock\n", __func__);
2885                                 return -EIO;
2886                         }
2887                 }
2888
2889                 /* Force exit from while loop after few attempts */
2890                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2891                         dev_err(&adapter->pdev->dev,
2892                                 "%s: failed to get lock\n", __func__);
2893                         return -EIO;
2894                 }
2895         }
2896
2897         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2898         lock_alive_counter = val >> 8;
2899         lock_alive_counter++;
2900         val = lock_alive_counter << 8 | adapter->portnum;
2901         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2902
2903         return 0;
2904 }
2905
2906 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2907 {
2908         u32 val, lock_alive_counter, id;
2909
2910         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2911         id = val & 0xFF;
2912         lock_alive_counter = val >> 8;
2913
2914         if (id != adapter->portnum)
2915                 dev_err(&adapter->pdev->dev,
2916                         "%s:Warning func %d is unlocking lock owned by %d\n",
2917                         __func__, adapter->portnum, id);
2918
2919         val = (lock_alive_counter << 8) | 0xFF;
2920         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2921         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2922 }
2923
2924 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2925                                 u32 *data, u32 count)
2926 {
2927         int i, j, ret = 0;
2928         u32 temp;
2929         int err = 0;
2930
2931         /* Check alignment */
2932         if (addr & 0xF)
2933                 return -EIO;
2934
2935         mutex_lock(&adapter->ahw->mem_lock);
2936         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2937
2938         for (i = 0; i < count; i++, addr += 16) {
2939                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2940                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2941                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2942                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2943                         mutex_unlock(&adapter->ahw->mem_lock);
2944                         return -EIO;
2945                 }
2946
2947                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2948                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2949                                              *data++);
2950                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2951                                              *data++);
2952                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2953                                              *data++);
2954                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2955                                              *data++);
2956                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2957                                              QLCNIC_TA_WRITE_ENABLE);
2958                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2959                                              QLCNIC_TA_WRITE_START);
2960
2961                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2962                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2963                         if (err == -EIO) {
2964                                 mutex_unlock(&adapter->ahw->mem_lock);
2965                                 return err;
2966                         }
2967
2968                         if ((temp & TA_CTL_BUSY) == 0)
2969                                 break;
2970                 }
2971
2972                 /* Status check failure */
2973                 if (j >= MAX_CTL_CHECK) {
2974                         printk_ratelimited(KERN_WARNING
2975                                            "MS memory write failed\n");
2976                         mutex_unlock(&adapter->ahw->mem_lock);
2977                         return -EIO;
2978                 }
2979         }
2980
2981         mutex_unlock(&adapter->ahw->mem_lock);
2982
2983         return ret;
2984 }
2985
2986 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2987                              u8 *p_data, int count)
2988 {
2989         u32 word, addr = flash_addr, ret;
2990         ulong  indirect_addr;
2991         int i, err = 0;
2992
2993         if (qlcnic_83xx_lock_flash(adapter) != 0)
2994                 return -EIO;
2995
2996         if (addr & 0x3) {
2997                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2998                 qlcnic_83xx_unlock_flash(adapter);
2999                 return -EIO;
3000         }
3001
3002         for (i = 0; i < count; i++) {
3003                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3004                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
3005                                                  (addr))) {
3006                         qlcnic_83xx_unlock_flash(adapter);
3007                         return -EIO;
3008                 }
3009
3010                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3011                 ret = QLCRD32(adapter, indirect_addr, &err);
3012                 if (err == -EIO)
3013                         return err;
3014
3015                 word = ret;
3016                 *(u32 *)p_data  = word;
3017                 p_data = p_data + 4;
3018                 addr = addr + 4;
3019         }
3020
3021         qlcnic_83xx_unlock_flash(adapter);
3022
3023         return 0;
3024 }
3025
3026 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3027 {
3028         u8 pci_func;
3029         int err;
3030         u32 config = 0, state;
3031         struct qlcnic_cmd_args cmd;
3032         struct qlcnic_hardware_context *ahw = adapter->ahw;
3033
3034         if (qlcnic_sriov_vf_check(adapter))
3035                 pci_func = adapter->portnum;
3036         else
3037                 pci_func = ahw->pci_func;
3038
3039         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3040         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3041                 dev_info(&adapter->pdev->dev, "link state down\n");
3042                 return config;
3043         }
3044
3045         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3046         if (err)
3047                 return err;
3048
3049         err = qlcnic_issue_cmd(adapter, &cmd);
3050         if (err) {
3051                 dev_info(&adapter->pdev->dev,
3052                          "Get Link Status Command failed: 0x%x\n", err);
3053                 goto out;
3054         } else {
3055                 config = cmd.rsp.arg[1];
3056                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3057                 case QLC_83XX_10M_LINK:
3058                         ahw->link_speed = SPEED_10;
3059                         break;
3060                 case QLC_83XX_100M_LINK:
3061                         ahw->link_speed = SPEED_100;
3062                         break;
3063                 case QLC_83XX_1G_LINK:
3064                         ahw->link_speed = SPEED_1000;
3065                         break;
3066                 case QLC_83XX_10G_LINK:
3067                         ahw->link_speed = SPEED_10000;
3068                         break;
3069                 default:
3070                         ahw->link_speed = 0;
3071                         break;
3072                 }
3073                 config = cmd.rsp.arg[3];
3074                 if (QLC_83XX_SFP_PRESENT(config)) {
3075                         switch (ahw->module_type) {
3076                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3077                         case LINKEVENT_MODULE_OPTICAL_SRLR:
3078                         case LINKEVENT_MODULE_OPTICAL_LRM:
3079                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3080                                 ahw->supported_type = PORT_FIBRE;
3081                                 break;
3082                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3083                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3084                         case LINKEVENT_MODULE_TWINAX:
3085                                 ahw->supported_type = PORT_TP;
3086                                 break;
3087                         default:
3088                                 ahw->supported_type = PORT_OTHER;
3089                         }
3090                 }
3091                 if (config & 1)
3092                         err = 1;
3093         }
3094 out:
3095         qlcnic_free_mbx_args(&cmd);
3096         return config;
3097 }
3098
3099 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3100                              struct ethtool_cmd *ecmd)
3101 {
3102         u32 config = 0;
3103         int status = 0;
3104         struct qlcnic_hardware_context *ahw = adapter->ahw;
3105
3106         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3107                 /* Get port configuration info */
3108                 status = qlcnic_83xx_get_port_info(adapter);
3109                 /* Get Link Status related info */
3110                 config = qlcnic_83xx_test_link(adapter);
3111                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3112         }
3113
3114         /* hard code until there is a way to get it from flash */
3115         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3116
3117         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3118                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3119                 ecmd->duplex = ahw->link_duplex;
3120                 ecmd->autoneg = ahw->link_autoneg;
3121         } else {
3122                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3123                 ecmd->duplex = DUPLEX_UNKNOWN;
3124                 ecmd->autoneg = AUTONEG_DISABLE;
3125         }
3126
3127         if (ahw->port_type == QLCNIC_XGBE) {
3128                 ecmd->supported = SUPPORTED_10000baseT_Full;
3129                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3130         } else {
3131                 ecmd->supported = (SUPPORTED_10baseT_Half |
3132                                    SUPPORTED_10baseT_Full |
3133                                    SUPPORTED_100baseT_Half |
3134                                    SUPPORTED_100baseT_Full |
3135                                    SUPPORTED_1000baseT_Half |
3136                                    SUPPORTED_1000baseT_Full);
3137                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3138                                      ADVERTISED_100baseT_Full |
3139                                      ADVERTISED_1000baseT_Half |
3140                                      ADVERTISED_1000baseT_Full);
3141         }
3142
3143         switch (ahw->supported_type) {
3144         case PORT_FIBRE:
3145                 ecmd->supported |= SUPPORTED_FIBRE;
3146                 ecmd->advertising |= ADVERTISED_FIBRE;
3147                 ecmd->port = PORT_FIBRE;
3148                 ecmd->transceiver = XCVR_EXTERNAL;
3149                 break;
3150         case PORT_TP:
3151                 ecmd->supported |= SUPPORTED_TP;
3152                 ecmd->advertising |= ADVERTISED_TP;
3153                 ecmd->port = PORT_TP;
3154                 ecmd->transceiver = XCVR_INTERNAL;
3155                 break;
3156         default:
3157                 ecmd->supported |= SUPPORTED_FIBRE;
3158                 ecmd->advertising |= ADVERTISED_FIBRE;
3159                 ecmd->port = PORT_OTHER;
3160                 ecmd->transceiver = XCVR_EXTERNAL;
3161                 break;
3162         }
3163         ecmd->phy_address = ahw->physical_port;
3164         return status;
3165 }
3166
3167 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3168                              struct ethtool_cmd *ecmd)
3169 {
3170         int status = 0;
3171         u32 config = adapter->ahw->port_config;
3172
3173         if (ecmd->autoneg)
3174                 adapter->ahw->port_config |= BIT_15;
3175
3176         switch (ethtool_cmd_speed(ecmd)) {
3177         case SPEED_10:
3178                 adapter->ahw->port_config |= BIT_8;
3179                 break;
3180         case SPEED_100:
3181                 adapter->ahw->port_config |= BIT_9;
3182                 break;
3183         case SPEED_1000:
3184                 adapter->ahw->port_config |= BIT_10;
3185                 break;
3186         case SPEED_10000:
3187                 adapter->ahw->port_config |= BIT_11;
3188                 break;
3189         default:
3190                 return -EINVAL;
3191         }
3192
3193         status = qlcnic_83xx_set_port_config(adapter);
3194         if (status) {
3195                 dev_info(&adapter->pdev->dev,
3196                          "Failed to Set Link Speed and autoneg.\n");
3197                 adapter->ahw->port_config = config;
3198         }
3199         return status;
3200 }
3201
3202 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3203                                           u64 *data, int index)
3204 {
3205         u32 low, hi;
3206         u64 val;
3207
3208         low = cmd->rsp.arg[index];
3209         hi = cmd->rsp.arg[index + 1];
3210         val = (((u64) low) | (((u64) hi) << 32));
3211         *data++ = val;
3212         return data;
3213 }
3214
3215 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3216                                    struct qlcnic_cmd_args *cmd, u64 *data,
3217                                    int type, int *ret)
3218 {
3219         int err, k, total_regs;
3220
3221         *ret = 0;
3222         err = qlcnic_issue_cmd(adapter, cmd);
3223         if (err != QLCNIC_RCODE_SUCCESS) {
3224                 dev_info(&adapter->pdev->dev,
3225                          "Error in get statistics mailbox command\n");
3226                 *ret = -EIO;
3227                 return data;
3228         }
3229         total_regs = cmd->rsp.num;
3230         switch (type) {
3231         case QLC_83XX_STAT_MAC:
3232                 /* fill in MAC tx counters */
3233                 for (k = 2; k < 28; k += 2)
3234                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3235                 /* skip 24 bytes of reserved area */
3236                 /* fill in MAC rx counters */
3237                 for (k += 6; k < 60; k += 2)
3238                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3239                 /* skip 24 bytes of reserved area */
3240                 /* fill in MAC rx frame stats */
3241                 for (k += 6; k < 80; k += 2)
3242                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3243                 /* fill in eSwitch stats */
3244                 for (; k < total_regs; k += 2)
3245                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3246                 break;
3247         case QLC_83XX_STAT_RX:
3248                 for (k = 2; k < 8; k += 2)
3249                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3250                 /* skip 8 bytes of reserved data */
3251                 for (k += 2; k < 24; k += 2)
3252                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3253                 /* skip 8 bytes containing RE1FBQ error data */
3254                 for (k += 2; k < total_regs; k += 2)
3255                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3256                 break;
3257         case QLC_83XX_STAT_TX:
3258                 for (k = 2; k < 10; k += 2)
3259                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3260                 /* skip 8 bytes of reserved data */
3261                 for (k += 2; k < total_regs; k += 2)
3262                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3263                 break;
3264         default:
3265                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3266                 *ret = -EIO;
3267         }
3268         return data;
3269 }
3270
3271 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3272 {
3273         struct qlcnic_cmd_args cmd;
3274         struct net_device *netdev = adapter->netdev;
3275         int ret = 0;
3276
3277         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3278         if (ret)
3279                 return;
3280         /* Get Tx stats */
3281         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3282         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3283         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3284                                       QLC_83XX_STAT_TX, &ret);
3285         if (ret) {
3286                 netdev_err(netdev, "Error getting Tx stats\n");
3287                 goto out;
3288         }
3289         /* Get MAC stats */
3290         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3291         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3292         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3293         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3294                                       QLC_83XX_STAT_MAC, &ret);
3295         if (ret) {
3296                 netdev_err(netdev, "Error getting MAC stats\n");
3297                 goto out;
3298         }
3299         /* Get Rx stats */
3300         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3301         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3302         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3303         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3304                                       QLC_83XX_STAT_RX, &ret);
3305         if (ret)
3306                 netdev_err(netdev, "Error getting Rx stats\n");
3307 out:
3308         qlcnic_free_mbx_args(&cmd);
3309 }
3310
3311 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3312 {
3313         u32 major, minor, sub;
3314
3315         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3316         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3317         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3318
3319         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3320                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3321                          __func__);
3322                 return 1;
3323         }
3324         return 0;
3325 }
3326
3327 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3328 {
3329         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3330                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3331                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3332                 sizeof(*adapter->ahw->reg_tbl));
3333 }
3334
3335 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3336 {
3337         int i, j = 0;
3338
3339         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3340              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3341                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3342
3343         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3344                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3345         return i;
3346 }
3347
3348 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3349 {
3350         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3351         struct qlcnic_hardware_context *ahw = adapter->ahw;
3352         struct qlcnic_cmd_args cmd;
3353         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3354         u8 drv_tx_rings = adapter->drv_tx_rings;
3355         u32 data;
3356         u16 intrpt_id, id;
3357         int ret;
3358
3359         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3360                 netdev_info(netdev, "Device is resetting\n");
3361                 return -EBUSY;
3362         }
3363
3364         if (qlcnic_get_diag_lock(adapter)) {
3365                 netdev_info(netdev, "Device in diagnostics mode\n");
3366                 return -EBUSY;
3367         }
3368
3369         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3370                                          drv_sds_rings);
3371         if (ret)
3372                 goto fail_diag_irq;
3373
3374         ahw->diag_cnt = 0;
3375         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3376         if (ret)
3377                 goto fail_diag_irq;
3378
3379         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3380                 intrpt_id = ahw->intr_tbl[0].id;
3381         else
3382                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3383
3384         cmd.req.arg[1] = 1;
3385         cmd.req.arg[2] = intrpt_id;
3386         cmd.req.arg[3] = BIT_0;
3387
3388         ret = qlcnic_issue_cmd(adapter, &cmd);
3389         data = cmd.rsp.arg[2];
3390         id = LSW(data);
3391         val = LSB(MSW(data));
3392         if (id != intrpt_id)
3393                 dev_info(&adapter->pdev->dev,
3394                          "Interrupt generated: 0x%x, requested:0x%x\n",
3395                          id, intrpt_id);
3396         if (val)
3397                 dev_err(&adapter->pdev->dev,
3398                          "Interrupt test error: 0x%x\n", val);
3399         if (ret)
3400                 goto done;
3401
3402         msleep(20);
3403         ret = !ahw->diag_cnt;
3404
3405 done:
3406         qlcnic_free_mbx_args(&cmd);
3407         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3408
3409 fail_diag_irq:
3410         adapter->drv_sds_rings = drv_sds_rings;
3411         adapter->drv_tx_rings = drv_tx_rings;
3412         qlcnic_release_diag_lock(adapter);
3413         return ret;
3414 }
3415
3416 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3417                                 struct ethtool_pauseparam *pause)
3418 {
3419         struct qlcnic_hardware_context *ahw = adapter->ahw;
3420         int status = 0;
3421         u32 config;
3422
3423         status = qlcnic_83xx_get_port_config(adapter);
3424         if (status) {
3425                 dev_err(&adapter->pdev->dev,
3426                         "%s: Get Pause Config failed\n", __func__);
3427                 return;
3428         }
3429         config = ahw->port_config;
3430         if (config & QLC_83XX_CFG_STD_PAUSE) {
3431                 switch (MSW(config)) {
3432                 case QLC_83XX_TX_PAUSE:
3433                         pause->tx_pause = 1;
3434                         break;
3435                 case QLC_83XX_RX_PAUSE:
3436                         pause->rx_pause = 1;
3437                         break;
3438                 case QLC_83XX_TX_RX_PAUSE:
3439                 default:
3440                         /* Backward compatibility for existing
3441                          * flash definitions
3442                          */
3443                         pause->tx_pause = 1;
3444                         pause->rx_pause = 1;
3445                 }
3446         }
3447
3448         if (QLC_83XX_AUTONEG(config))
3449                 pause->autoneg = 1;
3450 }
3451
3452 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3453                                struct ethtool_pauseparam *pause)
3454 {
3455         struct qlcnic_hardware_context *ahw = adapter->ahw;
3456         int status = 0;
3457         u32 config;
3458
3459         status = qlcnic_83xx_get_port_config(adapter);
3460         if (status) {
3461                 dev_err(&adapter->pdev->dev,
3462                         "%s: Get Pause Config failed.\n", __func__);
3463                 return status;
3464         }
3465         config = ahw->port_config;
3466
3467         if (ahw->port_type == QLCNIC_GBE) {
3468                 if (pause->autoneg)
3469                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3470                 if (!pause->autoneg)
3471                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3472         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3473                 return -EOPNOTSUPP;
3474         }
3475
3476         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3477                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3478
3479         if (pause->rx_pause && pause->tx_pause) {
3480                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3481         } else if (pause->rx_pause && !pause->tx_pause) {
3482                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3483                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3484         } else if (pause->tx_pause && !pause->rx_pause) {
3485                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3486                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3487         } else if (!pause->rx_pause && !pause->tx_pause) {
3488                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3489                                       QLC_83XX_CFG_STD_PAUSE);
3490         }
3491         status = qlcnic_83xx_set_port_config(adapter);
3492         if (status) {
3493                 dev_err(&adapter->pdev->dev,
3494                         "%s: Set Pause Config failed.\n", __func__);
3495                 ahw->port_config = config;
3496         }
3497         return status;
3498 }
3499
3500 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3501 {
3502         int ret, err = 0;
3503         u32 temp;
3504
3505         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3506                                      QLC_83XX_FLASH_OEM_READ_SIG);
3507         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3508                                      QLC_83XX_FLASH_READ_CTRL);
3509         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3510         if (ret)
3511                 return -EIO;
3512
3513         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3514         if (err == -EIO)
3515                 return err;
3516
3517         return temp & 0xFF;
3518 }
3519
3520 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3521 {
3522         int status;
3523
3524         status = qlcnic_83xx_read_flash_status_reg(adapter);
3525         if (status == -EIO) {
3526                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3527                          __func__);
3528                 return 1;
3529         }
3530         return 0;
3531 }
3532
3533 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3534 {
3535         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3536         struct net_device *netdev = adapter->netdev;
3537         int retval;
3538
3539         netif_device_detach(netdev);
3540         qlcnic_cancel_idc_work(adapter);
3541
3542         if (netif_running(netdev))
3543                 qlcnic_down(adapter, netdev);
3544
3545         qlcnic_83xx_disable_mbx_intr(adapter);
3546         cancel_delayed_work_sync(&adapter->idc_aen_work);
3547
3548         retval = pci_save_state(pdev);
3549         if (retval)
3550                 return retval;
3551
3552         return 0;
3553 }
3554
3555 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3556 {
3557         struct qlcnic_hardware_context *ahw = adapter->ahw;
3558         struct qlc_83xx_idc *idc = &ahw->idc;
3559         int err = 0;
3560
3561         err = qlcnic_83xx_idc_init(adapter);
3562         if (err)
3563                 return err;
3564
3565         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3566                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3567                         qlcnic_83xx_set_vnic_opmode(adapter);
3568                 } else {
3569                         err = qlcnic_83xx_check_vnic_state(adapter);
3570                         if (err)
3571                                 return err;
3572                 }
3573         }
3574
3575         err = qlcnic_83xx_idc_reattach_driver(adapter);
3576         if (err)
3577                 return err;
3578
3579         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3580                              idc->delay);
3581         return err;
3582 }
3583
3584 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3585 {
3586         reinit_completion(&mbx->completion);
3587         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3588 }
3589
3590 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3591 {
3592         if (!mbx)
3593                 return;
3594
3595         destroy_workqueue(mbx->work_q);
3596         kfree(mbx);
3597 }
3598
3599 static inline void
3600 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3601                                   struct qlcnic_cmd_args *cmd)
3602 {
3603         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3604
3605         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3606                 qlcnic_free_mbx_args(cmd);
3607                 kfree(cmd);
3608                 return;
3609         }
3610         complete(&cmd->completion);
3611 }
3612
3613 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3614 {
3615         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3616         struct list_head *head = &mbx->cmd_q;
3617         struct qlcnic_cmd_args *cmd = NULL;
3618
3619         spin_lock(&mbx->queue_lock);
3620
3621         while (!list_empty(head)) {
3622                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3623                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3624                          __func__, cmd->cmd_op);
3625                 list_del(&cmd->list);
3626                 mbx->num_cmds--;
3627                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3628         }
3629
3630         spin_unlock(&mbx->queue_lock);
3631 }
3632
3633 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3634 {
3635         struct qlcnic_hardware_context *ahw = adapter->ahw;
3636         struct qlcnic_mailbox *mbx = ahw->mailbox;
3637         u32 host_mbx_ctrl;
3638
3639         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3640                 return -EBUSY;
3641
3642         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3643         if (host_mbx_ctrl) {
3644                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3645                 ahw->idc.collect_dump = 1;
3646                 return -EIO;
3647         }
3648
3649         return 0;
3650 }
3651
3652 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3653                                               u8 issue_cmd)
3654 {
3655         if (issue_cmd)
3656                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3657         else
3658                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3659 }
3660
3661 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3662                                         struct qlcnic_cmd_args *cmd)
3663 {
3664         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3665
3666         spin_lock(&mbx->queue_lock);
3667
3668         list_del(&cmd->list);
3669         mbx->num_cmds--;
3670
3671         spin_unlock(&mbx->queue_lock);
3672
3673         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3674 }
3675
3676 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3677                                        struct qlcnic_cmd_args *cmd)
3678 {
3679         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3680         struct qlcnic_hardware_context *ahw = adapter->ahw;
3681         int i, j;
3682
3683         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3684                 mbx_cmd = cmd->req.arg[0];
3685                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3686                 for (i = 1; i < cmd->req.num; i++)
3687                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3688         } else {
3689                 fw_hal_version = ahw->fw_hal_version;
3690                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3691                 total_size = cmd->pay_size + hdr_size;
3692                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3693                 mbx_cmd = tmp | fw_hal_version << 29;
3694                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3695
3696                 /* Back channel specific operations bits */
3697                 mbx_cmd = 0x1 | 1 << 4;
3698
3699                 if (qlcnic_sriov_pf_check(adapter))
3700                         mbx_cmd |= cmd->func_num << 5;
3701
3702                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3703
3704                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3705                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3706                 for (j = 0; j < cmd->pay_size; j++, i++)
3707                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3708         }
3709 }
3710
3711 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3712 {
3713         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3714
3715         if (!mbx)
3716                 return;
3717
3718         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3719         complete(&mbx->completion);
3720         cancel_work_sync(&mbx->work);
3721         flush_workqueue(mbx->work_q);
3722         qlcnic_83xx_flush_mbx_queue(adapter);
3723 }
3724
3725 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3726                                        struct qlcnic_cmd_args *cmd,
3727                                        unsigned long *timeout)
3728 {
3729         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3730
3731         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3732                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3733                 init_completion(&cmd->completion);
3734                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3735
3736                 spin_lock(&mbx->queue_lock);
3737
3738                 list_add_tail(&cmd->list, &mbx->cmd_q);
3739                 mbx->num_cmds++;
3740                 cmd->total_cmds = mbx->num_cmds;
3741                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3742                 queue_work(mbx->work_q, &mbx->work);
3743
3744                 spin_unlock(&mbx->queue_lock);
3745
3746                 return 0;
3747         }
3748
3749         return -EBUSY;
3750 }
3751
3752 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3753                                        struct qlcnic_cmd_args *cmd)
3754 {
3755         u8 mac_cmd_rcode;
3756         u32 fw_data;
3757
3758         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3759                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3760                 mac_cmd_rcode = (u8)fw_data;
3761                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3762                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3763                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3764                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3765                         return QLCNIC_RCODE_SUCCESS;
3766                 }
3767         }
3768
3769         return -EINVAL;
3770 }
3771
3772 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3773                                        struct qlcnic_cmd_args *cmd)
3774 {
3775         struct qlcnic_hardware_context *ahw = adapter->ahw;
3776         struct device *dev = &adapter->pdev->dev;
3777         u8 mbx_err_code;
3778         u32 fw_data;
3779
3780         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3781         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3782         qlcnic_83xx_get_mbx_data(adapter, cmd);
3783
3784         switch (mbx_err_code) {
3785         case QLCNIC_MBX_RSP_OK:
3786         case QLCNIC_MBX_PORT_RSP_OK:
3787                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3788                 break;
3789         default:
3790                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3791                         break;
3792
3793                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3794                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3795                         ahw->op_mode, mbx_err_code);
3796                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3797                 qlcnic_dump_mbx(adapter, cmd);
3798         }
3799
3800         return;
3801 }
3802
3803 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3804 {
3805         struct qlcnic_hardware_context *ahw = adapter->ahw;
3806         u32 offset;
3807
3808         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3809         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3810                  readl(ahw->pci_base0 + offset),
3811                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3812                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3813                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3814 }
3815
3816 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3817 {
3818         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3819                                                   work);
3820         struct qlcnic_adapter *adapter = mbx->adapter;
3821         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3822         struct device *dev = &adapter->pdev->dev;
3823         atomic_t *rsp_status = &mbx->rsp_status;
3824         struct list_head *head = &mbx->cmd_q;
3825         struct qlcnic_hardware_context *ahw;
3826         struct qlcnic_cmd_args *cmd = NULL;
3827
3828         ahw = adapter->ahw;
3829
3830         while (true) {
3831                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3832                         qlcnic_83xx_flush_mbx_queue(adapter);
3833                         return;
3834                 }
3835
3836                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3837
3838                 spin_lock(&mbx->queue_lock);
3839
3840                 if (list_empty(head)) {
3841                         spin_unlock(&mbx->queue_lock);
3842                         return;
3843                 }
3844                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3845
3846                 spin_unlock(&mbx->queue_lock);
3847
3848                 mbx_ops->encode_cmd(adapter, cmd);
3849                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3850
3851                 if (wait_for_completion_timeout(&mbx->completion,
3852                                                 QLC_83XX_MBX_TIMEOUT)) {
3853                         mbx_ops->decode_resp(adapter, cmd);
3854                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3855                 } else {
3856                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3857                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3858                                 ahw->op_mode);
3859                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3860                         qlcnic_dump_mailbox_registers(adapter);
3861                         qlcnic_83xx_get_mbx_data(adapter, cmd);
3862                         qlcnic_dump_mbx(adapter, cmd);
3863                         qlcnic_83xx_idc_request_reset(adapter,
3864                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3865                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3866                 }
3867                 mbx_ops->dequeue_cmd(adapter, cmd);
3868         }
3869 }
3870
3871 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3872         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3873         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3874         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3875         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3876         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3877 };
3878
3879 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3880 {
3881         struct qlcnic_hardware_context *ahw = adapter->ahw;
3882         struct qlcnic_mailbox *mbx;
3883
3884         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3885         if (!ahw->mailbox)
3886                 return -ENOMEM;
3887
3888         mbx = ahw->mailbox;
3889         mbx->ops = &qlcnic_83xx_mbx_ops;
3890         mbx->adapter = adapter;
3891
3892         spin_lock_init(&mbx->queue_lock);
3893         spin_lock_init(&mbx->aen_lock);
3894         INIT_LIST_HEAD(&mbx->cmd_q);
3895         init_completion(&mbx->completion);
3896
3897         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3898         if (mbx->work_q == NULL) {
3899                 kfree(mbx);
3900                 return -ENOMEM;
3901         }
3902
3903         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3904         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3905         return 0;
3906 }
3907
3908 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3909                                                pci_channel_state_t state)
3910 {
3911         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3912
3913         if (state == pci_channel_io_perm_failure)
3914                 return PCI_ERS_RESULT_DISCONNECT;
3915
3916         if (state == pci_channel_io_normal)
3917                 return PCI_ERS_RESULT_RECOVERED;
3918
3919         set_bit(__QLCNIC_AER, &adapter->state);
3920         set_bit(__QLCNIC_RESETTING, &adapter->state);
3921
3922         qlcnic_83xx_aer_stop_poll_work(adapter);
3923
3924         pci_save_state(pdev);
3925         pci_disable_device(pdev);
3926
3927         return PCI_ERS_RESULT_NEED_RESET;
3928 }
3929
3930 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3931 {
3932         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3933         int err = 0;
3934
3935         pdev->error_state = pci_channel_io_normal;
3936         err = pci_enable_device(pdev);
3937         if (err)
3938                 goto disconnect;
3939
3940         pci_set_power_state(pdev, PCI_D0);
3941         pci_set_master(pdev);
3942         pci_restore_state(pdev);
3943
3944         err = qlcnic_83xx_aer_reset(adapter);
3945         if (err == 0)
3946                 return PCI_ERS_RESULT_RECOVERED;
3947 disconnect:
3948         clear_bit(__QLCNIC_AER, &adapter->state);
3949         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3950         return PCI_ERS_RESULT_DISCONNECT;
3951 }
3952
3953 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3954 {
3955         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3956
3957         pci_cleanup_aer_uncorrect_error_status(pdev);
3958         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3959                 qlcnic_83xx_aer_start_poll_work(adapter);
3960 }