drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hw.h"
  10
  11 /* Reset template definitions */
  12 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  13 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  14 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  15
  16 #define QLC_83XX_OPCODE_NOP                     0x0000
  17 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  18 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  19 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  20 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  21 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  22 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  23 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  24 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  25 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  26
  27 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  28 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
  29 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  30 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  31
  32 /* Template header */
  33 struct qlc_83xx_reset_hdr {
  34         u16     version;
  35         u16     signature;
  36         u16     size;
  37         u16     entries;
  38         u16     hdr_size;
  39         u16     checksum;
  40         u16     init_offset;
  41         u16     start_offset;
  42 } __packed;
  43
  44 /* Command entry header. */
  45 struct qlc_83xx_entry_hdr {
  46         u16 cmd;
  47         u16 size;
  48         u16 count;
  49         u16 delay;
  50 } __packed;
  51
  52 /* Generic poll command */
  53 struct qlc_83xx_poll {
  54         u32     mask;
  55         u32     status;
  56 } __packed;
  57
  58 /* Read modify write command */
  59 struct qlc_83xx_rmw {
  60         u32     mask;
  61         u32     xor_value;
  62         u32     or_value;
  63         u8      shl;
  64         u8      shr;
  65         u8      index_a;
  66         u8      rsvd;
  67 } __packed;
  68
  69 /* Generic command with 2 DWORD */
  70 struct qlc_83xx_entry {
  71         u32 arg1;
  72         u32 arg2;
  73 } __packed;
  74
  75 /* Generic command with 4 DWORD */
  76 struct qlc_83xx_quad_entry {
  77         u32 dr_addr;
  78         u32 dr_value;
  79         u32 ar_addr;
  80         u32 ar_value;
  81 } __packed;
  82 static const char *const qlc_83xx_idc_states[] = {
  83         "Unknown",
  84         "Cold",
  85         "Init",
  86         "Ready",
  87         "Need Reset",
  88         "Need Quiesce",
  89         "Failed",
  90         "Quiesce"
  91 };
  92
  93 /* Device States */
  94 enum qlcnic_83xx_states {
  95         QLC_83XX_IDC_DEV_UNKNOWN,
  96         QLC_83XX_IDC_DEV_COLD,
  97         QLC_83XX_IDC_DEV_INIT,
  98         QLC_83XX_IDC_DEV_READY,
  99         QLC_83XX_IDC_DEV_NEED_RESET,
 100         QLC_83XX_IDC_DEV_NEED_QUISCENT,
 101         QLC_83XX_IDC_DEV_FAILED,
 102         QLC_83XX_IDC_DEV_QUISCENT
 103 };
 104
 105 static int
 106 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 107 {
 108         u32 val;
 109
 110         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 111         if ((val & 0xFFFF))
 112                 return 1;
 113         else
 114                 return 0;
 115 }
 116
 117 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 118 {
 119         u32 cur, prev;
 120         cur = adapter->ahw->idc.curr_state;
 121         prev = adapter->ahw->idc.prev_state;
 122
 123         dev_info(&adapter->pdev->dev,
 124                  "current state  = %s,  prev state = %s\n",
 125                  adapter->ahw->idc.name[cur],
 126                  adapter->ahw->idc.name[prev]);
 127 }
 128
 129 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 130                                             u8 mode, int lock)
 131 {
 132         u32 val;
 133         int seconds;
 134
 135         if (lock) {
 136                 if (qlcnic_83xx_lock_driver(adapter))
 137                         return -EBUSY;
 138         }
 139
 140         val = adapter->portnum & 0xf;
 141         val |= mode << 7;
 142         if (mode)
 143                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 144         else
 145                 seconds = jiffies / HZ;
 146
 147         val |= seconds << 8;
 148         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 149         adapter->ahw->idc.sec_counter = jiffies / HZ;
 150
 151         if (lock)
 152                 qlcnic_83xx_unlock_driver(adapter);
 153
 154         return 0;
 155 }
 156
 157 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 158 {
 159         u32 val;
 160
 161         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 162         val = val & ~(0x3 << (adapter->portnum * 2));
 163         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 164         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 165 }
 166
 167 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 168                                                 int lock)
 169 {
 170         u32 val;
 171
 172         if (lock) {
 173                 if (qlcnic_83xx_lock_driver(adapter))
 174                         return -EBUSY;
 175         }
 176
 177         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 178         val = val & ~0xFF;
 179         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 180         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 181
 182         if (lock)
 183                 qlcnic_83xx_unlock_driver(adapter);
 184
 185         return 0;
 186 }
 187
 188 static int
 189 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 190                                         int status, int lock)
 191 {
 192         u32 val;
 193
 194         if (lock) {
 195                 if (qlcnic_83xx_lock_driver(adapter))
 196                         return -EBUSY;
 197         }
 198
 199         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 200
 201         if (status)
 202                 val = val | (1 << adapter->portnum);
 203         else
 204                 val = val & ~(1 << adapter->portnum);
 205
 206         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 207         qlcnic_83xx_idc_update_minor_version(adapter);
 208
 209         if (lock)
 210                 qlcnic_83xx_unlock_driver(adapter);
 211
 212         return 0;
 213 }
 214
 215 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 216 {
 217         u32 val;
 218         u8 version;
 219
 220         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 221         version = val & 0xFF;
 222
 223         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 224                 dev_info(&adapter->pdev->dev,
 225                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 226                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 227                 return -EIO;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 234                                            int lock)
 235 {
 236         u32 val;
 237
 238         if (lock) {
 239                 if (qlcnic_83xx_lock_driver(adapter))
 240                         return -EBUSY;
 241         }
 242
 243         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 244         /* Clear gracefull reset bit */
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 246         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 247         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 248
 249         if (lock)
 250                 qlcnic_83xx_unlock_driver(adapter);
 251
 252         return 0;
 253 }
 254
 255 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 256                                               int flag, int lock)
 257 {
 258         u32 val;
 259
 260         if (lock) {
 261                 if (qlcnic_83xx_lock_driver(adapter))
 262                         return -EBUSY;
 263         }
 264
 265         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 266         if (flag)
 267                 val = val | (1 << adapter->portnum);
 268         else
 269                 val = val & ~(1 << adapter->portnum);
 270         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 271
 272         if (lock)
 273                 qlcnic_83xx_unlock_driver(adapter);
 274
 275         return 0;
 276 }
 277
 278 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 279                                          int time_limit)
 280 {
 281         u64 seconds;
 282
 283         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 284         if (seconds <= time_limit)
 285                 return 0;
 286         else
 287                 return -EBUSY;
 288 }
 289
 290 /**
 291  * qlcnic_83xx_idc_check_reset_ack_reg
 292  *
 293  * @adapter: adapter structure
 294  *
 295  * Check ACK wait limit and clear the functions which failed to ACK
 296  *
 297  * Return 0 if all functions have acknowledged the reset request.
 298  **/
 299 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 300 {
 301         int timeout;
 302         u32 ack, presence, val;
 303
 304         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 305         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 306         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 307         dev_info(&adapter->pdev->dev,
 308                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 309         if (!((ack & presence) == presence)) {
 310                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 311                         /* Clear functions which failed to ACK */
 312                         dev_info(&adapter->pdev->dev,
 313                                  "%s: ACK wait exceeds time limit\n", __func__);
 314                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 315                         val = val & ~(ack ^ presence);
 316                         if (qlcnic_83xx_lock_driver(adapter))
 317                                 return -EBUSY;
 318                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 319                         dev_info(&adapter->pdev->dev,
 320                                  "%s: updated drv presence reg = 0x%x\n",
 321                                  __func__, val);
 322                         qlcnic_83xx_unlock_driver(adapter);
 323                         return 0;
 324
 325                 } else {
 326                         return 1;
 327                 }
 328         } else {
 329                 dev_info(&adapter->pdev->dev,
 330                          "%s: Reset ACK received from all functions\n",
 331                          __func__);
 332                 return 0;
 333         }
 334 }
 335
 336 /**
 337  * qlcnic_83xx_idc_tx_soft_reset
 338  *
 339  * @adapter: adapter structure
 340  *
 341  * Handle context deletion and recreation request from transmit routine
 342  *
 343  * Returns -EBUSY  or Success (0)
 344  *
 345  **/
 346 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 347 {
 348         struct net_device *netdev = adapter->netdev;
 349
 350         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 351                 return -EBUSY;
 352
 353         netif_device_detach(netdev);
 354         qlcnic_down(adapter, netdev);
 355         qlcnic_up(adapter, netdev);
 356         netif_device_attach(netdev);
 357         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 358         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 359
 360         adapter->netdev->trans_start = jiffies;
 361
 362         return 0;
 363 }
 364
 365 /**
 366  * qlcnic_83xx_idc_detach_driver
 367  *
 368  * @adapter: adapter structure
 369  * Detach net interface, stop TX and cleanup resources before the HW reset.
 370  * Returns: None
 371  *
 372  **/
 373 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 374 {
 375         int i;
 376         struct net_device *netdev = adapter->netdev;
 377
 378         netif_device_detach(netdev);
 379         /* Disable mailbox interrupt */
 380         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 381         qlcnic_down(adapter, netdev);
 382         for (i = 0; i < adapter->ahw->num_msix; i++) {
 383                 adapter->ahw->intr_tbl[i].id = i;
 384                 adapter->ahw->intr_tbl[i].enabled = 0;
 385                 adapter->ahw->intr_tbl[i].src = 0;
 386         }
 387 }
 388
 389 /**
 390  * qlcnic_83xx_idc_attach_driver
 391  *
 392  * @adapter: adapter structure
 393  *
 394  * Re-attach and re-enable net interface
 395  * Returns: None
 396  *
 397  **/
 398 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 399 {
 400         struct net_device *netdev = adapter->netdev;
 401
 402         if (netif_running(netdev)) {
 403                 if (qlcnic_up(adapter, netdev))
 404                         goto done;
 405                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 406         }
 407 done:
 408         netif_device_attach(netdev);
 409         if (netif_running(netdev)) {
 410                 netif_carrier_on(netdev);
 411                 netif_wake_queue(netdev);
 412         }
 413 }
 414
 415 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 416                                               int lock)
 417 {
 418         if (lock) {
 419                 if (qlcnic_83xx_lock_driver(adapter))
 420                         return -EBUSY;
 421         }
 422
 423         qlcnic_83xx_idc_clear_registers(adapter, 0);
 424         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 425         if (lock)
 426                 qlcnic_83xx_unlock_driver(adapter);
 427
 428         qlcnic_83xx_idc_log_state_history(adapter);
 429         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 430
 431         return 0;
 432 }
 433
 434 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 435                                             int lock)
 436 {
 437         if (lock) {
 438                 if (qlcnic_83xx_lock_driver(adapter))
 439                         return -EBUSY;
 440         }
 441
 442         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 443
 444         if (lock)
 445                 qlcnic_83xx_unlock_driver(adapter);
 446
 447         return 0;
 448 }
 449
 450 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 451                                               int lock)
 452 {
 453         if (lock) {
 454                 if (qlcnic_83xx_lock_driver(adapter))
 455                         return -EBUSY;
 456         }
 457
 458         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 459                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 460
 461         if (lock)
 462                 qlcnic_83xx_unlock_driver(adapter);
 463
 464         return 0;
 465 }
 466
 467 static int
 468 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 469 {
 470         if (lock) {
 471                 if (qlcnic_83xx_lock_driver(adapter))
 472                         return -EBUSY;
 473         }
 474
 475         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 476                QLC_83XX_IDC_DEV_NEED_RESET);
 477
 478         if (lock)
 479                 qlcnic_83xx_unlock_driver(adapter);
 480
 481         return 0;
 482 }
 483
 484 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 485                                              int lock)
 486 {
 487         if (lock) {
 488                 if (qlcnic_83xx_lock_driver(adapter))
 489                         return -EBUSY;
 490         }
 491
 492         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 493         if (lock)
 494                 qlcnic_83xx_unlock_driver(adapter);
 495
 496         return 0;
 497 }
 498
 499 /**
 500  * qlcnic_83xx_idc_find_reset_owner_id
 501  *
 502  * @adapter: adapter structure
 503  *
 504  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 505  * Within the same class, function with lowest PCI ID assumes ownership
 506  *
 507  * Returns: reset owner id or failure indication (-EIO)
 508  *
 509  **/
 510 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 511 {
 512         u32 reg, reg1, reg2, i, j, owner, class;
 513
 514         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 515         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 516         owner = QLCNIC_TYPE_NIC;
 517         i = 0;
 518         j = 0;
 519         reg = reg1;
 520
 521         do {
 522                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 523                 if (class == owner)
 524                         break;
 525                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 526                         reg = reg2;
 527                         j = 0;
 528                 } else {
 529                         j++;
 530                 }
 531
 532                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 533                         if (owner == QLCNIC_TYPE_NIC)
 534                                 owner = QLCNIC_TYPE_ISCSI;
 535                         else if (owner == QLCNIC_TYPE_ISCSI)
 536                                 owner = QLCNIC_TYPE_FCOE;
 537                         else if (owner == QLCNIC_TYPE_FCOE)
 538                                 return -EIO;
 539                         reg = reg1;
 540                         j = 0;
 541                         i = 0;
 542                 }
 543         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 544
 545         return i;
 546 }
 547
 548 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 549 {
 550         int ret = 0;
 551
 552         ret = qlcnic_83xx_restart_hw(adapter);
 553
 554         if (ret) {
 555                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 556         } else {
 557                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 558                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 559         }
 560
 561         return ret;
 562 }
 563
 564 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 565 {
 566         u32 status;
 567
 568         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 569
 570         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 571                 dev_err(&adapter->pdev->dev,
 572                         "peg halt status1=0x%x\n", status);
 573                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 574                         dev_err(&adapter->pdev->dev,
 575                                 "On board active cooling fan failed. "
 576                                 "Device has been halted.\n");
 577                         dev_err(&adapter->pdev->dev,
 578                                 "Replace the adapter.\n");
 579                         return -EIO;
 580                 }
 581         }
 582
 583         return 0;
 584 }
 585
 586 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 587 {
 588         /* register for NIC IDC AEN Events */
 589         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 590
 591         qlcnic_83xx_enable_mbx_intrpt(adapter);
 592         if ((adapter->flags & QLCNIC_MSIX_ENABLED)) {
 593                 if (qlcnic_83xx_config_intrpt(adapter, 1)) {
 594                         netdev_err(adapter->netdev,
 595                                    "Failed to enable mbx intr\n");
 596                         return -EIO;
 597                 }
 598         }
 599
 600         if (qlcnic_83xx_configure_opmode(adapter)) {
 601                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 602                 return -EIO;
 603         }
 604
 605         if (adapter->nic_ops->init_driver(adapter)) {
 606                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 607                 return -EIO;
 608         }
 609
 610         qlcnic_83xx_idc_attach_driver(adapter);
 611
 612         return 0;
 613 }
 614
 615 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 616 {
 617         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 618         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 619         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 620         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 621         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 622         adapter->ahw->idc.quiesce_req = 0;
 623         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 624         adapter->ahw->idc.err_code = 0;
 625         adapter->ahw->idc.collect_dump = 0;
 626 }
 627
 628 /**
 629  * qlcnic_83xx_idc_ready_state_entry
 630  *
 631  * @adapter: adapter structure
 632  *
 633  * Perform ready state initialization, this routine will get invoked only
 634  * once from READY state.
 635  *
 636  * Returns: Error code or Success(0)
 637  *
 638  **/
 639 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 640 {
 641         struct qlcnic_hardware_context *ahw = adapter->ahw;
 642
 643         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 644                 qlcnic_83xx_idc_update_idc_params(adapter);
 645                 /* Re-attach the device if required */
 646                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 647                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 648                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 649                                 return -EIO;
 650                 }
 651         }
 652
 653         return 0;
 654 }
 655
 656 /**
 657  * qlcnic_83xx_idc_vnic_pf_entry
 658  *
 659  * @adapter: adapter structure
 660  *
 661  * Ensure vNIC mode privileged function starts only after vNIC mode is
 662  * enabled by management function.
 663  * If vNIC mode is ready, start initialization.
 664  *
 665  * Returns: -EIO or 0
 666  *
 667  **/
 668 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 669 {
 670         u32 state;
 671         struct qlcnic_hardware_context *ahw = adapter->ahw;
 672
 673         /* Privileged function waits till mgmt function enables VNIC mode */
 674         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 675         if (state != QLCNIC_DEV_NPAR_OPER) {
 676                 if (!ahw->idc.vnic_wait_limit--) {
 677                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 678                         return -EIO;
 679                 }
 680                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 681                 return -EIO;
 682
 683         } else {
 684                 /* Perform one time initialization from ready state */
 685                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 686                         qlcnic_83xx_idc_update_idc_params(adapter);
 687
 688                         /* If the previous state is UNKNOWN, device will be
 689                            already attached properly by Init routine*/
 690                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 691                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 692                                         return -EIO;
 693                         }
 694                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 695                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 696                 }
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 703 {
 704         adapter->ahw->idc.err_code = -EIO;
 705         dev_err(&adapter->pdev->dev,
 706                 "%s: Device in unknown state\n", __func__);
 707         return 0;
 708 }
 709
 710 /**
 711  * qlcnic_83xx_idc_cold_state
 712  *
 713  * @adapter: adapter structure
 714  *
 715  * If HW is up and running device will enter READY state.
 716  * If firmware image from host needs to be loaded, device is
 717  * forced to start with the file firmware image.
 718  *
 719  * Returns: Error code or Success(0)
 720  *
 721  **/
 722 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 723 {
 724         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 725         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 726
 727         if (qlcnic_load_fw_file) {
 728                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 729         } else {
 730                 if (qlcnic_83xx_check_hw_status(adapter)) {
 731                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 732                         return -EIO;
 733                 } else {
 734                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 735                 }
 736         }
 737         return 0;
 738 }
 739
 740 /**
 741  * qlcnic_83xx_idc_init_state
 742  *
 743  * @adapter: adapter structure
 744  *
 745  * Reset owner will restart the device from this state.
 746  * Device will enter failed state if it remains
 747  * in this state for more than DEV_INIT time limit.
 748  *
 749  * Returns: Error code or Success(0)
 750  *
 751  **/
 752 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 753 {
 754         int timeout, ret = 0;
 755         u32 owner;
 756
 757         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 758         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 759                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 760                 if (adapter->ahw->pci_func == owner)
 761                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 762         } else {
 763                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 764                 return ret;
 765         }
 766
 767         return ret;
 768 }
 769
 770 /**
 771  * qlcnic_83xx_idc_ready_state
 772  *
 773  * @adapter: adapter structure
 774  *
 775  * Perform IDC protocol specicifed actions after monitoring device state and
 776  * events.
 777  *
 778  * Returns: Error code or Success(0)
 779  *
 780  **/
 781 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 782 {
 783         u32 val;
 784         struct qlcnic_hardware_context *ahw = adapter->ahw;
 785         int ret = 0;
 786
 787         /* Perform NIC configuration based ready state entry actions */
 788         if (ahw->idc.state_entry(adapter))
 789                 return -EIO;
 790
 791         if (qlcnic_check_temp(adapter)) {
 792                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 793                         qlcnic_83xx_idc_check_fan_failure(adapter);
 794                         dev_err(&adapter->pdev->dev,
 795                                 "Error: device temperature %d above limits\n",
 796                                 adapter->ahw->temp);
 797                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 798                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 799                         qlcnic_83xx_idc_detach_driver(adapter);
 800                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 801                         return -EIO;
 802                 }
 803         }
 804
 805         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 806         ret = qlcnic_83xx_check_heartbeat(adapter);
 807         if (ret) {
 808                 adapter->flags |= QLCNIC_FW_HANG;
 809                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 810                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 811                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 812                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 813                 }
 814                 return -EIO;
 815         }
 816
 817         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 818                 /* Move to need reset state and prepare for reset */
 819                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 820                 return ret;
 821         }
 822
 823         /* Check for soft reset request */
 824         if (ahw->reset_context &&
 825             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 826                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 827                 return ret;
 828         }
 829
 830         /* Move to need quiesce state if requested */
 831         if (adapter->ahw->idc.quiesce_req) {
 832                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 833                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 834                 return ret;
 835         }
 836
 837         return ret;
 838 }
 839
 840 /**
 841  * qlcnic_83xx_idc_need_reset_state
 842  *
 843  * @adapter: adapter structure
 844  *
 845  * Device will remain in this state until:
 846  *      Reset request ACK's are recieved from all the functions
 847  *      Wait time exceeds max time limit
 848  *
 849  * Returns: Error code or Success(0)
 850  *
 851  **/
 852 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 853 {
 854         int ret = 0;
 855
 856         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 857                 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 858                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 859                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 860                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 861                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 862                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 863                 qlcnic_83xx_idc_detach_driver(adapter);
 864         }
 865
 866         /* Check ACK from other functions */
 867         ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 868         if (ret) {
 869                 dev_info(&adapter->pdev->dev,
 870                          "%s: Waiting for reset ACK\n", __func__);
 871                 return 0;
 872         }
 873
 874         /* Transit to INIT state and restart the HW */
 875         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 876
 877         return ret;
 878 }
 879
 880 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 881 {
 882         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 883         return 0;
 884 }
 885
 886 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 887 {
 888         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 889         adapter->ahw->idc.err_code = -EIO;
 890
 891         return 0;
 892 }
 893
 894 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 895 {
 896         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 897         return 0;
 898 }
 899
 900 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 901                                                 u32 state)
 902 {
 903         u32 cur, prev, next;
 904
 905         cur = adapter->ahw->idc.curr_state;
 906         prev = adapter->ahw->idc.prev_state;
 907         next = state;
 908
 909         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 910             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 911                 dev_err(&adapter->pdev->dev,
 912                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 913                         __func__, cur, prev, state);
 914                 return 1;
 915         }
 916
 917         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 918             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 919                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 920                     (next != QLC_83XX_IDC_DEV_READY)) {
 921                         dev_err(&adapter->pdev->dev,
 922                                 "%s: failed, cur %d prev %d next %d\n",
 923                                 __func__, cur, prev, next);
 924                         return 1;
 925                 }
 926         }
 927
 928         if (next == QLC_83XX_IDC_DEV_INIT) {
 929                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 930                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 931                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 932                         dev_err(&adapter->pdev->dev,
 933                                 "%s: failed, cur %d prev %d next %d\n",
 934                                 __func__, cur, prev, next);
 935                         return 1;
 936                 }
 937         }
 938
 939         return 0;
 940 }
 941
 942 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 943 {
 944         if (adapter->fhash.fnum)
 945                 qlcnic_prune_lb_filters(adapter);
 946 }
 947
 948 /**
 949  * qlcnic_83xx_idc_poll_dev_state
 950  *
 951  * @work: kernel work queue structure used to schedule the function
 952  *
 953  * Poll device state periodically and perform state specific
 954  * actions defined by Inter Driver Communication (IDC) protocol.
 955  *
 956  * Returns: None
 957  *
 958  **/
 959 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
 960 {
 961         struct qlcnic_adapter *adapter;
 962         u32 state;
 963
 964         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
 965         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 966
 967         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
 968                 qlcnic_83xx_idc_log_state_history(adapter);
 969                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
 970         } else {
 971                 adapter->ahw->idc.curr_state = state;
 972         }
 973
 974         switch (adapter->ahw->idc.curr_state) {
 975         case QLC_83XX_IDC_DEV_READY:
 976                 qlcnic_83xx_idc_ready_state(adapter);
 977                 break;
 978         case QLC_83XX_IDC_DEV_NEED_RESET:
 979                 qlcnic_83xx_idc_need_reset_state(adapter);
 980                 break;
 981         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
 982                 qlcnic_83xx_idc_need_quiesce_state(adapter);
 983                 break;
 984         case QLC_83XX_IDC_DEV_FAILED:
 985                 qlcnic_83xx_idc_failed_state(adapter);
 986                 return;
 987         case QLC_83XX_IDC_DEV_INIT:
 988                 qlcnic_83xx_idc_init_state(adapter);
 989                 break;
 990         case QLC_83XX_IDC_DEV_QUISCENT:
 991                 qlcnic_83xx_idc_quiesce_state(adapter);
 992                 break;
 993         default:
 994                 qlcnic_83xx_idc_unknown_state(adapter);
 995                 return;
 996         }
 997         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
 998         qlcnic_83xx_periodic_tasks(adapter);
 999
1000         /* Re-schedule the function */
1001         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1002                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1003                                      adapter->ahw->idc.delay);
1004 }
1005
1006 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1007 {
1008         u32 idc_params, val;
1009
1010         if (qlcnic_83xx_lockless_flash_read32(adapter,
1011                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1012                                               (u8 *)&idc_params, 1)) {
1013                 dev_info(&adapter->pdev->dev,
1014                          "%s:failed to get IDC params from flash\n", __func__);
1015                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1016                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1017         } else {
1018                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1019                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1020         }
1021
1022         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1023         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1024         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1025         adapter->ahw->idc.err_code = 0;
1026         adapter->ahw->idc.collect_dump = 0;
1027         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1028
1029         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1030         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1031         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1032
1033         /* Check if reset recovery is disabled */
1034         if (!qlcnic_auto_fw_reset) {
1035                 /* Propagate do not reset request to other functions */
1036                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1037                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1038                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1039         }
1040 }
1041
1042 static int
1043 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1044 {
1045         u32 state, val;
1046
1047         if (qlcnic_83xx_lock_driver(adapter))
1048                 return -EIO;
1049
1050         /* Clear driver lock register */
1051         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1052         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1053                 qlcnic_83xx_unlock_driver(adapter);
1054                 return -EIO;
1055         }
1056
1057         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1058         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1059                 qlcnic_83xx_unlock_driver(adapter);
1060                 return -EIO;
1061         }
1062
1063         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1064                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1065                        QLC_83XX_IDC_DEV_COLD);
1066                 state = QLC_83XX_IDC_DEV_COLD;
1067         }
1068
1069         adapter->ahw->idc.curr_state = state;
1070         /* First to load function should cold boot the device */
1071         if (state == QLC_83XX_IDC_DEV_COLD)
1072                 qlcnic_83xx_idc_cold_state_handler(adapter);
1073
1074         /* Check if reset recovery is enabled */
1075         if (qlcnic_auto_fw_reset) {
1076                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1077                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1078                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1079         }
1080
1081         qlcnic_83xx_unlock_driver(adapter);
1082
1083         return 0;
1084 }
1085
1086 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1087 {
1088         int ret = -EIO;
1089
1090         qlcnic_83xx_setup_idc_parameters(adapter);
1091
1092         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1093                 return ret;
1094
1095         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1096                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1097                         return -EIO;
1098         } else {
1099                 if (qlcnic_83xx_idc_check_major_version(adapter))
1100                         return -EIO;
1101         }
1102
1103         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1104
1105         return 0;
1106 }
1107
1108 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1109 {
1110         int id;
1111         u32 val;
1112
1113         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1114                 usleep_range(10000, 11000);
1115
1116         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1117         id = id & 0xFF;
1118
1119         if (id == adapter->portnum) {
1120                 dev_err(&adapter->pdev->dev,
1121                         "%s: wait for lock recovery.. %d\n", __func__, id);
1122                 msleep(20);
1123                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1124                 id = id & 0xFF;
1125         }
1126
1127         /* Clear driver presence bit */
1128         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1129         val = val & ~(1 << adapter->portnum);
1130         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1131         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1132         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1133
1134         cancel_delayed_work_sync(&adapter->fw_work);
1135 }
1136
1137 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1138 {
1139         u32 val;
1140
1141         if (qlcnic_83xx_lock_driver(adapter)) {
1142                 dev_err(&adapter->pdev->dev,
1143                         "%s:failed, please retry\n", __func__);
1144                 return;
1145         }
1146
1147         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1148         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1149             !qlcnic_auto_fw_reset) {
1150                 dev_err(&adapter->pdev->dev,
1151                         "%s:failed, device in non reset mode\n", __func__);
1152                 qlcnic_83xx_unlock_driver(adapter);
1153                 return;
1154         }
1155
1156         if (key == QLCNIC_FORCE_FW_RESET) {
1157                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1158                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1159                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1160         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1161                 adapter->ahw->idc.collect_dump = 1;
1162         }
1163
1164         qlcnic_83xx_unlock_driver(adapter);
1165         return;
1166 }
1167
1168 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1169 {
1170         u8 *p_cache;
1171         u32 src, size;
1172         u64 dest;
1173         int ret = -EIO;
1174
1175         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1176         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1177         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1178
1179         /* alignment check */
1180         if (size & 0xF)
1181                 size = (size + 16) & ~0xF;
1182
1183         p_cache = kzalloc(size, GFP_KERNEL);
1184         if (p_cache == NULL)
1185                 return -ENOMEM;
1186
1187         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1188                                                 size / sizeof(u32));
1189         if (ret) {
1190                 kfree(p_cache);
1191                 return ret;
1192         }
1193         /* 16 byte write to MS memory */
1194         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1195                                           size / 16);
1196         if (ret) {
1197                 kfree(p_cache);
1198                 return ret;
1199         }
1200         kfree(p_cache);
1201
1202         return ret;
1203 }
1204
1205 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1206 {
1207         u32 dest, *p_cache;
1208         u64 addr;
1209         u8 data[16];
1210         size_t size;
1211         int i, ret = -EIO;
1212
1213         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1214         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1215         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1216         addr = (u64)dest;
1217
1218         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1219                                           (u32 *)p_cache, size / 16);
1220         if (ret) {
1221                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1222                 release_firmware(adapter->ahw->fw_info.fw);
1223                 adapter->ahw->fw_info.fw = NULL;
1224                 return -EIO;
1225         }
1226
1227         /* alignment check */
1228         if (adapter->ahw->fw_info.fw->size & 0xF) {
1229                 addr = dest + size;
1230                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1231                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1232                 for (; i < 16; i++)
1233                         data[i] = 0;
1234                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1235                                                   (u32 *)data, 1);
1236                 if (ret) {
1237                         dev_err(&adapter->pdev->dev,
1238                                 "MS memory write failed\n");
1239                         release_firmware(adapter->ahw->fw_info.fw);
1240                         adapter->ahw->fw_info.fw = NULL;
1241                         return -EIO;
1242                 }
1243         }
1244         release_firmware(adapter->ahw->fw_info.fw);
1245         adapter->ahw->fw_info.fw = NULL;
1246
1247         return 0;
1248 }
1249
1250 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1251 {
1252         int i, j;
1253         u32 val = 0, val1 = 0, reg = 0;
1254
1255         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1256         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1257
1258         for (j = 0; j < 2; j++) {
1259                 if (j == 0) {
1260                         dev_info(&adapter->pdev->dev,
1261                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1262                         reg = QLC_83XX_PORT0_THRESHOLD;
1263                 } else if (j == 1) {
1264                         dev_info(&adapter->pdev->dev,
1265                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1266                         reg = QLC_83XX_PORT1_THRESHOLD;
1267                 }
1268                 for (i = 0; i < 8; i++) {
1269                         val = QLCRD32(adapter, reg + (i * 0x4));
1270                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1271                 }
1272                 dev_info(&adapter->pdev->dev, "\n");
1273         }
1274
1275         for (j = 0; j < 2; j++) {
1276                 if (j == 0) {
1277                         dev_info(&adapter->pdev->dev,
1278                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1279                         reg = QLC_83XX_PORT0_TC_MC_REG;
1280                 } else if (j == 1) {
1281                         dev_info(&adapter->pdev->dev,
1282                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1283                         reg = QLC_83XX_PORT1_TC_MC_REG;
1284                 }
1285                 for (i = 0; i < 4; i++) {
1286                         val = QLCRD32(adapter, reg + (i * 0x4));
1287                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1288                 }
1289                 dev_info(&adapter->pdev->dev, "\n");
1290         }
1291
1292         for (j = 0; j < 2; j++) {
1293                 if (j == 0) {
1294                         dev_info(&adapter->pdev->dev,
1295                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1296                         reg = QLC_83XX_PORT0_TC_STATS;
1297                 } else if (j == 1) {
1298                         dev_info(&adapter->pdev->dev,
1299                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1300                         reg = QLC_83XX_PORT1_TC_STATS;
1301                 }
1302                 for (i = 7; i >= 0; i--) {
1303                         val = QLCRD32(adapter, reg);
1304                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1305                         QLCWR32(adapter, reg, (val | (i << 29)));
1306                         val = QLCRD32(adapter, reg);
1307                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1308                 }
1309                 dev_info(&adapter->pdev->dev, "\n");
1310         }
1311
1312         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1313         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1314         dev_info(&adapter->pdev->dev,
1315                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1316                  val, val1);
1317 }
1318
1319
1320 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1321 {
1322         u32 reg = 0, i, j;
1323
1324         if (qlcnic_83xx_lock_driver(adapter)) {
1325                 dev_err(&adapter->pdev->dev,
1326                         "%s:failed to acquire driver lock\n", __func__);
1327                 return;
1328         }
1329
1330         qlcnic_83xx_dump_pause_control_regs(adapter);
1331         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1332
1333         for (j = 0; j < 2; j++) {
1334                 if (j == 0)
1335                         reg = QLC_83XX_PORT0_THRESHOLD;
1336                 else if (j == 1)
1337                         reg = QLC_83XX_PORT1_THRESHOLD;
1338
1339                 for (i = 0; i < 8; i++)
1340                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1341         }
1342
1343         for (j = 0; j < 2; j++) {
1344                 if (j == 0)
1345                         reg = QLC_83XX_PORT0_TC_MC_REG;
1346                 else if (j == 1)
1347                         reg = QLC_83XX_PORT1_TC_MC_REG;
1348
1349                 for (i = 0; i < 4; i++)
1350                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1351         }
1352
1353         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1354         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1355         dev_info(&adapter->pdev->dev,
1356                  "Disabled pause frames successfully on all ports\n");
1357         qlcnic_83xx_unlock_driver(adapter);
1358 }
1359
1360 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1361 {
1362         u32 heartbeat, peg_status;
1363         int retries, ret = -EIO;
1364
1365         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1366         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1367                                                QLCNIC_PEG_ALIVE_COUNTER);
1368
1369         do {
1370                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1371                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1372                                                 QLCNIC_PEG_ALIVE_COUNTER);
1373                 if (heartbeat != p_dev->heartbeat) {
1374                         ret = QLCNIC_RCODE_SUCCESS;
1375                         break;
1376                 }
1377         } while (--retries);
1378
1379         if (ret) {
1380                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1381                 qlcnic_83xx_disable_pause_frames(p_dev);
1382                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1383                                                  QLCNIC_PEG_HALT_STATUS1);
1384                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1385                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1386                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1387                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1388                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1389                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1390                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1391                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1392                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1393                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1394                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1395
1396                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1397                         dev_err(&p_dev->pdev->dev,
1398                                 "Device is being reset err code 0x00006700.\n");
1399         }
1400
1401         return ret;
1402 }
1403
1404 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1405 {
1406         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1407         u32 val;
1408
1409         do {
1410                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1411                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1412                         return 0;
1413                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1414         } while (--retries);
1415
1416         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1417         return -EIO;
1418 }
1419
1420 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1421 {
1422         int err;
1423
1424         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1425         if (err)
1426                 return err;
1427
1428         err = qlcnic_83xx_check_heartbeat(p_dev);
1429         if (err)
1430                 return err;
1431
1432         return err;
1433 }
1434
1435 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1436                                 int duration, u32 mask, u32 status)
1437 {
1438         u32 value;
1439         int timeout_error;
1440         u8 retries;
1441
1442         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1443         retries = duration / 10;
1444
1445         do {
1446                 if ((value & mask) != status) {
1447                         timeout_error = 1;
1448                         msleep(duration / 10);
1449                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1450                 } else {
1451                         timeout_error = 0;
1452                         break;
1453                 }
1454         } while (retries--);
1455
1456         if (timeout_error) {
1457                 p_dev->ahw->reset.seq_error++;
1458                 dev_err(&p_dev->pdev->dev,
1459                         "%s: Timeout Err, entry_num = %d\n",
1460                         __func__, p_dev->ahw->reset.seq_index);
1461                 dev_err(&p_dev->pdev->dev,
1462                         "0x%08x 0x%08x 0x%08x\n",
1463                         value, mask, status);
1464         }
1465
1466         return timeout_error;
1467 }
1468
1469 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1470 {
1471         u32 sum = 0;
1472         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1473         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1474
1475         while (count-- > 0)
1476                 sum += *buff++;
1477
1478         while (sum >> 16)
1479                 sum = (sum & 0xFFFF) + (sum >> 16);
1480
1481         if (~sum) {
1482                 return 0;
1483         } else {
1484                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1485                 return -1;
1486         }
1487 }
1488
1489 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1490 {
1491         u8 *p_buff;
1492         u32 addr, count;
1493         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1494
1495         ahw->reset.seq_error = 0;
1496         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1497         if (p_dev->ahw->reset.buff == NULL)
1498                 return -ENOMEM;
1499
1500         p_buff = p_dev->ahw->reset.buff;
1501         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1502         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1503
1504         /* Copy template header from flash */
1505         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1506                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1507                 return -EIO;
1508         }
1509         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1510         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1511         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1512         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1513
1514         /* Copy rest of the template */
1515         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1516                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1517                 return -EIO;
1518         }
1519
1520         if (qlcnic_83xx_reset_template_checksum(p_dev))
1521                 return -EIO;
1522         /* Get Stop, Start and Init command offsets */
1523         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1524         ahw->reset.start_offset = ahw->reset.buff +
1525                                   ahw->reset.hdr->start_offset;
1526         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1527         return 0;
1528 }
1529
1530 /* Read Write HW register command */
1531 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1532                                            u32 raddr, u32 waddr)
1533 {
1534         int value;
1535
1536         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1537         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1538 }
1539
1540 /* Read Modify Write HW register command */
1541 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1542                                     u32 raddr, u32 waddr,
1543                                     struct qlc_83xx_rmw *p_rmw_hdr)
1544 {
1545         int value;
1546
1547         if (p_rmw_hdr->index_a)
1548                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1549         else
1550                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1551
1552         value &= p_rmw_hdr->mask;
1553         value <<= p_rmw_hdr->shl;
1554         value >>= p_rmw_hdr->shr;
1555         value |= p_rmw_hdr->or_value;
1556         value ^= p_rmw_hdr->xor_value;
1557         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1558 }
1559
1560 /* Write HW register command */
1561 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1562                                    struct qlc_83xx_entry_hdr *p_hdr)
1563 {
1564         int i;
1565         struct qlc_83xx_entry *entry;
1566
1567         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1568                                           sizeof(struct qlc_83xx_entry_hdr));
1569
1570         for (i = 0; i < p_hdr->count; i++, entry++) {
1571                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1572                                              entry->arg2);
1573                 if (p_hdr->delay)
1574                         udelay((u32)(p_hdr->delay));
1575         }
1576 }
1577
1578 /* Read and Write instruction */
1579 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1580                                         struct qlc_83xx_entry_hdr *p_hdr)
1581 {
1582         int i;
1583         struct qlc_83xx_entry *entry;
1584
1585         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1586                                           sizeof(struct qlc_83xx_entry_hdr));
1587
1588         for (i = 0; i < p_hdr->count; i++, entry++) {
1589                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1590                                                entry->arg2);
1591                 if (p_hdr->delay)
1592                         udelay((u32)(p_hdr->delay));
1593         }
1594 }
1595
1596 /* Poll HW register command */
1597 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1598                                   struct qlc_83xx_entry_hdr *p_hdr)
1599 {
1600         long delay;
1601         struct qlc_83xx_entry *entry;
1602         struct qlc_83xx_poll *poll;
1603         int i;
1604         unsigned long arg1, arg2;
1605
1606         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1607                                         sizeof(struct qlc_83xx_entry_hdr));
1608
1609         entry = (struct qlc_83xx_entry *)((char *)poll +
1610                                           sizeof(struct qlc_83xx_poll));
1611         delay = (long)p_hdr->delay;
1612
1613         if (!delay) {
1614                 for (i = 0; i < p_hdr->count; i++, entry++)
1615                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1616                                              delay, poll->mask,
1617                                              poll->status);
1618         } else {
1619                 for (i = 0; i < p_hdr->count; i++, entry++) {
1620                         arg1 = entry->arg1;
1621                         arg2 = entry->arg2;
1622                         if (delay) {
1623                                 if (qlcnic_83xx_poll_reg(p_dev,
1624                                                          arg1, delay,
1625                                                          poll->mask,
1626                                                          poll->status)){
1627                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1628                                                                     arg1);
1629                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1630                                                                     arg2);
1631                                 }
1632                         }
1633                 }
1634         }
1635 }
1636
1637 /* Poll and write HW register command */
1638 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1639                                         struct qlc_83xx_entry_hdr *p_hdr)
1640 {
1641         int i;
1642         long delay;
1643         struct qlc_83xx_quad_entry *entry;
1644         struct qlc_83xx_poll *poll;
1645
1646         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1647                                         sizeof(struct qlc_83xx_entry_hdr));
1648         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1649                                                sizeof(struct qlc_83xx_poll));
1650         delay = (long)p_hdr->delay;
1651
1652         for (i = 0; i < p_hdr->count; i++, entry++) {
1653                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1654                                              entry->dr_value);
1655                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1656                                              entry->ar_value);
1657                 if (delay)
1658                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1659                                              poll->mask, poll->status);
1660         }
1661 }
1662
1663 /* Read Modify Write register command */
1664 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1665                                           struct qlc_83xx_entry_hdr *p_hdr)
1666 {
1667         int i;
1668         struct qlc_83xx_entry *entry;
1669         struct qlc_83xx_rmw *rmw_hdr;
1670
1671         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1672                                           sizeof(struct qlc_83xx_entry_hdr));
1673
1674         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1675                                           sizeof(struct qlc_83xx_rmw));
1676
1677         for (i = 0; i < p_hdr->count; i++, entry++) {
1678                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1679                                         entry->arg2, rmw_hdr);
1680                 if (p_hdr->delay)
1681                         udelay((u32)(p_hdr->delay));
1682         }
1683 }
1684
1685 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1686 {
1687         if (p_hdr->delay)
1688                 mdelay((u32)((long)p_hdr->delay));
1689 }
1690
1691 /* Read and poll register command */
1692 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1693                                        struct qlc_83xx_entry_hdr *p_hdr)
1694 {
1695         long delay;
1696         int index, i, j;
1697         struct qlc_83xx_quad_entry *entry;
1698         struct qlc_83xx_poll *poll;
1699         unsigned long addr;
1700
1701         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1702                                         sizeof(struct qlc_83xx_entry_hdr));
1703
1704         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1705                                                sizeof(struct qlc_83xx_poll));
1706         delay = (long)p_hdr->delay;
1707
1708         for (i = 0; i < p_hdr->count; i++, entry++) {
1709                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1710                                              entry->ar_value);
1711                 if (delay) {
1712                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1713                                                   poll->mask, poll->status)){
1714                                 index = p_dev->ahw->reset.array_index;
1715                                 addr = entry->dr_addr;
1716                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1717                                 p_dev->ahw->reset.array[index++] = j;
1718
1719                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1720                                         p_dev->ahw->reset.array_index = 1;
1721                         }
1722                 }
1723         }
1724 }
1725
1726 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1727 {
1728         p_dev->ahw->reset.seq_end = 1;
1729 }
1730
1731 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1732 {
1733         p_dev->ahw->reset.template_end = 1;
1734         if (p_dev->ahw->reset.seq_error == 0)
1735                 dev_err(&p_dev->pdev->dev,
1736                         "HW restart process completed successfully.\n");
1737         else
1738                 dev_err(&p_dev->pdev->dev,
1739                         "HW restart completed with timeout errors.\n");
1740 }
1741
1742 /**
1743 * qlcnic_83xx_exec_template_cmd
1744 *
1745 * @p_dev: adapter structure
1746 * @p_buff: Poiter to instruction template
1747 *
1748 * Template provides instructions to stop, restart and initalize firmware.
1749 * These instructions are abstracted as a series of read, write and
1750 * poll operations on hardware registers. Register information and operation
1751 * specifics are not exposed to the driver. Driver reads the template from
1752 * flash and executes the instructions located at pre-defined offsets.
1753 *
1754 * Returns: None
1755 * */
1756 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1757                                           char *p_buff)
1758 {
1759         int index, entries;
1760         struct qlc_83xx_entry_hdr *p_hdr;
1761         char *entry = p_buff;
1762
1763         p_dev->ahw->reset.seq_end = 0;
1764         p_dev->ahw->reset.template_end = 0;
1765         entries = p_dev->ahw->reset.hdr->entries;
1766         index = p_dev->ahw->reset.seq_index;
1767
1768         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1769                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1770
1771                 switch (p_hdr->cmd) {
1772                 case QLC_83XX_OPCODE_NOP:
1773                         break;
1774                 case QLC_83XX_OPCODE_WRITE_LIST:
1775                         qlcnic_83xx_write_list(p_dev, p_hdr);
1776                         break;
1777                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1778                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1779                         break;
1780                 case QLC_83XX_OPCODE_POLL_LIST:
1781                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1782                         break;
1783                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1784                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1785                         break;
1786                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1787                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1788                         break;
1789                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1790                         qlcnic_83xx_pause(p_hdr);
1791                         break;
1792                 case QLC_83XX_OPCODE_SEQ_END:
1793                         qlcnic_83xx_seq_end(p_dev);
1794                         break;
1795                 case QLC_83XX_OPCODE_TMPL_END:
1796                         qlcnic_83xx_template_end(p_dev);
1797                         break;
1798                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1799                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1800                         break;
1801                 default:
1802                         dev_err(&p_dev->pdev->dev,
1803                                 "%s: Unknown opcode 0x%04x in template %d\n",
1804                                 __func__, p_hdr->cmd, index);
1805                         break;
1806                 }
1807                 entry += p_hdr->size;
1808         }
1809         p_dev->ahw->reset.seq_index = index;
1810 }
1811
1812 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1813 {
1814         p_dev->ahw->reset.seq_index = 0;
1815
1816         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1817         if (p_dev->ahw->reset.seq_end != 1)
1818                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1819 }
1820
1821 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1822 {
1823         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1824         if (p_dev->ahw->reset.template_end != 1)
1825                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1826 }
1827
1828 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1829 {
1830         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1831         if (p_dev->ahw->reset.seq_end != 1)
1832                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1833 }
1834
1835 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1836 {
1837         int err = -EIO;
1838
1839         if (request_firmware(&adapter->ahw->fw_info.fw,
1840                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1841                 dev_err(&adapter->pdev->dev,
1842                         "No file FW image, loading flash FW image.\n");
1843                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1844                                     QLC_83XX_BOOT_FROM_FLASH);
1845         } else {
1846                 if (qlcnic_83xx_copy_fw_file(adapter))
1847                         return err;
1848                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1849                                     QLC_83XX_BOOT_FROM_FILE);
1850         }
1851
1852         return 0;
1853 }
1854
1855 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1856 {
1857         u32 val;
1858         int err = -EIO;
1859
1860         qlcnic_83xx_stop_hw(adapter);
1861
1862         /* Collect FW register dump if required */
1863         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1864         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1865                 qlcnic_dump_fw(adapter);
1866         qlcnic_83xx_init_hw(adapter);
1867
1868         if (qlcnic_83xx_copy_bootloader(adapter))
1869                 return err;
1870         /* Boot either flash image or firmware image from host file system */
1871         if (qlcnic_load_fw_file) {
1872                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1873                         return err;
1874         } else {
1875                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1876                                     QLC_83XX_BOOT_FROM_FLASH);
1877         }
1878
1879         qlcnic_83xx_start_hw(adapter);
1880         if (qlcnic_83xx_check_hw_status(adapter))
1881                 return -EIO;
1882
1883         return 0;
1884 }
1885
1886 /**
1887 * qlcnic_83xx_config_default_opmode
1888 *
1889 * @adapter: adapter structure
1890 *
1891 * Configure default driver operating mode
1892 *
1893 * Returns: Error code or Success(0)
1894 * */
1895 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1896 {
1897         u32 op_mode;
1898         struct qlcnic_hardware_context *ahw = adapter->ahw;
1899
1900         qlcnic_get_func_no(adapter);
1901         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1902
1903         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1904                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1905                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1906         } else {
1907                 return -EIO;
1908         }
1909
1910         return 0;
1911 }
1912
1913 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1914 {
1915         int err;
1916         struct qlcnic_info nic_info;
1917         struct qlcnic_hardware_context *ahw = adapter->ahw;
1918
1919         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1920         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1921         if (err)
1922                 return -EIO;
1923
1924         ahw->physical_port = (u8) nic_info.phys_port;
1925         ahw->switch_mode = nic_info.switch_mode;
1926         ahw->max_tx_ques = nic_info.max_tx_ques;
1927         ahw->max_rx_ques = nic_info.max_rx_ques;
1928         ahw->capabilities = nic_info.capabilities;
1929         ahw->max_mac_filters = nic_info.max_mac_filters;
1930         ahw->max_mtu = nic_info.max_mtu;
1931
1932         if (ahw->capabilities & BIT_23)
1933                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1934         else
1935                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1936
1937         return ahw->nic_mode;
1938 }
1939
1940 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1941 {
1942         int ret;
1943
1944         ret = qlcnic_83xx_get_nic_configuration(adapter);
1945         if (ret == -EIO)
1946                 return -EIO;
1947
1948         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
1949                 if (qlcnic_83xx_config_vnic_opmode(adapter))
1950                         return -EIO;
1951         } else if (ret == QLC_83XX_DEFAULT_MODE) {
1952                 if (qlcnic_83xx_config_default_opmode(adapter))
1953                         return -EIO;
1954         }
1955
1956         return 0;
1957 }
1958
1959 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
1960 {
1961         struct qlcnic_hardware_context *ahw = adapter->ahw;
1962
1963         if (ahw->port_type == QLCNIC_XGBE) {
1964                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
1965                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
1966                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1967                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1968
1969         } else if (ahw->port_type == QLCNIC_GBE) {
1970                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
1971                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
1972                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
1973                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
1974         }
1975         adapter->num_txd = MAX_CMD_DESCRIPTORS;
1976         adapter->max_rds_rings = MAX_RDS_RINGS;
1977 }
1978
1979 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
1980 {
1981         int err = -EIO;
1982
1983         qlcnic_83xx_get_minidump_template(adapter);
1984         if (qlcnic_83xx_get_port_info(adapter))
1985                 return err;
1986
1987         qlcnic_83xx_config_buff_descriptors(adapter);
1988         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
1989         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
1990
1991         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
1992                  adapter->ahw->fw_hal_version);
1993
1994         return 0;
1995 }
1996
1997 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
1998 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
1999 {
2000         struct qlcnic_cmd_args cmd;
2001         u32 presence_mask, audit_mask;
2002         int status;
2003
2004         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2005         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2006
2007         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2008                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2009                 cmd.req.arg[1] = BIT_31;
2010                 status = qlcnic_issue_cmd(adapter, &cmd);
2011                 if (status)
2012                         dev_err(&adapter->pdev->dev,
2013                                 "Failed to clean up the function resources\n");
2014                 qlcnic_free_mbx_args(&cmd);
2015         }
2016 }
2017
2018 int qlcnic_83xx_init(struct qlcnic_adapter *adapter)
2019 {
2020         struct qlcnic_hardware_context *ahw = adapter->ahw;
2021
2022         if (qlcnic_83xx_check_hw_status(adapter))
2023                 return -EIO;
2024
2025         /* Initilaize 83xx mailbox spinlock */
2026         spin_lock_init(&ahw->mbx_lock);
2027
2028         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2029         qlcnic_83xx_clear_function_resources(adapter);
2030
2031         /* register for NIC IDC AEN Events */
2032         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2033
2034         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2035                 qlcnic_83xx_read_flash_mfg_id(adapter);
2036
2037         if (qlcnic_83xx_idc_init(adapter))
2038                 return -EIO;
2039
2040         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2041         if (qlcnic_83xx_configure_opmode(adapter))
2042                 return -EIO;
2043
2044         /* Perform operating mode specific initialization */
2045         if (adapter->nic_ops->init_driver(adapter))
2046                 return -EIO;
2047
2048         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2049
2050         /* Periodically monitor device status */
2051         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2052
2053         return adapter->ahw->idc.err_code;
2054 }