drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * qlcnic_83xx_idc_detach_driver
 390  *
 391  * @adapter: adapter structure
 392  * Detach net interface, stop TX and cleanup resources before the HW reset.
 393  * Returns: None
 394  *
 395  **/
 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 397 {
 398         int i;
 399         struct net_device *netdev = adapter->netdev;
 400
 401         netif_device_detach(netdev);
 402
 403         /* Disable mailbox interrupt */
 404         qlcnic_83xx_disable_mbx_intr(adapter);
 405         qlcnic_down(adapter, netdev);
 406         for (i = 0; i < adapter->ahw->num_msix; i++) {
 407                 adapter->ahw->intr_tbl[i].id = i;
 408                 adapter->ahw->intr_tbl[i].enabled = 0;
 409                 adapter->ahw->intr_tbl[i].src = 0;
 410         }
 411
 412         if (qlcnic_sriov_pf_check(adapter))
 413                 qlcnic_sriov_pf_reset(adapter);
 414 }
 415
 416 /**
 417  * qlcnic_83xx_idc_attach_driver
 418  *
 419  * @adapter: adapter structure
 420  *
 421  * Re-attach and re-enable net interface
 422  * Returns: None
 423  *
 424  **/
 425 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 426 {
 427         struct net_device *netdev = adapter->netdev;
 428
 429         if (netif_running(netdev)) {
 430                 if (qlcnic_up(adapter, netdev))
 431                         goto done;
 432                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 433         }
 434 done:
 435         netif_device_attach(netdev);
 436 }
 437
 438 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 439                                               int lock)
 440 {
 441         if (lock) {
 442                 if (qlcnic_83xx_lock_driver(adapter))
 443                         return -EBUSY;
 444         }
 445
 446         qlcnic_83xx_idc_clear_registers(adapter, 0);
 447         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 448         if (lock)
 449                 qlcnic_83xx_unlock_driver(adapter);
 450
 451         qlcnic_83xx_idc_log_state_history(adapter);
 452         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 453
 454         return 0;
 455 }
 456
 457 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 458                                             int lock)
 459 {
 460         if (lock) {
 461                 if (qlcnic_83xx_lock_driver(adapter))
 462                         return -EBUSY;
 463         }
 464
 465         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 466
 467         if (lock)
 468                 qlcnic_83xx_unlock_driver(adapter);
 469
 470         return 0;
 471 }
 472
 473 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 474                                               int lock)
 475 {
 476         if (lock) {
 477                 if (qlcnic_83xx_lock_driver(adapter))
 478                         return -EBUSY;
 479         }
 480
 481         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 482                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 483
 484         if (lock)
 485                 qlcnic_83xx_unlock_driver(adapter);
 486
 487         return 0;
 488 }
 489
 490 static int
 491 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 492 {
 493         if (lock) {
 494                 if (qlcnic_83xx_lock_driver(adapter))
 495                         return -EBUSY;
 496         }
 497
 498         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 499                QLC_83XX_IDC_DEV_NEED_RESET);
 500
 501         if (lock)
 502                 qlcnic_83xx_unlock_driver(adapter);
 503
 504         return 0;
 505 }
 506
 507 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 508                                              int lock)
 509 {
 510         if (lock) {
 511                 if (qlcnic_83xx_lock_driver(adapter))
 512                         return -EBUSY;
 513         }
 514
 515         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 516         if (lock)
 517                 qlcnic_83xx_unlock_driver(adapter);
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * qlcnic_83xx_idc_find_reset_owner_id
 524  *
 525  * @adapter: adapter structure
 526  *
 527  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 528  * Within the same class, function with lowest PCI ID assumes ownership
 529  *
 530  * Returns: reset owner id or failure indication (-EIO)
 531  *
 532  **/
 533 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 534 {
 535         u32 reg, reg1, reg2, i, j, owner, class;
 536
 537         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 538         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 539         owner = QLCNIC_TYPE_NIC;
 540         i = 0;
 541         j = 0;
 542         reg = reg1;
 543
 544         do {
 545                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 546                 if (class == owner)
 547                         break;
 548                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 549                         reg = reg2;
 550                         j = 0;
 551                 } else {
 552                         j++;
 553                 }
 554
 555                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 556                         if (owner == QLCNIC_TYPE_NIC)
 557                                 owner = QLCNIC_TYPE_ISCSI;
 558                         else if (owner == QLCNIC_TYPE_ISCSI)
 559                                 owner = QLCNIC_TYPE_FCOE;
 560                         else if (owner == QLCNIC_TYPE_FCOE)
 561                                 return -EIO;
 562                         reg = reg1;
 563                         j = 0;
 564                         i = 0;
 565                 }
 566         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 567
 568         return i;
 569 }
 570
 571 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 572 {
 573         int ret = 0;
 574
 575         ret = qlcnic_83xx_restart_hw(adapter);
 576
 577         if (ret) {
 578                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 579         } else {
 580                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 581                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 582         }
 583
 584         return ret;
 585 }
 586
 587 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 588 {
 589         u32 status;
 590
 591         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 592
 593         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 594                 dev_err(&adapter->pdev->dev,
 595                         "peg halt status1=0x%x\n", status);
 596                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 597                         dev_err(&adapter->pdev->dev,
 598                                 "On board active cooling fan failed. "
 599                                 "Device has been halted.\n");
 600                         dev_err(&adapter->pdev->dev,
 601                                 "Replace the adapter.\n");
 602                         return -EIO;
 603                 }
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 610 {
 611         int err;
 612
 613         /* register for NIC IDC AEN Events */
 614         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 615
 616         err = qlcnic_sriov_pf_reinit(adapter);
 617         if (err)
 618                 return err;
 619
 620         qlcnic_83xx_enable_mbx_intrpt(adapter);
 621
 622         if (qlcnic_83xx_configure_opmode(adapter)) {
 623                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 624                 return -EIO;
 625         }
 626
 627         if (adapter->nic_ops->init_driver(adapter)) {
 628                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 629                 return -EIO;
 630         }
 631
 632         qlcnic_83xx_idc_attach_driver(adapter);
 633
 634         return 0;
 635 }
 636
 637 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 638 {
 639         struct qlcnic_hardware_context *ahw = adapter->ahw;
 640
 641         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 642         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 643         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 644         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 645
 646         ahw->idc.quiesce_req = 0;
 647         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 648         ahw->idc.err_code = 0;
 649         ahw->idc.collect_dump = 0;
 650         ahw->reset_context = 0;
 651         adapter->tx_timeo_cnt = 0;
 652         ahw->idc.delay_reset = 0;
 653
 654         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 655 }
 656
 657 /**
 658  * qlcnic_83xx_idc_ready_state_entry
 659  *
 660  * @adapter: adapter structure
 661  *
 662  * Perform ready state initialization, this routine will get invoked only
 663  * once from READY state.
 664  *
 665  * Returns: Error code or Success(0)
 666  *
 667  **/
 668 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 669 {
 670         struct qlcnic_hardware_context *ahw = adapter->ahw;
 671
 672         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 673                 qlcnic_83xx_idc_update_idc_params(adapter);
 674                 /* Re-attach the device if required */
 675                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 676                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 677                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 678                                 return -EIO;
 679                 }
 680         }
 681
 682         return 0;
 683 }
 684
 685 /**
 686  * qlcnic_83xx_idc_vnic_pf_entry
 687  *
 688  * @adapter: adapter structure
 689  *
 690  * Ensure vNIC mode privileged function starts only after vNIC mode is
 691  * enabled by management function.
 692  * If vNIC mode is ready, start initialization.
 693  *
 694  * Returns: -EIO or 0
 695  *
 696  **/
 697 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 698 {
 699         u32 state;
 700         struct qlcnic_hardware_context *ahw = adapter->ahw;
 701
 702         /* Privileged function waits till mgmt function enables VNIC mode */
 703         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 704         if (state != QLCNIC_DEV_NPAR_OPER) {
 705                 if (!ahw->idc.vnic_wait_limit--) {
 706                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 707                         return -EIO;
 708                 }
 709                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 710                 return -EIO;
 711
 712         } else {
 713                 /* Perform one time initialization from ready state */
 714                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 715                         qlcnic_83xx_idc_update_idc_params(adapter);
 716
 717                         /* If the previous state is UNKNOWN, device will be
 718                            already attached properly by Init routine*/
 719                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 720                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 721                                         return -EIO;
 722                         }
 723                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 724                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 725                 }
 726         }
 727
 728         return 0;
 729 }
 730
 731 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 732 {
 733         adapter->ahw->idc.err_code = -EIO;
 734         dev_err(&adapter->pdev->dev,
 735                 "%s: Device in unknown state\n", __func__);
 736         return 0;
 737 }
 738
 739 /**
 740  * qlcnic_83xx_idc_cold_state
 741  *
 742  * @adapter: adapter structure
 743  *
 744  * If HW is up and running device will enter READY state.
 745  * If firmware image from host needs to be loaded, device is
 746  * forced to start with the file firmware image.
 747  *
 748  * Returns: Error code or Success(0)
 749  *
 750  **/
 751 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 752 {
 753         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 754         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 755
 756         if (qlcnic_load_fw_file) {
 757                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 758         } else {
 759                 if (qlcnic_83xx_check_hw_status(adapter)) {
 760                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 761                         return -EIO;
 762                 } else {
 763                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 764                 }
 765         }
 766         return 0;
 767 }
 768
 769 /**
 770  * qlcnic_83xx_idc_init_state
 771  *
 772  * @adapter: adapter structure
 773  *
 774  * Reset owner will restart the device from this state.
 775  * Device will enter failed state if it remains
 776  * in this state for more than DEV_INIT time limit.
 777  *
 778  * Returns: Error code or Success(0)
 779  *
 780  **/
 781 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 782 {
 783         int timeout, ret = 0;
 784         u32 owner;
 785
 786         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 787         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 788                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 789                 if (adapter->ahw->pci_func == owner)
 790                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 791         } else {
 792                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 793                 return ret;
 794         }
 795
 796         return ret;
 797 }
 798
 799 /**
 800  * qlcnic_83xx_idc_ready_state
 801  *
 802  * @adapter: adapter structure
 803  *
 804  * Perform IDC protocol specicifed actions after monitoring device state and
 805  * events.
 806  *
 807  * Returns: Error code or Success(0)
 808  *
 809  **/
 810 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 811 {
 812         u32 val;
 813         struct qlcnic_hardware_context *ahw = adapter->ahw;
 814         int ret = 0;
 815
 816         /* Perform NIC configuration based ready state entry actions */
 817         if (ahw->idc.state_entry(adapter))
 818                 return -EIO;
 819
 820         if (qlcnic_check_temp(adapter)) {
 821                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 822                         qlcnic_83xx_idc_check_fan_failure(adapter);
 823                         dev_err(&adapter->pdev->dev,
 824                                 "Error: device temperature %d above limits\n",
 825                                 adapter->ahw->temp);
 826                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 827                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 828                         qlcnic_83xx_idc_detach_driver(adapter);
 829                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 830                         return -EIO;
 831                 }
 832         }
 833
 834         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 835         ret = qlcnic_83xx_check_heartbeat(adapter);
 836         if (ret) {
 837                 adapter->flags |= QLCNIC_FW_HANG;
 838                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 839                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 840                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 841                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 842                 }
 843                 return -EIO;
 844         }
 845
 846         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 847                 /* Move to need reset state and prepare for reset */
 848                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 849                 return ret;
 850         }
 851
 852         /* Check for soft reset request */
 853         if (ahw->reset_context &&
 854             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 855                 adapter->ahw->reset_context = 0;
 856                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 857                 return ret;
 858         }
 859
 860         /* Move to need quiesce state if requested */
 861         if (adapter->ahw->idc.quiesce_req) {
 862                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 863                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 864                 return ret;
 865         }
 866
 867         return ret;
 868 }
 869
 870 /**
 871  * qlcnic_83xx_idc_need_reset_state
 872  *
 873  * @adapter: adapter structure
 874  *
 875  * Device will remain in this state until:
 876  *      Reset request ACK's are recieved from all the functions
 877  *      Wait time exceeds max time limit
 878  *
 879  * Returns: Error code or Success(0)
 880  *
 881  **/
 882 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 883 {
 884         int ret = 0;
 885
 886         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 887                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 888                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 889                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 890                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 891                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 892
 893                 if (qlcnic_check_diag_status(adapter)) {
 894                         dev_info(&adapter->pdev->dev,
 895                                  "%s: Wait for diag completion\n", __func__);
 896                         adapter->ahw->idc.delay_reset = 1;
 897                         return 0;
 898                 } else {
 899                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 900                         qlcnic_83xx_idc_detach_driver(adapter);
 901                 }
 902         }
 903
 904         if (qlcnic_check_diag_status(adapter)) {
 905                 dev_info(&adapter->pdev->dev,
 906                          "%s: Wait for diag completion\n", __func__);
 907                 return  -1;
 908         } else {
 909                 if (adapter->ahw->idc.delay_reset) {
 910                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 911                         qlcnic_83xx_idc_detach_driver(adapter);
 912                         adapter->ahw->idc.delay_reset = 0;
 913                 }
 914
 915                 /* Check for ACK from other functions */
 916                 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 917                 if (ret) {
 918                         dev_info(&adapter->pdev->dev,
 919                                  "%s: Waiting for reset ACK\n", __func__);
 920                         return -1;
 921                 }
 922         }
 923
 924         /* Transit to INIT state and restart the HW */
 925         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 926
 927         return ret;
 928 }
 929
 930 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 931 {
 932         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 933         return 0;
 934 }
 935
 936 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 937 {
 938         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 939         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 940         adapter->ahw->idc.err_code = -EIO;
 941
 942         return 0;
 943 }
 944
 945 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 946 {
 947         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 948         return 0;
 949 }
 950
 951 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 952                                                 u32 state)
 953 {
 954         u32 cur, prev, next;
 955
 956         cur = adapter->ahw->idc.curr_state;
 957         prev = adapter->ahw->idc.prev_state;
 958         next = state;
 959
 960         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 961             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 962                 dev_err(&adapter->pdev->dev,
 963                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 964                         __func__, cur, prev, state);
 965                 return 1;
 966         }
 967
 968         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 969             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 970                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 971                     (next != QLC_83XX_IDC_DEV_READY)) {
 972                         dev_err(&adapter->pdev->dev,
 973                                 "%s: failed, cur %d prev %d next %d\n",
 974                                 __func__, cur, prev, next);
 975                         return 1;
 976                 }
 977         }
 978
 979         if (next == QLC_83XX_IDC_DEV_INIT) {
 980                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 981                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 982                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 983                         dev_err(&adapter->pdev->dev,
 984                                 "%s: failed, cur %d prev %d next %d\n",
 985                                 __func__, cur, prev, next);
 986                         return 1;
 987                 }
 988         }
 989
 990         return 0;
 991 }
 992
 993 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 994 {
 995         if (adapter->fhash.fnum)
 996                 qlcnic_prune_lb_filters(adapter);
 997 }
 998
 999 /**
1000  * qlcnic_83xx_idc_poll_dev_state
1001  *
1002  * @work: kernel work queue structure used to schedule the function
1003  *
1004  * Poll device state periodically and perform state specific
1005  * actions defined by Inter Driver Communication (IDC) protocol.
1006  *
1007  * Returns: None
1008  *
1009  **/
1010 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1011 {
1012         struct qlcnic_adapter *adapter;
1013         u32 state;
1014
1015         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1016         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1017
1018         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1019                 qlcnic_83xx_idc_log_state_history(adapter);
1020                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1021         } else {
1022                 adapter->ahw->idc.curr_state = state;
1023         }
1024
1025         switch (adapter->ahw->idc.curr_state) {
1026         case QLC_83XX_IDC_DEV_READY:
1027                 qlcnic_83xx_idc_ready_state(adapter);
1028                 break;
1029         case QLC_83XX_IDC_DEV_NEED_RESET:
1030                 qlcnic_83xx_idc_need_reset_state(adapter);
1031                 break;
1032         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1033                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1034                 break;
1035         case QLC_83XX_IDC_DEV_FAILED:
1036                 qlcnic_83xx_idc_failed_state(adapter);
1037                 return;
1038         case QLC_83XX_IDC_DEV_INIT:
1039                 qlcnic_83xx_idc_init_state(adapter);
1040                 break;
1041         case QLC_83XX_IDC_DEV_QUISCENT:
1042                 qlcnic_83xx_idc_quiesce_state(adapter);
1043                 break;
1044         default:
1045                 qlcnic_83xx_idc_unknown_state(adapter);
1046                 return;
1047         }
1048         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1049         qlcnic_83xx_periodic_tasks(adapter);
1050
1051         /* Re-schedule the function */
1052         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1053                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1054                                      adapter->ahw->idc.delay);
1055 }
1056
1057 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1058 {
1059         u32 idc_params, val;
1060
1061         if (qlcnic_83xx_lockless_flash_read32(adapter,
1062                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1063                                               (u8 *)&idc_params, 1)) {
1064                 dev_info(&adapter->pdev->dev,
1065                          "%s:failed to get IDC params from flash\n", __func__);
1066                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1067                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1068         } else {
1069                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1070                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1071         }
1072
1073         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1074         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1075         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1076         adapter->ahw->idc.err_code = 0;
1077         adapter->ahw->idc.collect_dump = 0;
1078         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1079
1080         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1081         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1082         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1083
1084         /* Check if reset recovery is disabled */
1085         if (!qlcnic_auto_fw_reset) {
1086                 /* Propagate do not reset request to other functions */
1087                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1088                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1089                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1090         }
1091 }
1092
1093 static int
1094 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1095 {
1096         u32 state, val;
1097
1098         if (qlcnic_83xx_lock_driver(adapter))
1099                 return -EIO;
1100
1101         /* Clear driver lock register */
1102         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1103         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1104                 qlcnic_83xx_unlock_driver(adapter);
1105                 return -EIO;
1106         }
1107
1108         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1109         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1110                 qlcnic_83xx_unlock_driver(adapter);
1111                 return -EIO;
1112         }
1113
1114         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1115                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1116                        QLC_83XX_IDC_DEV_COLD);
1117                 state = QLC_83XX_IDC_DEV_COLD;
1118         }
1119
1120         adapter->ahw->idc.curr_state = state;
1121         /* First to load function should cold boot the device */
1122         if (state == QLC_83XX_IDC_DEV_COLD)
1123                 qlcnic_83xx_idc_cold_state_handler(adapter);
1124
1125         /* Check if reset recovery is enabled */
1126         if (qlcnic_auto_fw_reset) {
1127                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1128                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1129                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1130         }
1131
1132         qlcnic_83xx_unlock_driver(adapter);
1133
1134         return 0;
1135 }
1136
1137 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1138 {
1139         int ret = -EIO;
1140
1141         qlcnic_83xx_setup_idc_parameters(adapter);
1142
1143         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1144                 return ret;
1145
1146         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1147                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1148                         return -EIO;
1149         } else {
1150                 if (qlcnic_83xx_idc_check_major_version(adapter))
1151                         return -EIO;
1152         }
1153
1154         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1155
1156         return 0;
1157 }
1158
1159 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1160 {
1161         int id;
1162         u32 val;
1163
1164         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1165                 usleep_range(10000, 11000);
1166
1167         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1168         id = id & 0xFF;
1169
1170         if (id == adapter->portnum) {
1171                 dev_err(&adapter->pdev->dev,
1172                         "%s: wait for lock recovery.. %d\n", __func__, id);
1173                 msleep(20);
1174                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1175                 id = id & 0xFF;
1176         }
1177
1178         /* Clear driver presence bit */
1179         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1180         val = val & ~(1 << adapter->portnum);
1181         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1182         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1183         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1184
1185         cancel_delayed_work_sync(&adapter->fw_work);
1186 }
1187
1188 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1189 {
1190         u32 val;
1191
1192         if (qlcnic_83xx_lock_driver(adapter)) {
1193                 dev_err(&adapter->pdev->dev,
1194                         "%s:failed, please retry\n", __func__);
1195                 return;
1196         }
1197
1198         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1199         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1200             !qlcnic_auto_fw_reset) {
1201                 dev_err(&adapter->pdev->dev,
1202                         "%s:failed, device in non reset mode\n", __func__);
1203                 qlcnic_83xx_unlock_driver(adapter);
1204                 return;
1205         }
1206
1207         if (key == QLCNIC_FORCE_FW_RESET) {
1208                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1209                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1210                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1211         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1212                 adapter->ahw->idc.collect_dump = 1;
1213         }
1214
1215         qlcnic_83xx_unlock_driver(adapter);
1216         return;
1217 }
1218
1219 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1220 {
1221         u8 *p_cache;
1222         u32 src, size;
1223         u64 dest;
1224         int ret = -EIO;
1225
1226         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1227         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1228         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1229
1230         /* alignment check */
1231         if (size & 0xF)
1232                 size = (size + 16) & ~0xF;
1233
1234         p_cache = kzalloc(size, GFP_KERNEL);
1235         if (p_cache == NULL)
1236                 return -ENOMEM;
1237
1238         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1239                                                 size / sizeof(u32));
1240         if (ret) {
1241                 kfree(p_cache);
1242                 return ret;
1243         }
1244         /* 16 byte write to MS memory */
1245         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1246                                           size / 16);
1247         if (ret) {
1248                 kfree(p_cache);
1249                 return ret;
1250         }
1251         kfree(p_cache);
1252
1253         return ret;
1254 }
1255
1256 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1257 {
1258         u32 dest, *p_cache;
1259         u64 addr;
1260         u8 data[16];
1261         size_t size;
1262         int i, ret = -EIO;
1263
1264         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1265         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1266         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1267         addr = (u64)dest;
1268
1269         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1270                                           (u32 *)p_cache, size / 16);
1271         if (ret) {
1272                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1273                 release_firmware(adapter->ahw->fw_info.fw);
1274                 adapter->ahw->fw_info.fw = NULL;
1275                 return -EIO;
1276         }
1277
1278         /* alignment check */
1279         if (adapter->ahw->fw_info.fw->size & 0xF) {
1280                 addr = dest + size;
1281                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1282                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1283                 for (; i < 16; i++)
1284                         data[i] = 0;
1285                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1286                                                   (u32 *)data, 1);
1287                 if (ret) {
1288                         dev_err(&adapter->pdev->dev,
1289                                 "MS memory write failed\n");
1290                         release_firmware(adapter->ahw->fw_info.fw);
1291                         adapter->ahw->fw_info.fw = NULL;
1292                         return -EIO;
1293                 }
1294         }
1295         release_firmware(adapter->ahw->fw_info.fw);
1296         adapter->ahw->fw_info.fw = NULL;
1297
1298         return 0;
1299 }
1300
1301 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1302 {
1303         int i, j;
1304         u32 val = 0, val1 = 0, reg = 0;
1305
1306         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1307         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1308
1309         for (j = 0; j < 2; j++) {
1310                 if (j == 0) {
1311                         dev_info(&adapter->pdev->dev,
1312                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1313                         reg = QLC_83XX_PORT0_THRESHOLD;
1314                 } else if (j == 1) {
1315                         dev_info(&adapter->pdev->dev,
1316                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1317                         reg = QLC_83XX_PORT1_THRESHOLD;
1318                 }
1319                 for (i = 0; i < 8; i++) {
1320                         val = QLCRD32(adapter, reg + (i * 0x4));
1321                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1322                 }
1323                 dev_info(&adapter->pdev->dev, "\n");
1324         }
1325
1326         for (j = 0; j < 2; j++) {
1327                 if (j == 0) {
1328                         dev_info(&adapter->pdev->dev,
1329                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1330                         reg = QLC_83XX_PORT0_TC_MC_REG;
1331                 } else if (j == 1) {
1332                         dev_info(&adapter->pdev->dev,
1333                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1334                         reg = QLC_83XX_PORT1_TC_MC_REG;
1335                 }
1336                 for (i = 0; i < 4; i++) {
1337                         val = QLCRD32(adapter, reg + (i * 0x4));
1338                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1339                 }
1340                 dev_info(&adapter->pdev->dev, "\n");
1341         }
1342
1343         for (j = 0; j < 2; j++) {
1344                 if (j == 0) {
1345                         dev_info(&adapter->pdev->dev,
1346                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1347                         reg = QLC_83XX_PORT0_TC_STATS;
1348                 } else if (j == 1) {
1349                         dev_info(&adapter->pdev->dev,
1350                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1351                         reg = QLC_83XX_PORT1_TC_STATS;
1352                 }
1353                 for (i = 7; i >= 0; i--) {
1354                         val = QLCRD32(adapter, reg);
1355                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1356                         QLCWR32(adapter, reg, (val | (i << 29)));
1357                         val = QLCRD32(adapter, reg);
1358                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1359                 }
1360                 dev_info(&adapter->pdev->dev, "\n");
1361         }
1362
1363         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1364         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1365         dev_info(&adapter->pdev->dev,
1366                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1367                  val, val1);
1368 }
1369
1370
1371 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1372 {
1373         u32 reg = 0, i, j;
1374
1375         if (qlcnic_83xx_lock_driver(adapter)) {
1376                 dev_err(&adapter->pdev->dev,
1377                         "%s:failed to acquire driver lock\n", __func__);
1378                 return;
1379         }
1380
1381         qlcnic_83xx_dump_pause_control_regs(adapter);
1382         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1383
1384         for (j = 0; j < 2; j++) {
1385                 if (j == 0)
1386                         reg = QLC_83XX_PORT0_THRESHOLD;
1387                 else if (j == 1)
1388                         reg = QLC_83XX_PORT1_THRESHOLD;
1389
1390                 for (i = 0; i < 8; i++)
1391                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1392         }
1393
1394         for (j = 0; j < 2; j++) {
1395                 if (j == 0)
1396                         reg = QLC_83XX_PORT0_TC_MC_REG;
1397                 else if (j == 1)
1398                         reg = QLC_83XX_PORT1_TC_MC_REG;
1399
1400                 for (i = 0; i < 4; i++)
1401                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1402         }
1403
1404         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1405         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1406         dev_info(&adapter->pdev->dev,
1407                  "Disabled pause frames successfully on all ports\n");
1408         qlcnic_83xx_unlock_driver(adapter);
1409 }
1410
1411 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1412 {
1413         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1414         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1415         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1416         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1417         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1418         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1419         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1420         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1421         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1422 }
1423
1424 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1425 {
1426         u32 heartbeat, peg_status;
1427         int retries, ret = -EIO;
1428
1429         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1430         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1431                                                QLCNIC_PEG_ALIVE_COUNTER);
1432
1433         do {
1434                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1435                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1436                                                 QLCNIC_PEG_ALIVE_COUNTER);
1437                 if (heartbeat != p_dev->heartbeat) {
1438                         ret = QLCNIC_RCODE_SUCCESS;
1439                         break;
1440                 }
1441         } while (--retries);
1442
1443         if (ret) {
1444                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1445                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1446                 qlcnic_83xx_disable_pause_frames(p_dev);
1447                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1448                                                  QLCNIC_PEG_HALT_STATUS1);
1449                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1450                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1451                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1452                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1453                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1454                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1455                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1456                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1457                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1458                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1459                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1460
1461                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1462                         dev_err(&p_dev->pdev->dev,
1463                                 "Device is being reset err code 0x00006700.\n");
1464         }
1465
1466         return ret;
1467 }
1468
1469 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1470 {
1471         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1472         u32 val;
1473
1474         do {
1475                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1476                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1477                         return 0;
1478                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1479         } while (--retries);
1480
1481         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1482         return -EIO;
1483 }
1484
1485 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1486 {
1487         int err;
1488
1489         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1490         if (err)
1491                 return err;
1492
1493         err = qlcnic_83xx_check_heartbeat(p_dev);
1494         if (err)
1495                 return err;
1496
1497         return err;
1498 }
1499
1500 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1501                                 int duration, u32 mask, u32 status)
1502 {
1503         u32 value;
1504         int timeout_error;
1505         u8 retries;
1506
1507         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1508         retries = duration / 10;
1509
1510         do {
1511                 if ((value & mask) != status) {
1512                         timeout_error = 1;
1513                         msleep(duration / 10);
1514                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1515                 } else {
1516                         timeout_error = 0;
1517                         break;
1518                 }
1519         } while (retries--);
1520
1521         if (timeout_error) {
1522                 p_dev->ahw->reset.seq_error++;
1523                 dev_err(&p_dev->pdev->dev,
1524                         "%s: Timeout Err, entry_num = %d\n",
1525                         __func__, p_dev->ahw->reset.seq_index);
1526                 dev_err(&p_dev->pdev->dev,
1527                         "0x%08x 0x%08x 0x%08x\n",
1528                         value, mask, status);
1529         }
1530
1531         return timeout_error;
1532 }
1533
1534 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1535 {
1536         u32 sum = 0;
1537         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1538         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1539
1540         while (count-- > 0)
1541                 sum += *buff++;
1542
1543         while (sum >> 16)
1544                 sum = (sum & 0xFFFF) + (sum >> 16);
1545
1546         if (~sum) {
1547                 return 0;
1548         } else {
1549                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1550                 return -1;
1551         }
1552 }
1553
1554 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1555 {
1556         u8 *p_buff;
1557         u32 addr, count;
1558         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1559
1560         ahw->reset.seq_error = 0;
1561         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1562         if (p_dev->ahw->reset.buff == NULL)
1563                 return -ENOMEM;
1564
1565         p_buff = p_dev->ahw->reset.buff;
1566         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1567         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1568
1569         /* Copy template header from flash */
1570         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1571                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1572                 return -EIO;
1573         }
1574         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1575         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1576         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1577         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1578
1579         /* Copy rest of the template */
1580         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1581                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1582                 return -EIO;
1583         }
1584
1585         if (qlcnic_83xx_reset_template_checksum(p_dev))
1586                 return -EIO;
1587         /* Get Stop, Start and Init command offsets */
1588         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1589         ahw->reset.start_offset = ahw->reset.buff +
1590                                   ahw->reset.hdr->start_offset;
1591         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1592         return 0;
1593 }
1594
1595 /* Read Write HW register command */
1596 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1597                                            u32 raddr, u32 waddr)
1598 {
1599         int value;
1600
1601         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1602         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1603 }
1604
1605 /* Read Modify Write HW register command */
1606 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1607                                     u32 raddr, u32 waddr,
1608                                     struct qlc_83xx_rmw *p_rmw_hdr)
1609 {
1610         int value;
1611
1612         if (p_rmw_hdr->index_a)
1613                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1614         else
1615                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1616
1617         value &= p_rmw_hdr->mask;
1618         value <<= p_rmw_hdr->shl;
1619         value >>= p_rmw_hdr->shr;
1620         value |= p_rmw_hdr->or_value;
1621         value ^= p_rmw_hdr->xor_value;
1622         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1623 }
1624
1625 /* Write HW register command */
1626 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1627                                    struct qlc_83xx_entry_hdr *p_hdr)
1628 {
1629         int i;
1630         struct qlc_83xx_entry *entry;
1631
1632         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1633                                           sizeof(struct qlc_83xx_entry_hdr));
1634
1635         for (i = 0; i < p_hdr->count; i++, entry++) {
1636                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1637                                              entry->arg2);
1638                 if (p_hdr->delay)
1639                         udelay((u32)(p_hdr->delay));
1640         }
1641 }
1642
1643 /* Read and Write instruction */
1644 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1645                                         struct qlc_83xx_entry_hdr *p_hdr)
1646 {
1647         int i;
1648         struct qlc_83xx_entry *entry;
1649
1650         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1651                                           sizeof(struct qlc_83xx_entry_hdr));
1652
1653         for (i = 0; i < p_hdr->count; i++, entry++) {
1654                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1655                                                entry->arg2);
1656                 if (p_hdr->delay)
1657                         udelay((u32)(p_hdr->delay));
1658         }
1659 }
1660
1661 /* Poll HW register command */
1662 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1663                                   struct qlc_83xx_entry_hdr *p_hdr)
1664 {
1665         long delay;
1666         struct qlc_83xx_entry *entry;
1667         struct qlc_83xx_poll *poll;
1668         int i;
1669         unsigned long arg1, arg2;
1670
1671         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1672                                         sizeof(struct qlc_83xx_entry_hdr));
1673
1674         entry = (struct qlc_83xx_entry *)((char *)poll +
1675                                           sizeof(struct qlc_83xx_poll));
1676         delay = (long)p_hdr->delay;
1677
1678         if (!delay) {
1679                 for (i = 0; i < p_hdr->count; i++, entry++)
1680                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1681                                              delay, poll->mask,
1682                                              poll->status);
1683         } else {
1684                 for (i = 0; i < p_hdr->count; i++, entry++) {
1685                         arg1 = entry->arg1;
1686                         arg2 = entry->arg2;
1687                         if (delay) {
1688                                 if (qlcnic_83xx_poll_reg(p_dev,
1689                                                          arg1, delay,
1690                                                          poll->mask,
1691                                                          poll->status)){
1692                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1693                                                                     arg1);
1694                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1695                                                                     arg2);
1696                                 }
1697                         }
1698                 }
1699         }
1700 }
1701
1702 /* Poll and write HW register command */
1703 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1704                                         struct qlc_83xx_entry_hdr *p_hdr)
1705 {
1706         int i;
1707         long delay;
1708         struct qlc_83xx_quad_entry *entry;
1709         struct qlc_83xx_poll *poll;
1710
1711         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1712                                         sizeof(struct qlc_83xx_entry_hdr));
1713         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1714                                                sizeof(struct qlc_83xx_poll));
1715         delay = (long)p_hdr->delay;
1716
1717         for (i = 0; i < p_hdr->count; i++, entry++) {
1718                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1719                                              entry->dr_value);
1720                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1721                                              entry->ar_value);
1722                 if (delay)
1723                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1724                                              poll->mask, poll->status);
1725         }
1726 }
1727
1728 /* Read Modify Write register command */
1729 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1730                                           struct qlc_83xx_entry_hdr *p_hdr)
1731 {
1732         int i;
1733         struct qlc_83xx_entry *entry;
1734         struct qlc_83xx_rmw *rmw_hdr;
1735
1736         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1737                                           sizeof(struct qlc_83xx_entry_hdr));
1738
1739         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1740                                           sizeof(struct qlc_83xx_rmw));
1741
1742         for (i = 0; i < p_hdr->count; i++, entry++) {
1743                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1744                                         entry->arg2, rmw_hdr);
1745                 if (p_hdr->delay)
1746                         udelay((u32)(p_hdr->delay));
1747         }
1748 }
1749
1750 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1751 {
1752         if (p_hdr->delay)
1753                 mdelay((u32)((long)p_hdr->delay));
1754 }
1755
1756 /* Read and poll register command */
1757 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1758                                        struct qlc_83xx_entry_hdr *p_hdr)
1759 {
1760         long delay;
1761         int index, i, j;
1762         struct qlc_83xx_quad_entry *entry;
1763         struct qlc_83xx_poll *poll;
1764         unsigned long addr;
1765
1766         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1767                                         sizeof(struct qlc_83xx_entry_hdr));
1768
1769         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1770                                                sizeof(struct qlc_83xx_poll));
1771         delay = (long)p_hdr->delay;
1772
1773         for (i = 0; i < p_hdr->count; i++, entry++) {
1774                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1775                                              entry->ar_value);
1776                 if (delay) {
1777                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1778                                                   poll->mask, poll->status)){
1779                                 index = p_dev->ahw->reset.array_index;
1780                                 addr = entry->dr_addr;
1781                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1782                                 p_dev->ahw->reset.array[index++] = j;
1783
1784                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1785                                         p_dev->ahw->reset.array_index = 1;
1786                         }
1787                 }
1788         }
1789 }
1790
1791 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1792 {
1793         p_dev->ahw->reset.seq_end = 1;
1794 }
1795
1796 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1797 {
1798         p_dev->ahw->reset.template_end = 1;
1799         if (p_dev->ahw->reset.seq_error == 0)
1800                 dev_err(&p_dev->pdev->dev,
1801                         "HW restart process completed successfully.\n");
1802         else
1803                 dev_err(&p_dev->pdev->dev,
1804                         "HW restart completed with timeout errors.\n");
1805 }
1806
1807 /**
1808 * qlcnic_83xx_exec_template_cmd
1809 *
1810 * @p_dev: adapter structure
1811 * @p_buff: Poiter to instruction template
1812 *
1813 * Template provides instructions to stop, restart and initalize firmware.
1814 * These instructions are abstracted as a series of read, write and
1815 * poll operations on hardware registers. Register information and operation
1816 * specifics are not exposed to the driver. Driver reads the template from
1817 * flash and executes the instructions located at pre-defined offsets.
1818 *
1819 * Returns: None
1820 * */
1821 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1822                                           char *p_buff)
1823 {
1824         int index, entries;
1825         struct qlc_83xx_entry_hdr *p_hdr;
1826         char *entry = p_buff;
1827
1828         p_dev->ahw->reset.seq_end = 0;
1829         p_dev->ahw->reset.template_end = 0;
1830         entries = p_dev->ahw->reset.hdr->entries;
1831         index = p_dev->ahw->reset.seq_index;
1832
1833         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1834                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1835
1836                 switch (p_hdr->cmd) {
1837                 case QLC_83XX_OPCODE_NOP:
1838                         break;
1839                 case QLC_83XX_OPCODE_WRITE_LIST:
1840                         qlcnic_83xx_write_list(p_dev, p_hdr);
1841                         break;
1842                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1843                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1844                         break;
1845                 case QLC_83XX_OPCODE_POLL_LIST:
1846                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1847                         break;
1848                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1849                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1850                         break;
1851                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1852                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1853                         break;
1854                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1855                         qlcnic_83xx_pause(p_hdr);
1856                         break;
1857                 case QLC_83XX_OPCODE_SEQ_END:
1858                         qlcnic_83xx_seq_end(p_dev);
1859                         break;
1860                 case QLC_83XX_OPCODE_TMPL_END:
1861                         qlcnic_83xx_template_end(p_dev);
1862                         break;
1863                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1864                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1865                         break;
1866                 default:
1867                         dev_err(&p_dev->pdev->dev,
1868                                 "%s: Unknown opcode 0x%04x in template %d\n",
1869                                 __func__, p_hdr->cmd, index);
1870                         break;
1871                 }
1872                 entry += p_hdr->size;
1873         }
1874         p_dev->ahw->reset.seq_index = index;
1875 }
1876
1877 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1878 {
1879         p_dev->ahw->reset.seq_index = 0;
1880
1881         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1882         if (p_dev->ahw->reset.seq_end != 1)
1883                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1884 }
1885
1886 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1887 {
1888         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1889         if (p_dev->ahw->reset.template_end != 1)
1890                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1891 }
1892
1893 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1894 {
1895         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1896         if (p_dev->ahw->reset.seq_end != 1)
1897                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1898 }
1899
1900 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1901 {
1902         int err = -EIO;
1903
1904         if (request_firmware(&adapter->ahw->fw_info.fw,
1905                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1906                 dev_err(&adapter->pdev->dev,
1907                         "No file FW image, loading flash FW image.\n");
1908                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1909                                     QLC_83XX_BOOT_FROM_FLASH);
1910         } else {
1911                 if (qlcnic_83xx_copy_fw_file(adapter))
1912                         return err;
1913                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1914                                     QLC_83XX_BOOT_FROM_FILE);
1915         }
1916
1917         return 0;
1918 }
1919
1920 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1921 {
1922         u32 val;
1923         int err = -EIO;
1924
1925         qlcnic_83xx_stop_hw(adapter);
1926
1927         /* Collect FW register dump if required */
1928         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1929         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1930                 qlcnic_dump_fw(adapter);
1931         qlcnic_83xx_init_hw(adapter);
1932
1933         if (qlcnic_83xx_copy_bootloader(adapter))
1934                 return err;
1935         /* Boot either flash image or firmware image from host file system */
1936         if (qlcnic_load_fw_file) {
1937                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1938                         return err;
1939         } else {
1940                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1941                                     QLC_83XX_BOOT_FROM_FLASH);
1942         }
1943
1944         qlcnic_83xx_start_hw(adapter);
1945         if (qlcnic_83xx_check_hw_status(adapter))
1946                 return -EIO;
1947
1948         return 0;
1949 }
1950
1951 /**
1952 * qlcnic_83xx_config_default_opmode
1953 *
1954 * @adapter: adapter structure
1955 *
1956 * Configure default driver operating mode
1957 *
1958 * Returns: Error code or Success(0)
1959 * */
1960 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1961 {
1962         u32 op_mode;
1963         struct qlcnic_hardware_context *ahw = adapter->ahw;
1964
1965         qlcnic_get_func_no(adapter);
1966         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1967
1968         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1969                 op_mode = QLC_83XX_DEFAULT_OPMODE;
1970
1971         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1972                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1973                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1974         } else {
1975                 return -EIO;
1976         }
1977
1978         return 0;
1979 }
1980
1981 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1982 {
1983         int err;
1984         struct qlcnic_info nic_info;
1985         struct qlcnic_hardware_context *ahw = adapter->ahw;
1986
1987         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1988         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1989         if (err)
1990                 return -EIO;
1991
1992         ahw->physical_port = (u8) nic_info.phys_port;
1993         ahw->switch_mode = nic_info.switch_mode;
1994         ahw->max_tx_ques = nic_info.max_tx_ques;
1995         ahw->max_rx_ques = nic_info.max_rx_ques;
1996         ahw->capabilities = nic_info.capabilities;
1997         ahw->max_mac_filters = nic_info.max_mac_filters;
1998         ahw->max_mtu = nic_info.max_mtu;
1999
2000         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2001          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2002          * exclusive. So in case of sriov capable device load driver in
2003          * default mode
2004          */
2005         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2006                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2007                 return ahw->nic_mode;
2008         }
2009
2010         if (ahw->capabilities & BIT_23)
2011                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2012         else
2013                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2014
2015         return ahw->nic_mode;
2016 }
2017
2018 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2019 {
2020         int ret;
2021
2022         ret = qlcnic_83xx_get_nic_configuration(adapter);
2023         if (ret == -EIO)
2024                 return -EIO;
2025
2026         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2027                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2028                         return -EIO;
2029         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2030                 if (qlcnic_83xx_config_default_opmode(adapter))
2031                         return -EIO;
2032         }
2033
2034         return 0;
2035 }
2036
2037 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2038 {
2039         struct qlcnic_hardware_context *ahw = adapter->ahw;
2040
2041         if (ahw->port_type == QLCNIC_XGBE) {
2042                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2043                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2044                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2045                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2046
2047         } else if (ahw->port_type == QLCNIC_GBE) {
2048                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2049                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2050                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2051                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2052         }
2053         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2054         adapter->max_rds_rings = MAX_RDS_RINGS;
2055 }
2056
2057 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2058 {
2059         int err = -EIO;
2060
2061         qlcnic_83xx_get_minidump_template(adapter);
2062         if (qlcnic_83xx_get_port_info(adapter))
2063                 return err;
2064
2065         qlcnic_83xx_config_buff_descriptors(adapter);
2066         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2067         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2068
2069         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2070                  adapter->ahw->fw_hal_version);
2071
2072         return 0;
2073 }
2074
2075 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2076 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2077 {
2078         struct qlcnic_cmd_args cmd;
2079         u32 presence_mask, audit_mask;
2080         int status;
2081
2082         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2083         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2084
2085         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2086                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2087                                                QLCNIC_CMD_STOP_NIC_FUNC);
2088                 if (status)
2089                         return;
2090
2091                 cmd.req.arg[1] = BIT_31;
2092                 status = qlcnic_issue_cmd(adapter, &cmd);
2093                 if (status)
2094                         dev_err(&adapter->pdev->dev,
2095                                 "Failed to clean up the function resources\n");
2096                 qlcnic_free_mbx_args(&cmd);
2097         }
2098 }
2099
2100 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2101 {
2102         struct qlcnic_hardware_context *ahw = adapter->ahw;
2103
2104         if (qlcnic_sriov_vf_check(adapter))
2105                 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2106
2107         if (qlcnic_83xx_check_hw_status(adapter))
2108                 return -EIO;
2109
2110         /* Initilaize 83xx mailbox spinlock */
2111         spin_lock_init(&ahw->mbx_lock);
2112
2113         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2114         qlcnic_83xx_clear_function_resources(adapter);
2115
2116         /* register for NIC IDC AEN Events */
2117         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2118
2119         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2120                 qlcnic_83xx_read_flash_mfg_id(adapter);
2121
2122         if (qlcnic_83xx_idc_init(adapter))
2123                 return -EIO;
2124
2125         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2126         if (qlcnic_83xx_configure_opmode(adapter))
2127                 return -EIO;
2128
2129         /* Perform operating mode specific initialization */
2130         if (adapter->nic_ops->init_driver(adapter))
2131                 return -EIO;
2132
2133         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2134
2135         /* Periodically monitor device status */
2136         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2137
2138         return adapter->ahw->idc.err_code;
2139 }