2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL 0x28084E50
30 #define QLC_83XX_RESET_REG 0x28084E60
31 #define QLC_83XX_RESET_PORT0 0x28084E70
32 #define QLC_83XX_RESET_PORT1 0x28084E80
33 #define QLC_83XX_RESET_PORT2 0x28084E90
34 #define QLC_83XX_RESET_PORT3 0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
44 struct qlc_83xx_reset_hdr {
45 #if defined(__LITTLE_ENDIAN)
54 #elif defined(__BIG_ENDIAN)
66 /* Command entry header. */
67 struct qlc_83xx_entry_hdr {
68 #if defined(__LITTLE_ENDIAN)
73 #elif defined(__BIG_ENDIAN)
81 /* Generic poll command */
82 struct qlc_83xx_poll {
87 /* Read modify write command */
92 #if defined(__LITTLE_ENDIAN)
97 #elif defined(__BIG_ENDIAN)
105 /* Generic command with 2 DWORD */
106 struct qlc_83xx_entry {
111 /* Generic command with 4 DWORD */
112 struct qlc_83xx_quad_entry {
118 static const char *const qlc_83xx_idc_states[] = {
130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
160 if (qlcnic_83xx_lock_driver(adapter))
164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
170 seconds = jiffies / HZ;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
177 qlcnic_83xx_unlock_driver(adapter);
182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
198 if (qlcnic_83xx_lock_driver(adapter))
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
208 qlcnic_83xx_unlock_driver(adapter);
214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
220 if (qlcnic_83xx_lock_driver(adapter))
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
227 val = val | (1 << adapter->portnum);
229 val = val & ~(1 << adapter->portnum);
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
235 qlcnic_83xx_unlock_driver(adapter);
240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
264 if (qlcnic_83xx_lock_driver(adapter))
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
275 qlcnic_83xx_unlock_driver(adapter);
280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
286 if (qlcnic_83xx_lock_driver(adapter))
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
292 val = val | (1 << adapter->portnum);
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
298 qlcnic_83xx_unlock_driver(adapter);
303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
316 * qlcnic_83xx_idc_check_reset_ack_reg
318 * @adapter: adapter structure
320 * Check ACK wait limit and clear the functions which failed to ACK
322 * Return 0 if all functions have acknowledged the reset request.
324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
327 u32 ack, presence, val;
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
347 qlcnic_83xx_unlock_driver(adapter);
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
362 * qlcnic_83xx_idc_tx_soft_reset
364 * @adapter: adapter structure
366 * Handle context deletion and recreation request from transmit routine
368 * Returns -EBUSY or Success (0)
371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
373 struct net_device *netdev = adapter->netdev;
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
389 * qlcnic_83xx_idc_detach_driver
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
399 struct net_device *netdev = adapter->netdev;
401 netif_device_detach(netdev);
403 /* Disable mailbox interrupt */
404 qlcnic_83xx_disable_mbx_intr(adapter);
405 qlcnic_down(adapter, netdev);
406 for (i = 0; i < adapter->ahw->num_msix; i++) {
407 adapter->ahw->intr_tbl[i].id = i;
408 adapter->ahw->intr_tbl[i].enabled = 0;
409 adapter->ahw->intr_tbl[i].src = 0;
412 if (qlcnic_sriov_pf_check(adapter))
413 qlcnic_sriov_pf_reset(adapter);
417 * qlcnic_83xx_idc_attach_driver
419 * @adapter: adapter structure
421 * Re-attach and re-enable net interface
425 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
427 struct net_device *netdev = adapter->netdev;
429 if (netif_running(netdev)) {
430 if (qlcnic_up(adapter, netdev))
432 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
435 netif_device_attach(netdev);
438 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
442 if (qlcnic_83xx_lock_driver(adapter))
446 qlcnic_83xx_idc_clear_registers(adapter, 0);
447 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
449 qlcnic_83xx_unlock_driver(adapter);
451 qlcnic_83xx_idc_log_state_history(adapter);
452 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
457 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
461 if (qlcnic_83xx_lock_driver(adapter))
465 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
468 qlcnic_83xx_unlock_driver(adapter);
473 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
477 if (qlcnic_83xx_lock_driver(adapter))
481 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
482 QLC_83XX_IDC_DEV_NEED_QUISCENT);
485 qlcnic_83xx_unlock_driver(adapter);
491 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
494 if (qlcnic_83xx_lock_driver(adapter))
498 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
499 QLC_83XX_IDC_DEV_NEED_RESET);
502 qlcnic_83xx_unlock_driver(adapter);
507 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
511 if (qlcnic_83xx_lock_driver(adapter))
515 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
517 qlcnic_83xx_unlock_driver(adapter);
523 * qlcnic_83xx_idc_find_reset_owner_id
525 * @adapter: adapter structure
527 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
528 * Within the same class, function with lowest PCI ID assumes ownership
530 * Returns: reset owner id or failure indication (-EIO)
533 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
535 u32 reg, reg1, reg2, i, j, owner, class;
537 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
538 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
539 owner = QLCNIC_TYPE_NIC;
545 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
548 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
555 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
556 if (owner == QLCNIC_TYPE_NIC)
557 owner = QLCNIC_TYPE_ISCSI;
558 else if (owner == QLCNIC_TYPE_ISCSI)
559 owner = QLCNIC_TYPE_FCOE;
560 else if (owner == QLCNIC_TYPE_FCOE)
566 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
571 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
575 ret = qlcnic_83xx_restart_hw(adapter);
578 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
580 qlcnic_83xx_idc_clear_registers(adapter, lock);
581 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
587 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
591 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
593 if (status & QLCNIC_RCODE_FATAL_ERROR) {
594 dev_err(&adapter->pdev->dev,
595 "peg halt status1=0x%x\n", status);
596 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
597 dev_err(&adapter->pdev->dev,
598 "On board active cooling fan failed. "
599 "Device has been halted.\n");
600 dev_err(&adapter->pdev->dev,
601 "Replace the adapter.\n");
609 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
613 /* register for NIC IDC AEN Events */
614 qlcnic_83xx_register_nic_idc_func(adapter, 1);
616 err = qlcnic_sriov_pf_reinit(adapter);
620 qlcnic_83xx_enable_mbx_intrpt(adapter);
622 if (qlcnic_83xx_configure_opmode(adapter)) {
623 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
627 if (adapter->nic_ops->init_driver(adapter)) {
628 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
632 if (adapter->portnum == 0)
633 qlcnic_set_drv_version(adapter);
634 qlcnic_83xx_idc_attach_driver(adapter);
639 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
641 struct qlcnic_hardware_context *ahw = adapter->ahw;
643 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
644 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
645 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
646 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
648 ahw->idc.quiesce_req = 0;
649 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
650 ahw->idc.err_code = 0;
651 ahw->idc.collect_dump = 0;
652 ahw->reset_context = 0;
653 adapter->tx_timeo_cnt = 0;
654 ahw->idc.delay_reset = 0;
656 clear_bit(__QLCNIC_RESETTING, &adapter->state);
660 * qlcnic_83xx_idc_ready_state_entry
662 * @adapter: adapter structure
664 * Perform ready state initialization, this routine will get invoked only
665 * once from READY state.
667 * Returns: Error code or Success(0)
670 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
672 struct qlcnic_hardware_context *ahw = adapter->ahw;
674 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
675 qlcnic_83xx_idc_update_idc_params(adapter);
676 /* Re-attach the device if required */
677 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
678 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
679 if (qlcnic_83xx_idc_reattach_driver(adapter))
688 * qlcnic_83xx_idc_vnic_pf_entry
690 * @adapter: adapter structure
692 * Ensure vNIC mode privileged function starts only after vNIC mode is
693 * enabled by management function.
694 * If vNIC mode is ready, start initialization.
699 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
702 struct qlcnic_hardware_context *ahw = adapter->ahw;
704 /* Privileged function waits till mgmt function enables VNIC mode */
705 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
706 if (state != QLCNIC_DEV_NPAR_OPER) {
707 if (!ahw->idc.vnic_wait_limit--) {
708 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
711 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
715 /* Perform one time initialization from ready state */
716 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
717 qlcnic_83xx_idc_update_idc_params(adapter);
719 /* If the previous state is UNKNOWN, device will be
720 already attached properly by Init routine*/
721 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
722 if (qlcnic_83xx_idc_reattach_driver(adapter))
725 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
726 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
733 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
735 adapter->ahw->idc.err_code = -EIO;
736 dev_err(&adapter->pdev->dev,
737 "%s: Device in unknown state\n", __func__);
742 * qlcnic_83xx_idc_cold_state
744 * @adapter: adapter structure
746 * If HW is up and running device will enter READY state.
747 * If firmware image from host needs to be loaded, device is
748 * forced to start with the file firmware image.
750 * Returns: Error code or Success(0)
753 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
755 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
756 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
758 if (qlcnic_load_fw_file) {
759 qlcnic_83xx_idc_restart_hw(adapter, 0);
761 if (qlcnic_83xx_check_hw_status(adapter)) {
762 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
765 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
772 * qlcnic_83xx_idc_init_state
774 * @adapter: adapter structure
776 * Reset owner will restart the device from this state.
777 * Device will enter failed state if it remains
778 * in this state for more than DEV_INIT time limit.
780 * Returns: Error code or Success(0)
783 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
785 int timeout, ret = 0;
788 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
789 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
790 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
791 if (adapter->ahw->pci_func == owner)
792 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
794 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
802 * qlcnic_83xx_idc_ready_state
804 * @adapter: adapter structure
806 * Perform IDC protocol specicifed actions after monitoring device state and
809 * Returns: Error code or Success(0)
812 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
815 struct qlcnic_hardware_context *ahw = adapter->ahw;
818 /* Perform NIC configuration based ready state entry actions */
819 if (ahw->idc.state_entry(adapter))
822 if (qlcnic_check_temp(adapter)) {
823 if (ahw->temp == QLCNIC_TEMP_PANIC) {
824 qlcnic_83xx_idc_check_fan_failure(adapter);
825 dev_err(&adapter->pdev->dev,
826 "Error: device temperature %d above limits\n",
828 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
829 set_bit(__QLCNIC_RESETTING, &adapter->state);
830 qlcnic_83xx_idc_detach_driver(adapter);
831 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
836 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
837 ret = qlcnic_83xx_check_heartbeat(adapter);
839 adapter->flags |= QLCNIC_FW_HANG;
840 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
841 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
842 set_bit(__QLCNIC_RESETTING, &adapter->state);
843 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
848 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
849 /* Move to need reset state and prepare for reset */
850 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
854 /* Check for soft reset request */
855 if (ahw->reset_context &&
856 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
857 adapter->ahw->reset_context = 0;
858 qlcnic_83xx_idc_tx_soft_reset(adapter);
862 /* Move to need quiesce state if requested */
863 if (adapter->ahw->idc.quiesce_req) {
864 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
865 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
873 * qlcnic_83xx_idc_need_reset_state
875 * @adapter: adapter structure
877 * Device will remain in this state until:
878 * Reset request ACK's are recieved from all the functions
879 * Wait time exceeds max time limit
881 * Returns: Error code or Success(0)
884 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
888 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
889 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
890 set_bit(__QLCNIC_RESETTING, &adapter->state);
891 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
892 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
893 qlcnic_83xx_disable_vnic_mode(adapter, 1);
895 if (qlcnic_check_diag_status(adapter)) {
896 dev_info(&adapter->pdev->dev,
897 "%s: Wait for diag completion\n", __func__);
898 adapter->ahw->idc.delay_reset = 1;
901 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
902 qlcnic_83xx_idc_detach_driver(adapter);
906 if (qlcnic_check_diag_status(adapter)) {
907 dev_info(&adapter->pdev->dev,
908 "%s: Wait for diag completion\n", __func__);
911 if (adapter->ahw->idc.delay_reset) {
912 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
913 qlcnic_83xx_idc_detach_driver(adapter);
914 adapter->ahw->idc.delay_reset = 0;
917 /* Check for ACK from other functions */
918 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
920 dev_info(&adapter->pdev->dev,
921 "%s: Waiting for reset ACK\n", __func__);
926 /* Transit to INIT state and restart the HW */
927 qlcnic_83xx_idc_enter_init_state(adapter, 1);
932 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
934 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
938 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
940 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
941 clear_bit(__QLCNIC_RESETTING, &adapter->state);
942 adapter->ahw->idc.err_code = -EIO;
947 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
949 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
953 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
958 cur = adapter->ahw->idc.curr_state;
959 prev = adapter->ahw->idc.prev_state;
962 if ((next < QLC_83XX_IDC_DEV_COLD) ||
963 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
964 dev_err(&adapter->pdev->dev,
965 "%s: curr %d, prev %d, next state %d is invalid\n",
966 __func__, cur, prev, state);
970 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
971 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
972 if ((next != QLC_83XX_IDC_DEV_COLD) &&
973 (next != QLC_83XX_IDC_DEV_READY)) {
974 dev_err(&adapter->pdev->dev,
975 "%s: failed, cur %d prev %d next %d\n",
976 __func__, cur, prev, next);
981 if (next == QLC_83XX_IDC_DEV_INIT) {
982 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
983 (prev != QLC_83XX_IDC_DEV_COLD) &&
984 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
985 dev_err(&adapter->pdev->dev,
986 "%s: failed, cur %d prev %d next %d\n",
987 __func__, cur, prev, next);
995 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
997 if (adapter->fhash.fnum)
998 qlcnic_prune_lb_filters(adapter);
1002 * qlcnic_83xx_idc_poll_dev_state
1004 * @work: kernel work queue structure used to schedule the function
1006 * Poll device state periodically and perform state specific
1007 * actions defined by Inter Driver Communication (IDC) protocol.
1012 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1014 struct qlcnic_adapter *adapter;
1017 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1018 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1020 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1021 qlcnic_83xx_idc_log_state_history(adapter);
1022 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1024 adapter->ahw->idc.curr_state = state;
1027 switch (adapter->ahw->idc.curr_state) {
1028 case QLC_83XX_IDC_DEV_READY:
1029 qlcnic_83xx_idc_ready_state(adapter);
1031 case QLC_83XX_IDC_DEV_NEED_RESET:
1032 qlcnic_83xx_idc_need_reset_state(adapter);
1034 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1035 qlcnic_83xx_idc_need_quiesce_state(adapter);
1037 case QLC_83XX_IDC_DEV_FAILED:
1038 qlcnic_83xx_idc_failed_state(adapter);
1040 case QLC_83XX_IDC_DEV_INIT:
1041 qlcnic_83xx_idc_init_state(adapter);
1043 case QLC_83XX_IDC_DEV_QUISCENT:
1044 qlcnic_83xx_idc_quiesce_state(adapter);
1047 qlcnic_83xx_idc_unknown_state(adapter);
1050 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1051 qlcnic_83xx_periodic_tasks(adapter);
1053 /* Re-schedule the function */
1054 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1055 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1056 adapter->ahw->idc.delay);
1059 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1061 u32 idc_params, val;
1063 if (qlcnic_83xx_lockless_flash_read32(adapter,
1064 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1065 (u8 *)&idc_params, 1)) {
1066 dev_info(&adapter->pdev->dev,
1067 "%s:failed to get IDC params from flash\n", __func__);
1068 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1069 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1071 adapter->dev_init_timeo = idc_params & 0xFFFF;
1072 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1075 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1076 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1077 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1078 adapter->ahw->idc.err_code = 0;
1079 adapter->ahw->idc.collect_dump = 0;
1080 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1082 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1083 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1084 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1086 /* Check if reset recovery is disabled */
1087 if (!qlcnic_auto_fw_reset) {
1088 /* Propagate do not reset request to other functions */
1089 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1090 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1091 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1096 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1100 if (qlcnic_83xx_lock_driver(adapter))
1103 /* Clear driver lock register */
1104 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1105 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1106 qlcnic_83xx_unlock_driver(adapter);
1110 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1111 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1112 qlcnic_83xx_unlock_driver(adapter);
1116 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1117 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1118 QLC_83XX_IDC_DEV_COLD);
1119 state = QLC_83XX_IDC_DEV_COLD;
1122 adapter->ahw->idc.curr_state = state;
1123 /* First to load function should cold boot the device */
1124 if (state == QLC_83XX_IDC_DEV_COLD)
1125 qlcnic_83xx_idc_cold_state_handler(adapter);
1127 /* Check if reset recovery is enabled */
1128 if (qlcnic_auto_fw_reset) {
1129 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1130 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1131 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1134 qlcnic_83xx_unlock_driver(adapter);
1139 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1143 qlcnic_83xx_setup_idc_parameters(adapter);
1145 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1148 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1149 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1152 if (qlcnic_83xx_idc_check_major_version(adapter))
1156 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1161 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1166 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1167 usleep_range(10000, 11000);
1169 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1172 if (id == adapter->portnum) {
1173 dev_err(&adapter->pdev->dev,
1174 "%s: wait for lock recovery.. %d\n", __func__, id);
1176 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1180 /* Clear driver presence bit */
1181 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1182 val = val & ~(1 << adapter->portnum);
1183 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1184 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1185 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1187 cancel_delayed_work_sync(&adapter->fw_work);
1190 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1194 if (qlcnic_83xx_lock_driver(adapter)) {
1195 dev_err(&adapter->pdev->dev,
1196 "%s:failed, please retry\n", __func__);
1200 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1201 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1202 !qlcnic_auto_fw_reset) {
1203 dev_err(&adapter->pdev->dev,
1204 "%s:failed, device in non reset mode\n", __func__);
1205 qlcnic_83xx_unlock_driver(adapter);
1209 if (key == QLCNIC_FORCE_FW_RESET) {
1210 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1211 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1212 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1213 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1214 adapter->ahw->idc.collect_dump = 1;
1217 qlcnic_83xx_unlock_driver(adapter);
1221 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1228 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1229 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1230 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1232 /* alignment check */
1234 size = (size + 16) & ~0xF;
1236 p_cache = kzalloc(size, GFP_KERNEL);
1237 if (p_cache == NULL)
1240 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1241 size / sizeof(u32));
1246 /* 16 byte write to MS memory */
1247 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1258 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1266 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1267 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1268 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1271 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1272 (u32 *)p_cache, size / 16);
1274 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1275 release_firmware(adapter->ahw->fw_info.fw);
1276 adapter->ahw->fw_info.fw = NULL;
1280 /* alignment check */
1281 if (adapter->ahw->fw_info.fw->size & 0xF) {
1283 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1284 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1287 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1290 dev_err(&adapter->pdev->dev,
1291 "MS memory write failed\n");
1292 release_firmware(adapter->ahw->fw_info.fw);
1293 adapter->ahw->fw_info.fw = NULL;
1297 release_firmware(adapter->ahw->fw_info.fw);
1298 adapter->ahw->fw_info.fw = NULL;
1303 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1306 u32 val = 0, val1 = 0, reg = 0;
1309 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1312 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1314 for (j = 0; j < 2; j++) {
1316 dev_info(&adapter->pdev->dev,
1317 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1318 reg = QLC_83XX_PORT0_THRESHOLD;
1319 } else if (j == 1) {
1320 dev_info(&adapter->pdev->dev,
1321 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1322 reg = QLC_83XX_PORT1_THRESHOLD;
1324 for (i = 0; i < 8; i++) {
1325 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1328 dev_info(&adapter->pdev->dev, "0x%x ", val);
1330 dev_info(&adapter->pdev->dev, "\n");
1333 for (j = 0; j < 2; j++) {
1335 dev_info(&adapter->pdev->dev,
1336 "Port 0 RxB TC Max Cell Registers[4..1]:");
1337 reg = QLC_83XX_PORT0_TC_MC_REG;
1338 } else if (j == 1) {
1339 dev_info(&adapter->pdev->dev,
1340 "Port 1 RxB TC Max Cell Registers[4..1]:");
1341 reg = QLC_83XX_PORT1_TC_MC_REG;
1343 for (i = 0; i < 4; i++) {
1344 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1347 dev_info(&adapter->pdev->dev, "0x%x ", val);
1349 dev_info(&adapter->pdev->dev, "\n");
1352 for (j = 0; j < 2; j++) {
1354 dev_info(&adapter->pdev->dev,
1355 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1356 reg = QLC_83XX_PORT0_TC_STATS;
1357 } else if (j == 1) {
1358 dev_info(&adapter->pdev->dev,
1359 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1360 reg = QLC_83XX_PORT1_TC_STATS;
1362 for (i = 7; i >= 0; i--) {
1363 val = QLCRD32(adapter, reg, &err);
1366 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1367 QLCWR32(adapter, reg, (val | (i << 29)));
1368 val = QLCRD32(adapter, reg, &err);
1371 dev_info(&adapter->pdev->dev, "0x%x ", val);
1373 dev_info(&adapter->pdev->dev, "\n");
1376 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1379 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1382 dev_info(&adapter->pdev->dev,
1383 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1388 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1392 if (qlcnic_83xx_lock_driver(adapter)) {
1393 dev_err(&adapter->pdev->dev,
1394 "%s:failed to acquire driver lock\n", __func__);
1398 qlcnic_83xx_dump_pause_control_regs(adapter);
1399 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1401 for (j = 0; j < 2; j++) {
1403 reg = QLC_83XX_PORT0_THRESHOLD;
1405 reg = QLC_83XX_PORT1_THRESHOLD;
1407 for (i = 0; i < 8; i++)
1408 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1411 for (j = 0; j < 2; j++) {
1413 reg = QLC_83XX_PORT0_TC_MC_REG;
1415 reg = QLC_83XX_PORT1_TC_MC_REG;
1417 for (i = 0; i < 4; i++)
1418 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1421 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1422 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1423 dev_info(&adapter->pdev->dev,
1424 "Disabled pause frames successfully on all ports\n");
1425 qlcnic_83xx_unlock_driver(adapter);
1428 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1430 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1431 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1432 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1433 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1434 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1435 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1436 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1437 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1438 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1441 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1443 u32 heartbeat, peg_status;
1444 int retries, ret = -EIO, err = 0;
1446 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1447 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1448 QLCNIC_PEG_ALIVE_COUNTER);
1451 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1452 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1453 QLCNIC_PEG_ALIVE_COUNTER);
1454 if (heartbeat != p_dev->heartbeat) {
1455 ret = QLCNIC_RCODE_SUCCESS;
1458 } while (--retries);
1461 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1462 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1463 qlcnic_83xx_disable_pause_frames(p_dev);
1464 peg_status = QLC_SHARED_REG_RD32(p_dev,
1465 QLCNIC_PEG_HALT_STATUS1);
1466 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1467 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1468 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1469 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1470 "PEG_NET_4_PC: 0x%x\n", peg_status,
1471 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1472 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1473 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1474 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1475 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1476 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1478 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1479 dev_err(&p_dev->pdev->dev,
1480 "Device is being reset err code 0x00006700.\n");
1486 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1488 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1492 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1493 if (val == QLC_83XX_CMDPEG_COMPLETE)
1495 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1496 } while (--retries);
1498 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1502 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1506 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1510 err = qlcnic_83xx_check_heartbeat(p_dev);
1517 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1518 int duration, u32 mask, u32 status)
1520 int timeout_error, err = 0;
1524 value = QLCRD32(p_dev, addr, &err);
1527 retries = duration / 10;
1530 if ((value & mask) != status) {
1532 msleep(duration / 10);
1533 value = QLCRD32(p_dev, addr, &err);
1540 } while (retries--);
1542 if (timeout_error) {
1543 p_dev->ahw->reset.seq_error++;
1544 dev_err(&p_dev->pdev->dev,
1545 "%s: Timeout Err, entry_num = %d\n",
1546 __func__, p_dev->ahw->reset.seq_index);
1547 dev_err(&p_dev->pdev->dev,
1548 "0x%08x 0x%08x 0x%08x\n",
1549 value, mask, status);
1552 return timeout_error;
1555 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1558 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1559 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1565 sum = (sum & 0xFFFF) + (sum >> 16);
1570 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1575 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1577 struct qlcnic_hardware_context *ahw = p_dev->ahw;
1578 u32 addr, count, prev_ver, curr_ver;
1581 if (ahw->reset.buff != NULL) {
1582 prev_ver = p_dev->fw_version;
1583 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1584 if (curr_ver > prev_ver)
1585 kfree(ahw->reset.buff);
1590 ahw->reset.seq_error = 0;
1591 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1592 if (p_dev->ahw->reset.buff == NULL)
1595 p_buff = p_dev->ahw->reset.buff;
1596 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1597 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1599 /* Copy template header from flash */
1600 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1601 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1604 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1605 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1606 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1607 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1609 /* Copy rest of the template */
1610 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1611 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1615 if (qlcnic_83xx_reset_template_checksum(p_dev))
1617 /* Get Stop, Start and Init command offsets */
1618 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1619 ahw->reset.start_offset = ahw->reset.buff +
1620 ahw->reset.hdr->start_offset;
1621 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1625 /* Read Write HW register command */
1626 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1627 u32 raddr, u32 waddr)
1632 value = QLCRD32(p_dev, raddr, &err);
1635 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1638 /* Read Modify Write HW register command */
1639 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1640 u32 raddr, u32 waddr,
1641 struct qlc_83xx_rmw *p_rmw_hdr)
1646 if (p_rmw_hdr->index_a) {
1647 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1649 value = QLCRD32(p_dev, raddr, &err);
1654 value &= p_rmw_hdr->mask;
1655 value <<= p_rmw_hdr->shl;
1656 value >>= p_rmw_hdr->shr;
1657 value |= p_rmw_hdr->or_value;
1658 value ^= p_rmw_hdr->xor_value;
1659 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1662 /* Write HW register command */
1663 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1664 struct qlc_83xx_entry_hdr *p_hdr)
1667 struct qlc_83xx_entry *entry;
1669 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1670 sizeof(struct qlc_83xx_entry_hdr));
1672 for (i = 0; i < p_hdr->count; i++, entry++) {
1673 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1676 udelay((u32)(p_hdr->delay));
1680 /* Read and Write instruction */
1681 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1682 struct qlc_83xx_entry_hdr *p_hdr)
1685 struct qlc_83xx_entry *entry;
1687 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1688 sizeof(struct qlc_83xx_entry_hdr));
1690 for (i = 0; i < p_hdr->count; i++, entry++) {
1691 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1694 udelay((u32)(p_hdr->delay));
1698 /* Poll HW register command */
1699 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1700 struct qlc_83xx_entry_hdr *p_hdr)
1703 struct qlc_83xx_entry *entry;
1704 struct qlc_83xx_poll *poll;
1706 unsigned long arg1, arg2;
1708 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1709 sizeof(struct qlc_83xx_entry_hdr));
1711 entry = (struct qlc_83xx_entry *)((char *)poll +
1712 sizeof(struct qlc_83xx_poll));
1713 delay = (long)p_hdr->delay;
1716 for (i = 0; i < p_hdr->count; i++, entry++)
1717 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1721 for (i = 0; i < p_hdr->count; i++, entry++) {
1725 if (qlcnic_83xx_poll_reg(p_dev,
1729 QLCRD32(p_dev, arg1, &err);
1732 QLCRD32(p_dev, arg2, &err);
1741 /* Poll and write HW register command */
1742 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1743 struct qlc_83xx_entry_hdr *p_hdr)
1747 struct qlc_83xx_quad_entry *entry;
1748 struct qlc_83xx_poll *poll;
1750 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1751 sizeof(struct qlc_83xx_entry_hdr));
1752 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1753 sizeof(struct qlc_83xx_poll));
1754 delay = (long)p_hdr->delay;
1756 for (i = 0; i < p_hdr->count; i++, entry++) {
1757 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1759 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1762 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1763 poll->mask, poll->status);
1767 /* Read Modify Write register command */
1768 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1769 struct qlc_83xx_entry_hdr *p_hdr)
1772 struct qlc_83xx_entry *entry;
1773 struct qlc_83xx_rmw *rmw_hdr;
1775 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1776 sizeof(struct qlc_83xx_entry_hdr));
1778 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1779 sizeof(struct qlc_83xx_rmw));
1781 for (i = 0; i < p_hdr->count; i++, entry++) {
1782 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1783 entry->arg2, rmw_hdr);
1785 udelay((u32)(p_hdr->delay));
1789 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1792 mdelay((u32)((long)p_hdr->delay));
1795 /* Read and poll register command */
1796 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1797 struct qlc_83xx_entry_hdr *p_hdr)
1800 int index, i, j, err;
1801 struct qlc_83xx_quad_entry *entry;
1802 struct qlc_83xx_poll *poll;
1805 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1806 sizeof(struct qlc_83xx_entry_hdr));
1808 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1809 sizeof(struct qlc_83xx_poll));
1810 delay = (long)p_hdr->delay;
1812 for (i = 0; i < p_hdr->count; i++, entry++) {
1813 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1816 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1817 poll->mask, poll->status)){
1818 index = p_dev->ahw->reset.array_index;
1819 addr = entry->dr_addr;
1820 j = QLCRD32(p_dev, addr, &err);
1824 p_dev->ahw->reset.array[index++] = j;
1826 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1827 p_dev->ahw->reset.array_index = 1;
1833 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1835 p_dev->ahw->reset.seq_end = 1;
1838 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1840 p_dev->ahw->reset.template_end = 1;
1841 if (p_dev->ahw->reset.seq_error == 0)
1842 dev_err(&p_dev->pdev->dev,
1843 "HW restart process completed successfully.\n");
1845 dev_err(&p_dev->pdev->dev,
1846 "HW restart completed with timeout errors.\n");
1850 * qlcnic_83xx_exec_template_cmd
1852 * @p_dev: adapter structure
1853 * @p_buff: Poiter to instruction template
1855 * Template provides instructions to stop, restart and initalize firmware.
1856 * These instructions are abstracted as a series of read, write and
1857 * poll operations on hardware registers. Register information and operation
1858 * specifics are not exposed to the driver. Driver reads the template from
1859 * flash and executes the instructions located at pre-defined offsets.
1863 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1867 struct qlc_83xx_entry_hdr *p_hdr;
1868 char *entry = p_buff;
1870 p_dev->ahw->reset.seq_end = 0;
1871 p_dev->ahw->reset.template_end = 0;
1872 entries = p_dev->ahw->reset.hdr->entries;
1873 index = p_dev->ahw->reset.seq_index;
1875 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1876 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1878 switch (p_hdr->cmd) {
1879 case QLC_83XX_OPCODE_NOP:
1881 case QLC_83XX_OPCODE_WRITE_LIST:
1882 qlcnic_83xx_write_list(p_dev, p_hdr);
1884 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1885 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1887 case QLC_83XX_OPCODE_POLL_LIST:
1888 qlcnic_83xx_poll_list(p_dev, p_hdr);
1890 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1891 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1893 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1894 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1896 case QLC_83XX_OPCODE_SEQ_PAUSE:
1897 qlcnic_83xx_pause(p_hdr);
1899 case QLC_83XX_OPCODE_SEQ_END:
1900 qlcnic_83xx_seq_end(p_dev);
1902 case QLC_83XX_OPCODE_TMPL_END:
1903 qlcnic_83xx_template_end(p_dev);
1905 case QLC_83XX_OPCODE_POLL_READ_LIST:
1906 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1909 dev_err(&p_dev->pdev->dev,
1910 "%s: Unknown opcode 0x%04x in template %d\n",
1911 __func__, p_hdr->cmd, index);
1914 entry += p_hdr->size;
1916 p_dev->ahw->reset.seq_index = index;
1919 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1921 p_dev->ahw->reset.seq_index = 0;
1923 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1924 if (p_dev->ahw->reset.seq_end != 1)
1925 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1928 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1930 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1931 if (p_dev->ahw->reset.template_end != 1)
1932 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1935 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1937 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1938 if (p_dev->ahw->reset.seq_end != 1)
1939 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1942 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1946 if (request_firmware(&adapter->ahw->fw_info.fw,
1947 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1948 dev_err(&adapter->pdev->dev,
1949 "No file FW image, loading flash FW image.\n");
1950 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1951 QLC_83XX_BOOT_FROM_FLASH);
1953 if (qlcnic_83xx_copy_fw_file(adapter))
1955 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1956 QLC_83XX_BOOT_FROM_FILE);
1962 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1967 qlcnic_83xx_stop_hw(adapter);
1969 /* Collect FW register dump if required */
1970 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1971 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1972 qlcnic_dump_fw(adapter);
1973 qlcnic_83xx_init_hw(adapter);
1975 if (qlcnic_83xx_copy_bootloader(adapter))
1977 /* Boot either flash image or firmware image from host file system */
1978 if (qlcnic_load_fw_file) {
1979 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1982 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1983 QLC_83XX_BOOT_FROM_FLASH);
1986 qlcnic_83xx_start_hw(adapter);
1987 if (qlcnic_83xx_check_hw_status(adapter))
1994 * qlcnic_83xx_config_default_opmode
1996 * @adapter: adapter structure
1998 * Configure default driver operating mode
2000 * Returns: Error code or Success(0)
2002 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
2005 struct qlcnic_hardware_context *ahw = adapter->ahw;
2007 qlcnic_get_func_no(adapter);
2008 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
2010 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2011 op_mode = QLC_83XX_DEFAULT_OPMODE;
2013 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
2014 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2015 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2023 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2026 struct qlcnic_info nic_info;
2027 struct qlcnic_hardware_context *ahw = adapter->ahw;
2029 memset(&nic_info, 0, sizeof(struct qlcnic_info));
2030 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2034 ahw->physical_port = (u8) nic_info.phys_port;
2035 ahw->switch_mode = nic_info.switch_mode;
2036 ahw->max_tx_ques = nic_info.max_tx_ques;
2037 ahw->max_rx_ques = nic_info.max_rx_ques;
2038 ahw->capabilities = nic_info.capabilities;
2039 ahw->max_mac_filters = nic_info.max_mac_filters;
2040 ahw->max_mtu = nic_info.max_mtu;
2042 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2043 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2044 * exclusive. So in case of sriov capable device load driver in
2047 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2048 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2049 return ahw->nic_mode;
2052 if (ahw->capabilities & BIT_23)
2053 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2055 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2057 return ahw->nic_mode;
2060 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2064 ret = qlcnic_83xx_get_nic_configuration(adapter);
2068 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2069 if (qlcnic_83xx_config_vnic_opmode(adapter))
2071 } else if (ret == QLC_83XX_DEFAULT_MODE) {
2072 if (qlcnic_83xx_config_default_opmode(adapter))
2079 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2081 struct qlcnic_hardware_context *ahw = adapter->ahw;
2083 if (ahw->port_type == QLCNIC_XGBE) {
2084 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2085 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2086 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2087 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2089 } else if (ahw->port_type == QLCNIC_GBE) {
2090 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2091 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2092 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2093 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2095 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2096 adapter->max_rds_rings = MAX_RDS_RINGS;
2099 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2103 qlcnic_83xx_get_minidump_template(adapter);
2104 if (qlcnic_83xx_get_port_info(adapter))
2107 qlcnic_83xx_config_buff_descriptors(adapter);
2108 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2109 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2111 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2112 adapter->ahw->fw_hal_version);
2117 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2118 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2120 struct qlcnic_cmd_args cmd;
2121 u32 presence_mask, audit_mask;
2124 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2125 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2127 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2128 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2129 QLCNIC_CMD_STOP_NIC_FUNC);
2133 cmd.req.arg[1] = BIT_31;
2134 status = qlcnic_issue_cmd(adapter, &cmd);
2136 dev_err(&adapter->pdev->dev,
2137 "Failed to clean up the function resources\n");
2138 qlcnic_free_mbx_args(&cmd);
2142 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2144 struct qlcnic_hardware_context *ahw = adapter->ahw;
2146 if (qlcnic_sriov_vf_check(adapter))
2147 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2149 if (qlcnic_83xx_check_hw_status(adapter))
2152 /* Initilaize 83xx mailbox spinlock */
2153 spin_lock_init(&ahw->mbx_lock);
2155 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2156 qlcnic_83xx_clear_function_resources(adapter);
2158 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2160 /* register for NIC IDC AEN Events */
2161 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2163 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2164 qlcnic_83xx_read_flash_mfg_id(adapter);
2166 if (qlcnic_83xx_idc_init(adapter))
2169 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2170 if (qlcnic_83xx_configure_opmode(adapter))
2173 /* Perform operating mode specific initialization */
2174 if (adapter->nic_ops->init_driver(adapter))
2177 /* Periodically monitor device status */
2178 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2180 return adapter->ahw->idc.err_code;