2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include <linux/types.h>
11 #define QLC_DCB_NUM_PARAM 3
12 #define QLC_DCB_LOCAL_IDX 0
13 #define QLC_DCB_OPER_IDX 1
14 #define QLC_DCB_PEER_IDX 2
16 #define QLC_DCB_GET_MAP(V) (1 << V)
18 #define QLC_DCB_AEN_BIT 0x2
19 #define QLC_DCB_FW_VER 0x2
20 #define QLC_DCB_MAX_TC 0x8
21 #define QLC_DCB_MAX_APP 0x8
22 #define QLC_DCB_MAX_PRIO QLC_DCB_MAX_TC
23 #define QLC_DCB_MAX_PG QLC_DCB_MAX_TC
25 #define QLC_DCB_TSA_SUPPORT(V) (V & 0x1)
26 #define QLC_DCB_ETS_SUPPORT(V) ((V >> 1) & 0x1)
27 #define QLC_DCB_VERSION_SUPPORT(V) ((V >> 2) & 0xf)
28 #define QLC_DCB_MAX_NUM_TC(V) ((V >> 20) & 0xf)
29 #define QLC_DCB_MAX_NUM_ETS_TC(V) ((V >> 24) & 0xf)
30 #define QLC_DCB_MAX_NUM_PFC_TC(V) ((V >> 28) & 0xf)
31 #define QLC_DCB_GET_TC_PRIO(X, P) ((X >> (P * 3)) & 0x7)
32 #define QLC_DCB_GET_PGID_PRIO(X, P) ((X >> (P * 8)) & 0xff)
33 #define QLC_DCB_GET_BWPER_PG(X, P) ((X >> (P * 8)) & 0xff)
34 #define QLC_DCB_GET_TSA_PG(X, P) ((X >> (P * 8)) & 0xff)
35 #define QLC_DCB_GET_PFC_PRIO(X, P) (((X >> 24) >> P) & 0x1)
36 #define QLC_DCB_GET_PROTO_ID_APP(X) ((X >> 8) & 0xffff)
37 #define QLC_DCB_GET_SELECTOR_APP(X) (X & 0xff)
39 #define QLC_DCB_LOCAL_PARAM_FWID 0x3
40 #define QLC_DCB_OPER_PARAM_FWID 0x1
41 #define QLC_DCB_PEER_PARAM_FWID 0x2
43 #define QLC_83XX_DCB_GET_NUMAPP(X) ((X >> 2) & 0xf)
44 #define QLC_83XX_DCB_TSA_VALID(X) (X & 0x1)
45 #define QLC_83XX_DCB_PFC_VALID(X) ((X >> 1) & 0x1)
46 #define QLC_83XX_DCB_GET_PRIOMAP_APP(X) (X >> 24)
48 #define QLC_82XX_DCB_GET_NUMAPP(X) ((X >> 12) & 0xf)
49 #define QLC_82XX_DCB_TSA_VALID(X) ((X >> 4) & 0x1)
50 #define QLC_82XX_DCB_PFC_VALID(X) ((X >> 5) & 0x1)
51 #define QLC_82XX_DCB_GET_PRIOVAL_APP(X) ((X >> 24) & 0x7)
52 #define QLC_82XX_DCB_GET_PRIOMAP_APP(X) (1 << X)
53 #define QLC_82XX_DCB_PRIO_TC_MAP (0x76543210)
55 static const struct dcbnl_rtnl_ops qlcnic_dcbnl_ops;
57 static void qlcnic_dcb_aen_work(struct work_struct *);
58 static void qlcnic_dcb_data_cee_param_map(struct qlcnic_adapter *);
60 static inline void __qlcnic_init_dcbnl_ops(struct qlcnic_dcb *);
61 static void __qlcnic_dcb_free(struct qlcnic_dcb *);
62 static int __qlcnic_dcb_attach(struct qlcnic_dcb *);
63 static int __qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *, char *);
64 static void __qlcnic_dcb_get_info(struct qlcnic_dcb *);
66 static int qlcnic_82xx_dcb_get_hw_capability(struct qlcnic_dcb *);
67 static int qlcnic_82xx_dcb_query_cee_param(struct qlcnic_dcb *, char *, u8);
68 static int qlcnic_82xx_dcb_get_cee_cfg(struct qlcnic_dcb *);
69 static void qlcnic_82xx_dcb_aen_handler(struct qlcnic_dcb *, void *);
71 static int qlcnic_83xx_dcb_get_hw_capability(struct qlcnic_dcb *);
72 static int qlcnic_83xx_dcb_query_cee_param(struct qlcnic_dcb *, char *, u8);
73 static int qlcnic_83xx_dcb_get_cee_cfg(struct qlcnic_dcb *);
74 static int qlcnic_83xx_dcb_register_aen(struct qlcnic_dcb *, bool);
75 static void qlcnic_83xx_dcb_aen_handler(struct qlcnic_dcb *, void *);
77 struct qlcnic_dcb_capability {
86 struct qlcnic_dcb_param {
87 u32 hdr_prio_pfc_map[2];
91 u32 app[QLC_DCB_MAX_APP];
94 struct qlcnic_dcb_mbx_params {
95 /* 1st local, 2nd operational 3rd remote */
96 struct qlcnic_dcb_param type[3];
100 struct qlcnic_82xx_dcb_param_mbx_le {
101 __le32 hdr_prio_pfc_map[2];
102 __le32 prio_pg_map[2];
104 __le32 pg_tsa_map[2];
105 __le32 app[QLC_DCB_MAX_APP];
108 enum qlcnic_dcb_selector {
109 QLC_SELECTOR_DEF = 0x0,
115 enum qlcnic_dcb_prio_type {
121 enum qlcnic_dcb_pfc_type {
122 QLC_PFC_DISABLED = 0,
128 struct qlcnic_dcb_prio_cfg {
130 enum qlcnic_dcb_pfc_type pfc_type;
133 struct qlcnic_dcb_pg_cfg {
135 u8 total_bw_percent; /* of Link/ port BW */
140 struct qlcnic_dcb_tc_cfg {
142 struct qlcnic_dcb_prio_cfg prio_cfg[QLC_DCB_MAX_PRIO];
143 enum qlcnic_dcb_prio_type prio_type; /* always prio_link */
144 u8 link_percent; /* % of link bandwidth */
145 u8 bwg_percent; /* % of BWG's bandwidth */
150 struct qlcnic_dcb_app {
152 enum qlcnic_dcb_selector selector;
157 struct qlcnic_dcb_cee {
158 struct qlcnic_dcb_tc_cfg tc_cfg[QLC_DCB_MAX_TC];
159 struct qlcnic_dcb_pg_cfg pg_cfg[QLC_DCB_MAX_PG];
160 struct qlcnic_dcb_app app[QLC_DCB_MAX_APP];
162 bool pfc_mode_enable;
165 struct qlcnic_dcb_cfg {
166 /* 0 - local, 1 - operational, 2 - remote */
167 struct qlcnic_dcb_cee type[QLC_DCB_NUM_PARAM];
168 struct qlcnic_dcb_capability capability;
172 static struct qlcnic_dcb_ops qlcnic_83xx_dcb_ops = {
173 .init_dcbnl_ops = __qlcnic_init_dcbnl_ops,
174 .free = __qlcnic_dcb_free,
175 .attach = __qlcnic_dcb_attach,
176 .query_hw_capability = __qlcnic_dcb_query_hw_capability,
177 .get_info = __qlcnic_dcb_get_info,
179 .get_hw_capability = qlcnic_83xx_dcb_get_hw_capability,
180 .query_cee_param = qlcnic_83xx_dcb_query_cee_param,
181 .get_cee_cfg = qlcnic_83xx_dcb_get_cee_cfg,
182 .register_aen = qlcnic_83xx_dcb_register_aen,
183 .aen_handler = qlcnic_83xx_dcb_aen_handler,
186 static struct qlcnic_dcb_ops qlcnic_82xx_dcb_ops = {
187 .init_dcbnl_ops = __qlcnic_init_dcbnl_ops,
188 .free = __qlcnic_dcb_free,
189 .attach = __qlcnic_dcb_attach,
190 .query_hw_capability = __qlcnic_dcb_query_hw_capability,
191 .get_info = __qlcnic_dcb_get_info,
193 .get_hw_capability = qlcnic_82xx_dcb_get_hw_capability,
194 .query_cee_param = qlcnic_82xx_dcb_query_cee_param,
195 .get_cee_cfg = qlcnic_82xx_dcb_get_cee_cfg,
196 .aen_handler = qlcnic_82xx_dcb_aen_handler,
199 static u8 qlcnic_dcb_get_num_app(struct qlcnic_adapter *adapter, u32 val)
201 if (qlcnic_82xx_check(adapter))
202 return QLC_82XX_DCB_GET_NUMAPP(val);
204 return QLC_83XX_DCB_GET_NUMAPP(val);
207 static inline u8 qlcnic_dcb_pfc_hdr_valid(struct qlcnic_adapter *adapter,
210 if (qlcnic_82xx_check(adapter))
211 return QLC_82XX_DCB_PFC_VALID(val);
213 return QLC_83XX_DCB_PFC_VALID(val);
216 static inline u8 qlcnic_dcb_tsa_hdr_valid(struct qlcnic_adapter *adapter,
219 if (qlcnic_82xx_check(adapter))
220 return QLC_82XX_DCB_TSA_VALID(val);
222 return QLC_83XX_DCB_TSA_VALID(val);
225 static inline u8 qlcnic_dcb_get_prio_map_app(struct qlcnic_adapter *adapter,
228 if (qlcnic_82xx_check(adapter))
229 return QLC_82XX_DCB_GET_PRIOMAP_APP(val);
231 return QLC_83XX_DCB_GET_PRIOMAP_APP(val);
234 static int qlcnic_dcb_prio_count(u8 up_tc_map)
238 for (j = 0; j < QLC_DCB_MAX_TC; j++)
239 if (up_tc_map & QLC_DCB_GET_MAP(j))
245 static inline void __qlcnic_init_dcbnl_ops(struct qlcnic_dcb *dcb)
247 if (test_bit(QLCNIC_DCB_STATE, &dcb->state))
248 dcb->adapter->netdev->dcbnl_ops = &qlcnic_dcbnl_ops;
251 static void qlcnic_set_dcb_ops(struct qlcnic_adapter *adapter)
253 if (qlcnic_82xx_check(adapter))
254 adapter->dcb->ops = &qlcnic_82xx_dcb_ops;
255 else if (qlcnic_83xx_check(adapter))
256 adapter->dcb->ops = &qlcnic_83xx_dcb_ops;
259 int qlcnic_register_dcb(struct qlcnic_adapter *adapter)
261 struct qlcnic_dcb *dcb;
263 dcb = kzalloc(sizeof(struct qlcnic_dcb), GFP_ATOMIC);
268 dcb->adapter = adapter;
269 qlcnic_set_dcb_ops(adapter);
275 static void __qlcnic_dcb_free(struct qlcnic_dcb *dcb)
277 struct qlcnic_adapter *adapter;
282 adapter = dcb->adapter;
283 qlcnic_dcb_register_aen(dcb, 0);
285 while (test_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
286 usleep_range(10000, 11000);
288 cancel_delayed_work_sync(&dcb->aen_work);
291 destroy_workqueue(dcb->wq);
303 static void __qlcnic_dcb_get_info(struct qlcnic_dcb *dcb)
305 qlcnic_dcb_get_hw_capability(dcb);
306 qlcnic_dcb_get_cee_cfg(dcb);
307 qlcnic_dcb_register_aen(dcb, 1);
310 static int __qlcnic_dcb_attach(struct qlcnic_dcb *dcb)
314 INIT_DELAYED_WORK(&dcb->aen_work, qlcnic_dcb_aen_work);
316 dcb->wq = create_singlethread_workqueue("qlcnic-dcb");
318 dev_err(&dcb->adapter->pdev->dev,
319 "DCB workqueue allocation failed. DCB will be disabled\n");
323 dcb->cfg = kzalloc(sizeof(struct qlcnic_dcb_cfg), GFP_ATOMIC);
329 dcb->param = kzalloc(sizeof(struct qlcnic_dcb_mbx_params), GFP_ATOMIC);
335 qlcnic_dcb_get_info(dcb);
343 destroy_workqueue(dcb->wq);
349 static int __qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *dcb, char *buf)
351 struct qlcnic_adapter *adapter = dcb->adapter;
352 struct qlcnic_cmd_args cmd;
356 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_CAP);
360 err = qlcnic_issue_cmd(adapter, &cmd);
362 dev_err(&adapter->pdev->dev,
363 "Failed to query DCBX capability, err %d\n", err);
365 mbx_out = cmd.rsp.arg[1];
367 memcpy(buf, &mbx_out, sizeof(u32));
370 qlcnic_free_mbx_args(&cmd);
375 static int __qlcnic_dcb_get_capability(struct qlcnic_dcb *dcb, u32 *val)
377 struct qlcnic_dcb_capability *cap = &dcb->cfg->capability;
381 memset(cap, 0, sizeof(struct qlcnic_dcb_capability));
383 err = qlcnic_dcb_query_hw_capability(dcb, (char *)val);
388 if (QLC_DCB_TSA_SUPPORT(mbx_out))
389 cap->tsa_capability = true;
391 if (QLC_DCB_ETS_SUPPORT(mbx_out))
392 cap->ets_capability = true;
394 cap->max_num_tc = QLC_DCB_MAX_NUM_TC(mbx_out);
395 cap->max_ets_tc = QLC_DCB_MAX_NUM_ETS_TC(mbx_out);
396 cap->max_pfc_tc = QLC_DCB_MAX_NUM_PFC_TC(mbx_out);
398 if (cap->max_num_tc > QLC_DCB_MAX_TC ||
399 cap->max_ets_tc > cap->max_num_tc ||
400 cap->max_pfc_tc > cap->max_num_tc) {
401 dev_err(&dcb->adapter->pdev->dev, "Invalid DCB configuration\n");
408 static int qlcnic_82xx_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
410 struct qlcnic_dcb_cfg *cfg = dcb->cfg;
411 struct qlcnic_dcb_capability *cap;
415 err = __qlcnic_dcb_get_capability(dcb, &mbx_out);
419 cap = &cfg->capability;
420 cap->dcb_capability = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_LLD_MANAGED;
422 if (cap->dcb_capability && cap->tsa_capability && cap->ets_capability)
423 set_bit(QLCNIC_DCB_STATE, &dcb->state);
428 static int qlcnic_82xx_dcb_query_cee_param(struct qlcnic_dcb *dcb,
431 u16 size = sizeof(struct qlcnic_82xx_dcb_param_mbx_le);
432 struct qlcnic_adapter *adapter = dcb->adapter;
433 struct qlcnic_82xx_dcb_param_mbx_le *prsp_le;
434 struct device *dev = &adapter->pdev->dev;
435 dma_addr_t cardrsp_phys_addr;
436 struct qlcnic_dcb_param rsp;
437 struct qlcnic_cmd_args cmd;
443 case QLC_DCB_LOCAL_PARAM_FWID:
444 case QLC_DCB_OPER_PARAM_FWID:
445 case QLC_DCB_PEER_PARAM_FWID:
448 dev_err(dev, "Invalid parameter type %d\n", type);
452 addr = dma_alloc_coherent(dev, size, &cardrsp_phys_addr, GFP_KERNEL);
458 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_PARAM);
462 phys_addr = cardrsp_phys_addr;
463 cmd.req.arg[1] = size | (type << 16);
464 cmd.req.arg[2] = MSD(phys_addr);
465 cmd.req.arg[3] = LSD(phys_addr);
467 err = qlcnic_issue_cmd(adapter, &cmd);
469 dev_err(dev, "Failed to query DCBX parameter, err %d\n", err);
473 memset(&rsp, 0, sizeof(struct qlcnic_dcb_param));
474 rsp.hdr_prio_pfc_map[0] = le32_to_cpu(prsp_le->hdr_prio_pfc_map[0]);
475 rsp.hdr_prio_pfc_map[1] = le32_to_cpu(prsp_le->hdr_prio_pfc_map[1]);
476 rsp.prio_pg_map[0] = le32_to_cpu(prsp_le->prio_pg_map[0]);
477 rsp.prio_pg_map[1] = le32_to_cpu(prsp_le->prio_pg_map[1]);
478 rsp.pg_bw_map[0] = le32_to_cpu(prsp_le->pg_bw_map[0]);
479 rsp.pg_bw_map[1] = le32_to_cpu(prsp_le->pg_bw_map[1]);
480 rsp.pg_tsa_map[0] = le32_to_cpu(prsp_le->pg_tsa_map[0]);
481 rsp.pg_tsa_map[1] = le32_to_cpu(prsp_le->pg_tsa_map[1]);
483 for (i = 0; i < QLC_DCB_MAX_APP; i++)
484 rsp.app[i] = le32_to_cpu(prsp_le->app[i]);
487 memcpy(buf, &rsp, size);
489 qlcnic_free_mbx_args(&cmd);
492 dma_free_coherent(dev, size, addr, cardrsp_phys_addr);
497 static int qlcnic_82xx_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
499 struct qlcnic_dcb_mbx_params *mbx;
506 err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[0],
507 QLC_DCB_LOCAL_PARAM_FWID);
511 err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[1],
512 QLC_DCB_OPER_PARAM_FWID);
516 err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[2],
517 QLC_DCB_PEER_PARAM_FWID);
521 mbx->prio_tc_map = QLC_82XX_DCB_PRIO_TC_MAP;
523 qlcnic_dcb_data_cee_param_map(dcb->adapter);
528 static void qlcnic_dcb_aen_work(struct work_struct *work)
530 struct qlcnic_dcb *dcb;
532 dcb = container_of(work, struct qlcnic_dcb, aen_work.work);
534 qlcnic_dcb_get_cee_cfg(dcb);
535 clear_bit(QLCNIC_DCB_AEN_MODE, &dcb->state);
538 static void qlcnic_82xx_dcb_aen_handler(struct qlcnic_dcb *dcb, void *data)
540 if (test_and_set_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
543 queue_delayed_work(dcb->wq, &dcb->aen_work, 0);
546 static int qlcnic_83xx_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
548 struct qlcnic_dcb_capability *cap = &dcb->cfg->capability;
552 err = __qlcnic_dcb_get_capability(dcb, &mbx_out);
557 cap->dcb_capability = DCB_CAP_DCBX_VER_CEE;
559 cap->dcb_capability |= DCB_CAP_DCBX_VER_IEEE;
560 if (cap->dcb_capability)
561 cap->dcb_capability |= DCB_CAP_DCBX_LLD_MANAGED;
563 if (cap->dcb_capability && cap->tsa_capability && cap->ets_capability)
564 set_bit(QLCNIC_DCB_STATE, &dcb->state);
569 static int qlcnic_83xx_dcb_query_cee_param(struct qlcnic_dcb *dcb,
572 struct qlcnic_adapter *adapter = dcb->adapter;
573 struct qlcnic_dcb_mbx_params mbx_out;
574 int err, i, j, k, max_app, size;
575 struct qlcnic_dcb_param *each;
576 struct qlcnic_cmd_args cmd;
581 memset(&mbx_out, 0, sizeof(struct qlcnic_dcb_mbx_params));
582 memset(buf, 0, sizeof(struct qlcnic_dcb_mbx_params));
584 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_PARAM);
588 cmd.req.arg[0] |= QLC_DCB_FW_VER << 29;
589 err = qlcnic_issue_cmd(adapter, &cmd);
591 dev_err(&adapter->pdev->dev,
592 "Failed to query DCBX param, err %d\n", err);
596 mbx_out.prio_tc_map = cmd.rsp.arg[1];
597 p = memcpy(buf, &mbx_out, sizeof(u32));
601 for (j = 0; j < QLC_DCB_NUM_PARAM; j++) {
602 each = &mbx_out.type[j];
604 each->hdr_prio_pfc_map[0] = cmd.rsp.arg[k++];
605 each->hdr_prio_pfc_map[1] = cmd.rsp.arg[k++];
606 each->prio_pg_map[0] = cmd.rsp.arg[k++];
607 each->prio_pg_map[1] = cmd.rsp.arg[k++];
608 each->pg_bw_map[0] = cmd.rsp.arg[k++];
609 each->pg_bw_map[1] = cmd.rsp.arg[k++];
610 each->pg_tsa_map[0] = cmd.rsp.arg[k++];
611 each->pg_tsa_map[1] = cmd.rsp.arg[k++];
612 val = each->hdr_prio_pfc_map[0];
614 max_app = qlcnic_dcb_get_num_app(adapter, val);
615 for (i = 0; i < max_app; i++)
616 each->app[i] = cmd.rsp.arg[i + k];
618 size = 16 * sizeof(u32);
619 memcpy(p, &each->hdr_prio_pfc_map[0], size);
627 qlcnic_free_mbx_args(&cmd);
632 static int qlcnic_83xx_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
636 err = qlcnic_dcb_query_cee_param(dcb, (char *)dcb->param, 0);
640 qlcnic_dcb_data_cee_param_map(dcb->adapter);
645 static int qlcnic_83xx_dcb_register_aen(struct qlcnic_dcb *dcb, bool flag)
647 u8 val = (flag ? QLCNIC_CMD_INIT_NIC_FUNC : QLCNIC_CMD_STOP_NIC_FUNC);
648 struct qlcnic_adapter *adapter = dcb->adapter;
649 struct qlcnic_cmd_args cmd;
652 err = qlcnic_alloc_mbx_args(&cmd, adapter, val);
656 cmd.req.arg[1] = QLC_DCB_AEN_BIT;
658 err = qlcnic_issue_cmd(adapter, &cmd);
660 dev_err(&adapter->pdev->dev, "Failed to %s DCBX AEN, err %d\n",
661 (flag ? "register" : "unregister"), err);
663 qlcnic_free_mbx_args(&cmd);
668 static void qlcnic_83xx_dcb_aen_handler(struct qlcnic_dcb *dcb, void *data)
672 if (test_and_set_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
676 set_bit(QLCNIC_DCB_STATE, &dcb->state);
678 clear_bit(QLCNIC_DCB_STATE, &dcb->state);
680 queue_delayed_work(dcb->wq, &dcb->aen_work, 0);
683 static void qlcnic_dcb_fill_cee_tc_params(struct qlcnic_dcb_mbx_params *mbx,
684 struct qlcnic_dcb_param *each,
685 struct qlcnic_dcb_cee *type)
687 struct qlcnic_dcb_tc_cfg *tc_cfg;
690 for (i = 0; i < QLC_DCB_MAX_PRIO; i++) {
691 tc = QLC_DCB_GET_TC_PRIO(mbx->prio_tc_map, i);
692 tc_cfg = &type->tc_cfg[tc];
693 tc_cfg->valid = true;
694 tc_cfg->up_tc_map |= QLC_DCB_GET_MAP(i);
696 if (QLC_DCB_GET_PFC_PRIO(each->hdr_prio_pfc_map[1], i) &&
697 type->pfc_mode_enable) {
698 tc_cfg->prio_cfg[i].valid = true;
699 tc_cfg->prio_cfg[i].pfc_type = QLC_PFC_FULL;
703 pgid = QLC_DCB_GET_PGID_PRIO(each->prio_pg_map[0], i);
705 pgid = QLC_DCB_GET_PGID_PRIO(each->prio_pg_map[1], i);
709 tc_cfg->prio_type = QLC_PRIO_LINK;
710 type->pg_cfg[tc_cfg->pgid].prio_count++;
714 static void qlcnic_dcb_fill_cee_pg_params(struct qlcnic_dcb_param *each,
715 struct qlcnic_dcb_cee *type)
717 struct qlcnic_dcb_pg_cfg *pg_cfg;
720 for (i = 0; i < QLC_DCB_MAX_PG; i++) {
721 pg_cfg = &type->pg_cfg[i];
722 pg_cfg->valid = true;
725 bw_per = QLC_DCB_GET_BWPER_PG(each->pg_bw_map[0], i);
726 tsa = QLC_DCB_GET_TSA_PG(each->pg_tsa_map[0], i);
728 bw_per = QLC_DCB_GET_BWPER_PG(each->pg_bw_map[1], i);
729 tsa = QLC_DCB_GET_TSA_PG(each->pg_tsa_map[1], i);
732 pg_cfg->total_bw_percent = bw_per;
733 pg_cfg->tsa_type = tsa;
738 qlcnic_dcb_fill_cee_app_params(struct qlcnic_adapter *adapter, u8 idx,
739 struct qlcnic_dcb_param *each,
740 struct qlcnic_dcb_cee *type)
742 struct qlcnic_dcb_app *app;
743 u8 i, num_app, map, cnt;
744 struct dcb_app new_app;
746 num_app = qlcnic_dcb_get_num_app(adapter, each->hdr_prio_pfc_map[0]);
747 for (i = 0; i < num_app; i++) {
751 /* Only for CEE (-1) */
752 app->selector = QLC_DCB_GET_SELECTOR_APP(each->app[i]) - 1;
753 new_app.selector = app->selector;
754 app->protocol = QLC_DCB_GET_PROTO_ID_APP(each->app[i]);
755 new_app.protocol = app->protocol;
756 map = qlcnic_dcb_get_prio_map_app(adapter, each->app[i]);
757 cnt = qlcnic_dcb_prio_count(map);
759 if (cnt >= QLC_DCB_MAX_TC)
763 new_app.priority = cnt;
765 if (idx == QLC_DCB_OPER_IDX && adapter->netdev->dcbnl_ops)
766 dcb_setapp(adapter->netdev, &new_app);
770 static void qlcnic_dcb_map_cee_params(struct qlcnic_adapter *adapter, u8 idx)
772 struct qlcnic_dcb_mbx_params *mbx = adapter->dcb->param;
773 struct qlcnic_dcb_param *each = &mbx->type[idx];
774 struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
775 struct qlcnic_dcb_cee *type = &cfg->type[idx];
777 type->tc_param_valid = false;
778 type->pfc_mode_enable = false;
779 memset(type->tc_cfg, 0,
780 sizeof(struct qlcnic_dcb_tc_cfg) * QLC_DCB_MAX_TC);
781 memset(type->pg_cfg, 0,
782 sizeof(struct qlcnic_dcb_pg_cfg) * QLC_DCB_MAX_TC);
784 if (qlcnic_dcb_pfc_hdr_valid(adapter, each->hdr_prio_pfc_map[0]) &&
785 cfg->capability.max_pfc_tc)
786 type->pfc_mode_enable = true;
788 if (qlcnic_dcb_tsa_hdr_valid(adapter, each->hdr_prio_pfc_map[0]) &&
789 cfg->capability.max_ets_tc)
790 type->tc_param_valid = true;
792 qlcnic_dcb_fill_cee_tc_params(mbx, each, type);
793 qlcnic_dcb_fill_cee_pg_params(each, type);
794 qlcnic_dcb_fill_cee_app_params(adapter, idx, each, type);
797 static void qlcnic_dcb_data_cee_param_map(struct qlcnic_adapter *adapter)
801 for (i = 0; i < QLC_DCB_NUM_PARAM; i++)
802 qlcnic_dcb_map_cee_params(adapter, i);
804 dcbnl_cee_notify(adapter->netdev, RTM_GETDCB, DCB_CMD_CEE_GET, 0, 0);
807 static u8 qlcnic_dcb_get_state(struct net_device *netdev)
809 struct qlcnic_adapter *adapter = netdev_priv(netdev);
811 return test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state);
814 static void qlcnic_dcb_get_perm_hw_addr(struct net_device *netdev, u8 *addr)
816 memcpy(addr, netdev->perm_addr, netdev->addr_len);
820 qlcnic_dcb_get_pg_tc_cfg_tx(struct net_device *netdev, int tc, u8 *prio,
821 u8 *pgid, u8 *bw_per, u8 *up_tc_map)
823 struct qlcnic_adapter *adapter = netdev_priv(netdev);
824 struct qlcnic_dcb_tc_cfg *tc_cfg, *temp;
825 struct qlcnic_dcb_cee *type;
828 type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
829 *prio = *pgid = *bw_per = *up_tc_map = 0;
831 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
832 !type->tc_param_valid)
835 if (tc < 0 || (tc > QLC_DCB_MAX_TC))
838 tc_cfg = &type->tc_cfg[tc];
842 *pgid = tc_cfg->pgid;
843 *prio = tc_cfg->prio_type;
844 *up_tc_map = tc_cfg->up_tc_map;
847 for (i = 0, cnt = 0; i < QLC_DCB_MAX_TC; i++) {
848 temp = &type->tc_cfg[i];
849 if (temp->valid && (pg == temp->pgid))
853 tc_cfg->bwg_percent = (100 / cnt);
854 *bw_per = tc_cfg->bwg_percent;
857 static void qlcnic_dcb_get_pg_bwg_cfg_tx(struct net_device *netdev, int pgid,
860 struct qlcnic_adapter *adapter = netdev_priv(netdev);
861 struct qlcnic_dcb_pg_cfg *pgcfg;
862 struct qlcnic_dcb_cee *type;
865 type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
867 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
868 !type->tc_param_valid)
871 if (pgid < 0 || pgid > QLC_DCB_MAX_PG)
874 pgcfg = &type->pg_cfg[pgid];
878 *bw_pct = pgcfg->total_bw_percent;
881 static void qlcnic_dcb_get_pfc_cfg(struct net_device *netdev, int prio,
884 struct qlcnic_adapter *adapter = netdev_priv(netdev);
885 struct qlcnic_dcb_tc_cfg *tc_cfg;
886 u8 val = QLC_DCB_GET_MAP(prio);
887 struct qlcnic_dcb_cee *type;
891 type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
893 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
894 !type->pfc_mode_enable)
897 for (i = 0; i < QLC_DCB_MAX_TC; i++) {
898 tc_cfg = &type->tc_cfg[i];
902 if ((val & tc_cfg->up_tc_map) && (tc_cfg->prio_cfg[prio].valid))
903 *setting = tc_cfg->prio_cfg[prio].pfc_type;
907 static u8 qlcnic_dcb_get_capability(struct net_device *netdev, int capid,
910 struct qlcnic_adapter *adapter = netdev_priv(netdev);
912 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
916 case DCB_CAP_ATTR_PG:
917 case DCB_CAP_ATTR_UP2TC:
918 case DCB_CAP_ATTR_PFC:
919 case DCB_CAP_ATTR_GSP:
922 case DCB_CAP_ATTR_PG_TCS:
923 case DCB_CAP_ATTR_PFC_TCS:
924 *cap = 0x80; /* 8 priorities for PGs */
926 case DCB_CAP_ATTR_DCBX:
927 *cap = adapter->dcb->cfg->capability.dcb_capability;
936 static int qlcnic_dcb_get_num_tcs(struct net_device *netdev, int attr, u8 *num)
938 struct qlcnic_adapter *adapter = netdev_priv(netdev);
939 struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
941 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
945 case DCB_NUMTCS_ATTR_PG:
946 *num = cfg->capability.max_ets_tc;
948 case DCB_NUMTCS_ATTR_PFC:
949 *num = cfg->capability.max_pfc_tc;
956 static u8 qlcnic_dcb_get_app(struct net_device *netdev, u8 idtype, u16 id)
958 struct qlcnic_adapter *adapter = netdev_priv(netdev);
959 struct dcb_app app = {
964 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
967 return dcb_getapp(netdev, &app);
970 static u8 qlcnic_dcb_get_pfc_state(struct net_device *netdev)
972 struct qlcnic_adapter *adapter = netdev_priv(netdev);
973 struct qlcnic_dcb *dcb = adapter->dcb;
975 if (!test_bit(QLCNIC_DCB_STATE, &dcb->state))
978 return dcb->cfg->type[QLC_DCB_OPER_IDX].pfc_mode_enable;
981 static u8 qlcnic_dcb_get_dcbx(struct net_device *netdev)
983 struct qlcnic_adapter *adapter = netdev_priv(netdev);
984 struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
986 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
989 return cfg->capability.dcb_capability;
992 static u8 qlcnic_dcb_get_feat_cfg(struct net_device *netdev, int fid, u8 *flag)
994 struct qlcnic_adapter *adapter = netdev_priv(netdev);
995 struct qlcnic_dcb_cee *type;
997 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1000 type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
1004 case DCB_FEATCFG_ATTR_PG:
1005 if (type->tc_param_valid)
1006 *flag |= DCB_FEATCFG_ENABLE;
1008 *flag |= DCB_FEATCFG_ERROR;
1010 case DCB_FEATCFG_ATTR_PFC:
1011 if (type->pfc_mode_enable) {
1012 if (type->tc_cfg[0].prio_cfg[0].pfc_type)
1013 *flag |= DCB_FEATCFG_ENABLE;
1015 *flag |= DCB_FEATCFG_ERROR;
1018 case DCB_FEATCFG_ATTR_APP:
1019 *flag |= DCB_FEATCFG_ENABLE;
1022 netdev_err(netdev, "Invalid Feature ID %d\n", fid);
1030 qlcnic_dcb_get_pg_tc_cfg_rx(struct net_device *netdev, int prio, u8 *prio_type,
1031 u8 *pgid, u8 *bw_pct, u8 *up_map)
1033 *prio_type = *pgid = *bw_pct = *up_map = 0;
1037 qlcnic_dcb_get_pg_bwg_cfg_rx(struct net_device *netdev, int pgid, u8 *bw_pct)
1042 static int qlcnic_dcb_peer_app_info(struct net_device *netdev,
1043 struct dcb_peer_app_info *info,
1046 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1047 struct qlcnic_dcb_cee *peer;
1052 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1055 peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
1057 for (i = 0; i < QLC_DCB_MAX_APP; i++) {
1058 if (peer->app[i].valid)
1065 static int qlcnic_dcb_peer_app_table(struct net_device *netdev,
1066 struct dcb_app *table)
1068 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1069 struct qlcnic_dcb_cee *peer;
1070 struct qlcnic_dcb_app *app;
1073 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1076 peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
1078 for (i = 0, j = 0; i < QLC_DCB_MAX_APP; i++) {
1079 app = &peer->app[i];
1083 table[j].selector = app->selector;
1084 table[j].priority = app->priority;
1085 table[j++].protocol = app->protocol;
1091 static int qlcnic_dcb_cee_peer_get_pg(struct net_device *netdev,
1094 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1095 struct qlcnic_dcb_cee *peer;
1098 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1101 peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
1103 for (i = 0, j = 0; i < QLC_DCB_MAX_PG; i++) {
1104 if (!peer->pg_cfg[i].valid)
1107 pg->pg_bw[j] = peer->pg_cfg[i].total_bw_percent;
1109 for (k = 0; k < QLC_DCB_MAX_TC; k++) {
1110 if (peer->tc_cfg[i].valid &&
1111 (peer->tc_cfg[i].pgid == i)) {
1112 map = peer->tc_cfg[i].up_tc_map;
1113 pg->prio_pg[j++] = map;
1122 static int qlcnic_dcb_cee_peer_get_pfc(struct net_device *netdev,
1123 struct cee_pfc *pfc)
1125 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1126 struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
1127 struct qlcnic_dcb_tc_cfg *tc;
1128 struct qlcnic_dcb_cee *peer;
1129 u8 i, setting, prio;
1133 if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
1136 peer = &cfg->type[QLC_DCB_PEER_IDX];
1138 for (i = 0; i < QLC_DCB_MAX_TC; i++) {
1139 tc = &peer->tc_cfg[i];
1140 prio = qlcnic_dcb_prio_count(tc->up_tc_map);
1143 qlcnic_dcb_get_pfc_cfg(netdev, prio, &setting);
1145 pfc->pfc_en |= QLC_DCB_GET_MAP(i);
1148 pfc->tcs_supported = cfg->capability.max_pfc_tc;
1153 static const struct dcbnl_rtnl_ops qlcnic_dcbnl_ops = {
1154 .getstate = qlcnic_dcb_get_state,
1155 .getpermhwaddr = qlcnic_dcb_get_perm_hw_addr,
1156 .getpgtccfgtx = qlcnic_dcb_get_pg_tc_cfg_tx,
1157 .getpgbwgcfgtx = qlcnic_dcb_get_pg_bwg_cfg_tx,
1158 .getpfccfg = qlcnic_dcb_get_pfc_cfg,
1159 .getcap = qlcnic_dcb_get_capability,
1160 .getnumtcs = qlcnic_dcb_get_num_tcs,
1161 .getapp = qlcnic_dcb_get_app,
1162 .getpfcstate = qlcnic_dcb_get_pfc_state,
1163 .getdcbx = qlcnic_dcb_get_dcbx,
1164 .getfeatcfg = qlcnic_dcb_get_feat_cfg,
1166 .getpgtccfgrx = qlcnic_dcb_get_pg_tc_cfg_rx,
1167 .getpgbwgcfgrx = qlcnic_dcb_get_pg_bwg_cfg_rx,
1169 .peer_getappinfo = qlcnic_dcb_peer_app_info,
1170 .peer_getapptable = qlcnic_dcb_peer_app_table,
1171 .cee_peer_getpg = qlcnic_dcb_cee_peer_get_pg,
1172 .cee_peer_getpfc = qlcnic_dcb_cee_peer_get_pfc,