1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
79 #include <asm/uaccess.h>
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
301 struct cp_dma_stats {
317 struct cp_extra_stats {
318 unsigned long rx_frags;
323 struct net_device *dev;
327 struct napi_struct napi;
329 struct pci_dev *pdev;
333 struct cp_extra_stats cp_stats;
335 unsigned rx_head ____cacheline_aligned;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
340 unsigned tx_head ____cacheline_aligned;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344 u32 tx_opts[CP_TX_RING_SIZE];
347 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
351 struct mii_if_info mii_if;
354 #define cpr8(reg) readb(cp->regs + (reg))
355 #define cpr16(reg) readw(cp->regs + (reg))
356 #define cpr32(reg) readl(cp->regs + (reg))
357 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
358 #define cpw16(reg,val) writew((val), cp->regs + (reg))
359 #define cpw32(reg,val) writel((val), cp->regs + (reg))
360 #define cpw8_f(reg,val) do { \
361 writeb((val), cp->regs + (reg)); \
362 readb(cp->regs + (reg)); \
364 #define cpw16_f(reg,val) do { \
365 writew((val), cp->regs + (reg)); \
366 readw(cp->regs + (reg)); \
368 #define cpw32_f(reg,val) do { \
369 writel((val), cp->regs + (reg)); \
370 readl(cp->regs + (reg)); \
374 static void __cp_set_rx_mode (struct net_device *dev);
375 static void cp_tx (struct cp_private *cp);
376 static void cp_clean_rings (struct cp_private *cp);
377 #ifdef CONFIG_NET_POLL_CONTROLLER
378 static void cp_poll_controller(struct net_device *dev);
380 static int cp_get_eeprom_len(struct net_device *dev);
381 static int cp_get_eeprom(struct net_device *dev,
382 struct ethtool_eeprom *eeprom, u8 *data);
383 static int cp_set_eeprom(struct net_device *dev,
384 struct ethtool_eeprom *eeprom, u8 *data);
387 const char str[ETH_GSTRING_LEN];
388 } ethtool_stats_keys[] = {
406 static inline void cp_set_rxbufsize (struct cp_private *cp)
408 unsigned int mtu = cp->dev->mtu;
410 if (mtu > ETH_DATA_LEN)
411 /* MTU + ethernet header + FCS + optional VLAN tag */
412 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
414 cp->rx_buf_sz = PKT_BUF_SZ;
417 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
418 struct cp_desc *desc)
420 u32 opts2 = le32_to_cpu(desc->opts2);
422 skb->protocol = eth_type_trans (skb, cp->dev);
424 cp->dev->stats.rx_packets++;
425 cp->dev->stats.rx_bytes += skb->len;
427 if (opts2 & RxVlanTagged)
428 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
430 napi_gro_receive(&cp->napi, skb);
433 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
436 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
437 rx_tail, status, len);
438 cp->dev->stats.rx_errors++;
439 if (status & RxErrFrame)
440 cp->dev->stats.rx_frame_errors++;
441 if (status & RxErrCRC)
442 cp->dev->stats.rx_crc_errors++;
443 if ((status & RxErrRunt) || (status & RxErrLong))
444 cp->dev->stats.rx_length_errors++;
445 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
446 cp->dev->stats.rx_length_errors++;
447 if (status & RxErrFIFO)
448 cp->dev->stats.rx_fifo_errors++;
451 static inline unsigned int cp_rx_csum_ok (u32 status)
453 unsigned int protocol = (status >> 16) & 0x3;
455 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
456 ((protocol == RxProtoUDP) && !(status & UDPFail)))
462 static int cp_rx_poll(struct napi_struct *napi, int budget)
464 struct cp_private *cp = container_of(napi, struct cp_private, napi);
465 struct net_device *dev = cp->dev;
466 unsigned int rx_tail = cp->rx_tail;
471 cpw16(IntrStatus, cp_rx_intr_mask);
473 while (rx < budget) {
475 dma_addr_t mapping, new_mapping;
476 struct sk_buff *skb, *new_skb;
477 struct cp_desc *desc;
478 const unsigned buflen = cp->rx_buf_sz;
480 skb = cp->rx_skb[rx_tail];
483 desc = &cp->rx_ring[rx_tail];
484 status = le32_to_cpu(desc->opts1);
485 if (status & DescOwn)
488 len = (status & 0x1fff) - 4;
489 mapping = le64_to_cpu(desc->addr);
491 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
492 /* we don't support incoming fragmented frames.
493 * instead, we attempt to ensure that the
494 * pre-allocated RX skbs are properly sized such
495 * that RX fragments are never encountered
497 cp_rx_err_acct(cp, rx_tail, status, len);
498 dev->stats.rx_dropped++;
499 cp->cp_stats.rx_frags++;
503 if (status & (RxError | RxErrFIFO)) {
504 cp_rx_err_acct(cp, rx_tail, status, len);
508 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
509 rx_tail, status, len);
511 new_skb = napi_alloc_skb(napi, buflen);
513 dev->stats.rx_dropped++;
517 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
519 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
520 dev->stats.rx_dropped++;
525 dma_unmap_single(&cp->pdev->dev, mapping,
526 buflen, PCI_DMA_FROMDEVICE);
528 /* Handle checksum offloading for incoming packets. */
529 if (cp_rx_csum_ok(status))
530 skb->ip_summed = CHECKSUM_UNNECESSARY;
532 skb_checksum_none_assert(skb);
536 cp->rx_skb[rx_tail] = new_skb;
538 cp_rx_skb(cp, skb, desc);
540 mapping = new_mapping;
543 cp->rx_ring[rx_tail].opts2 = 0;
544 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
545 if (rx_tail == (CP_RX_RING_SIZE - 1))
546 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
549 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
550 rx_tail = NEXT_RX(rx_tail);
553 cp->rx_tail = rx_tail;
555 /* if we did not reach work limit, then we're done with
556 * this round of polling
561 if (cpr16(IntrStatus) & cp_rx_intr_mask)
564 napi_gro_flush(napi, false);
565 spin_lock_irqsave(&cp->lock, flags);
566 __napi_complete(napi);
567 cpw16_f(IntrMask, cp_intr_mask);
568 spin_unlock_irqrestore(&cp->lock, flags);
574 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
576 struct net_device *dev = dev_instance;
577 struct cp_private *cp;
581 if (unlikely(dev == NULL))
583 cp = netdev_priv(dev);
585 spin_lock(&cp->lock);
587 status = cpr16(IntrStatus);
588 if (!status || (status == 0xFFFF))
593 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
594 status, cpr8(Cmd), cpr16(CpCmd));
596 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
598 /* close possible race's with dev_close */
599 if (unlikely(!netif_running(dev))) {
604 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
605 if (napi_schedule_prep(&cp->napi)) {
606 cpw16_f(IntrMask, cp_norx_intr_mask);
607 __napi_schedule(&cp->napi);
610 if (status & (TxOK | TxErr | TxEmpty | SWInt))
612 if (status & LinkChg)
613 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
616 if (status & PciErr) {
619 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
620 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
621 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
624 /* TODO: reset hardware */
628 spin_unlock(&cp->lock);
630 return IRQ_RETVAL(handled);
633 #ifdef CONFIG_NET_POLL_CONTROLLER
635 * Polling receive - used by netconsole and other diagnostic tools
636 * to allow network i/o with interrupts disabled.
638 static void cp_poll_controller(struct net_device *dev)
640 struct cp_private *cp = netdev_priv(dev);
641 const int irq = cp->pdev->irq;
644 cp_interrupt(irq, dev);
649 static void cp_tx (struct cp_private *cp)
651 unsigned tx_head = cp->tx_head;
652 unsigned tx_tail = cp->tx_tail;
653 unsigned bytes_compl = 0, pkts_compl = 0;
655 while (tx_tail != tx_head) {
656 struct cp_desc *txd = cp->tx_ring + tx_tail;
661 status = le32_to_cpu(txd->opts1);
662 if (status & DescOwn)
665 skb = cp->tx_skb[tx_tail];
668 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
669 cp->tx_opts[tx_tail] & 0xffff,
672 if (status & LastFrag) {
673 if (status & (TxError | TxFIFOUnder)) {
674 netif_dbg(cp, tx_err, cp->dev,
675 "tx err, status 0x%x\n", status);
676 cp->dev->stats.tx_errors++;
678 cp->dev->stats.tx_window_errors++;
679 if (status & TxMaxCol)
680 cp->dev->stats.tx_aborted_errors++;
681 if (status & TxLinkFail)
682 cp->dev->stats.tx_carrier_errors++;
683 if (status & TxFIFOUnder)
684 cp->dev->stats.tx_fifo_errors++;
686 cp->dev->stats.collisions +=
687 ((status >> TxColCntShift) & TxColCntMask);
688 cp->dev->stats.tx_packets++;
689 cp->dev->stats.tx_bytes += skb->len;
690 netif_dbg(cp, tx_done, cp->dev,
691 "tx done, slot %d\n", tx_tail);
693 bytes_compl += skb->len;
695 dev_kfree_skb_irq(skb);
698 cp->tx_skb[tx_tail] = NULL;
700 tx_tail = NEXT_TX(tx_tail);
703 cp->tx_tail = tx_tail;
705 netdev_completed_queue(cp->dev, pkts_compl, bytes_compl);
706 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
707 netif_wake_queue(cp->dev);
710 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
712 return skb_vlan_tag_present(skb) ?
713 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
716 static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb,
717 int first, int entry_last)
721 skb_frag_t *this_frag;
722 for (frag = 0; frag+first < entry_last; frag++) {
724 cp->tx_skb[index] = NULL;
725 txd = &cp->tx_ring[index];
726 this_frag = &skb_shinfo(skb)->frags[frag];
727 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
728 skb_frag_size(this_frag), PCI_DMA_TODEVICE);
732 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
733 struct net_device *dev)
735 struct cp_private *cp = netdev_priv(dev);
738 unsigned long intr_flags;
742 spin_lock_irqsave(&cp->lock, intr_flags);
744 /* This is a hard error, log it. */
745 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
746 netif_stop_queue(dev);
747 spin_unlock_irqrestore(&cp->lock, intr_flags);
748 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
749 return NETDEV_TX_BUSY;
753 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
754 mss = skb_shinfo(skb)->gso_size;
756 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
759 opts1 |= LargeSend | ((mss & MSSMask) << MSSShift);
760 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
761 const struct iphdr *ip = ip_hdr(skb);
762 if (ip->protocol == IPPROTO_TCP)
763 opts1 |= IPCS | TCPCS;
764 else if (ip->protocol == IPPROTO_UDP)
765 opts1 |= IPCS | UDPCS;
768 "Net bug: asked to checksum invalid Legacy IP packet\n");
773 if (skb_shinfo(skb)->nr_frags == 0) {
774 struct cp_desc *txd = &cp->tx_ring[entry];
779 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
780 if (dma_mapping_error(&cp->pdev->dev, mapping))
784 txd->addr = cpu_to_le64(mapping);
787 opts1 |= eor | len | FirstFrag | LastFrag;
789 txd->opts1 = cpu_to_le32(opts1);
792 cp->tx_skb[entry] = skb;
793 cp->tx_opts[entry] = opts1;
794 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
798 u32 first_len, first_eor, ctrl;
799 dma_addr_t first_mapping;
800 int frag, first_entry = entry;
802 /* We must give this initial chunk to the device last.
803 * Otherwise we could race with the device.
806 first_len = skb_headlen(skb);
807 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
808 first_len, PCI_DMA_TODEVICE);
809 if (dma_mapping_error(&cp->pdev->dev, first_mapping))
812 cp->tx_skb[entry] = skb;
814 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
815 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
819 entry = NEXT_TX(entry);
821 len = skb_frag_size(this_frag);
822 mapping = dma_map_single(&cp->pdev->dev,
823 skb_frag_address(this_frag),
824 len, PCI_DMA_TODEVICE);
825 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
826 unwind_tx_frag_mapping(cp, skb, first_entry, entry);
830 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
832 ctrl = opts1 | eor | len;
834 if (frag == skb_shinfo(skb)->nr_frags - 1)
837 txd = &cp->tx_ring[entry];
839 txd->addr = cpu_to_le64(mapping);
842 txd->opts1 = cpu_to_le32(ctrl);
845 cp->tx_opts[entry] = ctrl;
846 cp->tx_skb[entry] = skb;
849 txd = &cp->tx_ring[first_entry];
851 txd->addr = cpu_to_le64(first_mapping);
854 ctrl = opts1 | first_eor | first_len | FirstFrag;
855 txd->opts1 = cpu_to_le32(ctrl);
858 cp->tx_opts[first_entry] = ctrl;
859 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slots %d-%d, skblen %d\n",
860 first_entry, entry, skb->len);
862 cp->tx_head = NEXT_TX(entry);
864 netdev_sent_queue(dev, skb->len);
865 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
866 netif_stop_queue(dev);
869 spin_unlock_irqrestore(&cp->lock, intr_flags);
871 cpw8(TxPoll, NormalTxPoll);
875 dev_kfree_skb_any(skb);
876 cp->dev->stats.tx_dropped++;
880 /* Set or clear the multicast filter for this adaptor.
881 This routine is not state sensitive and need not be SMP locked. */
883 static void __cp_set_rx_mode (struct net_device *dev)
885 struct cp_private *cp = netdev_priv(dev);
886 u32 mc_filter[2]; /* Multicast hash filter */
889 /* Note: do not reorder, GCC is clever about common statements. */
890 if (dev->flags & IFF_PROMISC) {
891 /* Unconditionally log net taps. */
893 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
895 mc_filter[1] = mc_filter[0] = 0xffffffff;
896 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
897 (dev->flags & IFF_ALLMULTI)) {
898 /* Too many to filter perfectly -- accept all multicasts. */
899 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
900 mc_filter[1] = mc_filter[0] = 0xffffffff;
902 struct netdev_hw_addr *ha;
903 rx_mode = AcceptBroadcast | AcceptMyPhys;
904 mc_filter[1] = mc_filter[0] = 0;
905 netdev_for_each_mc_addr(ha, dev) {
906 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
908 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
909 rx_mode |= AcceptMulticast;
913 /* We can safely update without stopping the chip. */
914 cp->rx_config = cp_rx_config | rx_mode;
915 cpw32_f(RxConfig, cp->rx_config);
917 cpw32_f (MAR0 + 0, mc_filter[0]);
918 cpw32_f (MAR0 + 4, mc_filter[1]);
921 static void cp_set_rx_mode (struct net_device *dev)
924 struct cp_private *cp = netdev_priv(dev);
926 spin_lock_irqsave (&cp->lock, flags);
927 __cp_set_rx_mode(dev);
928 spin_unlock_irqrestore (&cp->lock, flags);
931 static void __cp_get_stats(struct cp_private *cp)
933 /* only lower 24 bits valid; write any value to clear */
934 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
938 static struct net_device_stats *cp_get_stats(struct net_device *dev)
940 struct cp_private *cp = netdev_priv(dev);
943 /* The chip only need report frame silently dropped. */
944 spin_lock_irqsave(&cp->lock, flags);
945 if (netif_running(dev) && netif_device_present(dev))
947 spin_unlock_irqrestore(&cp->lock, flags);
952 static void cp_stop_hw (struct cp_private *cp)
954 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
955 cpw16_f(IntrMask, 0);
958 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
961 cp->tx_head = cp->tx_tail = 0;
963 netdev_reset_queue(cp->dev);
966 static void cp_reset_hw (struct cp_private *cp)
968 unsigned work = 1000;
973 if (!(cpr8(Cmd) & CmdReset))
976 schedule_timeout_uninterruptible(10);
979 netdev_err(cp->dev, "hardware reset timeout\n");
982 static inline void cp_start_hw (struct cp_private *cp)
986 cpw16(CpCmd, cp->cpcmd);
989 * These (at least TxRingAddr) need to be configured after the
990 * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
991 * (C+ Command Register) recommends that these and more be configured
992 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
993 * it's been observed that the TxRingAddr is actually reset to garbage
994 * when C+ mode Tx is enabled in CpCmd.
996 cpw32_f(HiTxRingAddr, 0);
997 cpw32_f(HiTxRingAddr + 4, 0);
999 ring_dma = cp->ring_dma;
1000 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1001 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1003 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1004 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1005 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1008 * Strictly speaking, the datasheet says this should be enabled
1009 * *before* setting the descriptor addresses. But what, then, would
1010 * prevent it from doing DMA to random unconfigured addresses?
1011 * This variant appears to work fine.
1013 cpw8(Cmd, RxOn | TxOn);
1015 netdev_reset_queue(cp->dev);
1018 static void cp_enable_irq(struct cp_private *cp)
1020 cpw16_f(IntrMask, cp_intr_mask);
1023 static void cp_init_hw (struct cp_private *cp)
1025 struct net_device *dev = cp->dev;
1029 cpw8_f (Cfg9346, Cfg9346_Unlock);
1031 /* Restore our idea of the MAC address. */
1032 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1033 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1036 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1038 __cp_set_rx_mode(dev);
1039 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1041 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1042 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1043 cpw8(Config3, PARMEnable);
1044 cp->wol_enabled = 0;
1046 cpw8(Config5, cpr8(Config5) & PMEStatus);
1048 cpw16(MultiIntr, 0);
1050 cpw8_f(Cfg9346, Cfg9346_Lock);
1053 static int cp_refill_rx(struct cp_private *cp)
1055 struct net_device *dev = cp->dev;
1058 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1059 struct sk_buff *skb;
1062 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1066 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1067 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1068 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
1072 cp->rx_skb[i] = skb;
1074 cp->rx_ring[i].opts2 = 0;
1075 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1076 if (i == (CP_RX_RING_SIZE - 1))
1077 cp->rx_ring[i].opts1 =
1078 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1080 cp->rx_ring[i].opts1 =
1081 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1091 static void cp_init_rings_index (struct cp_private *cp)
1094 cp->tx_head = cp->tx_tail = 0;
1097 static int cp_init_rings (struct cp_private *cp)
1099 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1100 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1101 memset(cp->tx_opts, 0, sizeof(cp->tx_opts));
1103 cp_init_rings_index(cp);
1105 return cp_refill_rx (cp);
1108 static int cp_alloc_rings (struct cp_private *cp)
1110 struct device *d = &cp->pdev->dev;
1114 mem = dma_alloc_coherent(d, CP_RING_BYTES, &cp->ring_dma, GFP_KERNEL);
1119 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1121 rc = cp_init_rings(cp);
1123 dma_free_coherent(d, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1128 static void cp_clean_rings (struct cp_private *cp)
1130 struct cp_desc *desc;
1133 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1134 if (cp->rx_skb[i]) {
1135 desc = cp->rx_ring + i;
1136 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1137 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1138 dev_kfree_skb_any(cp->rx_skb[i]);
1142 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1143 if (cp->tx_skb[i]) {
1144 struct sk_buff *skb = cp->tx_skb[i];
1146 desc = cp->tx_ring + i;
1147 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1148 le32_to_cpu(desc->opts1) & 0xffff,
1150 if (le32_to_cpu(desc->opts1) & LastFrag)
1151 dev_kfree_skb_any(skb);
1152 cp->dev->stats.tx_dropped++;
1155 netdev_reset_queue(cp->dev);
1157 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1158 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1159 memset(cp->tx_opts, 0, sizeof(cp->tx_opts));
1161 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1162 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1165 static void cp_free_rings (struct cp_private *cp)
1168 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1174 static int cp_open (struct net_device *dev)
1176 struct cp_private *cp = netdev_priv(dev);
1177 const int irq = cp->pdev->irq;
1180 netif_dbg(cp, ifup, dev, "enabling interface\n");
1182 rc = cp_alloc_rings(cp);
1186 napi_enable(&cp->napi);
1190 rc = request_irq(irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1196 netif_carrier_off(dev);
1197 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1198 netif_start_queue(dev);
1203 napi_disable(&cp->napi);
1209 static int cp_close (struct net_device *dev)
1211 struct cp_private *cp = netdev_priv(dev);
1212 unsigned long flags;
1214 napi_disable(&cp->napi);
1216 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1218 spin_lock_irqsave(&cp->lock, flags);
1220 netif_stop_queue(dev);
1221 netif_carrier_off(dev);
1225 spin_unlock_irqrestore(&cp->lock, flags);
1227 free_irq(cp->pdev->irq, dev);
1233 static void cp_tx_timeout(struct net_device *dev)
1235 struct cp_private *cp = netdev_priv(dev);
1236 unsigned long flags;
1239 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1240 cpr8(Cmd), cpr16(CpCmd),
1241 cpr16(IntrStatus), cpr16(IntrMask));
1243 spin_lock_irqsave(&cp->lock, flags);
1247 rc = cp_init_rings(cp);
1249 __cp_set_rx_mode(dev);
1250 cpw16_f(IntrMask, cp_norx_intr_mask);
1252 netif_wake_queue(dev);
1253 napi_schedule_irqoff(&cp->napi);
1255 spin_unlock_irqrestore(&cp->lock, flags);
1258 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1260 struct cp_private *cp = netdev_priv(dev);
1262 /* check for invalid MTU, according to hardware limits */
1263 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1266 /* if network interface not up, no need for complexity */
1267 if (!netif_running(dev)) {
1269 cp_set_rxbufsize(cp); /* set new rx buf size */
1273 /* network IS up, close it, reset MTU, and come up again. */
1276 cp_set_rxbufsize(cp);
1277 return cp_open(dev);
1280 static const char mii_2_8139_map[8] = {
1291 static int mdio_read(struct net_device *dev, int phy_id, int location)
1293 struct cp_private *cp = netdev_priv(dev);
1295 return location < 8 && mii_2_8139_map[location] ?
1296 readw(cp->regs + mii_2_8139_map[location]) : 0;
1300 static void mdio_write(struct net_device *dev, int phy_id, int location,
1303 struct cp_private *cp = netdev_priv(dev);
1305 if (location == 0) {
1306 cpw8(Cfg9346, Cfg9346_Unlock);
1307 cpw16(BasicModeCtrl, value);
1308 cpw8(Cfg9346, Cfg9346_Lock);
1309 } else if (location < 8 && mii_2_8139_map[location])
1310 cpw16(mii_2_8139_map[location], value);
1313 /* Set the ethtool Wake-on-LAN settings */
1314 static int netdev_set_wol (struct cp_private *cp,
1315 const struct ethtool_wolinfo *wol)
1319 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1320 /* If WOL is being disabled, no need for complexity */
1322 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1323 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1326 cpw8 (Cfg9346, Cfg9346_Unlock);
1327 cpw8 (Config3, options);
1328 cpw8 (Cfg9346, Cfg9346_Lock);
1330 options = 0; /* Paranoia setting */
1331 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1332 /* If WOL is being disabled, no need for complexity */
1334 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1335 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1336 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1339 cpw8 (Config5, options);
1341 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1346 /* Get the ethtool Wake-on-LAN settings */
1347 static void netdev_get_wol (struct cp_private *cp,
1348 struct ethtool_wolinfo *wol)
1352 wol->wolopts = 0; /* Start from scratch */
1353 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1354 WAKE_MCAST | WAKE_UCAST;
1355 /* We don't need to go on if WOL is disabled */
1356 if (!cp->wol_enabled) return;
1358 options = cpr8 (Config3);
1359 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1360 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1362 options = 0; /* Paranoia setting */
1363 options = cpr8 (Config5);
1364 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1365 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1366 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1369 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1371 struct cp_private *cp = netdev_priv(dev);
1373 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1374 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1375 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1378 static void cp_get_ringparam(struct net_device *dev,
1379 struct ethtool_ringparam *ring)
1381 ring->rx_max_pending = CP_RX_RING_SIZE;
1382 ring->tx_max_pending = CP_TX_RING_SIZE;
1383 ring->rx_pending = CP_RX_RING_SIZE;
1384 ring->tx_pending = CP_TX_RING_SIZE;
1387 static int cp_get_regs_len(struct net_device *dev)
1389 return CP_REGS_SIZE;
1392 static int cp_get_sset_count (struct net_device *dev, int sset)
1396 return CP_NUM_STATS;
1402 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1404 struct cp_private *cp = netdev_priv(dev);
1406 unsigned long flags;
1408 spin_lock_irqsave(&cp->lock, flags);
1409 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1410 spin_unlock_irqrestore(&cp->lock, flags);
1415 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1417 struct cp_private *cp = netdev_priv(dev);
1419 unsigned long flags;
1421 spin_lock_irqsave(&cp->lock, flags);
1422 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1423 spin_unlock_irqrestore(&cp->lock, flags);
1428 static int cp_nway_reset(struct net_device *dev)
1430 struct cp_private *cp = netdev_priv(dev);
1431 return mii_nway_restart(&cp->mii_if);
1434 static u32 cp_get_msglevel(struct net_device *dev)
1436 struct cp_private *cp = netdev_priv(dev);
1437 return cp->msg_enable;
1440 static void cp_set_msglevel(struct net_device *dev, u32 value)
1442 struct cp_private *cp = netdev_priv(dev);
1443 cp->msg_enable = value;
1446 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1448 struct cp_private *cp = netdev_priv(dev);
1449 unsigned long flags;
1451 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1454 spin_lock_irqsave(&cp->lock, flags);
1456 if (features & NETIF_F_RXCSUM)
1457 cp->cpcmd |= RxChkSum;
1459 cp->cpcmd &= ~RxChkSum;
1461 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1462 cp->cpcmd |= RxVlanOn;
1464 cp->cpcmd &= ~RxVlanOn;
1466 cpw16_f(CpCmd, cp->cpcmd);
1467 spin_unlock_irqrestore(&cp->lock, flags);
1472 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1475 struct cp_private *cp = netdev_priv(dev);
1476 unsigned long flags;
1478 if (regs->len < CP_REGS_SIZE)
1479 return /* -EINVAL */;
1481 regs->version = CP_REGS_VER;
1483 spin_lock_irqsave(&cp->lock, flags);
1484 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1485 spin_unlock_irqrestore(&cp->lock, flags);
1488 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1490 struct cp_private *cp = netdev_priv(dev);
1491 unsigned long flags;
1493 spin_lock_irqsave (&cp->lock, flags);
1494 netdev_get_wol (cp, wol);
1495 spin_unlock_irqrestore (&cp->lock, flags);
1498 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1500 struct cp_private *cp = netdev_priv(dev);
1501 unsigned long flags;
1504 spin_lock_irqsave (&cp->lock, flags);
1505 rc = netdev_set_wol (cp, wol);
1506 spin_unlock_irqrestore (&cp->lock, flags);
1511 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1513 switch (stringset) {
1515 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1523 static void cp_get_ethtool_stats (struct net_device *dev,
1524 struct ethtool_stats *estats, u64 *tmp_stats)
1526 struct cp_private *cp = netdev_priv(dev);
1527 struct cp_dma_stats *nic_stats;
1531 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1536 /* begin NIC statistics dump */
1537 cpw32(StatsAddr + 4, (u64)dma >> 32);
1538 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1541 for (i = 0; i < 1000; i++) {
1542 if ((cpr32(StatsAddr) & DumpStats) == 0)
1546 cpw32(StatsAddr, 0);
1547 cpw32(StatsAddr + 4, 0);
1551 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1552 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1553 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1554 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1555 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1556 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1557 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1558 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1559 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1560 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1561 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1562 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1563 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1564 tmp_stats[i++] = cp->cp_stats.rx_frags;
1565 BUG_ON(i != CP_NUM_STATS);
1567 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1570 static const struct ethtool_ops cp_ethtool_ops = {
1571 .get_drvinfo = cp_get_drvinfo,
1572 .get_regs_len = cp_get_regs_len,
1573 .get_sset_count = cp_get_sset_count,
1574 .get_settings = cp_get_settings,
1575 .set_settings = cp_set_settings,
1576 .nway_reset = cp_nway_reset,
1577 .get_link = ethtool_op_get_link,
1578 .get_msglevel = cp_get_msglevel,
1579 .set_msglevel = cp_set_msglevel,
1580 .get_regs = cp_get_regs,
1581 .get_wol = cp_get_wol,
1582 .set_wol = cp_set_wol,
1583 .get_strings = cp_get_strings,
1584 .get_ethtool_stats = cp_get_ethtool_stats,
1585 .get_eeprom_len = cp_get_eeprom_len,
1586 .get_eeprom = cp_get_eeprom,
1587 .set_eeprom = cp_set_eeprom,
1588 .get_ringparam = cp_get_ringparam,
1591 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1593 struct cp_private *cp = netdev_priv(dev);
1595 unsigned long flags;
1597 if (!netif_running(dev))
1600 spin_lock_irqsave(&cp->lock, flags);
1601 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1602 spin_unlock_irqrestore(&cp->lock, flags);
1606 static int cp_set_mac_address(struct net_device *dev, void *p)
1608 struct cp_private *cp = netdev_priv(dev);
1609 struct sockaddr *addr = p;
1611 if (!is_valid_ether_addr(addr->sa_data))
1612 return -EADDRNOTAVAIL;
1614 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1616 spin_lock_irq(&cp->lock);
1618 cpw8_f(Cfg9346, Cfg9346_Unlock);
1619 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1620 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1621 cpw8_f(Cfg9346, Cfg9346_Lock);
1623 spin_unlock_irq(&cp->lock);
1628 /* Serial EEPROM section. */
1630 /* EEPROM_Ctrl bits. */
1631 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1632 #define EE_CS 0x08 /* EEPROM chip select. */
1633 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1634 #define EE_WRITE_0 0x00
1635 #define EE_WRITE_1 0x02
1636 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1637 #define EE_ENB (0x80 | EE_CS)
1639 /* Delay between EEPROM clock transitions.
1640 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1643 #define eeprom_delay() readb(ee_addr)
1645 /* The EEPROM commands include the alway-set leading bit. */
1646 #define EE_EXTEND_CMD (4)
1647 #define EE_WRITE_CMD (5)
1648 #define EE_READ_CMD (6)
1649 #define EE_ERASE_CMD (7)
1651 #define EE_EWDS_ADDR (0)
1652 #define EE_WRAL_ADDR (1)
1653 #define EE_ERAL_ADDR (2)
1654 #define EE_EWEN_ADDR (3)
1656 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1658 static void eeprom_cmd_start(void __iomem *ee_addr)
1660 writeb (EE_ENB & ~EE_CS, ee_addr);
1661 writeb (EE_ENB, ee_addr);
1665 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1669 /* Shift the command bits out. */
1670 for (i = cmd_len - 1; i >= 0; i--) {
1671 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1672 writeb (EE_ENB | dataval, ee_addr);
1674 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1677 writeb (EE_ENB, ee_addr);
1681 static void eeprom_cmd_end(void __iomem *ee_addr)
1687 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1690 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1692 eeprom_cmd_start(ee_addr);
1693 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1694 eeprom_cmd_end(ee_addr);
1697 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1701 void __iomem *ee_addr = ioaddr + Cfg9346;
1702 int read_cmd = location | (EE_READ_CMD << addr_len);
1704 eeprom_cmd_start(ee_addr);
1705 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1707 for (i = 16; i > 0; i--) {
1708 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1711 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1713 writeb (EE_ENB, ee_addr);
1717 eeprom_cmd_end(ee_addr);
1722 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1726 void __iomem *ee_addr = ioaddr + Cfg9346;
1727 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1729 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1731 eeprom_cmd_start(ee_addr);
1732 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1733 eeprom_cmd(ee_addr, val, 16);
1734 eeprom_cmd_end(ee_addr);
1736 eeprom_cmd_start(ee_addr);
1737 for (i = 0; i < 20000; i++)
1738 if (readb(ee_addr) & EE_DATA_READ)
1740 eeprom_cmd_end(ee_addr);
1742 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1745 static int cp_get_eeprom_len(struct net_device *dev)
1747 struct cp_private *cp = netdev_priv(dev);
1750 spin_lock_irq(&cp->lock);
1751 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1752 spin_unlock_irq(&cp->lock);
1757 static int cp_get_eeprom(struct net_device *dev,
1758 struct ethtool_eeprom *eeprom, u8 *data)
1760 struct cp_private *cp = netdev_priv(dev);
1761 unsigned int addr_len;
1763 u32 offset = eeprom->offset >> 1;
1764 u32 len = eeprom->len;
1767 eeprom->magic = CP_EEPROM_MAGIC;
1769 spin_lock_irq(&cp->lock);
1771 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1773 if (eeprom->offset & 1) {
1774 val = read_eeprom(cp->regs, offset, addr_len);
1775 data[i++] = (u8)(val >> 8);
1779 while (i < len - 1) {
1780 val = read_eeprom(cp->regs, offset, addr_len);
1781 data[i++] = (u8)val;
1782 data[i++] = (u8)(val >> 8);
1787 val = read_eeprom(cp->regs, offset, addr_len);
1791 spin_unlock_irq(&cp->lock);
1795 static int cp_set_eeprom(struct net_device *dev,
1796 struct ethtool_eeprom *eeprom, u8 *data)
1798 struct cp_private *cp = netdev_priv(dev);
1799 unsigned int addr_len;
1801 u32 offset = eeprom->offset >> 1;
1802 u32 len = eeprom->len;
1805 if (eeprom->magic != CP_EEPROM_MAGIC)
1808 spin_lock_irq(&cp->lock);
1810 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1812 if (eeprom->offset & 1) {
1813 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1814 val |= (u16)data[i++] << 8;
1815 write_eeprom(cp->regs, offset, val, addr_len);
1819 while (i < len - 1) {
1820 val = (u16)data[i++];
1821 val |= (u16)data[i++] << 8;
1822 write_eeprom(cp->regs, offset, val, addr_len);
1827 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1828 val |= (u16)data[i];
1829 write_eeprom(cp->regs, offset, val, addr_len);
1832 spin_unlock_irq(&cp->lock);
1836 /* Put the board into D3cold state and wait for WakeUp signal */
1837 static void cp_set_d3_state (struct cp_private *cp)
1839 pci_enable_wake(cp->pdev, PCI_D0, 1); /* Enable PME# generation */
1840 pci_set_power_state (cp->pdev, PCI_D3hot);
1843 static const struct net_device_ops cp_netdev_ops = {
1844 .ndo_open = cp_open,
1845 .ndo_stop = cp_close,
1846 .ndo_validate_addr = eth_validate_addr,
1847 .ndo_set_mac_address = cp_set_mac_address,
1848 .ndo_set_rx_mode = cp_set_rx_mode,
1849 .ndo_get_stats = cp_get_stats,
1850 .ndo_do_ioctl = cp_ioctl,
1851 .ndo_start_xmit = cp_start_xmit,
1852 .ndo_tx_timeout = cp_tx_timeout,
1853 .ndo_set_features = cp_set_features,
1854 .ndo_change_mtu = cp_change_mtu,
1856 #ifdef CONFIG_NET_POLL_CONTROLLER
1857 .ndo_poll_controller = cp_poll_controller,
1861 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1863 struct net_device *dev;
1864 struct cp_private *cp;
1867 resource_size_t pciaddr;
1868 unsigned int addr_len, i, pci_using_dac;
1870 pr_info_once("%s", version);
1872 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1873 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1874 dev_info(&pdev->dev,
1875 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1876 pdev->vendor, pdev->device, pdev->revision);
1880 dev = alloc_etherdev(sizeof(struct cp_private));
1883 SET_NETDEV_DEV(dev, &pdev->dev);
1885 cp = netdev_priv(dev);
1888 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1889 spin_lock_init (&cp->lock);
1890 cp->mii_if.dev = dev;
1891 cp->mii_if.mdio_read = mdio_read;
1892 cp->mii_if.mdio_write = mdio_write;
1893 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1894 cp->mii_if.phy_id_mask = 0x1f;
1895 cp->mii_if.reg_num_mask = 0x1f;
1896 cp_set_rxbufsize(cp);
1898 rc = pci_enable_device(pdev);
1902 rc = pci_set_mwi(pdev);
1904 goto err_out_disable;
1906 rc = pci_request_regions(pdev, DRV_NAME);
1910 pciaddr = pci_resource_start(pdev, 1);
1913 dev_err(&pdev->dev, "no MMIO resource\n");
1916 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1918 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1919 (unsigned long long)pci_resource_len(pdev, 1));
1923 /* Configure DMA attributes. */
1924 if ((sizeof(dma_addr_t) > 4) &&
1925 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1926 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1931 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1934 "No usable DMA configuration, aborting\n");
1937 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1940 "No usable consistent DMA configuration, aborting\n");
1945 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1946 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1948 dev->features |= NETIF_F_RXCSUM;
1949 dev->hw_features |= NETIF_F_RXCSUM;
1951 regs = ioremap(pciaddr, CP_REGS_SIZE);
1954 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1955 (unsigned long long)pci_resource_len(pdev, 1),
1956 (unsigned long long)pciaddr);
1963 /* read MAC address from EEPROM */
1964 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1965 for (i = 0; i < 3; i++)
1966 ((__le16 *) (dev->dev_addr))[i] =
1967 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1969 dev->netdev_ops = &cp_netdev_ops;
1970 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1971 dev->ethtool_ops = &cp_ethtool_ops;
1972 dev->watchdog_timeo = TX_TIMEOUT;
1974 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1977 dev->features |= NETIF_F_HIGHDMA;
1979 /* disabled by default until verified */
1980 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1981 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1982 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1985 rc = register_netdev(dev);
1989 netdev_info(dev, "RTL-8139C+ at 0x%p, %pM, IRQ %d\n",
1990 regs, dev->dev_addr, pdev->irq);
1992 pci_set_drvdata(pdev, dev);
1994 /* enable busmastering and memory-write-invalidate */
1995 pci_set_master(pdev);
1997 if (cp->wol_enabled)
1998 cp_set_d3_state (cp);
2005 pci_release_regions(pdev);
2007 pci_clear_mwi(pdev);
2009 pci_disable_device(pdev);
2015 static void cp_remove_one (struct pci_dev *pdev)
2017 struct net_device *dev = pci_get_drvdata(pdev);
2018 struct cp_private *cp = netdev_priv(dev);
2020 unregister_netdev(dev);
2022 if (cp->wol_enabled)
2023 pci_set_power_state (pdev, PCI_D0);
2024 pci_release_regions(pdev);
2025 pci_clear_mwi(pdev);
2026 pci_disable_device(pdev);
2031 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2033 struct net_device *dev = pci_get_drvdata(pdev);
2034 struct cp_private *cp = netdev_priv(dev);
2035 unsigned long flags;
2037 if (!netif_running(dev))
2040 netif_device_detach (dev);
2041 netif_stop_queue (dev);
2043 spin_lock_irqsave (&cp->lock, flags);
2045 /* Disable Rx and Tx */
2046 cpw16 (IntrMask, 0);
2047 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2049 spin_unlock_irqrestore (&cp->lock, flags);
2051 pci_save_state(pdev);
2052 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2053 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2058 static int cp_resume (struct pci_dev *pdev)
2060 struct net_device *dev = pci_get_drvdata (pdev);
2061 struct cp_private *cp = netdev_priv(dev);
2062 unsigned long flags;
2064 if (!netif_running(dev))
2067 netif_device_attach (dev);
2069 pci_set_power_state(pdev, PCI_D0);
2070 pci_restore_state(pdev);
2071 pci_enable_wake(pdev, PCI_D0, 0);
2073 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2074 cp_init_rings_index (cp);
2077 netif_start_queue (dev);
2079 spin_lock_irqsave (&cp->lock, flags);
2081 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2083 spin_unlock_irqrestore (&cp->lock, flags);
2087 #endif /* CONFIG_PM */
2089 static const struct pci_device_id cp_pci_tbl[] = {
2090 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
2091 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
2094 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
2096 static struct pci_driver cp_driver = {
2098 .id_table = cp_pci_tbl,
2099 .probe = cp_init_one,
2100 .remove = cp_remove_one,
2102 .resume = cp_resume,
2103 .suspend = cp_suspend,
2107 module_pci_driver(cp_driver);