3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
46 Tigran Aivazian - bug fixes, skbuff free cleanup
48 Martin Mares - suggestions for PCI cleanup
50 David S. Miller - PCI DMA and softnet updates
52 Ernst Gill - fixes ported from BSD driver
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
57 Gerard Sharp - bug fix, testing and feedback
59 David Ford - Rx ring wrap fix
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
67 Santiago Garcia Mantinan - testing and feedback
69 Jens David - 2.2.x kernel backports
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
74 Jean-Jacques Michel - bug fix
76 Tobias Ringström - Rx interrupt status checking suggestion
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
83 Robert Kuebel - Save kernel thread from dying on any signal.
85 Submitting bug reports:
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/rtnetlink.h>
107 #include <linux/delay.h>
108 #include <linux/ethtool.h>
109 #include <linux/mii.h>
110 #include <linux/completion.h>
111 #include <linux/crc32.h>
112 #include <linux/io.h>
113 #include <linux/uaccess.h>
114 #include <linux/gfp.h>
117 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
125 /* define to 1, 2 or 3 to enable copious debugging info */
126 #define RTL8139_DEBUG 0
128 /* define to 1 to disable lightweight runtime debugging checks */
129 #undef RTL8139_NDEBUG
132 #ifdef RTL8139_NDEBUG
133 # define assert(expr) do {} while (0)
135 # define assert(expr) \
136 if (unlikely(!(expr))) { \
137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
143 /* A few user-configurable values. */
146 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
149 /* Whether to use MMIO or PIO. Default to MMIO. */
150 #ifdef CONFIG_8139TOO_PIO
151 static bool use_io = true;
153 static bool use_io = false;
156 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
157 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
158 static int multicast_filter_limit = 32;
160 /* bitmapped message enable number */
161 static int debug = -1;
165 * Warning: 64K ring has hardware issues and may lock up.
167 #if defined(CONFIG_SH_DREAMCAST)
168 #define RX_BUF_IDX 0 /* 8K ring */
170 #define RX_BUF_IDX 2 /* 32K ring */
172 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
173 #define RX_BUF_PAD 16
174 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
176 #if RX_BUF_LEN == 65536
177 #define RX_BUF_TOT_LEN RX_BUF_LEN
179 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
182 /* Number of Tx descriptor registers. */
183 #define NUM_TX_DESC 4
185 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
186 #define MAX_ETH_FRAME_SIZE 1536
188 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
189 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
190 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
192 /* PCI Tuning Parameters
193 Threshold is bytes transferred to chip before transmission starts. */
194 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
196 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
197 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
198 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
199 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
200 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
202 /* Operational parameters that usually are not changed. */
203 /* Time in jiffies before concluding the transmitter is hung. */
204 #define TX_TIMEOUT (6*HZ)
208 HAS_MII_XCVR = 0x010000,
209 HAS_CHIP_XCVR = 0x020000,
210 HAS_LNK_CHNG = 0x040000,
213 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
214 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
215 #define RTL_MIN_IO_SIZE 0x80
216 #define RTL8139B_IO_SIZE 256
218 #define RTL8129_CAPS HAS_MII_XCVR
219 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
227 /* indexed by board_t, above */
228 static const struct {
232 { "RealTek RTL8139", RTL8139_CAPS },
233 { "RealTek RTL8129", RTL8129_CAPS },
237 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 #ifdef CONFIG_SH_SECUREEDGE5410
259 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262 #ifdef CONFIG_8139TOO_8129
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
266 /* some crazy cards report invalid vendor ids like
267 * 0x0001 here. The other ids are valid and constant,
268 * so we simply don't match on the main vendor id.
270 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
272 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
279 const char str[ETH_GSTRING_LEN];
280 } ethtool_stats_keys[] = {
284 { "rx_lost_in_ring" },
287 /* The rest of these values should never change. */
289 /* Symbolic offsets to registers. */
290 enum RTL8139_registers {
291 MAC0 = 0, /* Ethernet hardware address. */
292 MAR0 = 8, /* Multicast filter. */
293 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
294 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
303 Timer = 0x48, /* A general-purpose counter. */
304 RxMissed = 0x4C, /* 24 bits valid, write clears. */
311 Config4 = 0x5A, /* absent on RTL-8139A */
315 BasicModeCtrl = 0x62,
316 BasicModeStatus = 0x64,
319 NWayExpansion = 0x6A,
320 /* Undocumented registers, but required for proper operation. */
321 FIFOTMS = 0x70, /* FIFO Control and test. */
322 CSCR = 0x74, /* Chip Status and Configuration Register. */
324 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
325 PARA7c = 0x7c, /* Magic transceiver parameter register. */
326 Config5 = 0xD8, /* absent on RTL-8139A */
330 MultiIntrClear = 0xF000,
332 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
342 /* Interrupt register bits, using my own meaningful names. */
343 enum IntrStatusBits {
354 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
361 TxOutOfWindow = 0x20000000,
362 TxAborted = 0x40000000,
363 TxCarrierLost = 0x80000000,
366 RxMulticast = 0x8000,
368 RxBroadcast = 0x2000,
369 RxBadSymbol = 0x0020,
377 /* Bits in RxConfig. */
381 AcceptBroadcast = 0x08,
382 AcceptMulticast = 0x04,
384 AcceptAllPhys = 0x01,
387 /* Bits in TxConfig. */
388 enum tx_config_bits {
389 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
391 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
392 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
393 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
394 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
396 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
397 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
398 TxClearAbt = (1 << 0), /* Clear abort (WO) */
399 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
400 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
402 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 /* Bits in Config1 */
407 Cfg1_PM_Enable = 0x01,
408 Cfg1_VPD_Enable = 0x02,
411 LWAKE = 0x10, /* not on 8139, 8139A */
412 Cfg1_Driver_Load = 0x20,
415 SLEEP = (1 << 1), /* only on 8139, 8139A */
416 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 /* Bits in Config3 */
421 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
422 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
423 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
424 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
425 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
426 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
427 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
428 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 /* Bits in Config4 */
433 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 /* Bits in Config5 */
438 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
439 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
440 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
441 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
442 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
443 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
444 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 /* rx fifo threshold */
450 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
456 /* rx ring buffer length */
458 RxCfgRcv16K = (1 << 11),
459 RxCfgRcv32K = (1 << 12),
460 RxCfgRcv64K = (1 << 11) | (1 << 12),
462 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 /* Twister tuning parameters from RealTek.
467 Completely undocumented, but required to tune bad links on some boards. */
469 CSCR_LinkOKBit = 0x0400,
470 CSCR_LinkChangeBit = 0x0800,
471 CSCR_LinkStatusBits = 0x0f000,
472 CSCR_LinkDownOffCmd = 0x003c0,
473 CSCR_LinkDownCmd = 0x0f3c0,
478 Cfg9346_Unlock = 0xC0,
495 HasHltClk = (1 << 0),
499 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
500 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
501 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
503 /* directly indexed by chip_t, above */
504 static const struct {
506 u32 version; /* from RTL8139C/RTL8139D docs */
508 } rtl_chip_info[] = {
510 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HW_REVID(1, 1, 1, 0, 0, 0, 0),
521 HasHltClk, /* XXX undocumented? */
525 HW_REVID(1, 1, 1, 0, 0, 1, 0),
526 HasHltClk, /* XXX undocumented? */
530 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HW_REVID(1, 1, 1, 0, 1, 0, 1),
551 HasHltClk /* XXX undocumented? */
556 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 struct rtl_extra_stats {
562 unsigned long early_rx;
563 unsigned long tx_buf_mapped;
564 unsigned long tx_timeouts;
565 unsigned long rx_lost_in_ring;
568 struct rtl8139_stats {
571 struct u64_stats_sync syncp;
574 struct rtl8139_private {
575 void __iomem *mmio_addr;
577 struct pci_dev *pci_dev;
579 struct napi_struct napi;
580 struct net_device *dev;
582 unsigned char *rx_ring;
583 unsigned int cur_rx; /* RX buf index of next pkt */
584 struct rtl8139_stats rx_stats;
585 dma_addr_t rx_ring_dma;
587 unsigned int tx_flag;
588 unsigned long cur_tx;
589 unsigned long dirty_tx;
590 struct rtl8139_stats tx_stats;
591 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
592 unsigned char *tx_bufs; /* Tx bounce buffer region. */
593 dma_addr_t tx_bufs_dma;
595 signed char phys[4]; /* MII device addresses. */
597 /* Twister tune state. */
598 char twistie, twist_row, twist_col;
600 unsigned int watchdog_fired : 1;
601 unsigned int default_port : 4; /* Last dev->if_port value. */
602 unsigned int have_thread : 1;
609 struct rtl_extra_stats xstats;
611 struct delayed_work thread;
613 struct mii_if_info mii;
614 unsigned int regs_len;
615 unsigned long fifo_copy_timeout;
618 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
619 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
620 MODULE_LICENSE("GPL");
621 MODULE_VERSION(DRV_VERSION);
623 module_param(use_io, bool, 0);
624 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
625 module_param(multicast_filter_limit, int, 0);
626 module_param_array(media, int, NULL, 0);
627 module_param_array(full_duplex, int, NULL, 0);
628 module_param(debug, int, 0);
629 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
630 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
631 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
632 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
634 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
635 static int rtl8139_open (struct net_device *dev);
636 static int mdio_read (struct net_device *dev, int phy_id, int location);
637 static void mdio_write (struct net_device *dev, int phy_id, int location,
639 static void rtl8139_start_thread(struct rtl8139_private *tp);
640 static void rtl8139_tx_timeout (struct net_device *dev);
641 static void rtl8139_init_ring (struct net_device *dev);
642 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
643 struct net_device *dev);
644 #ifdef CONFIG_NET_POLL_CONTROLLER
645 static void rtl8139_poll_controller(struct net_device *dev);
647 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
648 static int rtl8139_poll(struct napi_struct *napi, int budget);
649 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
650 static int rtl8139_close (struct net_device *dev);
651 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
652 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
653 struct rtnl_link_stats64
655 static void rtl8139_set_rx_mode (struct net_device *dev);
656 static void __set_rx_mode (struct net_device *dev);
657 static void rtl8139_hw_start (struct net_device *dev);
658 static void rtl8139_thread (struct work_struct *work);
659 static void rtl8139_tx_timeout_task(struct work_struct *work);
660 static const struct ethtool_ops rtl8139_ethtool_ops;
662 /* write MMIO register, with flush */
663 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
664 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
665 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
666 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
668 /* write MMIO register */
669 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
670 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
671 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
673 /* read MMIO register */
674 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
675 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
676 #define RTL_R32(reg) ioread32 (ioaddr + (reg))
679 static const u16 rtl8139_intr_mask =
680 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
681 TxErr | TxOK | RxErr | RxOK;
683 static const u16 rtl8139_norx_intr_mask =
684 PCIErr | PCSTimeout | RxUnderrun |
685 TxErr | TxOK | RxErr ;
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv8K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 1
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv16K | RxNoWrap |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #elif RX_BUF_IDX == 2
698 static const unsigned int rtl8139_rx_config =
699 RxCfgRcv32K | RxNoWrap |
700 (RX_FIFO_THRESH << RxCfgFIFOShift) |
701 (RX_DMA_BURST << RxCfgDMAShift);
702 #elif RX_BUF_IDX == 3
703 static const unsigned int rtl8139_rx_config =
705 (RX_FIFO_THRESH << RxCfgFIFOShift) |
706 (RX_DMA_BURST << RxCfgDMAShift);
708 #error "Invalid configuration for 8139_RXBUF_IDX"
711 static const unsigned int rtl8139_tx_config =
712 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
714 static void __rtl8139_cleanup_dev (struct net_device *dev)
716 struct rtl8139_private *tp = netdev_priv(dev);
717 struct pci_dev *pdev;
719 assert (dev != NULL);
720 assert (tp->pci_dev != NULL);
724 pci_iounmap (pdev, tp->mmio_addr);
726 /* it's ok to call this even if we have no regions to free */
727 pci_release_regions (pdev);
733 static void rtl8139_chip_reset (void __iomem *ioaddr)
737 /* Soft reset the chip. */
738 RTL_W8 (ChipCmd, CmdReset);
740 /* Check that the chip has finished the reset. */
741 for (i = 1000; i > 0; i--) {
743 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
750 static struct net_device *rtl8139_init_board(struct pci_dev *pdev)
752 struct device *d = &pdev->dev;
753 void __iomem *ioaddr;
754 struct net_device *dev;
755 struct rtl8139_private *tp;
757 int rc, disable_dev_on_err = 0;
759 unsigned long io_len;
761 static const struct {
765 { IORESOURCE_IO, "PIO" },
766 { IORESOURCE_MEM, "MMIO" }
769 assert (pdev != NULL);
771 /* dev and priv zeroed in alloc_etherdev */
772 dev = alloc_etherdev (sizeof (*tp));
774 return ERR_PTR(-ENOMEM);
776 SET_NETDEV_DEV(dev, &pdev->dev);
778 tp = netdev_priv(dev);
781 /* enable device (incl. PCI PM wakeup and hotplug setup) */
782 rc = pci_enable_device (pdev);
786 rc = pci_request_regions (pdev, DRV_NAME);
789 disable_dev_on_err = 1;
791 pci_set_master (pdev);
794 /* PIO bar register comes first. */
797 io_len = pci_resource_len(pdev, bar);
799 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
801 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
802 dev_err(d, "region #%d not a %s resource, aborting\n", bar,
807 if (io_len < RTL_MIN_IO_SIZE) {
808 dev_err(d, "Invalid PCI %s region size(s), aborting\n",
814 ioaddr = pci_iomap(pdev, bar, 0);
816 dev_err(d, "cannot map %s\n", res[bar].type);
824 tp->regs_len = io_len;
825 tp->mmio_addr = ioaddr;
827 /* Bring old chips out of low-power mode. */
828 RTL_W8 (HltClk, 'R');
830 /* check for missing/broken hardware */
831 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
832 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
837 /* identify chip attached to board */
838 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
839 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
840 if (version == rtl_chip_info[i].version) {
845 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
847 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
848 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
852 pr_debug("chipset id (%d) == index %d, '%s'\n",
853 version, i, rtl_chip_info[i].name);
855 if (tp->chipset >= CH_8139B) {
856 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
857 pr_debug("PCI PM wakeup\n");
858 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
861 new_tmp8 |= Cfg1_PM_Enable;
862 if (new_tmp8 != tmp8) {
863 RTL_W8 (Cfg9346, Cfg9346_Unlock);
864 RTL_W8 (Config1, tmp8);
865 RTL_W8 (Cfg9346, Cfg9346_Lock);
867 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
868 tmp8 = RTL_R8 (Config4);
870 RTL_W8 (Cfg9346, Cfg9346_Unlock);
871 RTL_W8 (Config4, tmp8 & ~LWPTN);
872 RTL_W8 (Cfg9346, Cfg9346_Lock);
876 pr_debug("Old chip wakeup\n");
877 tmp8 = RTL_R8 (Config1);
878 tmp8 &= ~(SLEEP | PWRDN);
879 RTL_W8 (Config1, tmp8);
882 rtl8139_chip_reset (ioaddr);
887 __rtl8139_cleanup_dev (dev);
888 if (disable_dev_on_err)
889 pci_disable_device (pdev);
893 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
895 struct rtl8139_private *tp = netdev_priv(dev);
897 netdev_features_t changed = features ^ dev->features;
898 void __iomem *ioaddr = tp->mmio_addr;
900 if (!(changed & (NETIF_F_RXALL)))
903 spin_lock_irqsave(&tp->lock, flags);
905 if (changed & NETIF_F_RXALL) {
906 int rx_mode = tp->rx_config;
907 if (features & NETIF_F_RXALL)
908 rx_mode |= (AcceptErr | AcceptRunt);
910 rx_mode &= ~(AcceptErr | AcceptRunt);
911 tp->rx_config = rtl8139_rx_config | rx_mode;
912 RTL_W32_F(RxConfig, tp->rx_config);
915 spin_unlock_irqrestore(&tp->lock, flags);
920 static const struct net_device_ops rtl8139_netdev_ops = {
921 .ndo_open = rtl8139_open,
922 .ndo_stop = rtl8139_close,
923 .ndo_get_stats64 = rtl8139_get_stats64,
924 .ndo_change_mtu = eth_change_mtu,
925 .ndo_validate_addr = eth_validate_addr,
926 .ndo_set_mac_address = rtl8139_set_mac_address,
927 .ndo_start_xmit = rtl8139_start_xmit,
928 .ndo_set_rx_mode = rtl8139_set_rx_mode,
929 .ndo_do_ioctl = netdev_ioctl,
930 .ndo_tx_timeout = rtl8139_tx_timeout,
931 #ifdef CONFIG_NET_POLL_CONTROLLER
932 .ndo_poll_controller = rtl8139_poll_controller,
934 .ndo_set_features = rtl8139_set_features,
937 static int rtl8139_init_one(struct pci_dev *pdev,
938 const struct pci_device_id *ent)
940 struct net_device *dev = NULL;
941 struct rtl8139_private *tp;
942 int i, addr_len, option;
943 void __iomem *ioaddr;
944 static int board_idx = -1;
946 assert (pdev != NULL);
947 assert (ent != NULL);
951 /* when we're built into the kernel, the driver version message
952 * is only printed if at least one 8139 board has been found
956 static int printed_version;
957 if (!printed_version++)
958 pr_info(RTL8139_DRIVER_NAME "\n");
962 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
963 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
965 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
966 pdev->vendor, pdev->device, pdev->revision);
970 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
971 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
972 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
973 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
974 pr_info("OQO Model 2 detected. Forcing PIO\n");
978 dev = rtl8139_init_board (pdev);
982 assert (dev != NULL);
983 tp = netdev_priv(dev);
986 ioaddr = tp->mmio_addr;
987 assert (ioaddr != NULL);
989 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
990 for (i = 0; i < 3; i++)
991 ((__le16 *) (dev->dev_addr))[i] =
992 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
994 /* The Rtl8139-specific entries in the device structure. */
995 dev->netdev_ops = &rtl8139_netdev_ops;
996 dev->ethtool_ops = &rtl8139_ethtool_ops;
997 dev->watchdog_timeo = TX_TIMEOUT;
998 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
1000 /* note: the hardware is not capable of sg/csum/highdma, however
1001 * through the use of skb_copy_and_csum_dev we enable these
1004 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1005 dev->vlan_features = dev->features;
1007 dev->hw_features |= NETIF_F_RXALL;
1008 dev->hw_features |= NETIF_F_RXFCS;
1010 /* tp zeroed and aligned in alloc_etherdev */
1011 tp = netdev_priv(dev);
1013 /* note: tp->chipset set in rtl8139_init_board */
1014 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1015 tp->mmio_addr = ioaddr;
1017 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1018 spin_lock_init (&tp->lock);
1019 spin_lock_init (&tp->rx_lock);
1020 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1022 tp->mii.mdio_read = mdio_read;
1023 tp->mii.mdio_write = mdio_write;
1024 tp->mii.phy_id_mask = 0x3f;
1025 tp->mii.reg_num_mask = 0x1f;
1027 /* dev is fully set up and ready to use now */
1028 pr_debug("about to register device named %s (%p)...\n",
1030 i = register_netdev (dev);
1031 if (i) goto err_out;
1033 pci_set_drvdata (pdev, dev);
1035 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n",
1036 board_info[ent->driver_data].name,
1037 ioaddr, dev->dev_addr, pdev->irq);
1039 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1040 rtl_chip_info[tp->chipset].name);
1042 /* Find the connected MII xcvrs.
1043 Doing this in open() would allow detecting external xcvrs later, but
1044 takes too much time. */
1045 #ifdef CONFIG_8139TOO_8129
1046 if (tp->drv_flags & HAS_MII_XCVR) {
1047 int phy, phy_idx = 0;
1048 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1049 int mii_status = mdio_read(dev, phy, 1);
1050 if (mii_status != 0xffff && mii_status != 0x0000) {
1051 u16 advertising = mdio_read(dev, phy, 4);
1052 tp->phys[phy_idx++] = phy;
1053 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1054 phy, mii_status, advertising);
1058 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1064 tp->mii.phy_id = tp->phys[0];
1066 /* The lower four bits are the media type. */
1067 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1069 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1070 tp->default_port = option & 0xFF;
1071 if (tp->default_port)
1072 tp->mii.force_media = 1;
1074 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1075 tp->mii.full_duplex = full_duplex[board_idx];
1076 if (tp->mii.full_duplex) {
1077 netdev_info(dev, "Media type forced to Full Duplex\n");
1078 /* Changing the MII-advertised media because might prevent
1080 tp->mii.force_media = 1;
1082 if (tp->default_port) {
1083 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1084 (option & 0x20 ? 100 : 10),
1085 (option & 0x10 ? "full" : "half"));
1086 mdio_write(dev, tp->phys[0], 0,
1087 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1088 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1091 /* Put the chip into low-power mode. */
1092 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1093 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1098 __rtl8139_cleanup_dev (dev);
1099 pci_disable_device (pdev);
1104 static void rtl8139_remove_one(struct pci_dev *pdev)
1106 struct net_device *dev = pci_get_drvdata (pdev);
1107 struct rtl8139_private *tp = netdev_priv(dev);
1109 assert (dev != NULL);
1111 cancel_delayed_work_sync(&tp->thread);
1113 unregister_netdev (dev);
1115 __rtl8139_cleanup_dev (dev);
1116 pci_disable_device (pdev);
1120 /* Serial EEPROM section. */
1122 /* EEPROM_Ctrl bits. */
1123 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1124 #define EE_CS 0x08 /* EEPROM chip select. */
1125 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1126 #define EE_WRITE_0 0x00
1127 #define EE_WRITE_1 0x02
1128 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1129 #define EE_ENB (0x80 | EE_CS)
1131 /* Delay between EEPROM clock transitions.
1132 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1135 #define eeprom_delay() (void)RTL_R8(Cfg9346)
1137 /* The EEPROM commands include the alway-set leading bit. */
1138 #define EE_WRITE_CMD (5)
1139 #define EE_READ_CMD (6)
1140 #define EE_ERASE_CMD (7)
1142 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len)
1145 unsigned retval = 0;
1146 int read_cmd = location | (EE_READ_CMD << addr_len);
1148 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1149 RTL_W8 (Cfg9346, EE_ENB);
1152 /* Shift the read command bits out. */
1153 for (i = 4 + addr_len; i >= 0; i--) {
1154 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1155 RTL_W8 (Cfg9346, EE_ENB | dataval);
1157 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1160 RTL_W8 (Cfg9346, EE_ENB);
1163 for (i = 16; i > 0; i--) {
1164 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1167 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1169 RTL_W8 (Cfg9346, EE_ENB);
1173 /* Terminate the EEPROM access. */
1180 /* MII serial management: mostly bogus for now. */
1181 /* Read and write the MII management registers using software-generated
1182 serial MDIO protocol.
1183 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1184 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1185 "overclocking" issues. */
1186 #define MDIO_DIR 0x80
1187 #define MDIO_DATA_OUT 0x04
1188 #define MDIO_DATA_IN 0x02
1189 #define MDIO_CLK 0x01
1190 #define MDIO_WRITE0 (MDIO_DIR)
1191 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1193 #define mdio_delay() RTL_R8(Config4)
1196 static const char mii_2_8139_map[8] = {
1208 #ifdef CONFIG_8139TOO_8129
1209 /* Syncronize the MII management interface by shifting 32 one bits out. */
1210 static void mdio_sync (void __iomem *ioaddr)
1214 for (i = 32; i >= 0; i--) {
1215 RTL_W8 (Config4, MDIO_WRITE1);
1217 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1223 static int mdio_read (struct net_device *dev, int phy_id, int location)
1225 struct rtl8139_private *tp = netdev_priv(dev);
1227 #ifdef CONFIG_8139TOO_8129
1228 void __iomem *ioaddr = tp->mmio_addr;
1229 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1233 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1234 void __iomem *ioaddr = tp->mmio_addr;
1235 return location < 8 && mii_2_8139_map[location] ?
1236 RTL_R16 (mii_2_8139_map[location]) : 0;
1239 #ifdef CONFIG_8139TOO_8129
1241 /* Shift the read command bits out. */
1242 for (i = 15; i >= 0; i--) {
1243 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1245 RTL_W8 (Config4, MDIO_DIR | dataval);
1247 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1251 /* Read the two transition, 16 data, and wire-idle bits. */
1252 for (i = 19; i > 0; i--) {
1253 RTL_W8 (Config4, 0);
1255 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1256 RTL_W8 (Config4, MDIO_CLK);
1261 return (retval >> 1) & 0xffff;
1265 static void mdio_write (struct net_device *dev, int phy_id, int location,
1268 struct rtl8139_private *tp = netdev_priv(dev);
1269 #ifdef CONFIG_8139TOO_8129
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1275 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1276 void __iomem *ioaddr = tp->mmio_addr;
1277 if (location == 0) {
1278 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1279 RTL_W16 (BasicModeCtrl, value);
1280 RTL_W8 (Cfg9346, Cfg9346_Lock);
1281 } else if (location < 8 && mii_2_8139_map[location])
1282 RTL_W16 (mii_2_8139_map[location], value);
1286 #ifdef CONFIG_8139TOO_8129
1289 /* Shift the command bits out. */
1290 for (i = 31; i >= 0; i--) {
1292 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1293 RTL_W8 (Config4, dataval);
1295 RTL_W8 (Config4, dataval | MDIO_CLK);
1298 /* Clear out extra bits. */
1299 for (i = 2; i > 0; i--) {
1300 RTL_W8 (Config4, 0);
1302 RTL_W8 (Config4, MDIO_CLK);
1309 static int rtl8139_open (struct net_device *dev)
1311 struct rtl8139_private *tp = netdev_priv(dev);
1312 void __iomem *ioaddr = tp->mmio_addr;
1313 const int irq = tp->pci_dev->irq;
1316 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1320 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1321 &tp->tx_bufs_dma, GFP_KERNEL);
1322 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1323 &tp->rx_ring_dma, GFP_KERNEL);
1324 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1328 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1329 tp->tx_bufs, tp->tx_bufs_dma);
1331 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1332 tp->rx_ring, tp->rx_ring_dma);
1338 napi_enable(&tp->napi);
1340 tp->mii.full_duplex = tp->mii.force_media;
1341 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1343 rtl8139_init_ring (dev);
1344 rtl8139_hw_start (dev);
1345 netif_start_queue (dev);
1347 netif_dbg(tp, ifup, dev,
1348 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1350 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1351 irq, RTL_R8 (MediaStatus),
1352 tp->mii.full_duplex ? "full" : "half");
1354 rtl8139_start_thread(tp);
1360 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1362 struct rtl8139_private *tp = netdev_priv(dev);
1364 if (tp->phys[0] >= 0) {
1365 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1369 /* Start the hardware at open or resume. */
1370 static void rtl8139_hw_start (struct net_device *dev)
1372 struct rtl8139_private *tp = netdev_priv(dev);
1373 void __iomem *ioaddr = tp->mmio_addr;
1377 /* Bring old chips out of low-power mode. */
1378 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1379 RTL_W8 (HltClk, 'R');
1381 rtl8139_chip_reset (ioaddr);
1383 /* unlock Config[01234] and BMCR register writes */
1384 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1385 /* Restore our idea of the MAC address. */
1386 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1387 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1391 /* init Rx ring buffer DMA address */
1392 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1394 /* Must enable Tx/Rx before setting transfer thresholds! */
1395 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1397 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1398 RTL_W32 (RxConfig, tp->rx_config);
1399 RTL_W32 (TxConfig, rtl8139_tx_config);
1401 rtl_check_media (dev, 1);
1403 if (tp->chipset >= CH_8139B) {
1404 /* Disable magic packet scanning, which is enabled
1405 * when PM is enabled in Config1. It can be reenabled
1406 * via ETHTOOL_SWOL if desired. */
1407 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1410 netdev_dbg(dev, "init buffer addresses\n");
1412 /* Lock Config[01234] and BMCR register writes */
1413 RTL_W8 (Cfg9346, Cfg9346_Lock);
1415 /* init Tx buffer DMA addresses */
1416 for (i = 0; i < NUM_TX_DESC; i++)
1417 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1419 RTL_W32 (RxMissed, 0);
1421 rtl8139_set_rx_mode (dev);
1423 /* no early-rx interrupts */
1424 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1426 /* make sure RxTx has started */
1427 tmp = RTL_R8 (ChipCmd);
1428 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1429 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1431 /* Enable all known interrupts by setting the interrupt mask. */
1432 RTL_W16 (IntrMask, rtl8139_intr_mask);
1436 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1437 static void rtl8139_init_ring (struct net_device *dev)
1439 struct rtl8139_private *tp = netdev_priv(dev);
1446 for (i = 0; i < NUM_TX_DESC; i++)
1447 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1451 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1452 static int next_tick = 3 * HZ;
1454 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1455 static inline void rtl8139_tune_twister (struct net_device *dev,
1456 struct rtl8139_private *tp) {}
1458 enum TwisterParamVals {
1459 PARA78_default = 0x78fa8388,
1460 PARA7c_default = 0xcb38de43, /* param[0][3] */
1461 PARA7c_xxx = 0xcb38de43,
1464 static const unsigned long param[4][4] = {
1465 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1466 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1467 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1468 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1471 static void rtl8139_tune_twister (struct net_device *dev,
1472 struct rtl8139_private *tp)
1475 void __iomem *ioaddr = tp->mmio_addr;
1477 /* This is a complicated state machine to configure the "twister" for
1478 impedance/echos based on the cable length.
1479 All of this is magic and undocumented.
1481 switch (tp->twistie) {
1483 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1484 /* We have link beat, let us tune the twister. */
1485 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1486 tp->twistie = 2; /* Change to state 2. */
1487 next_tick = HZ / 10;
1489 /* Just put in some reasonable defaults for when beat returns. */
1490 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1491 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1492 RTL_W32 (PARA78, PARA78_default);
1493 RTL_W32 (PARA7c, PARA7c_default);
1494 tp->twistie = 0; /* Bail from future actions. */
1498 /* Read how long it took to hear the echo. */
1499 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1500 if (linkcase == 0x7000)
1502 else if (linkcase == 0x3000)
1504 else if (linkcase == 0x1000)
1509 tp->twistie = 3; /* Change to state 2. */
1510 next_tick = HZ / 10;
1513 /* Put out four tuning parameters, one per 100msec. */
1514 if (tp->twist_col == 0)
1515 RTL_W16 (FIFOTMS, 0);
1516 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1517 [(int) tp->twist_col]);
1518 next_tick = HZ / 10;
1519 if (++tp->twist_col >= 4) {
1520 /* For short cables we are done.
1521 For long cables (row == 3) check for mistune. */
1523 (tp->twist_row == 3) ? 4 : 0;
1527 /* Special case for long cables: check for mistune. */
1528 if ((RTL_R16 (CSCR) &
1529 CSCR_LinkStatusBits) == 0x7000) {
1533 RTL_W32 (PARA7c, 0xfb38de03);
1535 next_tick = HZ / 10;
1539 /* Retune for shorter cable (column 2). */
1540 RTL_W32 (FIFOTMS, 0x20);
1541 RTL_W32 (PARA78, PARA78_default);
1542 RTL_W32 (PARA7c, PARA7c_default);
1543 RTL_W32 (FIFOTMS, 0x00);
1547 next_tick = HZ / 10;
1555 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1557 static inline void rtl8139_thread_iter (struct net_device *dev,
1558 struct rtl8139_private *tp,
1559 void __iomem *ioaddr)
1563 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1565 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1566 int duplex = ((mii_lpa & LPA_100FULL) ||
1567 (mii_lpa & 0x01C0) == 0x0040);
1568 if (tp->mii.full_duplex != duplex) {
1569 tp->mii.full_duplex = duplex;
1572 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1573 tp->mii.full_duplex ? "full" : "half",
1574 tp->phys[0], mii_lpa);
1576 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1579 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1580 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1581 RTL_W8 (Cfg9346, Cfg9346_Lock);
1586 next_tick = HZ * 60;
1588 rtl8139_tune_twister (dev, tp);
1590 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1592 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1593 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1594 netdev_dbg(dev, "Chip config %02x %02x\n",
1595 RTL_R8(Config0), RTL_R8(Config1));
1598 static void rtl8139_thread (struct work_struct *work)
1600 struct rtl8139_private *tp =
1601 container_of(work, struct rtl8139_private, thread.work);
1602 struct net_device *dev = tp->mii.dev;
1603 unsigned long thr_delay = next_tick;
1607 if (!netif_running(dev))
1610 if (tp->watchdog_fired) {
1611 tp->watchdog_fired = 0;
1612 rtl8139_tx_timeout_task(work);
1614 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1616 if (tp->have_thread)
1617 schedule_delayed_work(&tp->thread, thr_delay);
1622 static void rtl8139_start_thread(struct rtl8139_private *tp)
1625 if (tp->chipset == CH_8139_K)
1627 else if (tp->drv_flags & HAS_LNK_CHNG)
1630 tp->have_thread = 1;
1631 tp->watchdog_fired = 0;
1633 schedule_delayed_work(&tp->thread, next_tick);
1636 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1641 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1644 static void rtl8139_tx_timeout_task (struct work_struct *work)
1646 struct rtl8139_private *tp =
1647 container_of(work, struct rtl8139_private, thread.work);
1648 struct net_device *dev = tp->mii.dev;
1649 void __iomem *ioaddr = tp->mmio_addr;
1653 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1654 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1655 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1656 /* Emit info to figure out what went wrong. */
1657 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1658 tp->cur_tx, tp->dirty_tx);
1659 for (i = 0; i < NUM_TX_DESC; i++)
1660 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1661 i, RTL_R32(TxStatus0 + (i * 4)),
1662 i == tp->dirty_tx % NUM_TX_DESC ?
1663 " (queue head)" : "");
1665 tp->xstats.tx_timeouts++;
1667 /* disable Tx ASAP, if not already */
1668 tmp8 = RTL_R8 (ChipCmd);
1669 if (tmp8 & CmdTxEnb)
1670 RTL_W8 (ChipCmd, CmdRxEnb);
1672 spin_lock_bh(&tp->rx_lock);
1673 /* Disable interrupts by clearing the interrupt mask. */
1674 RTL_W16 (IntrMask, 0x0000);
1676 /* Stop a shared interrupt from scavenging while we are. */
1677 spin_lock_irq(&tp->lock);
1678 rtl8139_tx_clear (tp);
1679 spin_unlock_irq(&tp->lock);
1681 /* ...and finally, reset everything */
1682 if (netif_running(dev)) {
1683 rtl8139_hw_start (dev);
1684 netif_wake_queue (dev);
1686 spin_unlock_bh(&tp->rx_lock);
1689 static void rtl8139_tx_timeout (struct net_device *dev)
1691 struct rtl8139_private *tp = netdev_priv(dev);
1693 tp->watchdog_fired = 1;
1694 if (!tp->have_thread) {
1695 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1696 schedule_delayed_work(&tp->thread, next_tick);
1700 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1701 struct net_device *dev)
1703 struct rtl8139_private *tp = netdev_priv(dev);
1704 void __iomem *ioaddr = tp->mmio_addr;
1706 unsigned int len = skb->len;
1707 unsigned long flags;
1709 /* Calculate the next Tx descriptor entry. */
1710 entry = tp->cur_tx % NUM_TX_DESC;
1712 /* Note: the chip doesn't have auto-pad! */
1713 if (likely(len < TX_BUF_SIZE)) {
1715 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1716 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1720 dev->stats.tx_dropped++;
1721 return NETDEV_TX_OK;
1724 spin_lock_irqsave(&tp->lock, flags);
1726 * Writing to TxStatus triggers a DMA transfer of the data
1727 * copied to tp->tx_buf[entry] above. Use a memory barrier
1728 * to make sure that the device sees the updated data.
1731 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1732 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1736 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1737 netif_stop_queue (dev);
1738 spin_unlock_irqrestore(&tp->lock, flags);
1740 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1743 return NETDEV_TX_OK;
1747 static void rtl8139_tx_interrupt (struct net_device *dev,
1748 struct rtl8139_private *tp,
1749 void __iomem *ioaddr)
1751 unsigned long dirty_tx, tx_left;
1753 assert (dev != NULL);
1754 assert (ioaddr != NULL);
1756 dirty_tx = tp->dirty_tx;
1757 tx_left = tp->cur_tx - dirty_tx;
1758 while (tx_left > 0) {
1759 int entry = dirty_tx % NUM_TX_DESC;
1762 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1764 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1765 break; /* It still hasn't been Txed */
1767 /* Note: TxCarrierLost is always asserted at 100mbps. */
1768 if (txstatus & (TxOutOfWindow | TxAborted)) {
1769 /* There was an major error, log it. */
1770 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1772 dev->stats.tx_errors++;
1773 if (txstatus & TxAborted) {
1774 dev->stats.tx_aborted_errors++;
1775 RTL_W32 (TxConfig, TxClearAbt);
1776 RTL_W16 (IntrStatus, TxErr);
1779 if (txstatus & TxCarrierLost)
1780 dev->stats.tx_carrier_errors++;
1781 if (txstatus & TxOutOfWindow)
1782 dev->stats.tx_window_errors++;
1784 if (txstatus & TxUnderrun) {
1785 /* Add 64 to the Tx FIFO threshold. */
1786 if (tp->tx_flag < 0x00300000)
1787 tp->tx_flag += 0x00020000;
1788 dev->stats.tx_fifo_errors++;
1790 dev->stats.collisions += (txstatus >> 24) & 15;
1791 u64_stats_update_begin(&tp->tx_stats.syncp);
1792 tp->tx_stats.packets++;
1793 tp->tx_stats.bytes += txstatus & 0x7ff;
1794 u64_stats_update_end(&tp->tx_stats.syncp);
1801 #ifndef RTL8139_NDEBUG
1802 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1803 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1804 dirty_tx, tp->cur_tx);
1805 dirty_tx += NUM_TX_DESC;
1807 #endif /* RTL8139_NDEBUG */
1809 /* only wake the queue if we did work, and the queue is stopped */
1810 if (tp->dirty_tx != dirty_tx) {
1811 tp->dirty_tx = dirty_tx;
1813 netif_wake_queue (dev);
1818 /* TODO: clean this up! Rx reset need not be this intensive */
1819 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1820 struct rtl8139_private *tp, void __iomem *ioaddr)
1823 #ifdef CONFIG_8139_OLD_RX_RESET
1827 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1829 dev->stats.rx_errors++;
1830 if (!(rx_status & RxStatusOK)) {
1831 if (rx_status & RxTooLong) {
1832 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1834 /* A.C.: The chip hangs here. */
1836 if (rx_status & (RxBadSymbol | RxBadAlign))
1837 dev->stats.rx_frame_errors++;
1838 if (rx_status & (RxRunt | RxTooLong))
1839 dev->stats.rx_length_errors++;
1840 if (rx_status & RxCRCErr)
1841 dev->stats.rx_crc_errors++;
1843 tp->xstats.rx_lost_in_ring++;
1846 #ifndef CONFIG_8139_OLD_RX_RESET
1847 tmp8 = RTL_R8 (ChipCmd);
1848 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1849 RTL_W8 (ChipCmd, tmp8);
1850 RTL_W32 (RxConfig, tp->rx_config);
1853 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1855 /* disable receive */
1856 RTL_W8_F (ChipCmd, CmdTxEnb);
1858 while (--tmp_work > 0) {
1860 tmp8 = RTL_R8 (ChipCmd);
1861 if (!(tmp8 & CmdRxEnb))
1865 netdev_warn(dev, "rx stop wait too long\n");
1866 /* restart receive */
1868 while (--tmp_work > 0) {
1869 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1871 tmp8 = RTL_R8 (ChipCmd);
1872 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1876 netdev_warn(dev, "tx/rx enable wait too long\n");
1878 /* and reinitialize all rx related registers */
1879 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1880 /* Must enable Tx/Rx before setting transfer thresholds! */
1881 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1883 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1884 RTL_W32 (RxConfig, tp->rx_config);
1887 netdev_dbg(dev, "init buffer addresses\n");
1889 /* Lock Config[01234] and BMCR register writes */
1890 RTL_W8 (Cfg9346, Cfg9346_Lock);
1892 /* init Rx ring buffer DMA address */
1893 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1895 /* A.C.: Reset the multicast list. */
1896 __set_rx_mode (dev);
1901 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1902 u32 offset, unsigned int size)
1904 u32 left = RX_BUF_LEN - offset;
1907 skb_copy_to_linear_data(skb, ring + offset, left);
1908 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1910 skb_copy_to_linear_data(skb, ring + offset, size);
1914 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1916 void __iomem *ioaddr = tp->mmio_addr;
1919 status = RTL_R16 (IntrStatus) & RxAckBits;
1921 /* Clear out errors and receive interrupts */
1922 if (likely(status != 0)) {
1923 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1924 tp->dev->stats.rx_errors++;
1925 if (status & RxFIFOOver)
1926 tp->dev->stats.rx_fifo_errors++;
1928 RTL_W16_F (IntrStatus, RxAckBits);
1932 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1935 void __iomem *ioaddr = tp->mmio_addr;
1937 unsigned char *rx_ring = tp->rx_ring;
1938 unsigned int cur_rx = tp->cur_rx;
1939 unsigned int rx_size = 0;
1941 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1942 __func__, (u16)cur_rx,
1943 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1945 while (netif_running(dev) && received < budget &&
1946 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1947 u32 ring_offset = cur_rx % RX_BUF_LEN;
1949 unsigned int pkt_size;
1950 struct sk_buff *skb;
1954 /* read size+status of next frame from DMA ring buffer */
1955 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1956 rx_size = rx_status >> 16;
1957 if (likely(!(dev->features & NETIF_F_RXFCS)))
1958 pkt_size = rx_size - 4;
1962 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1963 __func__, rx_status, rx_size, cur_rx);
1964 #if RTL8139_DEBUG > 2
1965 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1966 DUMP_PREFIX_OFFSET, 16, 1,
1967 &rx_ring[ring_offset], 70, true);
1970 /* Packet copy from FIFO still in progress.
1971 * Theoretically, this should never happen
1972 * since EarlyRx is disabled.
1974 if (unlikely(rx_size == 0xfff0)) {
1975 if (!tp->fifo_copy_timeout)
1976 tp->fifo_copy_timeout = jiffies + 2;
1977 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1978 netdev_dbg(dev, "hung FIFO. Reset\n");
1982 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1983 tp->xstats.early_rx++;
1988 tp->fifo_copy_timeout = 0;
1990 /* If Rx err or invalid rx_size/rx_status received
1991 * (which happens if we get lost in the ring),
1992 * Rx process gets reset, so we abort any further
1995 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1997 (!(rx_status & RxStatusOK)))) {
1998 if ((dev->features & NETIF_F_RXALL) &&
1999 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
2001 (!(rx_status & RxStatusOK))) {
2002 /* Length is at least mostly OK, but pkt has
2003 * error. I'm hoping we can handle some of these
2004 * errors without resetting the chip. --Ben
2006 dev->stats.rx_errors++;
2007 if (rx_status & RxCRCErr) {
2008 dev->stats.rx_crc_errors++;
2011 if (rx_status & RxRunt) {
2012 dev->stats.rx_length_errors++;
2016 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2022 /* Malloc up new buffer, compatible with net-2e. */
2023 /* Omit the four octet CRC from the length. */
2025 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
2028 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2030 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2032 skb_put (skb, pkt_size);
2034 skb->protocol = eth_type_trans (skb, dev);
2036 u64_stats_update_begin(&tp->rx_stats.syncp);
2037 tp->rx_stats.packets++;
2038 tp->rx_stats.bytes += pkt_size;
2039 u64_stats_update_end(&tp->rx_stats.syncp);
2041 netif_receive_skb (skb);
2043 dev->stats.rx_dropped++;
2047 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2048 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2050 rtl8139_isr_ack(tp);
2053 if (unlikely(!received || rx_size == 0xfff0))
2054 rtl8139_isr_ack(tp);
2056 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2058 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2060 tp->cur_rx = cur_rx;
2063 * The receive buffer should be mostly empty.
2064 * Tell NAPI to reenable the Rx irq.
2066 if (tp->fifo_copy_timeout)
2074 static void rtl8139_weird_interrupt (struct net_device *dev,
2075 struct rtl8139_private *tp,
2076 void __iomem *ioaddr,
2077 int status, int link_changed)
2079 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2081 assert (dev != NULL);
2082 assert (tp != NULL);
2083 assert (ioaddr != NULL);
2085 /* Update the error count. */
2086 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2087 RTL_W32 (RxMissed, 0);
2089 if ((status & RxUnderrun) && link_changed &&
2090 (tp->drv_flags & HAS_LNK_CHNG)) {
2091 rtl_check_media(dev, 0);
2092 status &= ~RxUnderrun;
2095 if (status & (RxUnderrun | RxErr))
2096 dev->stats.rx_errors++;
2098 if (status & PCSTimeout)
2099 dev->stats.rx_length_errors++;
2100 if (status & RxUnderrun)
2101 dev->stats.rx_fifo_errors++;
2102 if (status & PCIErr) {
2104 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2105 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2107 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2111 static int rtl8139_poll(struct napi_struct *napi, int budget)
2113 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2114 struct net_device *dev = tp->dev;
2115 void __iomem *ioaddr = tp->mmio_addr;
2118 spin_lock(&tp->rx_lock);
2120 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2121 work_done += rtl8139_rx(dev, tp, budget);
2123 if (work_done < budget) {
2124 unsigned long flags;
2126 * Order is important since data can get interrupted
2127 * again when we think we are done.
2129 spin_lock_irqsave(&tp->lock, flags);
2130 __napi_complete(napi);
2131 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2132 spin_unlock_irqrestore(&tp->lock, flags);
2134 spin_unlock(&tp->rx_lock);
2139 /* The interrupt handler does all of the Rx thread work and cleans up
2140 after the Tx thread. */
2141 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2143 struct net_device *dev = (struct net_device *) dev_instance;
2144 struct rtl8139_private *tp = netdev_priv(dev);
2145 void __iomem *ioaddr = tp->mmio_addr;
2146 u16 status, ackstat;
2147 int link_changed = 0; /* avoid bogus "uninit" warning */
2150 spin_lock (&tp->lock);
2151 status = RTL_R16 (IntrStatus);
2154 if (unlikely((status & rtl8139_intr_mask) == 0))
2159 /* h/w no longer present (hotplug?) or major error, bail */
2160 if (unlikely(status == 0xFFFF))
2163 /* close possible race's with dev_close */
2164 if (unlikely(!netif_running(dev))) {
2165 RTL_W16 (IntrMask, 0);
2169 /* Acknowledge all of the current interrupt sources ASAP, but
2170 an first get an additional status bit from CSCR. */
2171 if (unlikely(status & RxUnderrun))
2172 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2174 ackstat = status & ~(RxAckBits | TxErr);
2176 RTL_W16 (IntrStatus, ackstat);
2178 /* Receive packets are processed by poll routine.
2179 If not running start it now. */
2180 if (status & RxAckBits){
2181 if (napi_schedule_prep(&tp->napi)) {
2182 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2183 __napi_schedule(&tp->napi);
2187 /* Check uncommon events with one test. */
2188 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2189 rtl8139_weird_interrupt (dev, tp, ioaddr,
2190 status, link_changed);
2192 if (status & (TxOK | TxErr)) {
2193 rtl8139_tx_interrupt (dev, tp, ioaddr);
2195 RTL_W16 (IntrStatus, TxErr);
2198 spin_unlock (&tp->lock);
2200 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2201 RTL_R16(IntrStatus));
2202 return IRQ_RETVAL(handled);
2205 #ifdef CONFIG_NET_POLL_CONTROLLER
2207 * Polling receive - used by netconsole and other diagnostic tools
2208 * to allow network i/o with interrupts disabled.
2210 static void rtl8139_poll_controller(struct net_device *dev)
2212 struct rtl8139_private *tp = netdev_priv(dev);
2213 const int irq = tp->pci_dev->irq;
2216 rtl8139_interrupt(irq, dev);
2221 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2223 struct rtl8139_private *tp = netdev_priv(dev);
2224 void __iomem *ioaddr = tp->mmio_addr;
2225 struct sockaddr *addr = p;
2227 if (!is_valid_ether_addr(addr->sa_data))
2228 return -EADDRNOTAVAIL;
2230 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2232 spin_lock_irq(&tp->lock);
2234 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2235 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2236 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2237 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2239 spin_unlock_irq(&tp->lock);
2244 static int rtl8139_close (struct net_device *dev)
2246 struct rtl8139_private *tp = netdev_priv(dev);
2247 void __iomem *ioaddr = tp->mmio_addr;
2248 unsigned long flags;
2250 netif_stop_queue(dev);
2251 napi_disable(&tp->napi);
2253 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2254 RTL_R16(IntrStatus));
2256 spin_lock_irqsave (&tp->lock, flags);
2258 /* Stop the chip's Tx and Rx DMA processes. */
2259 RTL_W8 (ChipCmd, 0);
2261 /* Disable interrupts by clearing the interrupt mask. */
2262 RTL_W16 (IntrMask, 0);
2264 /* Update the error counts. */
2265 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2266 RTL_W32 (RxMissed, 0);
2268 spin_unlock_irqrestore (&tp->lock, flags);
2270 free_irq(tp->pci_dev->irq, dev);
2272 rtl8139_tx_clear (tp);
2274 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2275 tp->rx_ring, tp->rx_ring_dma);
2276 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2277 tp->tx_bufs, tp->tx_bufs_dma);
2281 /* Green! Put the chip in low-power mode. */
2282 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2284 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2285 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2291 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2292 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2293 other threads or interrupts aren't messing with the 8139. */
2294 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2296 struct rtl8139_private *tp = netdev_priv(dev);
2297 void __iomem *ioaddr = tp->mmio_addr;
2299 spin_lock_irq(&tp->lock);
2300 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2301 u8 cfg3 = RTL_R8 (Config3);
2302 u8 cfg5 = RTL_R8 (Config5);
2304 wol->supported = WAKE_PHY | WAKE_MAGIC
2305 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2308 if (cfg3 & Cfg3_LinkUp)
2309 wol->wolopts |= WAKE_PHY;
2310 if (cfg3 & Cfg3_Magic)
2311 wol->wolopts |= WAKE_MAGIC;
2312 /* (KON)FIXME: See how netdev_set_wol() handles the
2313 following constants. */
2314 if (cfg5 & Cfg5_UWF)
2315 wol->wolopts |= WAKE_UCAST;
2316 if (cfg5 & Cfg5_MWF)
2317 wol->wolopts |= WAKE_MCAST;
2318 if (cfg5 & Cfg5_BWF)
2319 wol->wolopts |= WAKE_BCAST;
2321 spin_unlock_irq(&tp->lock);
2325 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2326 that wol points to kernel memory and other threads or interrupts
2327 aren't messing with the 8139. */
2328 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2330 struct rtl8139_private *tp = netdev_priv(dev);
2331 void __iomem *ioaddr = tp->mmio_addr;
2335 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2336 ? (WAKE_PHY | WAKE_MAGIC
2337 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2339 if (wol->wolopts & ~support)
2342 spin_lock_irq(&tp->lock);
2343 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2344 if (wol->wolopts & WAKE_PHY)
2345 cfg3 |= Cfg3_LinkUp;
2346 if (wol->wolopts & WAKE_MAGIC)
2348 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2349 RTL_W8 (Config3, cfg3);
2350 RTL_W8 (Cfg9346, Cfg9346_Lock);
2352 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2353 /* (KON)FIXME: These are untested. We may have to set the
2354 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2356 if (wol->wolopts & WAKE_UCAST)
2358 if (wol->wolopts & WAKE_MCAST)
2360 if (wol->wolopts & WAKE_BCAST)
2362 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2363 spin_unlock_irq(&tp->lock);
2368 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2370 struct rtl8139_private *tp = netdev_priv(dev);
2371 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2372 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2373 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
2374 info->regdump_len = tp->regs_len;
2377 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2379 struct rtl8139_private *tp = netdev_priv(dev);
2380 spin_lock_irq(&tp->lock);
2381 mii_ethtool_gset(&tp->mii, cmd);
2382 spin_unlock_irq(&tp->lock);
2386 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2388 struct rtl8139_private *tp = netdev_priv(dev);
2390 spin_lock_irq(&tp->lock);
2391 rc = mii_ethtool_sset(&tp->mii, cmd);
2392 spin_unlock_irq(&tp->lock);
2396 static int rtl8139_nway_reset(struct net_device *dev)
2398 struct rtl8139_private *tp = netdev_priv(dev);
2399 return mii_nway_restart(&tp->mii);
2402 static u32 rtl8139_get_link(struct net_device *dev)
2404 struct rtl8139_private *tp = netdev_priv(dev);
2405 return mii_link_ok(&tp->mii);
2408 static u32 rtl8139_get_msglevel(struct net_device *dev)
2410 struct rtl8139_private *tp = netdev_priv(dev);
2411 return tp->msg_enable;
2414 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2416 struct rtl8139_private *tp = netdev_priv(dev);
2417 tp->msg_enable = datum;
2420 static int rtl8139_get_regs_len(struct net_device *dev)
2422 struct rtl8139_private *tp;
2423 /* TODO: we are too slack to do reg dumping for pio, for now */
2426 tp = netdev_priv(dev);
2427 return tp->regs_len;
2430 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2432 struct rtl8139_private *tp;
2434 /* TODO: we are too slack to do reg dumping for pio, for now */
2437 tp = netdev_priv(dev);
2439 regs->version = RTL_REGS_VER;
2441 spin_lock_irq(&tp->lock);
2442 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2443 spin_unlock_irq(&tp->lock);
2446 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2450 return RTL_NUM_STATS;
2456 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2458 struct rtl8139_private *tp = netdev_priv(dev);
2460 data[0] = tp->xstats.early_rx;
2461 data[1] = tp->xstats.tx_buf_mapped;
2462 data[2] = tp->xstats.tx_timeouts;
2463 data[3] = tp->xstats.rx_lost_in_ring;
2466 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2468 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2471 static const struct ethtool_ops rtl8139_ethtool_ops = {
2472 .get_drvinfo = rtl8139_get_drvinfo,
2473 .get_settings = rtl8139_get_settings,
2474 .set_settings = rtl8139_set_settings,
2475 .get_regs_len = rtl8139_get_regs_len,
2476 .get_regs = rtl8139_get_regs,
2477 .nway_reset = rtl8139_nway_reset,
2478 .get_link = rtl8139_get_link,
2479 .get_msglevel = rtl8139_get_msglevel,
2480 .set_msglevel = rtl8139_set_msglevel,
2481 .get_wol = rtl8139_get_wol,
2482 .set_wol = rtl8139_set_wol,
2483 .get_strings = rtl8139_get_strings,
2484 .get_sset_count = rtl8139_get_sset_count,
2485 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2488 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2490 struct rtl8139_private *tp = netdev_priv(dev);
2493 if (!netif_running(dev))
2496 spin_lock_irq(&tp->lock);
2497 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2498 spin_unlock_irq(&tp->lock);
2504 static struct rtnl_link_stats64 *
2505 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2507 struct rtl8139_private *tp = netdev_priv(dev);
2508 void __iomem *ioaddr = tp->mmio_addr;
2509 unsigned long flags;
2512 if (netif_running(dev)) {
2513 spin_lock_irqsave (&tp->lock, flags);
2514 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2515 RTL_W32 (RxMissed, 0);
2516 spin_unlock_irqrestore (&tp->lock, flags);
2519 netdev_stats_to_stats64(stats, &dev->stats);
2522 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
2523 stats->rx_packets = tp->rx_stats.packets;
2524 stats->rx_bytes = tp->rx_stats.bytes;
2525 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
2528 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
2529 stats->tx_packets = tp->tx_stats.packets;
2530 stats->tx_bytes = tp->tx_stats.bytes;
2531 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
2536 /* Set or clear the multicast filter for this adaptor.
2537 This routine is not state sensitive and need not be SMP locked. */
2539 static void __set_rx_mode (struct net_device *dev)
2541 struct rtl8139_private *tp = netdev_priv(dev);
2542 void __iomem *ioaddr = tp->mmio_addr;
2543 u32 mc_filter[2]; /* Multicast hash filter */
2547 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2548 dev->flags, RTL_R32(RxConfig));
2550 /* Note: do not reorder, GCC is clever about common statements. */
2551 if (dev->flags & IFF_PROMISC) {
2553 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2555 mc_filter[1] = mc_filter[0] = 0xffffffff;
2556 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2557 (dev->flags & IFF_ALLMULTI)) {
2558 /* Too many to filter perfectly -- accept all multicasts. */
2559 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2560 mc_filter[1] = mc_filter[0] = 0xffffffff;
2562 struct netdev_hw_addr *ha;
2563 rx_mode = AcceptBroadcast | AcceptMyPhys;
2564 mc_filter[1] = mc_filter[0] = 0;
2565 netdev_for_each_mc_addr(ha, dev) {
2566 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2568 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2569 rx_mode |= AcceptMulticast;
2573 if (dev->features & NETIF_F_RXALL)
2574 rx_mode |= (AcceptErr | AcceptRunt);
2576 /* We can safely update without stopping the chip. */
2577 tmp = rtl8139_rx_config | rx_mode;
2578 if (tp->rx_config != tmp) {
2579 RTL_W32_F (RxConfig, tmp);
2580 tp->rx_config = tmp;
2582 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2583 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2586 static void rtl8139_set_rx_mode (struct net_device *dev)
2588 unsigned long flags;
2589 struct rtl8139_private *tp = netdev_priv(dev);
2591 spin_lock_irqsave (&tp->lock, flags);
2593 spin_unlock_irqrestore (&tp->lock, flags);
2598 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2600 struct net_device *dev = pci_get_drvdata (pdev);
2601 struct rtl8139_private *tp = netdev_priv(dev);
2602 void __iomem *ioaddr = tp->mmio_addr;
2603 unsigned long flags;
2605 pci_save_state (pdev);
2607 if (!netif_running (dev))
2610 netif_device_detach (dev);
2612 spin_lock_irqsave (&tp->lock, flags);
2614 /* Disable interrupts, stop Tx and Rx. */
2615 RTL_W16 (IntrMask, 0);
2616 RTL_W8 (ChipCmd, 0);
2618 /* Update the error counts. */
2619 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2620 RTL_W32 (RxMissed, 0);
2622 spin_unlock_irqrestore (&tp->lock, flags);
2624 pci_set_power_state (pdev, PCI_D3hot);
2630 static int rtl8139_resume (struct pci_dev *pdev)
2632 struct net_device *dev = pci_get_drvdata (pdev);
2634 pci_restore_state (pdev);
2635 if (!netif_running (dev))
2637 pci_set_power_state (pdev, PCI_D0);
2638 rtl8139_init_ring (dev);
2639 rtl8139_hw_start (dev);
2640 netif_device_attach (dev);
2644 #endif /* CONFIG_PM */
2647 static struct pci_driver rtl8139_pci_driver = {
2649 .id_table = rtl8139_pci_tbl,
2650 .probe = rtl8139_init_one,
2651 .remove = rtl8139_remove_one,
2653 .suspend = rtl8139_suspend,
2654 .resume = rtl8139_resume,
2655 #endif /* CONFIG_PM */
2659 static int __init rtl8139_init_module (void)
2661 /* when we're a module, we always print a version message,
2662 * even if no 8139 board is found.
2665 pr_info(RTL8139_DRIVER_NAME "\n");
2668 return pci_register_driver(&rtl8139_pci_driver);
2672 static void __exit rtl8139_cleanup_module (void)
2674 pci_unregister_driver (&rtl8139_pci_driver);
2678 module_init(rtl8139_init_module);
2679 module_exit(rtl8139_cleanup_module);