2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
56 #define assert(expr) \
58 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
59 #expr,__FILE__,__func__,__LINE__); \
61 #define dprintk(fmt, args...) \
62 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
64 #define assert(expr) do {} while (0)
65 #define dprintk(fmt, args...) do {} while (0)
66 #endif /* RTL8169_DEBUG */
68 #define R8169_MSG_DEFAULT \
69 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
71 #define TX_SLOTS_AVAIL(tp) \
72 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
74 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
75 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
76 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
78 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
79 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
80 static const int multicast_filter_limit = 32;
82 #define MAX_READ_REQUEST_SHIFT 12
83 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86 #define R8169_REGS_SIZE 256
87 #define R8169_NAPI_WEIGHT 64
88 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
89 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
90 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
91 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
93 #define RTL8169_TX_TIMEOUT (6*HZ)
94 #define RTL8169_PHY_TIMEOUT (10*HZ)
96 /* write/read MMIO register */
97 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
98 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
99 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
100 #define RTL_R8(reg) readb (ioaddr + (reg))
101 #define RTL_R16(reg) readw (ioaddr + (reg))
102 #define RTL_R32(reg) readl (ioaddr + (reg))
105 RTL_GIGA_MAC_VER_01 = 0,
149 RTL_GIGA_MAC_NONE = 0xff,
152 enum rtl_tx_desc_version {
157 #define JUMBO_1K ETH_DATA_LEN
158 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
159 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
160 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
161 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
163 #define _R(NAME,TD,FW,SZ,B) { \
171 static const struct {
173 enum rtl_tx_desc_version txd_version;
177 } rtl_chip_infos[] = {
179 [RTL_GIGA_MAC_VER_01] =
180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
181 [RTL_GIGA_MAC_VER_02] =
182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_03] =
184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
185 [RTL_GIGA_MAC_VER_04] =
186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
187 [RTL_GIGA_MAC_VER_05] =
188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
189 [RTL_GIGA_MAC_VER_06] =
190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
192 [RTL_GIGA_MAC_VER_07] =
193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_08] =
195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_09] =
197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_10] =
199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
200 [RTL_GIGA_MAC_VER_11] =
201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
202 [RTL_GIGA_MAC_VER_12] =
203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
204 [RTL_GIGA_MAC_VER_13] =
205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_14] =
207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_15] =
209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_16] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_17] =
213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_18] =
215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_19] =
217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
218 [RTL_GIGA_MAC_VER_20] =
219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
220 [RTL_GIGA_MAC_VER_21] =
221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
222 [RTL_GIGA_MAC_VER_22] =
223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
224 [RTL_GIGA_MAC_VER_23] =
225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
226 [RTL_GIGA_MAC_VER_24] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_25] =
229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
231 [RTL_GIGA_MAC_VER_26] =
232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
234 [RTL_GIGA_MAC_VER_27] =
235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
236 [RTL_GIGA_MAC_VER_28] =
237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
238 [RTL_GIGA_MAC_VER_29] =
239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
241 [RTL_GIGA_MAC_VER_30] =
242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
244 [RTL_GIGA_MAC_VER_31] =
245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_32] =
247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
249 [RTL_GIGA_MAC_VER_33] =
250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
252 [RTL_GIGA_MAC_VER_34] =
253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
255 [RTL_GIGA_MAC_VER_35] =
256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
258 [RTL_GIGA_MAC_VER_36] =
259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
264 [RTL_GIGA_MAC_VER_38] =
265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
267 [RTL_GIGA_MAC_VER_39] =
268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
270 [RTL_GIGA_MAC_VER_40] =
271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
273 [RTL_GIGA_MAC_VER_41] =
274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
275 [RTL_GIGA_MAC_VER_42] =
276 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
278 [RTL_GIGA_MAC_VER_43] =
279 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
281 [RTL_GIGA_MAC_VER_44] =
282 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
293 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
294 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
298 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
299 { PCI_VENDOR_ID_DLINK, 0x4300,
300 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
301 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
302 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
303 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
304 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
305 { PCI_VENDOR_ID_LINKSYS, 0x1032,
306 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
308 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
312 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
314 static int rx_buf_sz = 16383;
321 MAC0 = 0, /* Ethernet hardware address. */
323 MAR0 = 8, /* Multicast filter. */
324 CounterAddrLow = 0x10,
325 CounterAddrHigh = 0x14,
326 TxDescStartAddrLow = 0x20,
327 TxDescStartAddrHigh = 0x24,
328 TxHDescStartAddrLow = 0x28,
329 TxHDescStartAddrHigh = 0x2c,
338 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
339 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
342 #define RX128_INT_EN (1 << 15) /* 8111c and later */
343 #define RX_MULTI_EN (1 << 14) /* 8111c only */
344 #define RXCFG_FIFO_SHIFT 13
345 /* No threshold before first PCI xfer */
346 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
347 #define RX_EARLY_OFF (1 << 11)
348 #define RXCFG_DMA_SHIFT 8
349 /* Unlimited maximum PCI burst. */
350 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
357 #define PME_SIGNAL (1 << 5) /* 8168c and later */
368 RxDescAddrLow = 0xe4,
369 RxDescAddrHigh = 0xe8,
370 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
372 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
374 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
376 #define TxPacketMax (8064 >> 7)
377 #define EarlySize 0x27
380 FuncEventMask = 0xf4,
381 FuncPresetState = 0xf8,
382 FuncForceEvent = 0xfc,
385 enum rtl8110_registers {
391 enum rtl8168_8101_registers {
394 #define CSIAR_FLAG 0x80000000
395 #define CSIAR_WRITE_CMD 0x80000000
396 #define CSIAR_BYTE_ENABLE 0x0f
397 #define CSIAR_BYTE_ENABLE_SHIFT 12
398 #define CSIAR_ADDR_MASK 0x0fff
399 #define CSIAR_FUNC_CARD 0x00000000
400 #define CSIAR_FUNC_SDIO 0x00010000
401 #define CSIAR_FUNC_NIC 0x00020000
402 #define CSIAR_FUNC_NIC2 0x00010000
405 #define EPHYAR_FLAG 0x80000000
406 #define EPHYAR_WRITE_CMD 0x80000000
407 #define EPHYAR_REG_MASK 0x1f
408 #define EPHYAR_REG_SHIFT 16
409 #define EPHYAR_DATA_MASK 0xffff
411 #define PFM_EN (1 << 6)
413 #define FIX_NAK_1 (1 << 4)
414 #define FIX_NAK_2 (1 << 3)
417 #define NOW_IS_OOB (1 << 7)
418 #define TX_EMPTY (1 << 5)
419 #define RX_EMPTY (1 << 4)
420 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
421 #define EN_NDP (1 << 3)
422 #define EN_OOB_RESET (1 << 2)
423 #define LINK_LIST_RDY (1 << 1)
425 #define EFUSEAR_FLAG 0x80000000
426 #define EFUSEAR_WRITE_CMD 0x80000000
427 #define EFUSEAR_READ_CMD 0x00000000
428 #define EFUSEAR_REG_MASK 0x03ff
429 #define EFUSEAR_REG_SHIFT 8
430 #define EFUSEAR_DATA_MASK 0xff
433 enum rtl8168_registers {
438 #define ERIAR_FLAG 0x80000000
439 #define ERIAR_WRITE_CMD 0x80000000
440 #define ERIAR_READ_CMD 0x00000000
441 #define ERIAR_ADDR_BYTE_ALIGN 4
442 #define ERIAR_TYPE_SHIFT 16
443 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
444 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
445 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
446 #define ERIAR_MASK_SHIFT 12
447 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
448 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
449 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
450 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
451 EPHY_RXER_NUM = 0x7c,
452 OCPDR = 0xb0, /* OCP GPHY access */
453 #define OCPDR_WRITE_CMD 0x80000000
454 #define OCPDR_READ_CMD 0x00000000
455 #define OCPDR_REG_MASK 0x7f
456 #define OCPDR_GPHY_REG_SHIFT 16
457 #define OCPDR_DATA_MASK 0xffff
459 #define OCPAR_FLAG 0x80000000
460 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
461 #define OCPAR_GPHY_READ_CMD 0x0000f060
463 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
464 MISC = 0xf0, /* 8168e only. */
465 #define TXPLA_RST (1 << 29)
466 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
467 #define PWM_EN (1 << 22)
468 #define RXDV_GATED_EN (1 << 19)
469 #define EARLY_TALLY_EN (1 << 16)
472 enum rtl_register_content {
473 /* InterruptStatusBits */
477 TxDescUnavail = 0x0080,
501 /* TXPoll register p.5 */
502 HPQ = 0x80, /* Poll cmd on the high prio queue */
503 NPQ = 0x40, /* Poll cmd on the low prio queue */
504 FSWInt = 0x01, /* Forced software interrupt */
508 Cfg9346_Unlock = 0xc0,
513 AcceptBroadcast = 0x08,
514 AcceptMulticast = 0x04,
516 AcceptAllPhys = 0x01,
517 #define RX_CONFIG_ACCEPT_MASK 0x3f
520 TxInterFrameGapShift = 24,
521 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
523 /* Config1 register p.24 */
526 Speed_down = (1 << 4),
530 PMEnable = (1 << 0), /* Power Management Enable */
532 /* Config2 register p. 25 */
533 ClkReqEn = (1 << 7), /* Clock Request Enable */
534 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
535 PCI_Clock_66MHz = 0x01,
536 PCI_Clock_33MHz = 0x00,
538 /* Config3 register p.25 */
539 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
540 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
541 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
542 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
544 /* Config4 register */
545 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
547 /* Config5 register p.27 */
548 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
549 MWF = (1 << 5), /* Accept Multicast wakeup frame */
550 UWF = (1 << 4), /* Accept Unicast wakeup frame */
552 LanWake = (1 << 1), /* LanWake enable/disable */
553 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
554 ASPM_en = (1 << 0), /* ASPM enable */
557 TBIReset = 0x80000000,
558 TBILoopback = 0x40000000,
559 TBINwEnable = 0x20000000,
560 TBINwRestart = 0x10000000,
561 TBILinkOk = 0x02000000,
562 TBINwComplete = 0x01000000,
565 EnableBist = (1 << 15), // 8168 8101
566 Mac_dbgo_oe = (1 << 14), // 8168 8101
567 Normal_mode = (1 << 13), // unused
568 Force_half_dup = (1 << 12), // 8168 8101
569 Force_rxflow_en = (1 << 11), // 8168 8101
570 Force_txflow_en = (1 << 10), // 8168 8101
571 Cxpl_dbg_sel = (1 << 9), // 8168 8101
572 ASF = (1 << 8), // 8168 8101
573 PktCntrDisable = (1 << 7), // 8168 8101
574 Mac_dbgo_sel = 0x001c, // 8168
579 INTT_0 = 0x0000, // 8168
580 INTT_1 = 0x0001, // 8168
581 INTT_2 = 0x0002, // 8168
582 INTT_3 = 0x0003, // 8168
584 /* rtl8169_PHYstatus */
595 TBILinkOK = 0x02000000,
597 /* DumpCounterCommand */
602 /* First doubleword. */
603 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
604 RingEnd = (1 << 30), /* End of descriptor ring */
605 FirstFrag = (1 << 29), /* First segment of a packet */
606 LastFrag = (1 << 28), /* Final segment of a packet */
610 enum rtl_tx_desc_bit {
611 /* First doubleword. */
612 TD_LSO = (1 << 27), /* Large Send Offload */
613 #define TD_MSS_MAX 0x07ffu /* MSS value */
615 /* Second doubleword. */
616 TxVlanTag = (1 << 17), /* Add VLAN tag */
619 /* 8169, 8168b and 810x except 8102e. */
620 enum rtl_tx_desc_bit_0 {
621 /* First doubleword. */
622 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
623 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
624 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
625 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
628 /* 8102e, 8168c and beyond. */
629 enum rtl_tx_desc_bit_1 {
630 /* Second doubleword. */
631 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
632 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
633 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
634 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
637 static const struct rtl_tx_desc_info {
644 } tx_desc_info [] = {
647 .udp = TD0_IP_CS | TD0_UDP_CS,
648 .tcp = TD0_IP_CS | TD0_TCP_CS
650 .mss_shift = TD0_MSS_SHIFT,
655 .udp = TD1_IP_CS | TD1_UDP_CS,
656 .tcp = TD1_IP_CS | TD1_TCP_CS
658 .mss_shift = TD1_MSS_SHIFT,
663 enum rtl_rx_desc_bit {
665 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
666 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
668 #define RxProtoUDP (PID1)
669 #define RxProtoTCP (PID0)
670 #define RxProtoIP (PID1 | PID0)
671 #define RxProtoMask RxProtoIP
673 IPFail = (1 << 16), /* IP checksum failed */
674 UDPFail = (1 << 15), /* UDP/IP checksum failed */
675 TCPFail = (1 << 14), /* TCP/IP checksum failed */
676 RxVlanTag = (1 << 16), /* VLAN tag available */
679 #define RsvdMask 0x3fffc000
696 u8 __pad[sizeof(void *) - sizeof(u32)];
700 RTL_FEATURE_WOL = (1 << 0),
701 RTL_FEATURE_MSI = (1 << 1),
702 RTL_FEATURE_GMII = (1 << 2),
705 struct rtl8169_counters {
712 __le32 tx_one_collision;
713 __le32 tx_multi_collision;
722 RTL_FLAG_TASK_ENABLED,
723 RTL_FLAG_TASK_SLOW_PENDING,
724 RTL_FLAG_TASK_RESET_PENDING,
725 RTL_FLAG_TASK_PHY_PENDING,
729 struct rtl8169_stats {
732 struct u64_stats_sync syncp;
735 struct rtl8169_private {
736 void __iomem *mmio_addr; /* memory map physical address */
737 struct pci_dev *pci_dev;
738 struct net_device *dev;
739 struct napi_struct napi;
743 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
744 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
746 struct rtl8169_stats rx_stats;
747 struct rtl8169_stats tx_stats;
748 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
749 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
750 dma_addr_t TxPhyAddr;
751 dma_addr_t RxPhyAddr;
752 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
753 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
754 struct timer_list timer;
760 void (*write)(struct rtl8169_private *, int, int);
761 int (*read)(struct rtl8169_private *, int);
764 struct pll_power_ops {
765 void (*down)(struct rtl8169_private *);
766 void (*up)(struct rtl8169_private *);
770 void (*enable)(struct rtl8169_private *);
771 void (*disable)(struct rtl8169_private *);
775 void (*write)(struct rtl8169_private *, int, int);
776 u32 (*read)(struct rtl8169_private *, int);
779 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
780 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
781 void (*phy_reset_enable)(struct rtl8169_private *tp);
782 void (*hw_start)(struct net_device *);
783 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
784 unsigned int (*link_ok)(void __iomem *);
785 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
788 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
790 struct work_struct work;
795 struct mii_if_info mii;
796 struct rtl8169_counters counters;
801 const struct firmware *fw;
803 #define RTL_VER_SIZE 32
805 char version[RTL_VER_SIZE];
807 struct rtl_fw_phy_action {
812 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
817 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
818 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
819 module_param(use_dac, int, 0);
820 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
821 module_param_named(debug, debug.msg_enable, int, 0);
822 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
823 MODULE_LICENSE("GPL");
824 MODULE_VERSION(RTL8169_VERSION);
825 MODULE_FIRMWARE(FIRMWARE_8168D_1);
826 MODULE_FIRMWARE(FIRMWARE_8168D_2);
827 MODULE_FIRMWARE(FIRMWARE_8168E_1);
828 MODULE_FIRMWARE(FIRMWARE_8168E_2);
829 MODULE_FIRMWARE(FIRMWARE_8168E_3);
830 MODULE_FIRMWARE(FIRMWARE_8105E_1);
831 MODULE_FIRMWARE(FIRMWARE_8168F_1);
832 MODULE_FIRMWARE(FIRMWARE_8168F_2);
833 MODULE_FIRMWARE(FIRMWARE_8402_1);
834 MODULE_FIRMWARE(FIRMWARE_8411_1);
835 MODULE_FIRMWARE(FIRMWARE_8411_2);
836 MODULE_FIRMWARE(FIRMWARE_8106E_1);
837 MODULE_FIRMWARE(FIRMWARE_8106E_2);
838 MODULE_FIRMWARE(FIRMWARE_8168G_2);
839 MODULE_FIRMWARE(FIRMWARE_8168G_3);
841 static void rtl_lock_work(struct rtl8169_private *tp)
843 mutex_lock(&tp->wk.mutex);
846 static void rtl_unlock_work(struct rtl8169_private *tp)
848 mutex_unlock(&tp->wk.mutex);
851 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
853 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
854 PCI_EXP_DEVCTL_READRQ, force);
858 bool (*check)(struct rtl8169_private *);
862 static void rtl_udelay(unsigned int d)
867 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
868 void (*delay)(unsigned int), unsigned int d, int n,
873 for (i = 0; i < n; i++) {
875 if (c->check(tp) == high)
878 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
879 c->msg, !high, n, d);
883 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
887 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
890 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
894 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
897 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
898 const struct rtl_cond *c,
899 unsigned int d, int n)
901 return rtl_loop_wait(tp, c, msleep, d, n, true);
904 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
905 const struct rtl_cond *c,
906 unsigned int d, int n)
908 return rtl_loop_wait(tp, c, msleep, d, n, false);
911 #define DECLARE_RTL_COND(name) \
912 static bool name ## _check(struct rtl8169_private *); \
914 static const struct rtl_cond name = { \
915 .check = name ## _check, \
919 static bool name ## _check(struct rtl8169_private *tp)
921 DECLARE_RTL_COND(rtl_ocpar_cond)
923 void __iomem *ioaddr = tp->mmio_addr;
925 return RTL_R32(OCPAR) & OCPAR_FLAG;
928 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
930 void __iomem *ioaddr = tp->mmio_addr;
932 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
934 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
938 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
940 void __iomem *ioaddr = tp->mmio_addr;
942 RTL_W32(OCPDR, data);
943 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
945 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
948 DECLARE_RTL_COND(rtl_eriar_cond)
950 void __iomem *ioaddr = tp->mmio_addr;
952 return RTL_R32(ERIAR) & ERIAR_FLAG;
955 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
957 void __iomem *ioaddr = tp->mmio_addr;
960 RTL_W32(ERIAR, 0x800010e8);
963 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
966 ocp_write(tp, 0x1, 0x30, 0x00000001);
969 #define OOB_CMD_RESET 0x00
970 #define OOB_CMD_DRIVER_START 0x05
971 #define OOB_CMD_DRIVER_STOP 0x06
973 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
975 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
978 DECLARE_RTL_COND(rtl_ocp_read_cond)
982 reg = rtl8168_get_ocp_reg(tp);
984 return ocp_read(tp, 0x0f, reg) & 0x00000800;
987 static void rtl8168_driver_start(struct rtl8169_private *tp)
989 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
991 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
994 static void rtl8168_driver_stop(struct rtl8169_private *tp)
996 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
998 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1001 static int r8168dp_check_dash(struct rtl8169_private *tp)
1003 u16 reg = rtl8168_get_ocp_reg(tp);
1005 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1008 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1010 if (reg & 0xffff0001) {
1011 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1017 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1019 void __iomem *ioaddr = tp->mmio_addr;
1021 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1024 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1026 void __iomem *ioaddr = tp->mmio_addr;
1028 if (rtl_ocp_reg_failure(tp, reg))
1031 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1033 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1036 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1038 void __iomem *ioaddr = tp->mmio_addr;
1040 if (rtl_ocp_reg_failure(tp, reg))
1043 RTL_W32(GPHY_OCP, reg << 15);
1045 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1046 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1049 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1051 void __iomem *ioaddr = tp->mmio_addr;
1053 if (rtl_ocp_reg_failure(tp, reg))
1056 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1059 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1061 void __iomem *ioaddr = tp->mmio_addr;
1063 if (rtl_ocp_reg_failure(tp, reg))
1066 RTL_W32(OCPDR, reg << 15);
1068 return RTL_R32(OCPDR);
1071 #define OCP_STD_PHY_BASE 0xa400
1073 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1076 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1080 if (tp->ocp_base != OCP_STD_PHY_BASE)
1083 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1086 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1088 if (tp->ocp_base != OCP_STD_PHY_BASE)
1091 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1094 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1097 tp->ocp_base = value << 4;
1101 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1104 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1106 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1109 DECLARE_RTL_COND(rtl_phyar_cond)
1111 void __iomem *ioaddr = tp->mmio_addr;
1113 return RTL_R32(PHYAR) & 0x80000000;
1116 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1118 void __iomem *ioaddr = tp->mmio_addr;
1120 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1122 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1124 * According to hardware specs a 20us delay is required after write
1125 * complete indication, but before sending next command.
1130 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1132 void __iomem *ioaddr = tp->mmio_addr;
1135 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1137 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1138 RTL_R32(PHYAR) & 0xffff : ~0;
1141 * According to hardware specs a 20us delay is required after read
1142 * complete indication, but before sending next command.
1149 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1151 void __iomem *ioaddr = tp->mmio_addr;
1153 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1154 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1155 RTL_W32(EPHY_RXER_NUM, 0);
1157 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1160 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1162 r8168dp_1_mdio_access(tp, reg,
1163 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1166 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1168 void __iomem *ioaddr = tp->mmio_addr;
1170 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1173 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1174 RTL_W32(EPHY_RXER_NUM, 0);
1176 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1177 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1180 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1182 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1184 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1187 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1189 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1192 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1194 void __iomem *ioaddr = tp->mmio_addr;
1196 r8168dp_2_mdio_start(ioaddr);
1198 r8169_mdio_write(tp, reg, value);
1200 r8168dp_2_mdio_stop(ioaddr);
1203 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1205 void __iomem *ioaddr = tp->mmio_addr;
1208 r8168dp_2_mdio_start(ioaddr);
1210 value = r8169_mdio_read(tp, reg);
1212 r8168dp_2_mdio_stop(ioaddr);
1217 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1219 tp->mdio_ops.write(tp, location, val);
1222 static int rtl_readphy(struct rtl8169_private *tp, int location)
1224 return tp->mdio_ops.read(tp, location);
1227 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1229 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1232 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1236 val = rtl_readphy(tp, reg_addr);
1237 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1240 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1243 struct rtl8169_private *tp = netdev_priv(dev);
1245 rtl_writephy(tp, location, val);
1248 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1250 struct rtl8169_private *tp = netdev_priv(dev);
1252 return rtl_readphy(tp, location);
1255 DECLARE_RTL_COND(rtl_ephyar_cond)
1257 void __iomem *ioaddr = tp->mmio_addr;
1259 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1262 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1264 void __iomem *ioaddr = tp->mmio_addr;
1266 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1267 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1269 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1276 void __iomem *ioaddr = tp->mmio_addr;
1278 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1280 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1281 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1284 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1287 void __iomem *ioaddr = tp->mmio_addr;
1289 BUG_ON((addr & 3) || (mask == 0));
1290 RTL_W32(ERIDR, val);
1291 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1293 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1296 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1298 void __iomem *ioaddr = tp->mmio_addr;
1300 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1302 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1303 RTL_R32(ERIDR) : ~0;
1306 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1311 val = rtl_eri_read(tp, addr, type);
1312 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1321 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1322 const struct exgmac_reg *r, int len)
1325 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1330 DECLARE_RTL_COND(rtl_efusear_cond)
1332 void __iomem *ioaddr = tp->mmio_addr;
1334 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1337 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1339 void __iomem *ioaddr = tp->mmio_addr;
1341 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1343 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1344 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1347 static u16 rtl_get_events(struct rtl8169_private *tp)
1349 void __iomem *ioaddr = tp->mmio_addr;
1351 return RTL_R16(IntrStatus);
1354 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1356 void __iomem *ioaddr = tp->mmio_addr;
1358 RTL_W16(IntrStatus, bits);
1362 static void rtl_irq_disable(struct rtl8169_private *tp)
1364 void __iomem *ioaddr = tp->mmio_addr;
1366 RTL_W16(IntrMask, 0);
1370 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1372 void __iomem *ioaddr = tp->mmio_addr;
1374 RTL_W16(IntrMask, bits);
1377 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1378 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1379 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1381 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1383 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1386 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1388 void __iomem *ioaddr = tp->mmio_addr;
1390 rtl_irq_disable(tp);
1391 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1395 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1397 void __iomem *ioaddr = tp->mmio_addr;
1399 return RTL_R32(TBICSR) & TBIReset;
1402 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1404 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1407 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1409 return RTL_R32(TBICSR) & TBILinkOk;
1412 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1414 return RTL_R8(PHYstatus) & LinkStatus;
1417 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1419 void __iomem *ioaddr = tp->mmio_addr;
1421 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1424 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1428 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1429 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1432 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1434 void __iomem *ioaddr = tp->mmio_addr;
1435 struct net_device *dev = tp->dev;
1437 if (!netif_running(dev))
1440 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1441 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1442 if (RTL_R8(PHYstatus) & _1000bpsF) {
1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1445 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1447 } else if (RTL_R8(PHYstatus) & _100bps) {
1448 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1450 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1458 /* Reset packet filter */
1459 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1461 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1463 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1464 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1465 if (RTL_R8(PHYstatus) & _1000bpsF) {
1466 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1468 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1471 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1473 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1476 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1477 if (RTL_R8(PHYstatus) & _10bps) {
1478 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1480 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1483 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1489 static void __rtl8169_check_link_status(struct net_device *dev,
1490 struct rtl8169_private *tp,
1491 void __iomem *ioaddr, bool pm)
1493 if (tp->link_ok(ioaddr)) {
1494 rtl_link_chg_patch(tp);
1495 /* This is to cancel a scheduled suspend if there's one. */
1497 pm_request_resume(&tp->pci_dev->dev);
1498 netif_carrier_on(dev);
1499 if (net_ratelimit())
1500 netif_info(tp, ifup, dev, "link up\n");
1502 netif_carrier_off(dev);
1503 netif_info(tp, ifdown, dev, "link down\n");
1505 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1509 static void rtl8169_check_link_status(struct net_device *dev,
1510 struct rtl8169_private *tp,
1511 void __iomem *ioaddr)
1513 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1516 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1518 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1520 void __iomem *ioaddr = tp->mmio_addr;
1524 options = RTL_R8(Config1);
1525 if (!(options & PMEnable))
1528 options = RTL_R8(Config3);
1529 if (options & LinkUp)
1530 wolopts |= WAKE_PHY;
1531 if (options & MagicPacket)
1532 wolopts |= WAKE_MAGIC;
1534 options = RTL_R8(Config5);
1536 wolopts |= WAKE_UCAST;
1538 wolopts |= WAKE_BCAST;
1540 wolopts |= WAKE_MCAST;
1545 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1547 struct rtl8169_private *tp = netdev_priv(dev);
1551 wol->supported = WAKE_ANY;
1552 wol->wolopts = __rtl8169_get_wol(tp);
1554 rtl_unlock_work(tp);
1557 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1559 void __iomem *ioaddr = tp->mmio_addr;
1561 static const struct {
1566 { WAKE_PHY, Config3, LinkUp },
1567 { WAKE_MAGIC, Config3, MagicPacket },
1568 { WAKE_UCAST, Config5, UWF },
1569 { WAKE_BCAST, Config5, BWF },
1570 { WAKE_MCAST, Config5, MWF },
1571 { WAKE_ANY, Config5, LanWake }
1575 RTL_W8(Cfg9346, Cfg9346_Unlock);
1577 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1578 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1579 if (wolopts & cfg[i].opt)
1580 options |= cfg[i].mask;
1581 RTL_W8(cfg[i].reg, options);
1584 switch (tp->mac_version) {
1585 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1586 options = RTL_R8(Config1) & ~PMEnable;
1588 options |= PMEnable;
1589 RTL_W8(Config1, options);
1592 options = RTL_R8(Config2) & ~PME_SIGNAL;
1594 options |= PME_SIGNAL;
1595 RTL_W8(Config2, options);
1599 RTL_W8(Cfg9346, Cfg9346_Lock);
1602 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1604 struct rtl8169_private *tp = netdev_priv(dev);
1609 tp->features |= RTL_FEATURE_WOL;
1611 tp->features &= ~RTL_FEATURE_WOL;
1612 __rtl8169_set_wol(tp, wol->wolopts);
1614 rtl_unlock_work(tp);
1616 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1621 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1623 return rtl_chip_infos[tp->mac_version].fw_name;
1626 static void rtl8169_get_drvinfo(struct net_device *dev,
1627 struct ethtool_drvinfo *info)
1629 struct rtl8169_private *tp = netdev_priv(dev);
1630 struct rtl_fw *rtl_fw = tp->rtl_fw;
1632 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1633 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1634 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1635 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1636 if (!IS_ERR_OR_NULL(rtl_fw))
1637 strlcpy(info->fw_version, rtl_fw->version,
1638 sizeof(info->fw_version));
1641 static int rtl8169_get_regs_len(struct net_device *dev)
1643 return R8169_REGS_SIZE;
1646 static int rtl8169_set_speed_tbi(struct net_device *dev,
1647 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650 void __iomem *ioaddr = tp->mmio_addr;
1654 reg = RTL_R32(TBICSR);
1655 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1656 (duplex == DUPLEX_FULL)) {
1657 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1658 } else if (autoneg == AUTONEG_ENABLE)
1659 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1661 netif_warn(tp, link, dev,
1662 "incorrect speed setting refused in TBI mode\n");
1669 static int rtl8169_set_speed_xmii(struct net_device *dev,
1670 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1672 struct rtl8169_private *tp = netdev_priv(dev);
1673 int giga_ctrl, bmcr;
1676 rtl_writephy(tp, 0x1f, 0x0000);
1678 if (autoneg == AUTONEG_ENABLE) {
1681 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1682 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1683 ADVERTISE_100HALF | ADVERTISE_100FULL);
1685 if (adv & ADVERTISED_10baseT_Half)
1686 auto_nego |= ADVERTISE_10HALF;
1687 if (adv & ADVERTISED_10baseT_Full)
1688 auto_nego |= ADVERTISE_10FULL;
1689 if (adv & ADVERTISED_100baseT_Half)
1690 auto_nego |= ADVERTISE_100HALF;
1691 if (adv & ADVERTISED_100baseT_Full)
1692 auto_nego |= ADVERTISE_100FULL;
1694 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1696 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1699 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1700 if (tp->mii.supports_gmii) {
1701 if (adv & ADVERTISED_1000baseT_Half)
1702 giga_ctrl |= ADVERTISE_1000HALF;
1703 if (adv & ADVERTISED_1000baseT_Full)
1704 giga_ctrl |= ADVERTISE_1000FULL;
1705 } else if (adv & (ADVERTISED_1000baseT_Half |
1706 ADVERTISED_1000baseT_Full)) {
1707 netif_info(tp, link, dev,
1708 "PHY does not support 1000Mbps\n");
1712 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1714 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1715 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1719 if (speed == SPEED_10)
1721 else if (speed == SPEED_100)
1722 bmcr = BMCR_SPEED100;
1726 if (duplex == DUPLEX_FULL)
1727 bmcr |= BMCR_FULLDPLX;
1730 rtl_writephy(tp, MII_BMCR, bmcr);
1732 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1733 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1734 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1735 rtl_writephy(tp, 0x17, 0x2138);
1736 rtl_writephy(tp, 0x0e, 0x0260);
1738 rtl_writephy(tp, 0x17, 0x2108);
1739 rtl_writephy(tp, 0x0e, 0x0000);
1748 static int rtl8169_set_speed(struct net_device *dev,
1749 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1751 struct rtl8169_private *tp = netdev_priv(dev);
1754 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1758 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1759 (advertising & ADVERTISED_1000baseT_Full)) {
1760 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1766 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1768 struct rtl8169_private *tp = netdev_priv(dev);
1771 del_timer_sync(&tp->timer);
1774 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1775 cmd->duplex, cmd->advertising);
1776 rtl_unlock_work(tp);
1781 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1782 netdev_features_t features)
1784 struct rtl8169_private *tp = netdev_priv(dev);
1786 if (dev->mtu > TD_MSS_MAX)
1787 features &= ~NETIF_F_ALL_TSO;
1789 if (dev->mtu > JUMBO_1K &&
1790 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1791 features &= ~NETIF_F_IP_CSUM;
1796 static void __rtl8169_set_features(struct net_device *dev,
1797 netdev_features_t features)
1799 struct rtl8169_private *tp = netdev_priv(dev);
1800 netdev_features_t changed = features ^ dev->features;
1801 void __iomem *ioaddr = tp->mmio_addr;
1803 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1804 NETIF_F_HW_VLAN_CTAG_RX)))
1807 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1808 if (features & NETIF_F_RXCSUM)
1809 tp->cp_cmd |= RxChkSum;
1811 tp->cp_cmd &= ~RxChkSum;
1813 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1814 tp->cp_cmd |= RxVlan;
1816 tp->cp_cmd &= ~RxVlan;
1818 RTL_W16(CPlusCmd, tp->cp_cmd);
1821 if (changed & NETIF_F_RXALL) {
1822 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1823 if (features & NETIF_F_RXALL)
1824 tmp |= (AcceptErr | AcceptRunt);
1825 RTL_W32(RxConfig, tmp);
1829 static int rtl8169_set_features(struct net_device *dev,
1830 netdev_features_t features)
1832 struct rtl8169_private *tp = netdev_priv(dev);
1835 __rtl8169_set_features(dev, features);
1836 rtl_unlock_work(tp);
1842 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1844 return (vlan_tx_tag_present(skb)) ?
1845 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1848 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1850 u32 opts2 = le32_to_cpu(desc->opts2);
1852 if (opts2 & RxVlanTag)
1853 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1856 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1858 struct rtl8169_private *tp = netdev_priv(dev);
1859 void __iomem *ioaddr = tp->mmio_addr;
1863 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1864 cmd->port = PORT_FIBRE;
1865 cmd->transceiver = XCVR_INTERNAL;
1867 status = RTL_R32(TBICSR);
1868 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1869 cmd->autoneg = !!(status & TBINwEnable);
1871 ethtool_cmd_speed_set(cmd, SPEED_1000);
1872 cmd->duplex = DUPLEX_FULL; /* Always set */
1877 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1879 struct rtl8169_private *tp = netdev_priv(dev);
1881 return mii_ethtool_gset(&tp->mii, cmd);
1884 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1886 struct rtl8169_private *tp = netdev_priv(dev);
1890 rc = tp->get_settings(dev, cmd);
1891 rtl_unlock_work(tp);
1896 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1899 struct rtl8169_private *tp = netdev_priv(dev);
1901 if (regs->len > R8169_REGS_SIZE)
1902 regs->len = R8169_REGS_SIZE;
1905 memcpy_fromio(p, tp->mmio_addr, regs->len);
1906 rtl_unlock_work(tp);
1909 static u32 rtl8169_get_msglevel(struct net_device *dev)
1911 struct rtl8169_private *tp = netdev_priv(dev);
1913 return tp->msg_enable;
1916 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1918 struct rtl8169_private *tp = netdev_priv(dev);
1920 tp->msg_enable = value;
1923 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1930 "tx_single_collisions",
1931 "tx_multi_collisions",
1939 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1943 return ARRAY_SIZE(rtl8169_gstrings);
1949 DECLARE_RTL_COND(rtl_counters_cond)
1951 void __iomem *ioaddr = tp->mmio_addr;
1953 return RTL_R32(CounterAddrLow) & CounterDump;
1956 static void rtl8169_update_counters(struct net_device *dev)
1958 struct rtl8169_private *tp = netdev_priv(dev);
1959 void __iomem *ioaddr = tp->mmio_addr;
1960 struct device *d = &tp->pci_dev->dev;
1961 struct rtl8169_counters *counters;
1966 * Some chips are unable to dump tally counters when the receiver
1969 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1972 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1976 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1977 cmd = (u64)paddr & DMA_BIT_MASK(32);
1978 RTL_W32(CounterAddrLow, cmd);
1979 RTL_W32(CounterAddrLow, cmd | CounterDump);
1981 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1982 memcpy(&tp->counters, counters, sizeof(*counters));
1984 RTL_W32(CounterAddrLow, 0);
1985 RTL_W32(CounterAddrHigh, 0);
1987 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1990 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1991 struct ethtool_stats *stats, u64 *data)
1993 struct rtl8169_private *tp = netdev_priv(dev);
1997 rtl8169_update_counters(dev);
1999 data[0] = le64_to_cpu(tp->counters.tx_packets);
2000 data[1] = le64_to_cpu(tp->counters.rx_packets);
2001 data[2] = le64_to_cpu(tp->counters.tx_errors);
2002 data[3] = le32_to_cpu(tp->counters.rx_errors);
2003 data[4] = le16_to_cpu(tp->counters.rx_missed);
2004 data[5] = le16_to_cpu(tp->counters.align_errors);
2005 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2006 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2007 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2008 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2009 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2010 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2011 data[12] = le16_to_cpu(tp->counters.tx_underun);
2014 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2018 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2023 static const struct ethtool_ops rtl8169_ethtool_ops = {
2024 .get_drvinfo = rtl8169_get_drvinfo,
2025 .get_regs_len = rtl8169_get_regs_len,
2026 .get_link = ethtool_op_get_link,
2027 .get_settings = rtl8169_get_settings,
2028 .set_settings = rtl8169_set_settings,
2029 .get_msglevel = rtl8169_get_msglevel,
2030 .set_msglevel = rtl8169_set_msglevel,
2031 .get_regs = rtl8169_get_regs,
2032 .get_wol = rtl8169_get_wol,
2033 .set_wol = rtl8169_set_wol,
2034 .get_strings = rtl8169_get_strings,
2035 .get_sset_count = rtl8169_get_sset_count,
2036 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2037 .get_ts_info = ethtool_op_get_ts_info,
2040 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2041 struct net_device *dev, u8 default_version)
2043 void __iomem *ioaddr = tp->mmio_addr;
2045 * The driver currently handles the 8168Bf and the 8168Be identically
2046 * but they can be identified more specifically through the test below
2049 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2051 * Same thing for the 8101Eb and the 8101Ec:
2053 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2055 static const struct rtl_mac_info {
2061 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2062 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2063 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2064 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2067 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2068 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2069 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2072 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2073 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2074 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2075 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2078 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2079 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2080 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2082 /* 8168DP family. */
2083 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2084 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2085 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2088 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2089 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2090 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2091 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2092 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2093 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2094 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2095 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2096 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2099 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2100 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2101 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2102 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2105 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2106 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2107 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2108 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2109 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2110 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2111 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2112 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2113 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2114 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2115 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2116 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2117 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2118 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2119 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2120 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2121 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2122 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2123 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2124 /* FIXME: where did these entries come from ? -- FR */
2125 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2126 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2129 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2130 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2131 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2132 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2133 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2134 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2137 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2139 const struct rtl_mac_info *p = mac_info;
2142 reg = RTL_R32(TxConfig);
2143 while ((reg & p->mask) != p->val)
2145 tp->mac_version = p->mac_version;
2147 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2148 netif_notice(tp, probe, dev,
2149 "unknown MAC, using family default\n");
2150 tp->mac_version = default_version;
2151 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2152 tp->mac_version = tp->mii.supports_gmii ?
2153 RTL_GIGA_MAC_VER_42 :
2154 RTL_GIGA_MAC_VER_43;
2158 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2160 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2168 static void rtl_writephy_batch(struct rtl8169_private *tp,
2169 const struct phy_reg *regs, int len)
2172 rtl_writephy(tp, regs->reg, regs->val);
2177 #define PHY_READ 0x00000000
2178 #define PHY_DATA_OR 0x10000000
2179 #define PHY_DATA_AND 0x20000000
2180 #define PHY_BJMPN 0x30000000
2181 #define PHY_MDIO_CHG 0x40000000
2182 #define PHY_CLEAR_READCOUNT 0x70000000
2183 #define PHY_WRITE 0x80000000
2184 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2185 #define PHY_COMP_EQ_SKIPN 0xa0000000
2186 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2187 #define PHY_WRITE_PREVIOUS 0xc0000000
2188 #define PHY_SKIPN 0xd0000000
2189 #define PHY_DELAY_MS 0xe0000000
2193 char version[RTL_VER_SIZE];
2199 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2201 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2203 const struct firmware *fw = rtl_fw->fw;
2204 struct fw_info *fw_info = (struct fw_info *)fw->data;
2205 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2206 char *version = rtl_fw->version;
2209 if (fw->size < FW_OPCODE_SIZE)
2212 if (!fw_info->magic) {
2213 size_t i, size, start;
2216 if (fw->size < sizeof(*fw_info))
2219 for (i = 0; i < fw->size; i++)
2220 checksum += fw->data[i];
2224 start = le32_to_cpu(fw_info->fw_start);
2225 if (start > fw->size)
2228 size = le32_to_cpu(fw_info->fw_len);
2229 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2232 memcpy(version, fw_info->version, RTL_VER_SIZE);
2234 pa->code = (__le32 *)(fw->data + start);
2237 if (fw->size % FW_OPCODE_SIZE)
2240 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2242 pa->code = (__le32 *)fw->data;
2243 pa->size = fw->size / FW_OPCODE_SIZE;
2245 version[RTL_VER_SIZE - 1] = 0;
2252 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2253 struct rtl_fw_phy_action *pa)
2258 for (index = 0; index < pa->size; index++) {
2259 u32 action = le32_to_cpu(pa->code[index]);
2260 u32 regno = (action & 0x0fff0000) >> 16;
2262 switch(action & 0xf0000000) {
2267 case PHY_CLEAR_READCOUNT:
2269 case PHY_WRITE_PREVIOUS:
2274 if (regno > index) {
2275 netif_err(tp, ifup, tp->dev,
2276 "Out of range of firmware\n");
2280 case PHY_READCOUNT_EQ_SKIP:
2281 if (index + 2 >= pa->size) {
2282 netif_err(tp, ifup, tp->dev,
2283 "Out of range of firmware\n");
2287 case PHY_COMP_EQ_SKIPN:
2288 case PHY_COMP_NEQ_SKIPN:
2290 if (index + 1 + regno >= pa->size) {
2291 netif_err(tp, ifup, tp->dev,
2292 "Out of range of firmware\n");
2298 netif_err(tp, ifup, tp->dev,
2299 "Invalid action 0x%08x\n", action);
2308 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2310 struct net_device *dev = tp->dev;
2313 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2314 netif_err(tp, ifup, dev, "invalid firwmare\n");
2318 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2324 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2326 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2327 struct mdio_ops org, *ops = &tp->mdio_ops;
2331 predata = count = 0;
2332 org.write = ops->write;
2333 org.read = ops->read;
2335 for (index = 0; index < pa->size; ) {
2336 u32 action = le32_to_cpu(pa->code[index]);
2337 u32 data = action & 0x0000ffff;
2338 u32 regno = (action & 0x0fff0000) >> 16;
2343 switch(action & 0xf0000000) {
2345 predata = rtl_readphy(tp, regno);
2362 ops->write = org.write;
2363 ops->read = org.read;
2364 } else if (data == 1) {
2365 ops->write = mac_mcu_write;
2366 ops->read = mac_mcu_read;
2371 case PHY_CLEAR_READCOUNT:
2376 rtl_writephy(tp, regno, data);
2379 case PHY_READCOUNT_EQ_SKIP:
2380 index += (count == data) ? 2 : 1;
2382 case PHY_COMP_EQ_SKIPN:
2383 if (predata == data)
2387 case PHY_COMP_NEQ_SKIPN:
2388 if (predata != data)
2392 case PHY_WRITE_PREVIOUS:
2393 rtl_writephy(tp, regno, predata);
2409 ops->write = org.write;
2410 ops->read = org.read;
2413 static void rtl_release_firmware(struct rtl8169_private *tp)
2415 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2416 release_firmware(tp->rtl_fw->fw);
2419 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2422 static void rtl_apply_firmware(struct rtl8169_private *tp)
2424 struct rtl_fw *rtl_fw = tp->rtl_fw;
2426 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2427 if (!IS_ERR_OR_NULL(rtl_fw))
2428 rtl_phy_write_fw(tp, rtl_fw);
2431 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2433 if (rtl_readphy(tp, reg) != val)
2434 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2436 rtl_apply_firmware(tp);
2439 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2441 static const struct phy_reg phy_reg_init[] = {
2503 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2506 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2508 static const struct phy_reg phy_reg_init[] = {
2514 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2519 struct pci_dev *pdev = tp->pci_dev;
2521 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2522 (pdev->subsystem_device != 0xe000))
2525 rtl_writephy(tp, 0x1f, 0x0001);
2526 rtl_writephy(tp, 0x10, 0xf01b);
2527 rtl_writephy(tp, 0x1f, 0x0000);
2530 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2532 static const struct phy_reg phy_reg_init[] = {
2572 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2574 rtl8169scd_hw_phy_config_quirk(tp);
2577 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2579 static const struct phy_reg phy_reg_init[] = {
2627 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2630 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2632 static const struct phy_reg phy_reg_init[] = {
2637 rtl_writephy(tp, 0x1f, 0x0001);
2638 rtl_patchphy(tp, 0x16, 1 << 0);
2640 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2643 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2645 static const struct phy_reg phy_reg_init[] = {
2651 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2654 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2656 static const struct phy_reg phy_reg_init[] = {
2664 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2667 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2669 static const struct phy_reg phy_reg_init[] = {
2675 rtl_writephy(tp, 0x1f, 0x0000);
2676 rtl_patchphy(tp, 0x14, 1 << 5);
2677 rtl_patchphy(tp, 0x0d, 1 << 5);
2679 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2682 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2684 static const struct phy_reg phy_reg_init[] = {
2704 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2706 rtl_patchphy(tp, 0x14, 1 << 5);
2707 rtl_patchphy(tp, 0x0d, 1 << 5);
2708 rtl_writephy(tp, 0x1f, 0x0000);
2711 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2713 static const struct phy_reg phy_reg_init[] = {
2731 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2733 rtl_patchphy(tp, 0x16, 1 << 0);
2734 rtl_patchphy(tp, 0x14, 1 << 5);
2735 rtl_patchphy(tp, 0x0d, 1 << 5);
2736 rtl_writephy(tp, 0x1f, 0x0000);
2739 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2741 static const struct phy_reg phy_reg_init[] = {
2753 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2755 rtl_patchphy(tp, 0x16, 1 << 0);
2756 rtl_patchphy(tp, 0x14, 1 << 5);
2757 rtl_patchphy(tp, 0x0d, 1 << 5);
2758 rtl_writephy(tp, 0x1f, 0x0000);
2761 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2763 rtl8168c_3_hw_phy_config(tp);
2766 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2768 static const struct phy_reg phy_reg_init_0[] = {
2769 /* Channel Estimation */
2790 * Enhance line driver power
2799 * Can not link to 1Gbps with bad cable
2800 * Decrease SNR threshold form 21.07dB to 19.04dB
2809 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2813 * Fine Tune Switching regulator parameter
2815 rtl_writephy(tp, 0x1f, 0x0002);
2816 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2817 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2819 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2820 static const struct phy_reg phy_reg_init[] = {
2830 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2832 val = rtl_readphy(tp, 0x0d);
2834 if ((val & 0x00ff) != 0x006c) {
2835 static const u32 set[] = {
2836 0x0065, 0x0066, 0x0067, 0x0068,
2837 0x0069, 0x006a, 0x006b, 0x006c
2841 rtl_writephy(tp, 0x1f, 0x0002);
2844 for (i = 0; i < ARRAY_SIZE(set); i++)
2845 rtl_writephy(tp, 0x0d, val | set[i]);
2848 static const struct phy_reg phy_reg_init[] = {
2856 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2859 /* RSET couple improve */
2860 rtl_writephy(tp, 0x1f, 0x0002);
2861 rtl_patchphy(tp, 0x0d, 0x0300);
2862 rtl_patchphy(tp, 0x0f, 0x0010);
2864 /* Fine tune PLL performance */
2865 rtl_writephy(tp, 0x1f, 0x0002);
2866 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2867 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2869 rtl_writephy(tp, 0x1f, 0x0005);
2870 rtl_writephy(tp, 0x05, 0x001b);
2872 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2874 rtl_writephy(tp, 0x1f, 0x0000);
2877 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2879 static const struct phy_reg phy_reg_init_0[] = {
2880 /* Channel Estimation */
2901 * Enhance line driver power
2910 * Can not link to 1Gbps with bad cable
2911 * Decrease SNR threshold form 21.07dB to 19.04dB
2920 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2922 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2923 static const struct phy_reg phy_reg_init[] = {
2934 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2936 val = rtl_readphy(tp, 0x0d);
2937 if ((val & 0x00ff) != 0x006c) {
2938 static const u32 set[] = {
2939 0x0065, 0x0066, 0x0067, 0x0068,
2940 0x0069, 0x006a, 0x006b, 0x006c
2944 rtl_writephy(tp, 0x1f, 0x0002);
2947 for (i = 0; i < ARRAY_SIZE(set); i++)
2948 rtl_writephy(tp, 0x0d, val | set[i]);
2951 static const struct phy_reg phy_reg_init[] = {
2959 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2962 /* Fine tune PLL performance */
2963 rtl_writephy(tp, 0x1f, 0x0002);
2964 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2965 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2967 /* Switching regulator Slew rate */
2968 rtl_writephy(tp, 0x1f, 0x0002);
2969 rtl_patchphy(tp, 0x0f, 0x0017);
2971 rtl_writephy(tp, 0x1f, 0x0005);
2972 rtl_writephy(tp, 0x05, 0x001b);
2974 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2976 rtl_writephy(tp, 0x1f, 0x0000);
2979 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2981 static const struct phy_reg phy_reg_init[] = {
3037 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3040 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3042 static const struct phy_reg phy_reg_init[] = {
3052 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3053 rtl_patchphy(tp, 0x0d, 1 << 5);
3056 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3058 static const struct phy_reg phy_reg_init[] = {
3059 /* Enable Delay cap */
3065 /* Channel estimation fine tune */
3074 /* Update PFM & 10M TX idle timer */
3086 rtl_apply_firmware(tp);
3088 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3090 /* DCO enable for 10M IDLE Power */
3091 rtl_writephy(tp, 0x1f, 0x0007);
3092 rtl_writephy(tp, 0x1e, 0x0023);
3093 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3094 rtl_writephy(tp, 0x1f, 0x0000);
3096 /* For impedance matching */
3097 rtl_writephy(tp, 0x1f, 0x0002);
3098 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3101 /* PHY auto speed down */
3102 rtl_writephy(tp, 0x1f, 0x0007);
3103 rtl_writephy(tp, 0x1e, 0x002d);
3104 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3105 rtl_writephy(tp, 0x1f, 0x0000);
3106 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3108 rtl_writephy(tp, 0x1f, 0x0005);
3109 rtl_writephy(tp, 0x05, 0x8b86);
3110 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3111 rtl_writephy(tp, 0x1f, 0x0000);
3113 rtl_writephy(tp, 0x1f, 0x0005);
3114 rtl_writephy(tp, 0x05, 0x8b85);
3115 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3116 rtl_writephy(tp, 0x1f, 0x0007);
3117 rtl_writephy(tp, 0x1e, 0x0020);
3118 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3119 rtl_writephy(tp, 0x1f, 0x0006);
3120 rtl_writephy(tp, 0x00, 0x5a00);
3121 rtl_writephy(tp, 0x1f, 0x0000);
3122 rtl_writephy(tp, 0x0d, 0x0007);
3123 rtl_writephy(tp, 0x0e, 0x003c);
3124 rtl_writephy(tp, 0x0d, 0x4007);
3125 rtl_writephy(tp, 0x0e, 0x0000);
3126 rtl_writephy(tp, 0x0d, 0x0000);
3129 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3132 addr[0] | (addr[1] << 8),
3133 addr[2] | (addr[3] << 8),
3134 addr[4] | (addr[5] << 8)
3136 const struct exgmac_reg e[] = {
3137 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3138 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3139 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3140 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3143 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3146 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3148 static const struct phy_reg phy_reg_init[] = {
3149 /* Enable Delay cap */
3158 /* Channel estimation fine tune */
3175 rtl_apply_firmware(tp);
3177 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3179 /* For 4-corner performance improve */
3180 rtl_writephy(tp, 0x1f, 0x0005);
3181 rtl_writephy(tp, 0x05, 0x8b80);
3182 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3183 rtl_writephy(tp, 0x1f, 0x0000);
3185 /* PHY auto speed down */
3186 rtl_writephy(tp, 0x1f, 0x0004);
3187 rtl_writephy(tp, 0x1f, 0x0007);
3188 rtl_writephy(tp, 0x1e, 0x002d);
3189 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3190 rtl_writephy(tp, 0x1f, 0x0002);
3191 rtl_writephy(tp, 0x1f, 0x0000);
3192 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3194 /* improve 10M EEE waveform */
3195 rtl_writephy(tp, 0x1f, 0x0005);
3196 rtl_writephy(tp, 0x05, 0x8b86);
3197 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3198 rtl_writephy(tp, 0x1f, 0x0000);
3200 /* Improve 2-pair detection performance */
3201 rtl_writephy(tp, 0x1f, 0x0005);
3202 rtl_writephy(tp, 0x05, 0x8b85);
3203 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3204 rtl_writephy(tp, 0x1f, 0x0000);
3207 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3208 rtl_writephy(tp, 0x1f, 0x0005);
3209 rtl_writephy(tp, 0x05, 0x8b85);
3210 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3211 rtl_writephy(tp, 0x1f, 0x0004);
3212 rtl_writephy(tp, 0x1f, 0x0007);
3213 rtl_writephy(tp, 0x1e, 0x0020);
3214 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3215 rtl_writephy(tp, 0x1f, 0x0002);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217 rtl_writephy(tp, 0x0d, 0x0007);
3218 rtl_writephy(tp, 0x0e, 0x003c);
3219 rtl_writephy(tp, 0x0d, 0x4007);
3220 rtl_writephy(tp, 0x0e, 0x0000);
3221 rtl_writephy(tp, 0x0d, 0x0000);
3224 rtl_writephy(tp, 0x1f, 0x0003);
3225 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3226 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3227 rtl_writephy(tp, 0x1f, 0x0000);
3229 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3230 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3233 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3235 /* For 4-corner performance improve */
3236 rtl_writephy(tp, 0x1f, 0x0005);
3237 rtl_writephy(tp, 0x05, 0x8b80);
3238 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3239 rtl_writephy(tp, 0x1f, 0x0000);
3241 /* PHY auto speed down */
3242 rtl_writephy(tp, 0x1f, 0x0007);
3243 rtl_writephy(tp, 0x1e, 0x002d);
3244 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3245 rtl_writephy(tp, 0x1f, 0x0000);
3246 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3248 /* Improve 10M EEE waveform */
3249 rtl_writephy(tp, 0x1f, 0x0005);
3250 rtl_writephy(tp, 0x05, 0x8b86);
3251 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3252 rtl_writephy(tp, 0x1f, 0x0000);
3255 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3257 static const struct phy_reg phy_reg_init[] = {
3258 /* Channel estimation fine tune */
3263 /* Modify green table for giga & fnet */
3280 /* Modify green table for 10M */
3286 /* Disable hiimpedance detection (RTCT) */
3292 rtl_apply_firmware(tp);
3294 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3296 rtl8168f_hw_phy_config(tp);
3298 /* Improve 2-pair detection performance */
3299 rtl_writephy(tp, 0x1f, 0x0005);
3300 rtl_writephy(tp, 0x05, 0x8b85);
3301 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3302 rtl_writephy(tp, 0x1f, 0x0000);
3305 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3307 rtl_apply_firmware(tp);
3309 rtl8168f_hw_phy_config(tp);
3312 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3314 static const struct phy_reg phy_reg_init[] = {
3315 /* Channel estimation fine tune */
3320 /* Modify green table for giga & fnet */
3337 /* Modify green table for 10M */
3343 /* Disable hiimpedance detection (RTCT) */
3350 rtl_apply_firmware(tp);
3352 rtl8168f_hw_phy_config(tp);
3354 /* Improve 2-pair detection performance */
3355 rtl_writephy(tp, 0x1f, 0x0005);
3356 rtl_writephy(tp, 0x05, 0x8b85);
3357 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3358 rtl_writephy(tp, 0x1f, 0x0000);
3360 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3362 /* Modify green table for giga */
3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x8b54);
3365 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3366 rtl_writephy(tp, 0x05, 0x8b5d);
3367 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3368 rtl_writephy(tp, 0x05, 0x8a7c);
3369 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370 rtl_writephy(tp, 0x05, 0x8a7f);
3371 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3372 rtl_writephy(tp, 0x05, 0x8a82);
3373 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3374 rtl_writephy(tp, 0x05, 0x8a85);
3375 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3376 rtl_writephy(tp, 0x05, 0x8a88);
3377 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3378 rtl_writephy(tp, 0x1f, 0x0000);
3380 /* uc same-seed solution */
3381 rtl_writephy(tp, 0x1f, 0x0005);
3382 rtl_writephy(tp, 0x05, 0x8b85);
3383 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3384 rtl_writephy(tp, 0x1f, 0x0000);
3387 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3388 rtl_writephy(tp, 0x1f, 0x0005);
3389 rtl_writephy(tp, 0x05, 0x8b85);
3390 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3391 rtl_writephy(tp, 0x1f, 0x0004);
3392 rtl_writephy(tp, 0x1f, 0x0007);
3393 rtl_writephy(tp, 0x1e, 0x0020);
3394 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3395 rtl_writephy(tp, 0x1f, 0x0000);
3396 rtl_writephy(tp, 0x0d, 0x0007);
3397 rtl_writephy(tp, 0x0e, 0x003c);
3398 rtl_writephy(tp, 0x0d, 0x4007);
3399 rtl_writephy(tp, 0x0e, 0x0000);
3400 rtl_writephy(tp, 0x0d, 0x0000);
3403 rtl_writephy(tp, 0x1f, 0x0003);
3404 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3405 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3406 rtl_writephy(tp, 0x1f, 0x0000);
3409 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3411 rtl_apply_firmware(tp);
3413 rtl_writephy(tp, 0x1f, 0x0a46);
3414 if (rtl_readphy(tp, 0x10) & 0x0100) {
3415 rtl_writephy(tp, 0x1f, 0x0bcc);
3416 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3418 rtl_writephy(tp, 0x1f, 0x0bcc);
3419 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3422 rtl_writephy(tp, 0x1f, 0x0a46);
3423 if (rtl_readphy(tp, 0x13) & 0x0100) {
3424 rtl_writephy(tp, 0x1f, 0x0c41);
3425 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3427 rtl_writephy(tp, 0x1f, 0x0c41);
3428 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3431 /* Enable PHY auto speed down */
3432 rtl_writephy(tp, 0x1f, 0x0a44);
3433 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3435 rtl_writephy(tp, 0x1f, 0x0bcc);
3436 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3437 rtl_writephy(tp, 0x1f, 0x0a44);
3438 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3439 rtl_writephy(tp, 0x1f, 0x0a43);
3440 rtl_writephy(tp, 0x13, 0x8084);
3441 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3442 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3444 /* EEE auto-fallback function */
3445 rtl_writephy(tp, 0x1f, 0x0a4b);
3446 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3448 /* Enable UC LPF tune function */
3449 rtl_writephy(tp, 0x1f, 0x0a43);
3450 rtl_writephy(tp, 0x13, 0x8012);
3451 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3453 rtl_writephy(tp, 0x1f, 0x0c42);
3454 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3456 /* Improve SWR Efficiency */
3457 rtl_writephy(tp, 0x1f, 0x0bcd);
3458 rtl_writephy(tp, 0x14, 0x5065);
3459 rtl_writephy(tp, 0x14, 0xd065);
3460 rtl_writephy(tp, 0x1f, 0x0bc8);
3461 rtl_writephy(tp, 0x11, 0x5655);
3462 rtl_writephy(tp, 0x1f, 0x0bcd);
3463 rtl_writephy(tp, 0x14, 0x1065);
3464 rtl_writephy(tp, 0x14, 0x9065);
3465 rtl_writephy(tp, 0x14, 0x1065);
3467 rtl_writephy(tp, 0x1f, 0x0000);
3470 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3472 rtl_apply_firmware(tp);
3475 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3477 static const struct phy_reg phy_reg_init[] = {
3484 rtl_writephy(tp, 0x1f, 0x0000);
3485 rtl_patchphy(tp, 0x11, 1 << 12);
3486 rtl_patchphy(tp, 0x19, 1 << 13);
3487 rtl_patchphy(tp, 0x10, 1 << 15);
3489 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3492 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3494 static const struct phy_reg phy_reg_init[] = {
3508 /* Disable ALDPS before ram code */
3509 rtl_writephy(tp, 0x1f, 0x0000);
3510 rtl_writephy(tp, 0x18, 0x0310);
3513 rtl_apply_firmware(tp);
3515 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3518 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3520 /* Disable ALDPS before setting firmware */
3521 rtl_writephy(tp, 0x1f, 0x0000);
3522 rtl_writephy(tp, 0x18, 0x0310);
3525 rtl_apply_firmware(tp);
3528 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3529 rtl_writephy(tp, 0x1f, 0x0004);
3530 rtl_writephy(tp, 0x10, 0x401f);
3531 rtl_writephy(tp, 0x19, 0x7030);
3532 rtl_writephy(tp, 0x1f, 0x0000);
3535 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3537 static const struct phy_reg phy_reg_init[] = {
3544 /* Disable ALDPS before ram code */
3545 rtl_writephy(tp, 0x1f, 0x0000);
3546 rtl_writephy(tp, 0x18, 0x0310);
3549 rtl_apply_firmware(tp);
3551 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3552 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3554 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3557 static void rtl_hw_phy_config(struct net_device *dev)
3559 struct rtl8169_private *tp = netdev_priv(dev);
3561 rtl8169_print_mac_version(tp);
3563 switch (tp->mac_version) {
3564 case RTL_GIGA_MAC_VER_01:
3566 case RTL_GIGA_MAC_VER_02:
3567 case RTL_GIGA_MAC_VER_03:
3568 rtl8169s_hw_phy_config(tp);
3570 case RTL_GIGA_MAC_VER_04:
3571 rtl8169sb_hw_phy_config(tp);
3573 case RTL_GIGA_MAC_VER_05:
3574 rtl8169scd_hw_phy_config(tp);
3576 case RTL_GIGA_MAC_VER_06:
3577 rtl8169sce_hw_phy_config(tp);
3579 case RTL_GIGA_MAC_VER_07:
3580 case RTL_GIGA_MAC_VER_08:
3581 case RTL_GIGA_MAC_VER_09:
3582 rtl8102e_hw_phy_config(tp);
3584 case RTL_GIGA_MAC_VER_11:
3585 rtl8168bb_hw_phy_config(tp);
3587 case RTL_GIGA_MAC_VER_12:
3588 rtl8168bef_hw_phy_config(tp);
3590 case RTL_GIGA_MAC_VER_17:
3591 rtl8168bef_hw_phy_config(tp);
3593 case RTL_GIGA_MAC_VER_18:
3594 rtl8168cp_1_hw_phy_config(tp);
3596 case RTL_GIGA_MAC_VER_19:
3597 rtl8168c_1_hw_phy_config(tp);
3599 case RTL_GIGA_MAC_VER_20:
3600 rtl8168c_2_hw_phy_config(tp);
3602 case RTL_GIGA_MAC_VER_21:
3603 rtl8168c_3_hw_phy_config(tp);
3605 case RTL_GIGA_MAC_VER_22:
3606 rtl8168c_4_hw_phy_config(tp);
3608 case RTL_GIGA_MAC_VER_23:
3609 case RTL_GIGA_MAC_VER_24:
3610 rtl8168cp_2_hw_phy_config(tp);
3612 case RTL_GIGA_MAC_VER_25:
3613 rtl8168d_1_hw_phy_config(tp);
3615 case RTL_GIGA_MAC_VER_26:
3616 rtl8168d_2_hw_phy_config(tp);
3618 case RTL_GIGA_MAC_VER_27:
3619 rtl8168d_3_hw_phy_config(tp);
3621 case RTL_GIGA_MAC_VER_28:
3622 rtl8168d_4_hw_phy_config(tp);
3624 case RTL_GIGA_MAC_VER_29:
3625 case RTL_GIGA_MAC_VER_30:
3626 rtl8105e_hw_phy_config(tp);
3628 case RTL_GIGA_MAC_VER_31:
3631 case RTL_GIGA_MAC_VER_32:
3632 case RTL_GIGA_MAC_VER_33:
3633 rtl8168e_1_hw_phy_config(tp);
3635 case RTL_GIGA_MAC_VER_34:
3636 rtl8168e_2_hw_phy_config(tp);
3638 case RTL_GIGA_MAC_VER_35:
3639 rtl8168f_1_hw_phy_config(tp);
3641 case RTL_GIGA_MAC_VER_36:
3642 rtl8168f_2_hw_phy_config(tp);
3645 case RTL_GIGA_MAC_VER_37:
3646 rtl8402_hw_phy_config(tp);
3649 case RTL_GIGA_MAC_VER_38:
3650 rtl8411_hw_phy_config(tp);
3653 case RTL_GIGA_MAC_VER_39:
3654 rtl8106e_hw_phy_config(tp);
3657 case RTL_GIGA_MAC_VER_40:
3658 rtl8168g_1_hw_phy_config(tp);
3660 case RTL_GIGA_MAC_VER_42:
3661 case RTL_GIGA_MAC_VER_43:
3662 case RTL_GIGA_MAC_VER_44:
3663 rtl8168g_2_hw_phy_config(tp);
3666 case RTL_GIGA_MAC_VER_41:
3672 static void rtl_phy_work(struct rtl8169_private *tp)
3674 struct timer_list *timer = &tp->timer;
3675 void __iomem *ioaddr = tp->mmio_addr;
3676 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3678 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3680 if (tp->phy_reset_pending(tp)) {
3682 * A busy loop could burn quite a few cycles on nowadays CPU.
3683 * Let's delay the execution of the timer for a few ticks.
3689 if (tp->link_ok(ioaddr))
3692 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3694 tp->phy_reset_enable(tp);
3697 mod_timer(timer, jiffies + timeout);
3700 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3702 if (!test_and_set_bit(flag, tp->wk.flags))
3703 schedule_work(&tp->wk.work);
3706 static void rtl8169_phy_timer(unsigned long __opaque)
3708 struct net_device *dev = (struct net_device *)__opaque;
3709 struct rtl8169_private *tp = netdev_priv(dev);
3711 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3714 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3715 void __iomem *ioaddr)
3718 pci_release_regions(pdev);
3719 pci_clear_mwi(pdev);
3720 pci_disable_device(pdev);
3724 DECLARE_RTL_COND(rtl_phy_reset_cond)
3726 return tp->phy_reset_pending(tp);
3729 static void rtl8169_phy_reset(struct net_device *dev,
3730 struct rtl8169_private *tp)
3732 tp->phy_reset_enable(tp);
3733 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3736 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3738 void __iomem *ioaddr = tp->mmio_addr;
3740 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3741 (RTL_R8(PHYstatus) & TBI_Enable);
3744 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3746 void __iomem *ioaddr = tp->mmio_addr;
3748 rtl_hw_phy_config(dev);
3750 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3751 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3755 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3757 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3758 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3760 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3761 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3763 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3764 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3767 rtl8169_phy_reset(dev, tp);
3769 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3770 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3771 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3772 (tp->mii.supports_gmii ?
3773 ADVERTISED_1000baseT_Half |
3774 ADVERTISED_1000baseT_Full : 0));
3776 if (rtl_tbi_enabled(tp))
3777 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3780 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3782 void __iomem *ioaddr = tp->mmio_addr;
3786 RTL_W8(Cfg9346, Cfg9346_Unlock);
3788 RTL_W32(MAC4, addr[4] | addr[5] << 8);
3791 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3794 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3795 rtl_rar_exgmac_set(tp, addr);
3797 RTL_W8(Cfg9346, Cfg9346_Lock);
3799 rtl_unlock_work(tp);
3802 static int rtl_set_mac_address(struct net_device *dev, void *p)
3804 struct rtl8169_private *tp = netdev_priv(dev);
3805 struct sockaddr *addr = p;
3807 if (!is_valid_ether_addr(addr->sa_data))
3808 return -EADDRNOTAVAIL;
3810 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3812 rtl_rar_set(tp, dev->dev_addr);
3817 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3819 struct rtl8169_private *tp = netdev_priv(dev);
3820 struct mii_ioctl_data *data = if_mii(ifr);
3822 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3825 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3826 struct mii_ioctl_data *data, int cmd)
3830 data->phy_id = 32; /* Internal PHY */
3834 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3838 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3844 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3849 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3851 if (tp->features & RTL_FEATURE_MSI) {
3852 pci_disable_msi(pdev);
3853 tp->features &= ~RTL_FEATURE_MSI;
3857 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3859 struct mdio_ops *ops = &tp->mdio_ops;
3861 switch (tp->mac_version) {
3862 case RTL_GIGA_MAC_VER_27:
3863 ops->write = r8168dp_1_mdio_write;
3864 ops->read = r8168dp_1_mdio_read;
3866 case RTL_GIGA_MAC_VER_28:
3867 case RTL_GIGA_MAC_VER_31:
3868 ops->write = r8168dp_2_mdio_write;
3869 ops->read = r8168dp_2_mdio_read;
3871 case RTL_GIGA_MAC_VER_40:
3872 case RTL_GIGA_MAC_VER_41:
3873 case RTL_GIGA_MAC_VER_42:
3874 case RTL_GIGA_MAC_VER_43:
3875 case RTL_GIGA_MAC_VER_44:
3876 ops->write = r8168g_mdio_write;
3877 ops->read = r8168g_mdio_read;
3880 ops->write = r8169_mdio_write;
3881 ops->read = r8169_mdio_read;
3886 static void rtl_speed_down(struct rtl8169_private *tp)
3891 rtl_writephy(tp, 0x1f, 0x0000);
3892 lpa = rtl_readphy(tp, MII_LPA);
3894 if (lpa & (LPA_10HALF | LPA_10FULL))
3895 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3896 else if (lpa & (LPA_100HALF | LPA_100FULL))
3897 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3898 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3900 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3901 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3902 (tp->mii.supports_gmii ?
3903 ADVERTISED_1000baseT_Half |
3904 ADVERTISED_1000baseT_Full : 0);
3906 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3910 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3912 void __iomem *ioaddr = tp->mmio_addr;
3914 switch (tp->mac_version) {
3915 case RTL_GIGA_MAC_VER_25:
3916 case RTL_GIGA_MAC_VER_26:
3917 case RTL_GIGA_MAC_VER_29:
3918 case RTL_GIGA_MAC_VER_30:
3919 case RTL_GIGA_MAC_VER_32:
3920 case RTL_GIGA_MAC_VER_33:
3921 case RTL_GIGA_MAC_VER_34:
3922 case RTL_GIGA_MAC_VER_37:
3923 case RTL_GIGA_MAC_VER_38:
3924 case RTL_GIGA_MAC_VER_39:
3925 case RTL_GIGA_MAC_VER_40:
3926 case RTL_GIGA_MAC_VER_41:
3927 case RTL_GIGA_MAC_VER_42:
3928 case RTL_GIGA_MAC_VER_43:
3929 case RTL_GIGA_MAC_VER_44:
3930 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3931 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3938 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3940 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3944 rtl_wol_suspend_quirk(tp);
3949 static void r810x_phy_power_down(struct rtl8169_private *tp)
3951 rtl_writephy(tp, 0x1f, 0x0000);
3952 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3955 static void r810x_phy_power_up(struct rtl8169_private *tp)
3957 rtl_writephy(tp, 0x1f, 0x0000);
3958 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3961 static void r810x_pll_power_down(struct rtl8169_private *tp)
3963 void __iomem *ioaddr = tp->mmio_addr;
3965 if (rtl_wol_pll_power_down(tp))
3968 r810x_phy_power_down(tp);
3970 switch (tp->mac_version) {
3971 case RTL_GIGA_MAC_VER_07:
3972 case RTL_GIGA_MAC_VER_08:
3973 case RTL_GIGA_MAC_VER_09:
3974 case RTL_GIGA_MAC_VER_10:
3975 case RTL_GIGA_MAC_VER_13:
3976 case RTL_GIGA_MAC_VER_16:
3979 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3984 static void r810x_pll_power_up(struct rtl8169_private *tp)
3986 void __iomem *ioaddr = tp->mmio_addr;
3988 r810x_phy_power_up(tp);
3990 switch (tp->mac_version) {
3991 case RTL_GIGA_MAC_VER_07:
3992 case RTL_GIGA_MAC_VER_08:
3993 case RTL_GIGA_MAC_VER_09:
3994 case RTL_GIGA_MAC_VER_10:
3995 case RTL_GIGA_MAC_VER_13:
3996 case RTL_GIGA_MAC_VER_16:
3999 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4004 static void r8168_phy_power_up(struct rtl8169_private *tp)
4006 rtl_writephy(tp, 0x1f, 0x0000);
4007 switch (tp->mac_version) {
4008 case RTL_GIGA_MAC_VER_11:
4009 case RTL_GIGA_MAC_VER_12:
4010 case RTL_GIGA_MAC_VER_17:
4011 case RTL_GIGA_MAC_VER_18:
4012 case RTL_GIGA_MAC_VER_19:
4013 case RTL_GIGA_MAC_VER_20:
4014 case RTL_GIGA_MAC_VER_21:
4015 case RTL_GIGA_MAC_VER_22:
4016 case RTL_GIGA_MAC_VER_23:
4017 case RTL_GIGA_MAC_VER_24:
4018 case RTL_GIGA_MAC_VER_25:
4019 case RTL_GIGA_MAC_VER_26:
4020 case RTL_GIGA_MAC_VER_27:
4021 case RTL_GIGA_MAC_VER_28:
4022 case RTL_GIGA_MAC_VER_31:
4023 rtl_writephy(tp, 0x0e, 0x0000);
4028 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4031 static void r8168_phy_power_down(struct rtl8169_private *tp)
4033 rtl_writephy(tp, 0x1f, 0x0000);
4034 switch (tp->mac_version) {
4035 case RTL_GIGA_MAC_VER_32:
4036 case RTL_GIGA_MAC_VER_33:
4037 case RTL_GIGA_MAC_VER_40:
4038 case RTL_GIGA_MAC_VER_41:
4039 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4042 case RTL_GIGA_MAC_VER_11:
4043 case RTL_GIGA_MAC_VER_12:
4044 case RTL_GIGA_MAC_VER_17:
4045 case RTL_GIGA_MAC_VER_18:
4046 case RTL_GIGA_MAC_VER_19:
4047 case RTL_GIGA_MAC_VER_20:
4048 case RTL_GIGA_MAC_VER_21:
4049 case RTL_GIGA_MAC_VER_22:
4050 case RTL_GIGA_MAC_VER_23:
4051 case RTL_GIGA_MAC_VER_24:
4052 case RTL_GIGA_MAC_VER_25:
4053 case RTL_GIGA_MAC_VER_26:
4054 case RTL_GIGA_MAC_VER_27:
4055 case RTL_GIGA_MAC_VER_28:
4056 case RTL_GIGA_MAC_VER_31:
4057 rtl_writephy(tp, 0x0e, 0x0200);
4059 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4064 static void r8168_pll_power_down(struct rtl8169_private *tp)
4066 void __iomem *ioaddr = tp->mmio_addr;
4068 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4069 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4070 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4071 r8168dp_check_dash(tp)) {
4075 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4076 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4077 (RTL_R16(CPlusCmd) & ASF)) {
4081 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4082 tp->mac_version == RTL_GIGA_MAC_VER_33)
4083 rtl_ephy_write(tp, 0x19, 0xff64);
4085 if (rtl_wol_pll_power_down(tp))
4088 r8168_phy_power_down(tp);
4090 switch (tp->mac_version) {
4091 case RTL_GIGA_MAC_VER_25:
4092 case RTL_GIGA_MAC_VER_26:
4093 case RTL_GIGA_MAC_VER_27:
4094 case RTL_GIGA_MAC_VER_28:
4095 case RTL_GIGA_MAC_VER_31:
4096 case RTL_GIGA_MAC_VER_32:
4097 case RTL_GIGA_MAC_VER_33:
4098 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4100 case RTL_GIGA_MAC_VER_40:
4101 case RTL_GIGA_MAC_VER_41:
4102 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4103 0xfc000000, ERIAR_EXGMAC);
4108 static void r8168_pll_power_up(struct rtl8169_private *tp)
4110 void __iomem *ioaddr = tp->mmio_addr;
4112 switch (tp->mac_version) {
4113 case RTL_GIGA_MAC_VER_25:
4114 case RTL_GIGA_MAC_VER_26:
4115 case RTL_GIGA_MAC_VER_27:
4116 case RTL_GIGA_MAC_VER_28:
4117 case RTL_GIGA_MAC_VER_31:
4118 case RTL_GIGA_MAC_VER_32:
4119 case RTL_GIGA_MAC_VER_33:
4120 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4122 case RTL_GIGA_MAC_VER_40:
4123 case RTL_GIGA_MAC_VER_41:
4124 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4125 0x00000000, ERIAR_EXGMAC);
4129 r8168_phy_power_up(tp);
4132 static void rtl_generic_op(struct rtl8169_private *tp,
4133 void (*op)(struct rtl8169_private *))
4139 static void rtl_pll_power_down(struct rtl8169_private *tp)
4141 rtl_generic_op(tp, tp->pll_power_ops.down);
4144 static void rtl_pll_power_up(struct rtl8169_private *tp)
4146 rtl_generic_op(tp, tp->pll_power_ops.up);
4149 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4151 struct pll_power_ops *ops = &tp->pll_power_ops;
4153 switch (tp->mac_version) {
4154 case RTL_GIGA_MAC_VER_07:
4155 case RTL_GIGA_MAC_VER_08:
4156 case RTL_GIGA_MAC_VER_09:
4157 case RTL_GIGA_MAC_VER_10:
4158 case RTL_GIGA_MAC_VER_16:
4159 case RTL_GIGA_MAC_VER_29:
4160 case RTL_GIGA_MAC_VER_30:
4161 case RTL_GIGA_MAC_VER_37:
4162 case RTL_GIGA_MAC_VER_39:
4163 case RTL_GIGA_MAC_VER_43:
4164 ops->down = r810x_pll_power_down;
4165 ops->up = r810x_pll_power_up;
4168 case RTL_GIGA_MAC_VER_11:
4169 case RTL_GIGA_MAC_VER_12:
4170 case RTL_GIGA_MAC_VER_17:
4171 case RTL_GIGA_MAC_VER_18:
4172 case RTL_GIGA_MAC_VER_19:
4173 case RTL_GIGA_MAC_VER_20:
4174 case RTL_GIGA_MAC_VER_21:
4175 case RTL_GIGA_MAC_VER_22:
4176 case RTL_GIGA_MAC_VER_23:
4177 case RTL_GIGA_MAC_VER_24:
4178 case RTL_GIGA_MAC_VER_25:
4179 case RTL_GIGA_MAC_VER_26:
4180 case RTL_GIGA_MAC_VER_27:
4181 case RTL_GIGA_MAC_VER_28:
4182 case RTL_GIGA_MAC_VER_31:
4183 case RTL_GIGA_MAC_VER_32:
4184 case RTL_GIGA_MAC_VER_33:
4185 case RTL_GIGA_MAC_VER_34:
4186 case RTL_GIGA_MAC_VER_35:
4187 case RTL_GIGA_MAC_VER_36:
4188 case RTL_GIGA_MAC_VER_38:
4189 case RTL_GIGA_MAC_VER_40:
4190 case RTL_GIGA_MAC_VER_41:
4191 case RTL_GIGA_MAC_VER_42:
4192 case RTL_GIGA_MAC_VER_44:
4193 ops->down = r8168_pll_power_down;
4194 ops->up = r8168_pll_power_up;
4204 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4206 void __iomem *ioaddr = tp->mmio_addr;
4208 switch (tp->mac_version) {
4209 case RTL_GIGA_MAC_VER_01:
4210 case RTL_GIGA_MAC_VER_02:
4211 case RTL_GIGA_MAC_VER_03:
4212 case RTL_GIGA_MAC_VER_04:
4213 case RTL_GIGA_MAC_VER_05:
4214 case RTL_GIGA_MAC_VER_06:
4215 case RTL_GIGA_MAC_VER_10:
4216 case RTL_GIGA_MAC_VER_11:
4217 case RTL_GIGA_MAC_VER_12:
4218 case RTL_GIGA_MAC_VER_13:
4219 case RTL_GIGA_MAC_VER_14:
4220 case RTL_GIGA_MAC_VER_15:
4221 case RTL_GIGA_MAC_VER_16:
4222 case RTL_GIGA_MAC_VER_17:
4223 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4225 case RTL_GIGA_MAC_VER_18:
4226 case RTL_GIGA_MAC_VER_19:
4227 case RTL_GIGA_MAC_VER_20:
4228 case RTL_GIGA_MAC_VER_21:
4229 case RTL_GIGA_MAC_VER_22:
4230 case RTL_GIGA_MAC_VER_23:
4231 case RTL_GIGA_MAC_VER_24:
4232 case RTL_GIGA_MAC_VER_34:
4233 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4235 case RTL_GIGA_MAC_VER_40:
4236 case RTL_GIGA_MAC_VER_41:
4237 case RTL_GIGA_MAC_VER_42:
4238 case RTL_GIGA_MAC_VER_43:
4239 case RTL_GIGA_MAC_VER_44:
4240 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4243 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4248 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4250 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4253 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4255 void __iomem *ioaddr = tp->mmio_addr;
4257 RTL_W8(Cfg9346, Cfg9346_Unlock);
4258 rtl_generic_op(tp, tp->jumbo_ops.enable);
4259 RTL_W8(Cfg9346, Cfg9346_Lock);
4262 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4264 void __iomem *ioaddr = tp->mmio_addr;
4266 RTL_W8(Cfg9346, Cfg9346_Unlock);
4267 rtl_generic_op(tp, tp->jumbo_ops.disable);
4268 RTL_W8(Cfg9346, Cfg9346_Lock);
4271 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4273 void __iomem *ioaddr = tp->mmio_addr;
4275 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4276 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4277 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4280 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4282 void __iomem *ioaddr = tp->mmio_addr;
4284 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4285 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4286 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4289 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4291 void __iomem *ioaddr = tp->mmio_addr;
4293 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4296 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4298 void __iomem *ioaddr = tp->mmio_addr;
4300 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4303 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4305 void __iomem *ioaddr = tp->mmio_addr;
4307 RTL_W8(MaxTxPacketSize, 0x3f);
4308 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4309 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4310 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4313 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4315 void __iomem *ioaddr = tp->mmio_addr;
4317 RTL_W8(MaxTxPacketSize, 0x0c);
4318 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4319 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4320 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4323 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4325 rtl_tx_performance_tweak(tp->pci_dev,
4326 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4329 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4331 rtl_tx_performance_tweak(tp->pci_dev,
4332 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4335 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4337 void __iomem *ioaddr = tp->mmio_addr;
4339 r8168b_0_hw_jumbo_enable(tp);
4341 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4344 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4346 void __iomem *ioaddr = tp->mmio_addr;
4348 r8168b_0_hw_jumbo_disable(tp);
4350 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4353 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4355 struct jumbo_ops *ops = &tp->jumbo_ops;
4357 switch (tp->mac_version) {
4358 case RTL_GIGA_MAC_VER_11:
4359 ops->disable = r8168b_0_hw_jumbo_disable;
4360 ops->enable = r8168b_0_hw_jumbo_enable;
4362 case RTL_GIGA_MAC_VER_12:
4363 case RTL_GIGA_MAC_VER_17:
4364 ops->disable = r8168b_1_hw_jumbo_disable;
4365 ops->enable = r8168b_1_hw_jumbo_enable;
4367 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4368 case RTL_GIGA_MAC_VER_19:
4369 case RTL_GIGA_MAC_VER_20:
4370 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4371 case RTL_GIGA_MAC_VER_22:
4372 case RTL_GIGA_MAC_VER_23:
4373 case RTL_GIGA_MAC_VER_24:
4374 case RTL_GIGA_MAC_VER_25:
4375 case RTL_GIGA_MAC_VER_26:
4376 ops->disable = r8168c_hw_jumbo_disable;
4377 ops->enable = r8168c_hw_jumbo_enable;
4379 case RTL_GIGA_MAC_VER_27:
4380 case RTL_GIGA_MAC_VER_28:
4381 ops->disable = r8168dp_hw_jumbo_disable;
4382 ops->enable = r8168dp_hw_jumbo_enable;
4384 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4385 case RTL_GIGA_MAC_VER_32:
4386 case RTL_GIGA_MAC_VER_33:
4387 case RTL_GIGA_MAC_VER_34:
4388 ops->disable = r8168e_hw_jumbo_disable;
4389 ops->enable = r8168e_hw_jumbo_enable;
4393 * No action needed for jumbo frames with 8169.
4394 * No jumbo for 810x at all.
4396 case RTL_GIGA_MAC_VER_40:
4397 case RTL_GIGA_MAC_VER_41:
4398 case RTL_GIGA_MAC_VER_42:
4399 case RTL_GIGA_MAC_VER_43:
4400 case RTL_GIGA_MAC_VER_44:
4402 ops->disable = NULL;
4408 DECLARE_RTL_COND(rtl_chipcmd_cond)
4410 void __iomem *ioaddr = tp->mmio_addr;
4412 return RTL_R8(ChipCmd) & CmdReset;
4415 static void rtl_hw_reset(struct rtl8169_private *tp)
4417 void __iomem *ioaddr = tp->mmio_addr;
4419 RTL_W8(ChipCmd, CmdReset);
4421 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4424 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4426 struct rtl_fw *rtl_fw;
4430 name = rtl_lookup_firmware_name(tp);
4432 goto out_no_firmware;
4434 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4438 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4442 rc = rtl_check_firmware(tp, rtl_fw);
4444 goto err_release_firmware;
4446 tp->rtl_fw = rtl_fw;
4450 err_release_firmware:
4451 release_firmware(rtl_fw->fw);
4455 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4462 static void rtl_request_firmware(struct rtl8169_private *tp)
4464 if (IS_ERR(tp->rtl_fw))
4465 rtl_request_uncached_firmware(tp);
4468 static void rtl_rx_close(struct rtl8169_private *tp)
4470 void __iomem *ioaddr = tp->mmio_addr;
4472 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4475 DECLARE_RTL_COND(rtl_npq_cond)
4477 void __iomem *ioaddr = tp->mmio_addr;
4479 return RTL_R8(TxPoll) & NPQ;
4482 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4484 void __iomem *ioaddr = tp->mmio_addr;
4486 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4489 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4491 void __iomem *ioaddr = tp->mmio_addr;
4493 /* Disable interrupts */
4494 rtl8169_irq_mask_and_ack(tp);
4498 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4499 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4500 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4501 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4502 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4503 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4504 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4505 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4506 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4507 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4508 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4509 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4510 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4511 tp->mac_version == RTL_GIGA_MAC_VER_38) {
4512 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4513 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4515 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4522 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4524 void __iomem *ioaddr = tp->mmio_addr;
4526 /* Set DMA burst size and Interframe Gap Time */
4527 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4528 (InterFrameGap << TxInterFrameGapShift));
4531 static void rtl_hw_start(struct net_device *dev)
4533 struct rtl8169_private *tp = netdev_priv(dev);
4537 rtl_irq_enable_all(tp);
4540 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4541 void __iomem *ioaddr)
4544 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4545 * register to be written before TxDescAddrLow to work.
4546 * Switching from MMIO to I/O access fixes the issue as well.
4548 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4549 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4550 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4551 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4554 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4558 cmd = RTL_R16(CPlusCmd);
4559 RTL_W16(CPlusCmd, cmd);
4563 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4565 /* Low hurts. Let's disable the filtering. */
4566 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4569 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4571 static const struct rtl_cfg2_info {
4576 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4577 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4578 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4579 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4581 const struct rtl_cfg2_info *p = cfg2_info;
4585 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4586 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4587 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4588 RTL_W32(0x7c, p->val);
4594 static void rtl_set_rx_mode(struct net_device *dev)
4596 struct rtl8169_private *tp = netdev_priv(dev);
4597 void __iomem *ioaddr = tp->mmio_addr;
4598 u32 mc_filter[2]; /* Multicast hash filter */
4602 if (dev->flags & IFF_PROMISC) {
4603 /* Unconditionally log net taps. */
4604 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4606 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4608 mc_filter[1] = mc_filter[0] = 0xffffffff;
4609 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4610 (dev->flags & IFF_ALLMULTI)) {
4611 /* Too many to filter perfectly -- accept all multicasts. */
4612 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4613 mc_filter[1] = mc_filter[0] = 0xffffffff;
4615 struct netdev_hw_addr *ha;
4617 rx_mode = AcceptBroadcast | AcceptMyPhys;
4618 mc_filter[1] = mc_filter[0] = 0;
4619 netdev_for_each_mc_addr(ha, dev) {
4620 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4621 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4622 rx_mode |= AcceptMulticast;
4626 if (dev->features & NETIF_F_RXALL)
4627 rx_mode |= (AcceptErr | AcceptRunt);
4629 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4631 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4632 u32 data = mc_filter[0];
4634 mc_filter[0] = swab32(mc_filter[1]);
4635 mc_filter[1] = swab32(data);
4638 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4639 mc_filter[1] = mc_filter[0] = 0xffffffff;
4641 RTL_W32(MAR0 + 4, mc_filter[1]);
4642 RTL_W32(MAR0 + 0, mc_filter[0]);
4644 RTL_W32(RxConfig, tmp);
4647 static void rtl_hw_start_8169(struct net_device *dev)
4649 struct rtl8169_private *tp = netdev_priv(dev);
4650 void __iomem *ioaddr = tp->mmio_addr;
4651 struct pci_dev *pdev = tp->pci_dev;
4653 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4654 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4655 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4658 RTL_W8(Cfg9346, Cfg9346_Unlock);
4659 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4660 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4661 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4662 tp->mac_version == RTL_GIGA_MAC_VER_04)
4663 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4667 RTL_W8(EarlyTxThres, NoEarlyTx);
4669 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4671 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4672 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4673 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4674 tp->mac_version == RTL_GIGA_MAC_VER_04)
4675 rtl_set_rx_tx_config_registers(tp);
4677 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4679 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4680 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4681 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4682 "Bit-3 and bit-14 MUST be 1\n");
4683 tp->cp_cmd |= (1 << 14);
4686 RTL_W16(CPlusCmd, tp->cp_cmd);
4688 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4691 * Undocumented corner. Supposedly:
4692 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4694 RTL_W16(IntrMitigate, 0x0000);
4696 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4698 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4699 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4700 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4701 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4702 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4703 rtl_set_rx_tx_config_registers(tp);
4706 RTL_W8(Cfg9346, Cfg9346_Lock);
4708 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4711 RTL_W32(RxMissed, 0);
4713 rtl_set_rx_mode(dev);
4715 /* no early-rx interrupts */
4716 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4719 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4721 if (tp->csi_ops.write)
4722 tp->csi_ops.write(tp, addr, value);
4725 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4727 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4730 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4734 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4735 rtl_csi_write(tp, 0x070c, csi | bits);
4738 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4740 rtl_csi_access_enable(tp, 0x17000000);
4743 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4745 rtl_csi_access_enable(tp, 0x27000000);
4748 DECLARE_RTL_COND(rtl_csiar_cond)
4750 void __iomem *ioaddr = tp->mmio_addr;
4752 return RTL_R32(CSIAR) & CSIAR_FLAG;
4755 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4757 void __iomem *ioaddr = tp->mmio_addr;
4759 RTL_W32(CSIDR, value);
4760 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4761 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4763 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4766 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4768 void __iomem *ioaddr = tp->mmio_addr;
4770 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4771 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4773 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4774 RTL_R32(CSIDR) : ~0;
4777 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4779 void __iomem *ioaddr = tp->mmio_addr;
4781 RTL_W32(CSIDR, value);
4782 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4783 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4786 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4789 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4791 void __iomem *ioaddr = tp->mmio_addr;
4793 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4794 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4796 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4797 RTL_R32(CSIDR) : ~0;
4800 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4802 void __iomem *ioaddr = tp->mmio_addr;
4804 RTL_W32(CSIDR, value);
4805 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4806 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4809 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4812 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4814 void __iomem *ioaddr = tp->mmio_addr;
4816 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4817 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4819 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4820 RTL_R32(CSIDR) : ~0;
4823 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4825 struct csi_ops *ops = &tp->csi_ops;
4827 switch (tp->mac_version) {
4828 case RTL_GIGA_MAC_VER_01:
4829 case RTL_GIGA_MAC_VER_02:
4830 case RTL_GIGA_MAC_VER_03:
4831 case RTL_GIGA_MAC_VER_04:
4832 case RTL_GIGA_MAC_VER_05:
4833 case RTL_GIGA_MAC_VER_06:
4834 case RTL_GIGA_MAC_VER_10:
4835 case RTL_GIGA_MAC_VER_11:
4836 case RTL_GIGA_MAC_VER_12:
4837 case RTL_GIGA_MAC_VER_13:
4838 case RTL_GIGA_MAC_VER_14:
4839 case RTL_GIGA_MAC_VER_15:
4840 case RTL_GIGA_MAC_VER_16:
4841 case RTL_GIGA_MAC_VER_17:
4846 case RTL_GIGA_MAC_VER_37:
4847 case RTL_GIGA_MAC_VER_38:
4848 ops->write = r8402_csi_write;
4849 ops->read = r8402_csi_read;
4852 case RTL_GIGA_MAC_VER_44:
4853 ops->write = r8411_csi_write;
4854 ops->read = r8411_csi_read;
4858 ops->write = r8169_csi_write;
4859 ops->read = r8169_csi_read;
4865 unsigned int offset;
4870 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4876 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4877 rtl_ephy_write(tp, e->offset, w);
4882 static void rtl_disable_clock_request(struct pci_dev *pdev)
4884 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4885 PCI_EXP_LNKCTL_CLKREQ_EN);
4888 static void rtl_enable_clock_request(struct pci_dev *pdev)
4890 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4891 PCI_EXP_LNKCTL_CLKREQ_EN);
4894 #define R8168_CPCMD_QUIRK_MASK (\
4905 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4907 void __iomem *ioaddr = tp->mmio_addr;
4908 struct pci_dev *pdev = tp->pci_dev;
4910 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4912 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4914 if (tp->dev->mtu <= ETH_DATA_LEN) {
4915 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4916 PCI_EXP_DEVCTL_NOSNOOP_EN);
4920 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4922 void __iomem *ioaddr = tp->mmio_addr;
4924 rtl_hw_start_8168bb(tp);
4926 RTL_W8(MaxTxPacketSize, TxPacketMax);
4928 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4931 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4933 void __iomem *ioaddr = tp->mmio_addr;
4934 struct pci_dev *pdev = tp->pci_dev;
4936 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4938 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4940 if (tp->dev->mtu <= ETH_DATA_LEN)
4941 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4943 rtl_disable_clock_request(pdev);
4945 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4948 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4950 static const struct ephy_info e_info_8168cp[] = {
4951 { 0x01, 0, 0x0001 },
4952 { 0x02, 0x0800, 0x1000 },
4953 { 0x03, 0, 0x0042 },
4954 { 0x06, 0x0080, 0x0000 },
4958 rtl_csi_access_enable_2(tp);
4960 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4962 __rtl_hw_start_8168cp(tp);
4965 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4967 void __iomem *ioaddr = tp->mmio_addr;
4968 struct pci_dev *pdev = tp->pci_dev;
4970 rtl_csi_access_enable_2(tp);
4972 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4974 if (tp->dev->mtu <= ETH_DATA_LEN)
4975 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4977 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4980 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4982 void __iomem *ioaddr = tp->mmio_addr;
4983 struct pci_dev *pdev = tp->pci_dev;
4985 rtl_csi_access_enable_2(tp);
4987 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4990 RTL_W8(DBG_REG, 0x20);
4992 RTL_W8(MaxTxPacketSize, TxPacketMax);
4994 if (tp->dev->mtu <= ETH_DATA_LEN)
4995 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4997 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5000 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5002 void __iomem *ioaddr = tp->mmio_addr;
5003 static const struct ephy_info e_info_8168c_1[] = {
5004 { 0x02, 0x0800, 0x1000 },
5005 { 0x03, 0, 0x0002 },
5006 { 0x06, 0x0080, 0x0000 }
5009 rtl_csi_access_enable_2(tp);
5011 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5013 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5015 __rtl_hw_start_8168cp(tp);
5018 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5020 static const struct ephy_info e_info_8168c_2[] = {
5021 { 0x01, 0, 0x0001 },
5022 { 0x03, 0x0400, 0x0220 }
5025 rtl_csi_access_enable_2(tp);
5027 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5029 __rtl_hw_start_8168cp(tp);
5032 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5034 rtl_hw_start_8168c_2(tp);
5037 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5039 rtl_csi_access_enable_2(tp);
5041 __rtl_hw_start_8168cp(tp);
5044 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5046 void __iomem *ioaddr = tp->mmio_addr;
5047 struct pci_dev *pdev = tp->pci_dev;
5049 rtl_csi_access_enable_2(tp);
5051 rtl_disable_clock_request(pdev);
5053 RTL_W8(MaxTxPacketSize, TxPacketMax);
5055 if (tp->dev->mtu <= ETH_DATA_LEN)
5056 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5058 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5061 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5063 void __iomem *ioaddr = tp->mmio_addr;
5064 struct pci_dev *pdev = tp->pci_dev;
5066 rtl_csi_access_enable_1(tp);
5068 if (tp->dev->mtu <= ETH_DATA_LEN)
5069 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5071 RTL_W8(MaxTxPacketSize, TxPacketMax);
5073 rtl_disable_clock_request(pdev);
5076 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5078 void __iomem *ioaddr = tp->mmio_addr;
5079 struct pci_dev *pdev = tp->pci_dev;
5080 static const struct ephy_info e_info_8168d_4[] = {
5082 { 0x19, 0x20, 0x50 },
5087 rtl_csi_access_enable_1(tp);
5089 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5091 RTL_W8(MaxTxPacketSize, TxPacketMax);
5093 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5094 const struct ephy_info *e = e_info_8168d_4 + i;
5097 w = rtl_ephy_read(tp, e->offset);
5098 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5101 rtl_enable_clock_request(pdev);
5104 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5106 void __iomem *ioaddr = tp->mmio_addr;
5107 struct pci_dev *pdev = tp->pci_dev;
5108 static const struct ephy_info e_info_8168e_1[] = {
5109 { 0x00, 0x0200, 0x0100 },
5110 { 0x00, 0x0000, 0x0004 },
5111 { 0x06, 0x0002, 0x0001 },
5112 { 0x06, 0x0000, 0x0030 },
5113 { 0x07, 0x0000, 0x2000 },
5114 { 0x00, 0x0000, 0x0020 },
5115 { 0x03, 0x5800, 0x2000 },
5116 { 0x03, 0x0000, 0x0001 },
5117 { 0x01, 0x0800, 0x1000 },
5118 { 0x07, 0x0000, 0x4000 },
5119 { 0x1e, 0x0000, 0x2000 },
5120 { 0x19, 0xffff, 0xfe6c },
5121 { 0x0a, 0x0000, 0x0040 }
5124 rtl_csi_access_enable_2(tp);
5126 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5128 if (tp->dev->mtu <= ETH_DATA_LEN)
5129 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5131 RTL_W8(MaxTxPacketSize, TxPacketMax);
5133 rtl_disable_clock_request(pdev);
5135 /* Reset tx FIFO pointer */
5136 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5137 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5139 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5142 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5144 void __iomem *ioaddr = tp->mmio_addr;
5145 struct pci_dev *pdev = tp->pci_dev;
5146 static const struct ephy_info e_info_8168e_2[] = {
5147 { 0x09, 0x0000, 0x0080 },
5148 { 0x19, 0x0000, 0x0224 }
5151 rtl_csi_access_enable_1(tp);
5153 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5155 if (tp->dev->mtu <= ETH_DATA_LEN)
5156 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5158 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5159 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5160 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5162 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5163 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5164 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5165 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5167 RTL_W8(MaxTxPacketSize, EarlySize);
5169 rtl_disable_clock_request(pdev);
5171 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5172 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5174 /* Adjust EEE LED frequency */
5175 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5177 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5178 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5179 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5182 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5184 void __iomem *ioaddr = tp->mmio_addr;
5185 struct pci_dev *pdev = tp->pci_dev;
5187 rtl_csi_access_enable_2(tp);
5189 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5191 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5192 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5193 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5194 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5195 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5196 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5197 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5198 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5199 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5200 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5202 RTL_W8(MaxTxPacketSize, EarlySize);
5204 rtl_disable_clock_request(pdev);
5206 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5207 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5208 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5209 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5210 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5213 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5215 void __iomem *ioaddr = tp->mmio_addr;
5216 static const struct ephy_info e_info_8168f_1[] = {
5217 { 0x06, 0x00c0, 0x0020 },
5218 { 0x08, 0x0001, 0x0002 },
5219 { 0x09, 0x0000, 0x0080 },
5220 { 0x19, 0x0000, 0x0224 }
5223 rtl_hw_start_8168f(tp);
5225 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5227 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5229 /* Adjust EEE LED frequency */
5230 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5233 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5235 static const struct ephy_info e_info_8168f_1[] = {
5236 { 0x06, 0x00c0, 0x0020 },
5237 { 0x0f, 0xffff, 0x5200 },
5238 { 0x1e, 0x0000, 0x4000 },
5239 { 0x19, 0x0000, 0x0224 }
5242 rtl_hw_start_8168f(tp);
5244 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5246 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5249 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5251 void __iomem *ioaddr = tp->mmio_addr;
5252 struct pci_dev *pdev = tp->pci_dev;
5254 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5256 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5257 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5258 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5259 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5261 rtl_csi_access_enable_1(tp);
5263 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5265 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5266 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5267 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5269 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5270 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5271 RTL_W8(MaxTxPacketSize, EarlySize);
5273 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5274 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5276 /* Adjust EEE LED frequency */
5277 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5279 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5280 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5283 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5285 void __iomem *ioaddr = tp->mmio_addr;
5286 static const struct ephy_info e_info_8168g_2[] = {
5287 { 0x00, 0x0000, 0x0008 },
5288 { 0x0c, 0x3df0, 0x0200 },
5289 { 0x19, 0xffff, 0xfc00 },
5290 { 0x1e, 0xffff, 0x20eb }
5293 rtl_hw_start_8168g_1(tp);
5295 /* disable aspm and clock request before access ephy */
5296 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5297 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5298 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5301 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5303 void __iomem *ioaddr = tp->mmio_addr;
5304 static const struct ephy_info e_info_8411_2[] = {
5305 { 0x00, 0x0000, 0x0008 },
5306 { 0x0c, 0x3df0, 0x0200 },
5307 { 0x0f, 0xffff, 0x5200 },
5308 { 0x19, 0x0020, 0x0000 },
5309 { 0x1e, 0x0000, 0x2000 }
5312 rtl_hw_start_8168g_1(tp);
5314 /* disable aspm and clock request before access ephy */
5315 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5316 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5317 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5320 static void rtl_hw_start_8168(struct net_device *dev)
5322 struct rtl8169_private *tp = netdev_priv(dev);
5323 void __iomem *ioaddr = tp->mmio_addr;
5325 RTL_W8(Cfg9346, Cfg9346_Unlock);
5327 RTL_W8(MaxTxPacketSize, TxPacketMax);
5329 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5331 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5333 RTL_W16(CPlusCmd, tp->cp_cmd);
5335 RTL_W16(IntrMitigate, 0x5151);
5337 /* Work around for RxFIFO overflow. */
5338 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5339 tp->event_slow |= RxFIFOOver | PCSTimeout;
5340 tp->event_slow &= ~RxOverflow;
5343 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5345 rtl_set_rx_tx_config_registers(tp);
5349 switch (tp->mac_version) {
5350 case RTL_GIGA_MAC_VER_11:
5351 rtl_hw_start_8168bb(tp);
5354 case RTL_GIGA_MAC_VER_12:
5355 case RTL_GIGA_MAC_VER_17:
5356 rtl_hw_start_8168bef(tp);
5359 case RTL_GIGA_MAC_VER_18:
5360 rtl_hw_start_8168cp_1(tp);
5363 case RTL_GIGA_MAC_VER_19:
5364 rtl_hw_start_8168c_1(tp);
5367 case RTL_GIGA_MAC_VER_20:
5368 rtl_hw_start_8168c_2(tp);
5371 case RTL_GIGA_MAC_VER_21:
5372 rtl_hw_start_8168c_3(tp);
5375 case RTL_GIGA_MAC_VER_22:
5376 rtl_hw_start_8168c_4(tp);
5379 case RTL_GIGA_MAC_VER_23:
5380 rtl_hw_start_8168cp_2(tp);
5383 case RTL_GIGA_MAC_VER_24:
5384 rtl_hw_start_8168cp_3(tp);
5387 case RTL_GIGA_MAC_VER_25:
5388 case RTL_GIGA_MAC_VER_26:
5389 case RTL_GIGA_MAC_VER_27:
5390 rtl_hw_start_8168d(tp);
5393 case RTL_GIGA_MAC_VER_28:
5394 rtl_hw_start_8168d_4(tp);
5397 case RTL_GIGA_MAC_VER_31:
5398 rtl_hw_start_8168dp(tp);
5401 case RTL_GIGA_MAC_VER_32:
5402 case RTL_GIGA_MAC_VER_33:
5403 rtl_hw_start_8168e_1(tp);
5405 case RTL_GIGA_MAC_VER_34:
5406 rtl_hw_start_8168e_2(tp);
5409 case RTL_GIGA_MAC_VER_35:
5410 case RTL_GIGA_MAC_VER_36:
5411 rtl_hw_start_8168f_1(tp);
5414 case RTL_GIGA_MAC_VER_38:
5415 rtl_hw_start_8411(tp);
5418 case RTL_GIGA_MAC_VER_40:
5419 case RTL_GIGA_MAC_VER_41:
5420 rtl_hw_start_8168g_1(tp);
5422 case RTL_GIGA_MAC_VER_42:
5423 rtl_hw_start_8168g_2(tp);
5426 case RTL_GIGA_MAC_VER_44:
5427 rtl_hw_start_8411_2(tp);
5431 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5432 dev->name, tp->mac_version);
5436 RTL_W8(Cfg9346, Cfg9346_Lock);
5438 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5440 rtl_set_rx_mode(dev);
5442 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5445 #define R810X_CPCMD_QUIRK_MASK (\
5456 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5458 void __iomem *ioaddr = tp->mmio_addr;
5459 struct pci_dev *pdev = tp->pci_dev;
5460 static const struct ephy_info e_info_8102e_1[] = {
5461 { 0x01, 0, 0x6e65 },
5462 { 0x02, 0, 0x091f },
5463 { 0x03, 0, 0xc2f9 },
5464 { 0x06, 0, 0xafb5 },
5465 { 0x07, 0, 0x0e00 },
5466 { 0x19, 0, 0xec80 },
5467 { 0x01, 0, 0x2e65 },
5472 rtl_csi_access_enable_2(tp);
5474 RTL_W8(DBG_REG, FIX_NAK_1);
5476 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5479 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5480 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5482 cfg1 = RTL_R8(Config1);
5483 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5484 RTL_W8(Config1, cfg1 & ~LEDS0);
5486 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5489 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5491 void __iomem *ioaddr = tp->mmio_addr;
5492 struct pci_dev *pdev = tp->pci_dev;
5494 rtl_csi_access_enable_2(tp);
5496 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5498 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5499 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5502 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5504 rtl_hw_start_8102e_2(tp);
5506 rtl_ephy_write(tp, 0x03, 0xc2f9);
5509 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5511 void __iomem *ioaddr = tp->mmio_addr;
5512 static const struct ephy_info e_info_8105e_1[] = {
5513 { 0x07, 0, 0x4000 },
5514 { 0x19, 0, 0x0200 },
5515 { 0x19, 0, 0x0020 },
5516 { 0x1e, 0, 0x2000 },
5517 { 0x03, 0, 0x0001 },
5518 { 0x19, 0, 0x0100 },
5519 { 0x19, 0, 0x0004 },
5523 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5524 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5526 /* Disable Early Tally Counter */
5527 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5529 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5530 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5532 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5535 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5537 rtl_hw_start_8105e_1(tp);
5538 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5541 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5543 void __iomem *ioaddr = tp->mmio_addr;
5544 static const struct ephy_info e_info_8402[] = {
5545 { 0x19, 0xffff, 0xff64 },
5549 rtl_csi_access_enable_2(tp);
5551 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5552 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5554 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5555 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5557 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5559 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5561 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5562 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5563 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5564 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5565 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5566 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5567 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5570 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5572 void __iomem *ioaddr = tp->mmio_addr;
5574 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5575 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5577 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5578 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5579 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5582 static void rtl_hw_start_8101(struct net_device *dev)
5584 struct rtl8169_private *tp = netdev_priv(dev);
5585 void __iomem *ioaddr = tp->mmio_addr;
5586 struct pci_dev *pdev = tp->pci_dev;
5588 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5589 tp->event_slow &= ~RxFIFOOver;
5591 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5592 tp->mac_version == RTL_GIGA_MAC_VER_16)
5593 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5594 PCI_EXP_DEVCTL_NOSNOOP_EN);
5596 RTL_W8(Cfg9346, Cfg9346_Unlock);
5598 RTL_W8(MaxTxPacketSize, TxPacketMax);
5600 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5602 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5603 RTL_W16(CPlusCmd, tp->cp_cmd);
5605 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5607 rtl_set_rx_tx_config_registers(tp);
5609 switch (tp->mac_version) {
5610 case RTL_GIGA_MAC_VER_07:
5611 rtl_hw_start_8102e_1(tp);
5614 case RTL_GIGA_MAC_VER_08:
5615 rtl_hw_start_8102e_3(tp);
5618 case RTL_GIGA_MAC_VER_09:
5619 rtl_hw_start_8102e_2(tp);
5622 case RTL_GIGA_MAC_VER_29:
5623 rtl_hw_start_8105e_1(tp);
5625 case RTL_GIGA_MAC_VER_30:
5626 rtl_hw_start_8105e_2(tp);
5629 case RTL_GIGA_MAC_VER_37:
5630 rtl_hw_start_8402(tp);
5633 case RTL_GIGA_MAC_VER_39:
5634 rtl_hw_start_8106(tp);
5636 case RTL_GIGA_MAC_VER_43:
5637 rtl_hw_start_8168g_2(tp);
5641 RTL_W8(Cfg9346, Cfg9346_Lock);
5643 RTL_W16(IntrMitigate, 0x0000);
5645 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5647 rtl_set_rx_mode(dev);
5651 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5654 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5656 struct rtl8169_private *tp = netdev_priv(dev);
5658 if (new_mtu < ETH_ZLEN ||
5659 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5662 if (new_mtu > ETH_DATA_LEN)
5663 rtl_hw_jumbo_enable(tp);
5665 rtl_hw_jumbo_disable(tp);
5668 netdev_update_features(dev);
5673 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5675 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5676 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5679 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5680 void **data_buff, struct RxDesc *desc)
5682 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5687 rtl8169_make_unusable_by_asic(desc);
5690 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5692 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5694 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5697 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5700 desc->addr = cpu_to_le64(mapping);
5702 rtl8169_mark_to_asic(desc, rx_buf_sz);
5705 static inline void *rtl8169_align(void *data)
5707 return (void *)ALIGN((long)data, 16);
5710 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5711 struct RxDesc *desc)
5715 struct device *d = &tp->pci_dev->dev;
5716 struct net_device *dev = tp->dev;
5717 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5719 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5723 if (rtl8169_align(data) != data) {
5725 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5730 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5732 if (unlikely(dma_mapping_error(d, mapping))) {
5733 if (net_ratelimit())
5734 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5738 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5746 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5750 for (i = 0; i < NUM_RX_DESC; i++) {
5751 if (tp->Rx_databuff[i]) {
5752 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5753 tp->RxDescArray + i);
5758 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5760 desc->opts1 |= cpu_to_le32(RingEnd);
5763 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5767 for (i = 0; i < NUM_RX_DESC; i++) {
5770 if (tp->Rx_databuff[i])
5773 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5775 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5778 tp->Rx_databuff[i] = data;
5781 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5785 rtl8169_rx_clear(tp);
5789 static int rtl8169_init_ring(struct net_device *dev)
5791 struct rtl8169_private *tp = netdev_priv(dev);
5793 rtl8169_init_ring_indexes(tp);
5795 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5796 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5798 return rtl8169_rx_fill(tp);
5801 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5802 struct TxDesc *desc)
5804 unsigned int len = tx_skb->len;
5806 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5814 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5819 for (i = 0; i < n; i++) {
5820 unsigned int entry = (start + i) % NUM_TX_DESC;
5821 struct ring_info *tx_skb = tp->tx_skb + entry;
5822 unsigned int len = tx_skb->len;
5825 struct sk_buff *skb = tx_skb->skb;
5827 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5828 tp->TxDescArray + entry);
5830 tp->dev->stats.tx_dropped++;
5838 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5840 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5841 tp->cur_tx = tp->dirty_tx = 0;
5844 static void rtl_reset_work(struct rtl8169_private *tp)
5846 struct net_device *dev = tp->dev;
5849 napi_disable(&tp->napi);
5850 netif_stop_queue(dev);
5851 synchronize_sched();
5853 rtl8169_hw_reset(tp);
5855 for (i = 0; i < NUM_RX_DESC; i++)
5856 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5858 rtl8169_tx_clear(tp);
5859 rtl8169_init_ring_indexes(tp);
5861 napi_enable(&tp->napi);
5863 netif_wake_queue(dev);
5864 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5867 static void rtl8169_tx_timeout(struct net_device *dev)
5869 struct rtl8169_private *tp = netdev_priv(dev);
5871 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5874 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5877 struct skb_shared_info *info = skb_shinfo(skb);
5878 unsigned int cur_frag, entry;
5879 struct TxDesc * uninitialized_var(txd);
5880 struct device *d = &tp->pci_dev->dev;
5883 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5884 const skb_frag_t *frag = info->frags + cur_frag;
5889 entry = (entry + 1) % NUM_TX_DESC;
5891 txd = tp->TxDescArray + entry;
5892 len = skb_frag_size(frag);
5893 addr = skb_frag_address(frag);
5894 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5895 if (unlikely(dma_mapping_error(d, mapping))) {
5896 if (net_ratelimit())
5897 netif_err(tp, drv, tp->dev,
5898 "Failed to map TX fragments DMA!\n");
5902 /* Anti gcc 2.95.3 bugware (sic) */
5903 status = opts[0] | len |
5904 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5906 txd->opts1 = cpu_to_le32(status);
5907 txd->opts2 = cpu_to_le32(opts[1]);
5908 txd->addr = cpu_to_le64(mapping);
5910 tp->tx_skb[entry].len = len;
5914 tp->tx_skb[entry].skb = skb;
5915 txd->opts1 |= cpu_to_le32(LastFrag);
5921 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5925 static bool rtl_skb_pad(struct sk_buff *skb)
5927 if (skb_padto(skb, ETH_ZLEN))
5929 skb_put(skb, ETH_ZLEN - skb->len);
5933 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5935 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5938 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5939 struct sk_buff *skb, u32 *opts)
5941 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5942 u32 mss = skb_shinfo(skb)->gso_size;
5943 int offset = info->opts_offset;
5947 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5948 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5949 const struct iphdr *ip = ip_hdr(skb);
5951 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5952 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5954 if (ip->protocol == IPPROTO_TCP)
5955 opts[offset] |= info->checksum.tcp;
5956 else if (ip->protocol == IPPROTO_UDP)
5957 opts[offset] |= info->checksum.udp;
5961 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5962 return rtl_skb_pad(skb);
5967 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5968 struct net_device *dev)
5970 struct rtl8169_private *tp = netdev_priv(dev);
5971 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5972 struct TxDesc *txd = tp->TxDescArray + entry;
5973 void __iomem *ioaddr = tp->mmio_addr;
5974 struct device *d = &tp->pci_dev->dev;
5980 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5981 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5985 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5988 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5991 if (!rtl8169_tso_csum(tp, skb, opts))
5992 goto err_update_stats;
5994 len = skb_headlen(skb);
5995 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5996 if (unlikely(dma_mapping_error(d, mapping))) {
5997 if (net_ratelimit())
5998 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6002 tp->tx_skb[entry].len = len;
6003 txd->addr = cpu_to_le64(mapping);
6005 frags = rtl8169_xmit_frags(tp, skb, opts);
6009 opts[0] |= FirstFrag;
6011 opts[0] |= FirstFrag | LastFrag;
6012 tp->tx_skb[entry].skb = skb;
6015 txd->opts2 = cpu_to_le32(opts[1]);
6017 skb_tx_timestamp(skb);
6021 /* Anti gcc 2.95.3 bugware (sic) */
6022 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6023 txd->opts1 = cpu_to_le32(status);
6025 tp->cur_tx += frags + 1;
6029 RTL_W8(TxPoll, NPQ);
6033 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6034 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6035 * not miss a ring update when it notices a stopped queue.
6038 netif_stop_queue(dev);
6039 /* Sync with rtl_tx:
6040 * - publish queue status and cur_tx ring index (write barrier)
6041 * - refresh dirty_tx ring index (read barrier).
6042 * May the current thread have a pessimistic view of the ring
6043 * status and forget to wake up queue, a racing rtl_tx thread
6047 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6048 netif_wake_queue(dev);
6051 return NETDEV_TX_OK;
6054 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6058 dev->stats.tx_dropped++;
6059 return NETDEV_TX_OK;
6062 netif_stop_queue(dev);
6063 dev->stats.tx_dropped++;
6064 return NETDEV_TX_BUSY;
6067 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6069 struct rtl8169_private *tp = netdev_priv(dev);
6070 struct pci_dev *pdev = tp->pci_dev;
6071 u16 pci_status, pci_cmd;
6073 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6074 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6076 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6077 pci_cmd, pci_status);
6080 * The recovery sequence below admits a very elaborated explanation:
6081 * - it seems to work;
6082 * - I did not see what else could be done;
6083 * - it makes iop3xx happy.
6085 * Feel free to adjust to your needs.
6087 if (pdev->broken_parity_status)
6088 pci_cmd &= ~PCI_COMMAND_PARITY;
6090 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6092 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6094 pci_write_config_word(pdev, PCI_STATUS,
6095 pci_status & (PCI_STATUS_DETECTED_PARITY |
6096 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6097 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6099 /* The infamous DAC f*ckup only happens at boot time */
6100 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6101 void __iomem *ioaddr = tp->mmio_addr;
6103 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6104 tp->cp_cmd &= ~PCIDAC;
6105 RTL_W16(CPlusCmd, tp->cp_cmd);
6106 dev->features &= ~NETIF_F_HIGHDMA;
6109 rtl8169_hw_reset(tp);
6111 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6114 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6116 unsigned int dirty_tx, tx_left;
6118 dirty_tx = tp->dirty_tx;
6120 tx_left = tp->cur_tx - dirty_tx;
6122 while (tx_left > 0) {
6123 unsigned int entry = dirty_tx % NUM_TX_DESC;
6124 struct ring_info *tx_skb = tp->tx_skb + entry;
6128 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6129 if (status & DescOwn)
6132 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6133 tp->TxDescArray + entry);
6134 if (status & LastFrag) {
6135 u64_stats_update_begin(&tp->tx_stats.syncp);
6136 tp->tx_stats.packets++;
6137 tp->tx_stats.bytes += tx_skb->skb->len;
6138 u64_stats_update_end(&tp->tx_stats.syncp);
6139 dev_kfree_skb(tx_skb->skb);
6146 if (tp->dirty_tx != dirty_tx) {
6147 tp->dirty_tx = dirty_tx;
6148 /* Sync with rtl8169_start_xmit:
6149 * - publish dirty_tx ring index (write barrier)
6150 * - refresh cur_tx ring index and queue status (read barrier)
6151 * May the current thread miss the stopped queue condition,
6152 * a racing xmit thread can only have a right view of the
6156 if (netif_queue_stopped(dev) &&
6157 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6158 netif_wake_queue(dev);
6161 * 8168 hack: TxPoll requests are lost when the Tx packets are
6162 * too close. Let's kick an extra TxPoll request when a burst
6163 * of start_xmit activity is detected (if it is not detected,
6164 * it is slow enough). -- FR
6166 if (tp->cur_tx != dirty_tx) {
6167 void __iomem *ioaddr = tp->mmio_addr;
6169 RTL_W8(TxPoll, NPQ);
6174 static inline int rtl8169_fragmented_frame(u32 status)
6176 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6179 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6181 u32 status = opts1 & RxProtoMask;
6183 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6184 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6185 skb->ip_summed = CHECKSUM_UNNECESSARY;
6187 skb_checksum_none_assert(skb);
6190 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6191 struct rtl8169_private *tp,
6195 struct sk_buff *skb;
6196 struct device *d = &tp->pci_dev->dev;
6198 data = rtl8169_align(data);
6199 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6201 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6203 memcpy(skb->data, data, pkt_size);
6204 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6209 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6211 unsigned int cur_rx, rx_left;
6214 cur_rx = tp->cur_rx;
6216 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6217 unsigned int entry = cur_rx % NUM_RX_DESC;
6218 struct RxDesc *desc = tp->RxDescArray + entry;
6222 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6224 if (status & DescOwn)
6226 if (unlikely(status & RxRES)) {
6227 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6229 dev->stats.rx_errors++;
6230 if (status & (RxRWT | RxRUNT))
6231 dev->stats.rx_length_errors++;
6233 dev->stats.rx_crc_errors++;
6234 if (status & RxFOVF) {
6235 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6236 dev->stats.rx_fifo_errors++;
6238 if ((status & (RxRUNT | RxCRC)) &&
6239 !(status & (RxRWT | RxFOVF)) &&
6240 (dev->features & NETIF_F_RXALL))
6243 struct sk_buff *skb;
6248 addr = le64_to_cpu(desc->addr);
6249 if (likely(!(dev->features & NETIF_F_RXFCS)))
6250 pkt_size = (status & 0x00003fff) - 4;
6252 pkt_size = status & 0x00003fff;
6255 * The driver does not support incoming fragmented
6256 * frames. They are seen as a symptom of over-mtu
6259 if (unlikely(rtl8169_fragmented_frame(status))) {
6260 dev->stats.rx_dropped++;
6261 dev->stats.rx_length_errors++;
6262 goto release_descriptor;
6265 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6266 tp, pkt_size, addr);
6268 dev->stats.rx_dropped++;
6269 goto release_descriptor;
6272 rtl8169_rx_csum(skb, status);
6273 skb_put(skb, pkt_size);
6274 skb->protocol = eth_type_trans(skb, dev);
6276 rtl8169_rx_vlan_tag(desc, skb);
6278 napi_gro_receive(&tp->napi, skb);
6280 u64_stats_update_begin(&tp->rx_stats.syncp);
6281 tp->rx_stats.packets++;
6282 tp->rx_stats.bytes += pkt_size;
6283 u64_stats_update_end(&tp->rx_stats.syncp);
6288 rtl8169_mark_to_asic(desc, rx_buf_sz);
6291 count = cur_rx - tp->cur_rx;
6292 tp->cur_rx = cur_rx;
6297 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6299 struct net_device *dev = dev_instance;
6300 struct rtl8169_private *tp = netdev_priv(dev);
6304 status = rtl_get_events(tp);
6305 if (status && status != 0xffff) {
6306 status &= RTL_EVENT_NAPI | tp->event_slow;
6310 rtl_irq_disable(tp);
6311 napi_schedule(&tp->napi);
6314 return IRQ_RETVAL(handled);
6318 * Workqueue context.
6320 static void rtl_slow_event_work(struct rtl8169_private *tp)
6322 struct net_device *dev = tp->dev;
6325 status = rtl_get_events(tp) & tp->event_slow;
6326 rtl_ack_events(tp, status);
6328 if (unlikely(status & RxFIFOOver)) {
6329 switch (tp->mac_version) {
6330 /* Work around for rx fifo overflow */
6331 case RTL_GIGA_MAC_VER_11:
6332 netif_stop_queue(dev);
6333 /* XXX - Hack alert. See rtl_task(). */
6334 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6340 if (unlikely(status & SYSErr))
6341 rtl8169_pcierr_interrupt(dev);
6343 if (status & LinkChg)
6344 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6346 rtl_irq_enable_all(tp);
6349 static void rtl_task(struct work_struct *work)
6351 static const struct {
6353 void (*action)(struct rtl8169_private *);
6355 /* XXX - keep rtl_slow_event_work() as first element. */
6356 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6357 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6358 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6360 struct rtl8169_private *tp =
6361 container_of(work, struct rtl8169_private, wk.work);
6362 struct net_device *dev = tp->dev;
6367 if (!netif_running(dev) ||
6368 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6371 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6374 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6376 rtl_work[i].action(tp);
6380 rtl_unlock_work(tp);
6383 static int rtl8169_poll(struct napi_struct *napi, int budget)
6385 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6386 struct net_device *dev = tp->dev;
6387 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6391 status = rtl_get_events(tp);
6392 rtl_ack_events(tp, status & ~tp->event_slow);
6394 if (status & RTL_EVENT_NAPI_RX)
6395 work_done = rtl_rx(dev, tp, (u32) budget);
6397 if (status & RTL_EVENT_NAPI_TX)
6400 if (status & tp->event_slow) {
6401 enable_mask &= ~tp->event_slow;
6403 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6406 if (work_done < budget) {
6407 napi_complete(napi);
6409 rtl_irq_enable(tp, enable_mask);
6416 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6418 struct rtl8169_private *tp = netdev_priv(dev);
6420 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6423 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6424 RTL_W32(RxMissed, 0);
6427 static void rtl8169_down(struct net_device *dev)
6429 struct rtl8169_private *tp = netdev_priv(dev);
6430 void __iomem *ioaddr = tp->mmio_addr;
6432 del_timer_sync(&tp->timer);
6434 napi_disable(&tp->napi);
6435 netif_stop_queue(dev);
6437 rtl8169_hw_reset(tp);
6439 * At this point device interrupts can not be enabled in any function,
6440 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6441 * and napi is disabled (rtl8169_poll).
6443 rtl8169_rx_missed(dev, ioaddr);
6445 /* Give a racing hard_start_xmit a few cycles to complete. */
6446 synchronize_sched();
6448 rtl8169_tx_clear(tp);
6450 rtl8169_rx_clear(tp);
6452 rtl_pll_power_down(tp);
6455 static int rtl8169_close(struct net_device *dev)
6457 struct rtl8169_private *tp = netdev_priv(dev);
6458 struct pci_dev *pdev = tp->pci_dev;
6460 pm_runtime_get_sync(&pdev->dev);
6462 /* Update counters before going down */
6463 rtl8169_update_counters(dev);
6466 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6469 rtl_unlock_work(tp);
6471 free_irq(pdev->irq, dev);
6473 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6475 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6477 tp->TxDescArray = NULL;
6478 tp->RxDescArray = NULL;
6480 pm_runtime_put_sync(&pdev->dev);
6485 #ifdef CONFIG_NET_POLL_CONTROLLER
6486 static void rtl8169_netpoll(struct net_device *dev)
6488 struct rtl8169_private *tp = netdev_priv(dev);
6490 rtl8169_interrupt(tp->pci_dev->irq, dev);
6494 static int rtl_open(struct net_device *dev)
6496 struct rtl8169_private *tp = netdev_priv(dev);
6497 void __iomem *ioaddr = tp->mmio_addr;
6498 struct pci_dev *pdev = tp->pci_dev;
6499 int retval = -ENOMEM;
6501 pm_runtime_get_sync(&pdev->dev);
6504 * Rx and Tx descriptors needs 256 bytes alignment.
6505 * dma_alloc_coherent provides more.
6507 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6508 &tp->TxPhyAddr, GFP_KERNEL);
6509 if (!tp->TxDescArray)
6510 goto err_pm_runtime_put;
6512 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6513 &tp->RxPhyAddr, GFP_KERNEL);
6514 if (!tp->RxDescArray)
6517 retval = rtl8169_init_ring(dev);
6521 INIT_WORK(&tp->wk.work, rtl_task);
6525 rtl_request_firmware(tp);
6527 retval = request_irq(pdev->irq, rtl8169_interrupt,
6528 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6531 goto err_release_fw_2;
6535 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6537 napi_enable(&tp->napi);
6539 rtl8169_init_phy(dev, tp);
6541 __rtl8169_set_features(dev, dev->features);
6543 rtl_pll_power_up(tp);
6547 netif_start_queue(dev);
6549 rtl_unlock_work(tp);
6551 tp->saved_wolopts = 0;
6552 pm_runtime_put_noidle(&pdev->dev);
6554 rtl8169_check_link_status(dev, tp, ioaddr);
6559 rtl_release_firmware(tp);
6560 rtl8169_rx_clear(tp);
6562 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6564 tp->RxDescArray = NULL;
6566 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6568 tp->TxDescArray = NULL;
6570 pm_runtime_put_noidle(&pdev->dev);
6574 static struct rtnl_link_stats64 *
6575 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6577 struct rtl8169_private *tp = netdev_priv(dev);
6578 void __iomem *ioaddr = tp->mmio_addr;
6581 if (netif_running(dev))
6582 rtl8169_rx_missed(dev, ioaddr);
6585 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6586 stats->rx_packets = tp->rx_stats.packets;
6587 stats->rx_bytes = tp->rx_stats.bytes;
6588 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6592 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6593 stats->tx_packets = tp->tx_stats.packets;
6594 stats->tx_bytes = tp->tx_stats.bytes;
6595 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6597 stats->rx_dropped = dev->stats.rx_dropped;
6598 stats->tx_dropped = dev->stats.tx_dropped;
6599 stats->rx_length_errors = dev->stats.rx_length_errors;
6600 stats->rx_errors = dev->stats.rx_errors;
6601 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6602 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6603 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6608 static void rtl8169_net_suspend(struct net_device *dev)
6610 struct rtl8169_private *tp = netdev_priv(dev);
6612 if (!netif_running(dev))
6615 netif_device_detach(dev);
6616 netif_stop_queue(dev);
6619 napi_disable(&tp->napi);
6620 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6621 rtl_unlock_work(tp);
6623 rtl_pll_power_down(tp);
6628 static int rtl8169_suspend(struct device *device)
6630 struct pci_dev *pdev = to_pci_dev(device);
6631 struct net_device *dev = pci_get_drvdata(pdev);
6633 rtl8169_net_suspend(dev);
6638 static void __rtl8169_resume(struct net_device *dev)
6640 struct rtl8169_private *tp = netdev_priv(dev);
6642 netif_device_attach(dev);
6644 rtl_pll_power_up(tp);
6647 napi_enable(&tp->napi);
6648 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6649 rtl_unlock_work(tp);
6651 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6654 static int rtl8169_resume(struct device *device)
6656 struct pci_dev *pdev = to_pci_dev(device);
6657 struct net_device *dev = pci_get_drvdata(pdev);
6658 struct rtl8169_private *tp = netdev_priv(dev);
6660 rtl8169_init_phy(dev, tp);
6662 if (netif_running(dev))
6663 __rtl8169_resume(dev);
6668 static int rtl8169_runtime_suspend(struct device *device)
6670 struct pci_dev *pdev = to_pci_dev(device);
6671 struct net_device *dev = pci_get_drvdata(pdev);
6672 struct rtl8169_private *tp = netdev_priv(dev);
6674 if (!tp->TxDescArray)
6678 tp->saved_wolopts = __rtl8169_get_wol(tp);
6679 __rtl8169_set_wol(tp, WAKE_ANY);
6680 rtl_unlock_work(tp);
6682 rtl8169_net_suspend(dev);
6687 static int rtl8169_runtime_resume(struct device *device)
6689 struct pci_dev *pdev = to_pci_dev(device);
6690 struct net_device *dev = pci_get_drvdata(pdev);
6691 struct rtl8169_private *tp = netdev_priv(dev);
6693 if (!tp->TxDescArray)
6697 __rtl8169_set_wol(tp, tp->saved_wolopts);
6698 tp->saved_wolopts = 0;
6699 rtl_unlock_work(tp);
6701 rtl8169_init_phy(dev, tp);
6703 __rtl8169_resume(dev);
6708 static int rtl8169_runtime_idle(struct device *device)
6710 struct pci_dev *pdev = to_pci_dev(device);
6711 struct net_device *dev = pci_get_drvdata(pdev);
6712 struct rtl8169_private *tp = netdev_priv(dev);
6714 return tp->TxDescArray ? -EBUSY : 0;
6717 static const struct dev_pm_ops rtl8169_pm_ops = {
6718 .suspend = rtl8169_suspend,
6719 .resume = rtl8169_resume,
6720 .freeze = rtl8169_suspend,
6721 .thaw = rtl8169_resume,
6722 .poweroff = rtl8169_suspend,
6723 .restore = rtl8169_resume,
6724 .runtime_suspend = rtl8169_runtime_suspend,
6725 .runtime_resume = rtl8169_runtime_resume,
6726 .runtime_idle = rtl8169_runtime_idle,
6729 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6731 #else /* !CONFIG_PM */
6733 #define RTL8169_PM_OPS NULL
6735 #endif /* !CONFIG_PM */
6737 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6739 void __iomem *ioaddr = tp->mmio_addr;
6741 /* WoL fails with 8168b when the receiver is disabled. */
6742 switch (tp->mac_version) {
6743 case RTL_GIGA_MAC_VER_11:
6744 case RTL_GIGA_MAC_VER_12:
6745 case RTL_GIGA_MAC_VER_17:
6746 pci_clear_master(tp->pci_dev);
6748 RTL_W8(ChipCmd, CmdRxEnb);
6757 static void rtl_shutdown(struct pci_dev *pdev)
6759 struct net_device *dev = pci_get_drvdata(pdev);
6760 struct rtl8169_private *tp = netdev_priv(dev);
6761 struct device *d = &pdev->dev;
6763 pm_runtime_get_sync(d);
6765 rtl8169_net_suspend(dev);
6767 /* Restore original MAC address */
6768 rtl_rar_set(tp, dev->perm_addr);
6770 rtl8169_hw_reset(tp);
6772 if (system_state == SYSTEM_POWER_OFF) {
6773 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6774 rtl_wol_suspend_quirk(tp);
6775 rtl_wol_shutdown_quirk(tp);
6778 pci_wake_from_d3(pdev, true);
6779 pci_set_power_state(pdev, PCI_D3hot);
6782 pm_runtime_put_noidle(d);
6785 static void rtl_remove_one(struct pci_dev *pdev)
6787 struct net_device *dev = pci_get_drvdata(pdev);
6788 struct rtl8169_private *tp = netdev_priv(dev);
6790 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6791 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6792 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6793 rtl8168_driver_stop(tp);
6796 cancel_work_sync(&tp->wk.work);
6798 netif_napi_del(&tp->napi);
6800 unregister_netdev(dev);
6802 rtl_release_firmware(tp);
6804 if (pci_dev_run_wake(pdev))
6805 pm_runtime_get_noresume(&pdev->dev);
6807 /* restore original MAC address */
6808 rtl_rar_set(tp, dev->perm_addr);
6810 rtl_disable_msi(pdev, tp);
6811 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6812 pci_set_drvdata(pdev, NULL);
6815 static const struct net_device_ops rtl_netdev_ops = {
6816 .ndo_open = rtl_open,
6817 .ndo_stop = rtl8169_close,
6818 .ndo_get_stats64 = rtl8169_get_stats64,
6819 .ndo_start_xmit = rtl8169_start_xmit,
6820 .ndo_tx_timeout = rtl8169_tx_timeout,
6821 .ndo_validate_addr = eth_validate_addr,
6822 .ndo_change_mtu = rtl8169_change_mtu,
6823 .ndo_fix_features = rtl8169_fix_features,
6824 .ndo_set_features = rtl8169_set_features,
6825 .ndo_set_mac_address = rtl_set_mac_address,
6826 .ndo_do_ioctl = rtl8169_ioctl,
6827 .ndo_set_rx_mode = rtl_set_rx_mode,
6828 #ifdef CONFIG_NET_POLL_CONTROLLER
6829 .ndo_poll_controller = rtl8169_netpoll,
6834 static const struct rtl_cfg_info {
6835 void (*hw_start)(struct net_device *);
6836 unsigned int region;
6841 } rtl_cfg_infos [] = {
6843 .hw_start = rtl_hw_start_8169,
6846 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6847 .features = RTL_FEATURE_GMII,
6848 .default_ver = RTL_GIGA_MAC_VER_01,
6851 .hw_start = rtl_hw_start_8168,
6854 .event_slow = SYSErr | LinkChg | RxOverflow,
6855 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6856 .default_ver = RTL_GIGA_MAC_VER_11,
6859 .hw_start = rtl_hw_start_8101,
6862 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6864 .features = RTL_FEATURE_MSI,
6865 .default_ver = RTL_GIGA_MAC_VER_13,
6869 /* Cfg9346_Unlock assumed. */
6870 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6871 const struct rtl_cfg_info *cfg)
6873 void __iomem *ioaddr = tp->mmio_addr;
6877 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6878 if (cfg->features & RTL_FEATURE_MSI) {
6879 if (pci_enable_msi(tp->pci_dev)) {
6880 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6883 msi = RTL_FEATURE_MSI;
6886 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6887 RTL_W8(Config2, cfg2);
6891 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6893 void __iomem *ioaddr = tp->mmio_addr;
6895 return RTL_R8(MCU) & LINK_LIST_RDY;
6898 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6900 void __iomem *ioaddr = tp->mmio_addr;
6902 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6905 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6907 void __iomem *ioaddr = tp->mmio_addr;
6910 tp->ocp_base = OCP_STD_PHY_BASE;
6912 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6914 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6917 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6920 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6922 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6924 data = r8168_mac_ocp_read(tp, 0xe8de);
6926 r8168_mac_ocp_write(tp, 0xe8de, data);
6928 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6931 data = r8168_mac_ocp_read(tp, 0xe8de);
6933 r8168_mac_ocp_write(tp, 0xe8de, data);
6935 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6939 static void rtl_hw_initialize(struct rtl8169_private *tp)
6941 switch (tp->mac_version) {
6942 case RTL_GIGA_MAC_VER_40:
6943 case RTL_GIGA_MAC_VER_41:
6944 case RTL_GIGA_MAC_VER_42:
6945 case RTL_GIGA_MAC_VER_43:
6946 case RTL_GIGA_MAC_VER_44:
6947 rtl_hw_init_8168g(tp);
6956 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6958 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6959 const unsigned int region = cfg->region;
6960 struct rtl8169_private *tp;
6961 struct mii_if_info *mii;
6962 struct net_device *dev;
6963 void __iomem *ioaddr;
6967 if (netif_msg_drv(&debug)) {
6968 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6969 MODULENAME, RTL8169_VERSION);
6972 dev = alloc_etherdev(sizeof (*tp));
6978 SET_NETDEV_DEV(dev, &pdev->dev);
6979 dev->netdev_ops = &rtl_netdev_ops;
6980 tp = netdev_priv(dev);
6983 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6987 mii->mdio_read = rtl_mdio_read;
6988 mii->mdio_write = rtl_mdio_write;
6989 mii->phy_id_mask = 0x1f;
6990 mii->reg_num_mask = 0x1f;
6991 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6993 /* disable ASPM completely as that cause random device stop working
6994 * problems as well as full system hangs for some PCIe devices users */
6995 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6996 PCIE_LINK_STATE_CLKPM);
6998 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6999 rc = pci_enable_device(pdev);
7001 netif_err(tp, probe, dev, "enable failure\n");
7002 goto err_out_free_dev_1;
7005 if (pci_set_mwi(pdev) < 0)
7006 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7008 /* make sure PCI base addr 1 is MMIO */
7009 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7010 netif_err(tp, probe, dev,
7011 "region #%d not an MMIO resource, aborting\n",
7017 /* check for weird/broken PCI region reporting */
7018 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7019 netif_err(tp, probe, dev,
7020 "Invalid PCI region size(s), aborting\n");
7025 rc = pci_request_regions(pdev, MODULENAME);
7027 netif_err(tp, probe, dev, "could not request regions\n");
7031 tp->cp_cmd = RxChkSum;
7033 if ((sizeof(dma_addr_t) > 4) &&
7034 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7035 tp->cp_cmd |= PCIDAC;
7036 dev->features |= NETIF_F_HIGHDMA;
7038 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7040 netif_err(tp, probe, dev, "DMA configuration failed\n");
7041 goto err_out_free_res_3;
7045 /* ioremap MMIO region */
7046 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7048 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7050 goto err_out_free_res_3;
7052 tp->mmio_addr = ioaddr;
7054 if (!pci_is_pcie(pdev))
7055 netif_info(tp, probe, dev, "not PCI Express\n");
7057 /* Identify chip attached to board */
7058 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7062 rtl_irq_disable(tp);
7064 rtl_hw_initialize(tp);
7068 rtl_ack_events(tp, 0xffff);
7070 pci_set_master(pdev);
7073 * Pretend we are using VLANs; This bypasses a nasty bug where
7074 * Interrupts stop flowing on high load on 8110SCd controllers.
7076 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7077 tp->cp_cmd |= RxVlan;
7079 rtl_init_mdio_ops(tp);
7080 rtl_init_pll_power_ops(tp);
7081 rtl_init_jumbo_ops(tp);
7082 rtl_init_csi_ops(tp);
7084 rtl8169_print_mac_version(tp);
7086 chipset = tp->mac_version;
7087 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7089 RTL_W8(Cfg9346, Cfg9346_Unlock);
7090 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7091 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
7092 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7093 tp->features |= RTL_FEATURE_WOL;
7094 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7095 tp->features |= RTL_FEATURE_WOL;
7096 tp->features |= rtl_try_msi(tp, cfg);
7097 RTL_W8(Cfg9346, Cfg9346_Lock);
7099 if (rtl_tbi_enabled(tp)) {
7100 tp->set_speed = rtl8169_set_speed_tbi;
7101 tp->get_settings = rtl8169_gset_tbi;
7102 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7103 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7104 tp->link_ok = rtl8169_tbi_link_ok;
7105 tp->do_ioctl = rtl_tbi_ioctl;
7107 tp->set_speed = rtl8169_set_speed_xmii;
7108 tp->get_settings = rtl8169_gset_xmii;
7109 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7110 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7111 tp->link_ok = rtl8169_xmii_link_ok;
7112 tp->do_ioctl = rtl_xmii_ioctl;
7115 mutex_init(&tp->wk.mutex);
7117 /* Get MAC address */
7118 for (i = 0; i < ETH_ALEN; i++)
7119 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7121 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7122 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7124 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7126 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7127 * properly for all devices */
7128 dev->features |= NETIF_F_RXCSUM |
7129 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7131 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7132 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7133 NETIF_F_HW_VLAN_CTAG_RX;
7134 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7137 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7138 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7139 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7141 dev->hw_features |= NETIF_F_RXALL;
7142 dev->hw_features |= NETIF_F_RXFCS;
7144 tp->hw_start = cfg->hw_start;
7145 tp->event_slow = cfg->event_slow;
7147 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7148 ~(RxBOVF | RxFOVF) : ~0;
7150 init_timer(&tp->timer);
7151 tp->timer.data = (unsigned long) dev;
7152 tp->timer.function = rtl8169_phy_timer;
7154 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7156 rc = register_netdev(dev);
7160 pci_set_drvdata(pdev, dev);
7162 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7163 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7164 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7165 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7166 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7167 "tx checksumming: %s]\n",
7168 rtl_chip_infos[chipset].jumbo_max,
7169 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7172 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7173 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7174 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7175 rtl8168_driver_start(tp);
7178 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7180 if (pci_dev_run_wake(pdev))
7181 pm_runtime_put_noidle(&pdev->dev);
7183 netif_carrier_off(dev);
7189 netif_napi_del(&tp->napi);
7190 rtl_disable_msi(pdev, tp);
7193 pci_release_regions(pdev);
7195 pci_clear_mwi(pdev);
7196 pci_disable_device(pdev);
7202 static struct pci_driver rtl8169_pci_driver = {
7204 .id_table = rtl8169_pci_tbl,
7205 .probe = rtl_init_one,
7206 .remove = rtl_remove_one,
7207 .shutdown = rtl_shutdown,
7208 .driver.pm = RTL8169_PM_OPS,
7211 module_pci_driver(rtl8169_pci_driver);