drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53
  54 #ifdef RTL8169_DEBUG
  55 #define assert(expr) \
  56         if (!(expr)) {                                  \
  57                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  58                 #expr,__FILE__,__func__,__LINE__);              \
  59         }
  60 #define dprintk(fmt, args...) \
  61         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  62 #else
  63 #define assert(expr) do {} while (0)
  64 #define dprintk(fmt, args...)   do {} while (0)
  65 #endif /* RTL8169_DEBUG */
  66
  67 #define R8169_MSG_DEFAULT \
  68         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  69
  70 #define TX_SLOTS_AVAIL(tp) \
  71         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  72
  73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  75         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  76
  77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  78    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  79 static const int multicast_filter_limit = 32;
  80
  81 #define MAX_READ_REQUEST_SHIFT  12
  82 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  83 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  84
  85 #define R8169_REGS_SIZE         256
  86 #define R8169_NAPI_WEIGHT       64
  87 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  88 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  89 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  90 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  91
  92 #define RTL8169_TX_TIMEOUT      (6*HZ)
  93 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_VER_37,
 141         RTL_GIGA_MAC_VER_38,
 142         RTL_GIGA_MAC_VER_39,
 143         RTL_GIGA_MAC_VER_40,
 144         RTL_GIGA_MAC_VER_41,
 145         RTL_GIGA_MAC_VER_42,
 146         RTL_GIGA_MAC_VER_43,
 147         RTL_GIGA_MAC_NONE   = 0xff,
 148 };
 149
 150 enum rtl_tx_desc_version {
 151         RTL_TD_0        = 0,
 152         RTL_TD_1        = 1,
 153 };
 154
 155 #define JUMBO_1K        ETH_DATA_LEN
 156 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 157 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 158 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 159 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 160
 161 #define _R(NAME,TD,FW,SZ,B) {   \
 162         .name = NAME,           \
 163         .txd_version = TD,      \
 164         .fw_name = FW,          \
 165         .jumbo_max = SZ,        \
 166         .jumbo_tx_csum = B      \
 167 }
 168
 169 static const struct {
 170         const char *name;
 171         enum rtl_tx_desc_version txd_version;
 172         const char *fw_name;
 173         u16 jumbo_max;
 174         bool jumbo_tx_csum;
 175 } rtl_chip_infos[] = {
 176         /* PCI devices. */
 177         [RTL_GIGA_MAC_VER_01] =
 178                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 179         [RTL_GIGA_MAC_VER_02] =
 180                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 181         [RTL_GIGA_MAC_VER_03] =
 182                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 183         [RTL_GIGA_MAC_VER_04] =
 184                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 185         [RTL_GIGA_MAC_VER_05] =
 186                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 187         [RTL_GIGA_MAC_VER_06] =
 188                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 189         /* PCI-E devices. */
 190         [RTL_GIGA_MAC_VER_07] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_08] =
 193                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_09] =
 195                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_10] =
 197                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_11] =
 199                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 200         [RTL_GIGA_MAC_VER_12] =
 201                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 202         [RTL_GIGA_MAC_VER_13] =
 203                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 204         [RTL_GIGA_MAC_VER_14] =
 205                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_15] =
 207                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_16] =
 209                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_17] =
 211                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 212         [RTL_GIGA_MAC_VER_18] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_19] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_20] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_21] =
 219                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 220         [RTL_GIGA_MAC_VER_22] =
 221                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 222         [RTL_GIGA_MAC_VER_23] =
 223                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 224         [RTL_GIGA_MAC_VER_24] =
 225                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 226         [RTL_GIGA_MAC_VER_25] =
 227                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 228                                                         JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_26] =
 230                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 231                                                         JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_27] =
 233                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 234         [RTL_GIGA_MAC_VER_28] =
 235                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 236         [RTL_GIGA_MAC_VER_29] =
 237                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 238                                                         JUMBO_1K, true),
 239         [RTL_GIGA_MAC_VER_30] =
 240                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 241                                                         JUMBO_1K, true),
 242         [RTL_GIGA_MAC_VER_31] =
 243                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 244         [RTL_GIGA_MAC_VER_32] =
 245                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 246                                                         JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_33] =
 248                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_34] =
 251                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_35] =
 254                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 255                                                         JUMBO_9K, false),
 256         [RTL_GIGA_MAC_VER_36] =
 257                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 258                                                         JUMBO_9K, false),
 259         [RTL_GIGA_MAC_VER_37] =
 260                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 261                                                         JUMBO_1K, true),
 262         [RTL_GIGA_MAC_VER_38] =
 263                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 264                                                         JUMBO_9K, false),
 265         [RTL_GIGA_MAC_VER_39] =
 266                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 267                                                         JUMBO_1K, true),
 268         [RTL_GIGA_MAC_VER_40] =
 269                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 270                                                         JUMBO_9K, false),
 271         [RTL_GIGA_MAC_VER_41] =
 272                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_42] =
 274                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 275                                                         JUMBO_9K, false),
 276         [RTL_GIGA_MAC_VER_43] =
 277                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 278                                                         JUMBO_1K, true),
 279 };
 280 #undef _R
 281
 282 enum cfg_version {
 283         RTL_CFG_0 = 0x00,
 284         RTL_CFG_1,
 285         RTL_CFG_2
 286 };
 287
 288 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 289         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 290         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 291         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 292         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 293         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 294         { PCI_VENDOR_ID_DLINK,                  0x4300,
 295                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 297         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 298         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 299         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 300         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 301                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 302         { 0x0001,                               0x8168,
 303                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 304         {0,},
 305 };
 306
 307 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 308
 309 static int rx_buf_sz = 16383;
 310 static int use_dac;
 311 static struct {
 312         u32 msg_enable;
 313 } debug = { -1 };
 314
 315 enum rtl_registers {
 316         MAC0            = 0,    /* Ethernet hardware address. */
 317         MAC4            = 4,
 318         MAR0            = 8,    /* Multicast filter. */
 319         CounterAddrLow          = 0x10,
 320         CounterAddrHigh         = 0x14,
 321         TxDescStartAddrLow      = 0x20,
 322         TxDescStartAddrHigh     = 0x24,
 323         TxHDescStartAddrLow     = 0x28,
 324         TxHDescStartAddrHigh    = 0x2c,
 325         FLASH           = 0x30,
 326         ERSR            = 0x36,
 327         ChipCmd         = 0x37,
 328         TxPoll          = 0x38,
 329         IntrMask        = 0x3c,
 330         IntrStatus      = 0x3e,
 331
 332         TxConfig        = 0x40,
 333 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 334 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 335
 336         RxConfig        = 0x44,
 337 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 338 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 339 #define RXCFG_FIFO_SHIFT                13
 340                                         /* No threshold before first PCI xfer */
 341 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 342 #define RX_EARLY_OFF                    (1 << 11)
 343 #define RXCFG_DMA_SHIFT                 8
 344                                         /* Unlimited maximum PCI burst. */
 345 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 346
 347         RxMissed        = 0x4c,
 348         Cfg9346         = 0x50,
 349         Config0         = 0x51,
 350         Config1         = 0x52,
 351         Config2         = 0x53,
 352 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 353
 354         Config3         = 0x54,
 355         Config4         = 0x55,
 356         Config5         = 0x56,
 357         MultiIntr       = 0x5c,
 358         PHYAR           = 0x60,
 359         PHYstatus       = 0x6c,
 360         RxMaxSize       = 0xda,
 361         CPlusCmd        = 0xe0,
 362         IntrMitigate    = 0xe2,
 363         RxDescAddrLow   = 0xe4,
 364         RxDescAddrHigh  = 0xe8,
 365         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 366
 367 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 368
 369         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 370
 371 #define TxPacketMax     (8064 >> 7)
 372 #define EarlySize       0x27
 373
 374         FuncEvent       = 0xf0,
 375         FuncEventMask   = 0xf4,
 376         FuncPresetState = 0xf8,
 377         FuncForceEvent  = 0xfc,
 378 };
 379
 380 enum rtl8110_registers {
 381         TBICSR                  = 0x64,
 382         TBI_ANAR                = 0x68,
 383         TBI_LPAR                = 0x6a,
 384 };
 385
 386 enum rtl8168_8101_registers {
 387         CSIDR                   = 0x64,
 388         CSIAR                   = 0x68,
 389 #define CSIAR_FLAG                      0x80000000
 390 #define CSIAR_WRITE_CMD                 0x80000000
 391 #define CSIAR_BYTE_ENABLE               0x0f
 392 #define CSIAR_BYTE_ENABLE_SHIFT         12
 393 #define CSIAR_ADDR_MASK                 0x0fff
 394 #define CSIAR_FUNC_CARD                 0x00000000
 395 #define CSIAR_FUNC_SDIO                 0x00010000
 396 #define CSIAR_FUNC_NIC                  0x00020000
 397         PMCH                    = 0x6f,
 398         EPHYAR                  = 0x80,
 399 #define EPHYAR_FLAG                     0x80000000
 400 #define EPHYAR_WRITE_CMD                0x80000000
 401 #define EPHYAR_REG_MASK                 0x1f
 402 #define EPHYAR_REG_SHIFT                16
 403 #define EPHYAR_DATA_MASK                0xffff
 404         DLLPR                   = 0xd0,
 405 #define PFM_EN                          (1 << 6)
 406         DBG_REG                 = 0xd1,
 407 #define FIX_NAK_1                       (1 << 4)
 408 #define FIX_NAK_2                       (1 << 3)
 409         TWSI                    = 0xd2,
 410         MCU                     = 0xd3,
 411 #define NOW_IS_OOB                      (1 << 7)
 412 #define TX_EMPTY                        (1 << 5)
 413 #define RX_EMPTY                        (1 << 4)
 414 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 415 #define EN_NDP                          (1 << 3)
 416 #define EN_OOB_RESET                    (1 << 2)
 417 #define LINK_LIST_RDY                   (1 << 1)
 418         EFUSEAR                 = 0xdc,
 419 #define EFUSEAR_FLAG                    0x80000000
 420 #define EFUSEAR_WRITE_CMD               0x80000000
 421 #define EFUSEAR_READ_CMD                0x00000000
 422 #define EFUSEAR_REG_MASK                0x03ff
 423 #define EFUSEAR_REG_SHIFT               8
 424 #define EFUSEAR_DATA_MASK               0xff
 425 };
 426
 427 enum rtl8168_registers {
 428         LED_FREQ                = 0x1a,
 429         EEE_LED                 = 0x1b,
 430         ERIDR                   = 0x70,
 431         ERIAR                   = 0x74,
 432 #define ERIAR_FLAG                      0x80000000
 433 #define ERIAR_WRITE_CMD                 0x80000000
 434 #define ERIAR_READ_CMD                  0x00000000
 435 #define ERIAR_ADDR_BYTE_ALIGN           4
 436 #define ERIAR_TYPE_SHIFT                16
 437 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 438 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 439 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 440 #define ERIAR_MASK_SHIFT                12
 441 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 442 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 443 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 444 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 445         EPHY_RXER_NUM           = 0x7c,
 446         OCPDR                   = 0xb0, /* OCP GPHY access */
 447 #define OCPDR_WRITE_CMD                 0x80000000
 448 #define OCPDR_READ_CMD                  0x00000000
 449 #define OCPDR_REG_MASK                  0x7f
 450 #define OCPDR_GPHY_REG_SHIFT            16
 451 #define OCPDR_DATA_MASK                 0xffff
 452         OCPAR                   = 0xb4,
 453 #define OCPAR_FLAG                      0x80000000
 454 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 455 #define OCPAR_GPHY_READ_CMD             0x0000f060
 456         GPHY_OCP                = 0xb8,
 457         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 458         MISC                    = 0xf0, /* 8168e only. */
 459 #define TXPLA_RST                       (1 << 29)
 460 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 461 #define PWM_EN                          (1 << 22)
 462 #define RXDV_GATED_EN                   (1 << 19)
 463 #define EARLY_TALLY_EN                  (1 << 16)
 464 };
 465
 466 enum rtl_register_content {
 467         /* InterruptStatusBits */
 468         SYSErr          = 0x8000,
 469         PCSTimeout      = 0x4000,
 470         SWInt           = 0x0100,
 471         TxDescUnavail   = 0x0080,
 472         RxFIFOOver      = 0x0040,
 473         LinkChg         = 0x0020,
 474         RxOverflow      = 0x0010,
 475         TxErr           = 0x0008,
 476         TxOK            = 0x0004,
 477         RxErr           = 0x0002,
 478         RxOK            = 0x0001,
 479
 480         /* RxStatusDesc */
 481         RxBOVF  = (1 << 24),
 482         RxFOVF  = (1 << 23),
 483         RxRWT   = (1 << 22),
 484         RxRES   = (1 << 21),
 485         RxRUNT  = (1 << 20),
 486         RxCRC   = (1 << 19),
 487
 488         /* ChipCmdBits */
 489         StopReq         = 0x80,
 490         CmdReset        = 0x10,
 491         CmdRxEnb        = 0x08,
 492         CmdTxEnb        = 0x04,
 493         RxBufEmpty      = 0x01,
 494
 495         /* TXPoll register p.5 */
 496         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 497         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 498         FSWInt          = 0x01,         /* Forced software interrupt */
 499
 500         /* Cfg9346Bits */
 501         Cfg9346_Lock    = 0x00,
 502         Cfg9346_Unlock  = 0xc0,
 503
 504         /* rx_mode_bits */
 505         AcceptErr       = 0x20,
 506         AcceptRunt      = 0x10,
 507         AcceptBroadcast = 0x08,
 508         AcceptMulticast = 0x04,
 509         AcceptMyPhys    = 0x02,
 510         AcceptAllPhys   = 0x01,
 511 #define RX_CONFIG_ACCEPT_MASK           0x3f
 512
 513         /* TxConfigBits */
 514         TxInterFrameGapShift = 24,
 515         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 516
 517         /* Config1 register p.24 */
 518         LEDS1           = (1 << 7),
 519         LEDS0           = (1 << 6),
 520         Speed_down      = (1 << 4),
 521         MEMMAP          = (1 << 3),
 522         IOMAP           = (1 << 2),
 523         VPD             = (1 << 1),
 524         PMEnable        = (1 << 0),     /* Power Management Enable */
 525
 526         /* Config2 register p. 25 */
 527         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 528         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 529         PCI_Clock_66MHz = 0x01,
 530         PCI_Clock_33MHz = 0x00,
 531
 532         /* Config3 register p.25 */
 533         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 534         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 535         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 536         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 537
 538         /* Config4 register */
 539         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 540
 541         /* Config5 register p.27 */
 542         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 543         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 544         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 545         Spi_en          = (1 << 3),
 546         LanWake         = (1 << 1),     /* LanWake enable/disable */
 547         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 548         ASPM_en         = (1 << 0),     /* ASPM enable */
 549
 550         /* TBICSR p.28 */
 551         TBIReset        = 0x80000000,
 552         TBILoopback     = 0x40000000,
 553         TBINwEnable     = 0x20000000,
 554         TBINwRestart    = 0x10000000,
 555         TBILinkOk       = 0x02000000,
 556         TBINwComplete   = 0x01000000,
 557
 558         /* CPlusCmd p.31 */
 559         EnableBist      = (1 << 15),    // 8168 8101
 560         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 561         Normal_mode     = (1 << 13),    // unused
 562         Force_half_dup  = (1 << 12),    // 8168 8101
 563         Force_rxflow_en = (1 << 11),    // 8168 8101
 564         Force_txflow_en = (1 << 10),    // 8168 8101
 565         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 566         ASF             = (1 << 8),     // 8168 8101
 567         PktCntrDisable  = (1 << 7),     // 8168 8101
 568         Mac_dbgo_sel    = 0x001c,       // 8168
 569         RxVlan          = (1 << 6),
 570         RxChkSum        = (1 << 5),
 571         PCIDAC          = (1 << 4),
 572         PCIMulRW        = (1 << 3),
 573         INTT_0          = 0x0000,       // 8168
 574         INTT_1          = 0x0001,       // 8168
 575         INTT_2          = 0x0002,       // 8168
 576         INTT_3          = 0x0003,       // 8168
 577
 578         /* rtl8169_PHYstatus */
 579         TBI_Enable      = 0x80,
 580         TxFlowCtrl      = 0x40,
 581         RxFlowCtrl      = 0x20,
 582         _1000bpsF       = 0x10,
 583         _100bps         = 0x08,
 584         _10bps          = 0x04,
 585         LinkStatus      = 0x02,
 586         FullDup         = 0x01,
 587
 588         /* _TBICSRBit */
 589         TBILinkOK       = 0x02000000,
 590
 591         /* DumpCounterCommand */
 592         CounterDump     = 0x8,
 593 };
 594
 595 enum rtl_desc_bit {
 596         /* First doubleword. */
 597         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 598         RingEnd         = (1 << 30), /* End of descriptor ring */
 599         FirstFrag       = (1 << 29), /* First segment of a packet */
 600         LastFrag        = (1 << 28), /* Final segment of a packet */
 601 };
 602
 603 /* Generic case. */
 604 enum rtl_tx_desc_bit {
 605         /* First doubleword. */
 606         TD_LSO          = (1 << 27),            /* Large Send Offload */
 607 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 608
 609         /* Second doubleword. */
 610         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 611 };
 612
 613 /* 8169, 8168b and 810x except 8102e. */
 614 enum rtl_tx_desc_bit_0 {
 615         /* First doubleword. */
 616 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 617         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 618         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 619         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 620 };
 621
 622 /* 8102e, 8168c and beyond. */
 623 enum rtl_tx_desc_bit_1 {
 624         /* Second doubleword. */
 625 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 626         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 627         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 628         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 629 };
 630
 631 static const struct rtl_tx_desc_info {
 632         struct {
 633                 u32 udp;
 634                 u32 tcp;
 635         } checksum;
 636         u16 mss_shift;
 637         u16 opts_offset;
 638 } tx_desc_info [] = {
 639         [RTL_TD_0] = {
 640                 .checksum = {
 641                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 642                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 643                 },
 644                 .mss_shift      = TD0_MSS_SHIFT,
 645                 .opts_offset    = 0
 646         },
 647         [RTL_TD_1] = {
 648                 .checksum = {
 649                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 650                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 651                 },
 652                 .mss_shift      = TD1_MSS_SHIFT,
 653                 .opts_offset    = 1
 654         }
 655 };
 656
 657 enum rtl_rx_desc_bit {
 658         /* Rx private */
 659         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 660         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 661
 662 #define RxProtoUDP      (PID1)
 663 #define RxProtoTCP      (PID0)
 664 #define RxProtoIP       (PID1 | PID0)
 665 #define RxProtoMask     RxProtoIP
 666
 667         IPFail          = (1 << 16), /* IP checksum failed */
 668         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 669         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 670         RxVlanTag       = (1 << 16), /* VLAN tag available */
 671 };
 672
 673 #define RsvdMask        0x3fffc000
 674
 675 struct TxDesc {
 676         __le32 opts1;
 677         __le32 opts2;
 678         __le64 addr;
 679 };
 680
 681 struct RxDesc {
 682         __le32 opts1;
 683         __le32 opts2;
 684         __le64 addr;
 685 };
 686
 687 struct ring_info {
 688         struct sk_buff  *skb;
 689         u32             len;
 690         u8              __pad[sizeof(void *) - sizeof(u32)];
 691 };
 692
 693 enum features {
 694         RTL_FEATURE_WOL         = (1 << 0),
 695         RTL_FEATURE_MSI         = (1 << 1),
 696         RTL_FEATURE_GMII        = (1 << 2),
 697 };
 698
 699 struct rtl8169_counters {
 700         __le64  tx_packets;
 701         __le64  rx_packets;
 702         __le64  tx_errors;
 703         __le32  rx_errors;
 704         __le16  rx_missed;
 705         __le16  align_errors;
 706         __le32  tx_one_collision;
 707         __le32  tx_multi_collision;
 708         __le64  rx_unicast;
 709         __le64  rx_broadcast;
 710         __le32  rx_multicast;
 711         __le16  tx_aborted;
 712         __le16  tx_underun;
 713 };
 714
 715 enum rtl_flag {
 716         RTL_FLAG_TASK_ENABLED,
 717         RTL_FLAG_TASK_SLOW_PENDING,
 718         RTL_FLAG_TASK_RESET_PENDING,
 719         RTL_FLAG_TASK_PHY_PENDING,
 720         RTL_FLAG_MAX
 721 };
 722
 723 struct rtl8169_stats {
 724         u64                     packets;
 725         u64                     bytes;
 726         struct u64_stats_sync   syncp;
 727 };
 728
 729 struct rtl8169_private {
 730         void __iomem *mmio_addr;        /* memory map physical address */
 731         struct pci_dev *pci_dev;
 732         struct net_device *dev;
 733         struct napi_struct napi;
 734         u32 msg_enable;
 735         u16 txd_version;
 736         u16 mac_version;
 737         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 738         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 739         u32 dirty_tx;
 740         struct rtl8169_stats rx_stats;
 741         struct rtl8169_stats tx_stats;
 742         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 743         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 744         dma_addr_t TxPhyAddr;
 745         dma_addr_t RxPhyAddr;
 746         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 747         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 748         struct timer_list timer;
 749         u16 cp_cmd;
 750
 751         u16 event_slow;
 752
 753         struct mdio_ops {
 754                 void (*write)(struct rtl8169_private *, int, int);
 755                 int (*read)(struct rtl8169_private *, int);
 756         } mdio_ops;
 757
 758         struct pll_power_ops {
 759                 void (*down)(struct rtl8169_private *);
 760                 void (*up)(struct rtl8169_private *);
 761         } pll_power_ops;
 762
 763         struct jumbo_ops {
 764                 void (*enable)(struct rtl8169_private *);
 765                 void (*disable)(struct rtl8169_private *);
 766         } jumbo_ops;
 767
 768         struct csi_ops {
 769                 void (*write)(struct rtl8169_private *, int, int);
 770                 u32 (*read)(struct rtl8169_private *, int);
 771         } csi_ops;
 772
 773         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 774         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 775         void (*phy_reset_enable)(struct rtl8169_private *tp);
 776         void (*hw_start)(struct net_device *);
 777         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 778         unsigned int (*link_ok)(void __iomem *);
 779         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 780
 781         struct {
 782                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 783                 struct mutex mutex;
 784                 struct work_struct work;
 785         } wk;
 786
 787         unsigned features;
 788
 789         struct mii_if_info mii;
 790         struct rtl8169_counters counters;
 791         u32 saved_wolopts;
 792         u32 opts1_mask;
 793
 794         struct rtl_fw {
 795                 const struct firmware *fw;
 796
 797 #define RTL_VER_SIZE            32
 798
 799                 char version[RTL_VER_SIZE];
 800
 801                 struct rtl_fw_phy_action {
 802                         __le32 *code;
 803                         size_t size;
 804                 } phy_action;
 805         } *rtl_fw;
 806 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 807
 808         u32 ocp_base;
 809 };
 810
 811 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 812 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 813 module_param(use_dac, int, 0);
 814 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 815 module_param_named(debug, debug.msg_enable, int, 0);
 816 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 817 MODULE_LICENSE("GPL");
 818 MODULE_VERSION(RTL8169_VERSION);
 819 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 820 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 821 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 822 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 823 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 824 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 825 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 826 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 827 MODULE_FIRMWARE(FIRMWARE_8402_1);
 828 MODULE_FIRMWARE(FIRMWARE_8411_1);
 829 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 830 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 831 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 832 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 833
 834 static void rtl_lock_work(struct rtl8169_private *tp)
 835 {
 836         mutex_lock(&tp->wk.mutex);
 837 }
 838
 839 static void rtl_unlock_work(struct rtl8169_private *tp)
 840 {
 841         mutex_unlock(&tp->wk.mutex);
 842 }
 843
 844 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 845 {
 846         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 847                                            PCI_EXP_DEVCTL_READRQ, force);
 848 }
 849
 850 struct rtl_cond {
 851         bool (*check)(struct rtl8169_private *);
 852         const char *msg;
 853 };
 854
 855 static void rtl_udelay(unsigned int d)
 856 {
 857         udelay(d);
 858 }
 859
 860 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 861                           void (*delay)(unsigned int), unsigned int d, int n,
 862                           bool high)
 863 {
 864         int i;
 865
 866         for (i = 0; i < n; i++) {
 867                 delay(d);
 868                 if (c->check(tp) == high)
 869                         return true;
 870         }
 871         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 872                   c->msg, !high, n, d);
 873         return false;
 874 }
 875
 876 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 877                                       const struct rtl_cond *c,
 878                                       unsigned int d, int n)
 879 {
 880         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 881 }
 882
 883 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 884                                      const struct rtl_cond *c,
 885                                      unsigned int d, int n)
 886 {
 887         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 888 }
 889
 890 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 891                                       const struct rtl_cond *c,
 892                                       unsigned int d, int n)
 893 {
 894         return rtl_loop_wait(tp, c, msleep, d, n, true);
 895 }
 896
 897 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 898                                      const struct rtl_cond *c,
 899                                      unsigned int d, int n)
 900 {
 901         return rtl_loop_wait(tp, c, msleep, d, n, false);
 902 }
 903
 904 #define DECLARE_RTL_COND(name)                          \
 905 static bool name ## _check(struct rtl8169_private *);   \
 906                                                         \
 907 static const struct rtl_cond name = {                   \
 908         .check  = name ## _check,                       \
 909         .msg    = #name                                 \
 910 };                                                      \
 911                                                         \
 912 static bool name ## _check(struct rtl8169_private *tp)
 913
 914 DECLARE_RTL_COND(rtl_ocpar_cond)
 915 {
 916         void __iomem *ioaddr = tp->mmio_addr;
 917
 918         return RTL_R32(OCPAR) & OCPAR_FLAG;
 919 }
 920
 921 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 922 {
 923         void __iomem *ioaddr = tp->mmio_addr;
 924
 925         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 926
 927         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 928                 RTL_R32(OCPDR) : ~0;
 929 }
 930
 931 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 932 {
 933         void __iomem *ioaddr = tp->mmio_addr;
 934
 935         RTL_W32(OCPDR, data);
 936         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 937
 938         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 939 }
 940
 941 DECLARE_RTL_COND(rtl_eriar_cond)
 942 {
 943         void __iomem *ioaddr = tp->mmio_addr;
 944
 945         return RTL_R32(ERIAR) & ERIAR_FLAG;
 946 }
 947
 948 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 949 {
 950         void __iomem *ioaddr = tp->mmio_addr;
 951
 952         RTL_W8(ERIDR, cmd);
 953         RTL_W32(ERIAR, 0x800010e8);
 954         msleep(2);
 955
 956         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 957                 return;
 958
 959         ocp_write(tp, 0x1, 0x30, 0x00000001);
 960 }
 961
 962 #define OOB_CMD_RESET           0x00
 963 #define OOB_CMD_DRIVER_START    0x05
 964 #define OOB_CMD_DRIVER_STOP     0x06
 965
 966 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 967 {
 968         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 969 }
 970
 971 DECLARE_RTL_COND(rtl_ocp_read_cond)
 972 {
 973         u16 reg;
 974
 975         reg = rtl8168_get_ocp_reg(tp);
 976
 977         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 978 }
 979
 980 static void rtl8168_driver_start(struct rtl8169_private *tp)
 981 {
 982         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 983
 984         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 985 }
 986
 987 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 988 {
 989         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 990
 991         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 992 }
 993
 994 static int r8168dp_check_dash(struct rtl8169_private *tp)
 995 {
 996         u16 reg = rtl8168_get_ocp_reg(tp);
 997
 998         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 999 }
1000
1001 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1002 {
1003         if (reg & 0xffff0001) {
1004                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1005                 return true;
1006         }
1007         return false;
1008 }
1009
1010 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1011 {
1012         void __iomem *ioaddr = tp->mmio_addr;
1013
1014         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1015 }
1016
1017 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1018 {
1019         void __iomem *ioaddr = tp->mmio_addr;
1020
1021         if (rtl_ocp_reg_failure(tp, reg))
1022                 return;
1023
1024         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1025
1026         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1027 }
1028
1029 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1030 {
1031         void __iomem *ioaddr = tp->mmio_addr;
1032
1033         if (rtl_ocp_reg_failure(tp, reg))
1034                 return 0;
1035
1036         RTL_W32(GPHY_OCP, reg << 15);
1037
1038         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1039                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1040 }
1041
1042 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1043 {
1044         void __iomem *ioaddr = tp->mmio_addr;
1045
1046         if (rtl_ocp_reg_failure(tp, reg))
1047                 return;
1048
1049         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1050 }
1051
1052 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1053 {
1054         void __iomem *ioaddr = tp->mmio_addr;
1055
1056         if (rtl_ocp_reg_failure(tp, reg))
1057                 return 0;
1058
1059         RTL_W32(OCPDR, reg << 15);
1060
1061         return RTL_R32(OCPDR);
1062 }
1063
1064 #define OCP_STD_PHY_BASE        0xa400
1065
1066 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1067 {
1068         if (reg == 0x1f) {
1069                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1070                 return;
1071         }
1072
1073         if (tp->ocp_base != OCP_STD_PHY_BASE)
1074                 reg -= 0x10;
1075
1076         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1077 }
1078
1079 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1080 {
1081         if (tp->ocp_base != OCP_STD_PHY_BASE)
1082                 reg -= 0x10;
1083
1084         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1085 }
1086
1087 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1088 {
1089         if (reg == 0x1f) {
1090                 tp->ocp_base = value << 4;
1091                 return;
1092         }
1093
1094         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1095 }
1096
1097 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1098 {
1099         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1100 }
1101
1102 DECLARE_RTL_COND(rtl_phyar_cond)
1103 {
1104         void __iomem *ioaddr = tp->mmio_addr;
1105
1106         return RTL_R32(PHYAR) & 0x80000000;
1107 }
1108
1109 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1110 {
1111         void __iomem *ioaddr = tp->mmio_addr;
1112
1113         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1114
1115         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1116         /*
1117          * According to hardware specs a 20us delay is required after write
1118          * complete indication, but before sending next command.
1119          */
1120         udelay(20);
1121 }
1122
1123 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1124 {
1125         void __iomem *ioaddr = tp->mmio_addr;
1126         int value;
1127
1128         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1129
1130         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1131                 RTL_R32(PHYAR) & 0xffff : ~0;
1132
1133         /*
1134          * According to hardware specs a 20us delay is required after read
1135          * complete indication, but before sending next command.
1136          */
1137         udelay(20);
1138
1139         return value;
1140 }
1141
1142 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1143 {
1144         void __iomem *ioaddr = tp->mmio_addr;
1145
1146         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1147         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1148         RTL_W32(EPHY_RXER_NUM, 0);
1149
1150         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1151 }
1152
1153 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1154 {
1155         r8168dp_1_mdio_access(tp, reg,
1156                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1157 }
1158
1159 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1160 {
1161         void __iomem *ioaddr = tp->mmio_addr;
1162
1163         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1164
1165         mdelay(1);
1166         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1167         RTL_W32(EPHY_RXER_NUM, 0);
1168
1169         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1170                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1171 }
1172
1173 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1174
1175 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1176 {
1177         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1178 }
1179
1180 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1181 {
1182         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1183 }
1184
1185 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1186 {
1187         void __iomem *ioaddr = tp->mmio_addr;
1188
1189         r8168dp_2_mdio_start(ioaddr);
1190
1191         r8169_mdio_write(tp, reg, value);
1192
1193         r8168dp_2_mdio_stop(ioaddr);
1194 }
1195
1196 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1197 {
1198         void __iomem *ioaddr = tp->mmio_addr;
1199         int value;
1200
1201         r8168dp_2_mdio_start(ioaddr);
1202
1203         value = r8169_mdio_read(tp, reg);
1204
1205         r8168dp_2_mdio_stop(ioaddr);
1206
1207         return value;
1208 }
1209
1210 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1211 {
1212         tp->mdio_ops.write(tp, location, val);
1213 }
1214
1215 static int rtl_readphy(struct rtl8169_private *tp, int location)
1216 {
1217         return tp->mdio_ops.read(tp, location);
1218 }
1219
1220 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1221 {
1222         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1223 }
1224
1225 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1226 {
1227         int val;
1228
1229         val = rtl_readphy(tp, reg_addr);
1230         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1231 }
1232
1233 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1234                            int val)
1235 {
1236         struct rtl8169_private *tp = netdev_priv(dev);
1237
1238         rtl_writephy(tp, location, val);
1239 }
1240
1241 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1242 {
1243         struct rtl8169_private *tp = netdev_priv(dev);
1244
1245         return rtl_readphy(tp, location);
1246 }
1247
1248 DECLARE_RTL_COND(rtl_ephyar_cond)
1249 {
1250         void __iomem *ioaddr = tp->mmio_addr;
1251
1252         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1253 }
1254
1255 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1256 {
1257         void __iomem *ioaddr = tp->mmio_addr;
1258
1259         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1260                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1261
1262         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1263
1264         udelay(10);
1265 }
1266
1267 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1268 {
1269         void __iomem *ioaddr = tp->mmio_addr;
1270
1271         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1272
1273         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1274                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1275 }
1276
1277 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1278                           u32 val, int type)
1279 {
1280         void __iomem *ioaddr = tp->mmio_addr;
1281
1282         BUG_ON((addr & 3) || (mask == 0));
1283         RTL_W32(ERIDR, val);
1284         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1285
1286         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1287 }
1288
1289 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1290 {
1291         void __iomem *ioaddr = tp->mmio_addr;
1292
1293         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1294
1295         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1296                 RTL_R32(ERIDR) : ~0;
1297 }
1298
1299 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1300                          u32 m, int type)
1301 {
1302         u32 val;
1303
1304         val = rtl_eri_read(tp, addr, type);
1305         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1306 }
1307
1308 struct exgmac_reg {
1309         u16 addr;
1310         u16 mask;
1311         u32 val;
1312 };
1313
1314 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1315                                    const struct exgmac_reg *r, int len)
1316 {
1317         while (len-- > 0) {
1318                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1319                 r++;
1320         }
1321 }
1322
1323 DECLARE_RTL_COND(rtl_efusear_cond)
1324 {
1325         void __iomem *ioaddr = tp->mmio_addr;
1326
1327         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1328 }
1329
1330 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1331 {
1332         void __iomem *ioaddr = tp->mmio_addr;
1333
1334         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1335
1336         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1337                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1338 }
1339
1340 static u16 rtl_get_events(struct rtl8169_private *tp)
1341 {
1342         void __iomem *ioaddr = tp->mmio_addr;
1343
1344         return RTL_R16(IntrStatus);
1345 }
1346
1347 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1348 {
1349         void __iomem *ioaddr = tp->mmio_addr;
1350
1351         RTL_W16(IntrStatus, bits);
1352         mmiowb();
1353 }
1354
1355 static void rtl_irq_disable(struct rtl8169_private *tp)
1356 {
1357         void __iomem *ioaddr = tp->mmio_addr;
1358
1359         RTL_W16(IntrMask, 0);
1360         mmiowb();
1361 }
1362
1363 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1364 {
1365         void __iomem *ioaddr = tp->mmio_addr;
1366
1367         RTL_W16(IntrMask, bits);
1368 }
1369
1370 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1371 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1372 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1373
1374 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1375 {
1376         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1377 }
1378
1379 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1380 {
1381         void __iomem *ioaddr = tp->mmio_addr;
1382
1383         rtl_irq_disable(tp);
1384         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1385         RTL_R8(ChipCmd);
1386 }
1387
1388 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1389 {
1390         void __iomem *ioaddr = tp->mmio_addr;
1391
1392         return RTL_R32(TBICSR) & TBIReset;
1393 }
1394
1395 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1396 {
1397         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1398 }
1399
1400 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1401 {
1402         return RTL_R32(TBICSR) & TBILinkOk;
1403 }
1404
1405 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1406 {
1407         return RTL_R8(PHYstatus) & LinkStatus;
1408 }
1409
1410 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1411 {
1412         void __iomem *ioaddr = tp->mmio_addr;
1413
1414         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1415 }
1416
1417 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1418 {
1419         unsigned int val;
1420
1421         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1422         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1423 }
1424
1425 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1426 {
1427         void __iomem *ioaddr = tp->mmio_addr;
1428         struct net_device *dev = tp->dev;
1429
1430         if (!netif_running(dev))
1431                 return;
1432
1433         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1434             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1435                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1436                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1437                                       ERIAR_EXGMAC);
1438                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1439                                       ERIAR_EXGMAC);
1440                 } else if (RTL_R8(PHYstatus) & _100bps) {
1441                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1442                                       ERIAR_EXGMAC);
1443                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1444                                       ERIAR_EXGMAC);
1445                 } else {
1446                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1447                                       ERIAR_EXGMAC);
1448                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1449                                       ERIAR_EXGMAC);
1450                 }
1451                 /* Reset packet filter */
1452                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1453                              ERIAR_EXGMAC);
1454                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1455                              ERIAR_EXGMAC);
1456         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1457                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1458                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1459                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1460                                       ERIAR_EXGMAC);
1461                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1462                                       ERIAR_EXGMAC);
1463                 } else {
1464                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1465                                       ERIAR_EXGMAC);
1466                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1467                                       ERIAR_EXGMAC);
1468                 }
1469         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1470                 if (RTL_R8(PHYstatus) & _10bps) {
1471                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1472                                       ERIAR_EXGMAC);
1473                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1474                                       ERIAR_EXGMAC);
1475                 } else {
1476                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1477                                       ERIAR_EXGMAC);
1478                 }
1479         }
1480 }
1481
1482 static void __rtl8169_check_link_status(struct net_device *dev,
1483                                         struct rtl8169_private *tp,
1484                                         void __iomem *ioaddr, bool pm)
1485 {
1486         if (tp->link_ok(ioaddr)) {
1487                 rtl_link_chg_patch(tp);
1488                 /* This is to cancel a scheduled suspend if there's one. */
1489                 if (pm)
1490                         pm_request_resume(&tp->pci_dev->dev);
1491                 netif_carrier_on(dev);
1492                 if (net_ratelimit())
1493                         netif_info(tp, ifup, dev, "link up\n");
1494         } else {
1495                 netif_carrier_off(dev);
1496                 netif_info(tp, ifdown, dev, "link down\n");
1497                 if (pm)
1498                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1499         }
1500 }
1501
1502 static void rtl8169_check_link_status(struct net_device *dev,
1503                                       struct rtl8169_private *tp,
1504                                       void __iomem *ioaddr)
1505 {
1506         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1507 }
1508
1509 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1510
1511 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1512 {
1513         void __iomem *ioaddr = tp->mmio_addr;
1514         u8 options;
1515         u32 wolopts = 0;
1516
1517         options = RTL_R8(Config1);
1518         if (!(options & PMEnable))
1519                 return 0;
1520
1521         options = RTL_R8(Config3);
1522         if (options & LinkUp)
1523                 wolopts |= WAKE_PHY;
1524         if (options & MagicPacket)
1525                 wolopts |= WAKE_MAGIC;
1526
1527         options = RTL_R8(Config5);
1528         if (options & UWF)
1529                 wolopts |= WAKE_UCAST;
1530         if (options & BWF)
1531                 wolopts |= WAKE_BCAST;
1532         if (options & MWF)
1533                 wolopts |= WAKE_MCAST;
1534
1535         return wolopts;
1536 }
1537
1538 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1539 {
1540         struct rtl8169_private *tp = netdev_priv(dev);
1541
1542         rtl_lock_work(tp);
1543
1544         wol->supported = WAKE_ANY;
1545         wol->wolopts = __rtl8169_get_wol(tp);
1546
1547         rtl_unlock_work(tp);
1548 }
1549
1550 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1551 {
1552         void __iomem *ioaddr = tp->mmio_addr;
1553         unsigned int i;
1554         static const struct {
1555                 u32 opt;
1556                 u16 reg;
1557                 u8  mask;
1558         } cfg[] = {
1559                 { WAKE_PHY,   Config3, LinkUp },
1560                 { WAKE_MAGIC, Config3, MagicPacket },
1561                 { WAKE_UCAST, Config5, UWF },
1562                 { WAKE_BCAST, Config5, BWF },
1563                 { WAKE_MCAST, Config5, MWF },
1564                 { WAKE_ANY,   Config5, LanWake }
1565         };
1566         u8 options;
1567
1568         RTL_W8(Cfg9346, Cfg9346_Unlock);
1569
1570         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1571                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1572                 if (wolopts & cfg[i].opt)
1573                         options |= cfg[i].mask;
1574                 RTL_W8(cfg[i].reg, options);
1575         }
1576
1577         switch (tp->mac_version) {
1578         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1579                 options = RTL_R8(Config1) & ~PMEnable;
1580                 if (wolopts)
1581                         options |= PMEnable;
1582                 RTL_W8(Config1, options);
1583                 break;
1584         default:
1585                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1586                 if (wolopts)
1587                         options |= PME_SIGNAL;
1588                 RTL_W8(Config2, options);
1589                 break;
1590         }
1591
1592         RTL_W8(Cfg9346, Cfg9346_Lock);
1593 }
1594
1595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1596 {
1597         struct rtl8169_private *tp = netdev_priv(dev);
1598
1599         rtl_lock_work(tp);
1600
1601         if (wol->wolopts)
1602                 tp->features |= RTL_FEATURE_WOL;
1603         else
1604                 tp->features &= ~RTL_FEATURE_WOL;
1605         __rtl8169_set_wol(tp, wol->wolopts);
1606
1607         rtl_unlock_work(tp);
1608
1609         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1610
1611         return 0;
1612 }
1613
1614 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1615 {
1616         return rtl_chip_infos[tp->mac_version].fw_name;
1617 }
1618
1619 static void rtl8169_get_drvinfo(struct net_device *dev,
1620                                 struct ethtool_drvinfo *info)
1621 {
1622         struct rtl8169_private *tp = netdev_priv(dev);
1623         struct rtl_fw *rtl_fw = tp->rtl_fw;
1624
1625         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1626         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1627         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1628         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1629         if (!IS_ERR_OR_NULL(rtl_fw))
1630                 strlcpy(info->fw_version, rtl_fw->version,
1631                         sizeof(info->fw_version));
1632 }
1633
1634 static int rtl8169_get_regs_len(struct net_device *dev)
1635 {
1636         return R8169_REGS_SIZE;
1637 }
1638
1639 static int rtl8169_set_speed_tbi(struct net_device *dev,
1640                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1641 {
1642         struct rtl8169_private *tp = netdev_priv(dev);
1643         void __iomem *ioaddr = tp->mmio_addr;
1644         int ret = 0;
1645         u32 reg;
1646
1647         reg = RTL_R32(TBICSR);
1648         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1649             (duplex == DUPLEX_FULL)) {
1650                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1651         } else if (autoneg == AUTONEG_ENABLE)
1652                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1653         else {
1654                 netif_warn(tp, link, dev,
1655                            "incorrect speed setting refused in TBI mode\n");
1656                 ret = -EOPNOTSUPP;
1657         }
1658
1659         return ret;
1660 }
1661
1662 static int rtl8169_set_speed_xmii(struct net_device *dev,
1663                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1664 {
1665         struct rtl8169_private *tp = netdev_priv(dev);
1666         int giga_ctrl, bmcr;
1667         int rc = -EINVAL;
1668
1669         rtl_writephy(tp, 0x1f, 0x0000);
1670
1671         if (autoneg == AUTONEG_ENABLE) {
1672                 int auto_nego;
1673
1674                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1675                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1676                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1677
1678                 if (adv & ADVERTISED_10baseT_Half)
1679                         auto_nego |= ADVERTISE_10HALF;
1680                 if (adv & ADVERTISED_10baseT_Full)
1681                         auto_nego |= ADVERTISE_10FULL;
1682                 if (adv & ADVERTISED_100baseT_Half)
1683                         auto_nego |= ADVERTISE_100HALF;
1684                 if (adv & ADVERTISED_100baseT_Full)
1685                         auto_nego |= ADVERTISE_100FULL;
1686
1687                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1688
1689                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1690                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1691
1692                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1693                 if (tp->mii.supports_gmii) {
1694                         if (adv & ADVERTISED_1000baseT_Half)
1695                                 giga_ctrl |= ADVERTISE_1000HALF;
1696                         if (adv & ADVERTISED_1000baseT_Full)
1697                                 giga_ctrl |= ADVERTISE_1000FULL;
1698                 } else if (adv & (ADVERTISED_1000baseT_Half |
1699                                   ADVERTISED_1000baseT_Full)) {
1700                         netif_info(tp, link, dev,
1701                                    "PHY does not support 1000Mbps\n");
1702                         goto out;
1703                 }
1704
1705                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1706
1707                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1708                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1709         } else {
1710                 giga_ctrl = 0;
1711
1712                 if (speed == SPEED_10)
1713                         bmcr = 0;
1714                 else if (speed == SPEED_100)
1715                         bmcr = BMCR_SPEED100;
1716                 else
1717                         goto out;
1718
1719                 if (duplex == DUPLEX_FULL)
1720                         bmcr |= BMCR_FULLDPLX;
1721         }
1722
1723         rtl_writephy(tp, MII_BMCR, bmcr);
1724
1725         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1726             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1727                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1728                         rtl_writephy(tp, 0x17, 0x2138);
1729                         rtl_writephy(tp, 0x0e, 0x0260);
1730                 } else {
1731                         rtl_writephy(tp, 0x17, 0x2108);
1732                         rtl_writephy(tp, 0x0e, 0x0000);
1733                 }
1734         }
1735
1736         rc = 0;
1737 out:
1738         return rc;
1739 }
1740
1741 static int rtl8169_set_speed(struct net_device *dev,
1742                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1743 {
1744         struct rtl8169_private *tp = netdev_priv(dev);
1745         int ret;
1746
1747         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1748         if (ret < 0)
1749                 goto out;
1750
1751         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1752             (advertising & ADVERTISED_1000baseT_Full)) {
1753                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1754         }
1755 out:
1756         return ret;
1757 }
1758
1759 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1760 {
1761         struct rtl8169_private *tp = netdev_priv(dev);
1762         int ret;
1763
1764         del_timer_sync(&tp->timer);
1765
1766         rtl_lock_work(tp);
1767         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1768                                 cmd->duplex, cmd->advertising);
1769         rtl_unlock_work(tp);
1770
1771         return ret;
1772 }
1773
1774 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1775         netdev_features_t features)
1776 {
1777         struct rtl8169_private *tp = netdev_priv(dev);
1778
1779         if (dev->mtu > TD_MSS_MAX)
1780                 features &= ~NETIF_F_ALL_TSO;
1781
1782         if (dev->mtu > JUMBO_1K &&
1783             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1784                 features &= ~NETIF_F_IP_CSUM;
1785
1786         return features;
1787 }
1788
1789 static void __rtl8169_set_features(struct net_device *dev,
1790                                    netdev_features_t features)
1791 {
1792         struct rtl8169_private *tp = netdev_priv(dev);
1793         netdev_features_t changed = features ^ dev->features;
1794         void __iomem *ioaddr = tp->mmio_addr;
1795
1796         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1797                 return;
1798
1799         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1800                 if (features & NETIF_F_RXCSUM)
1801                         tp->cp_cmd |= RxChkSum;
1802                 else
1803                         tp->cp_cmd &= ~RxChkSum;
1804
1805                 if (dev->features & NETIF_F_HW_VLAN_RX)
1806                         tp->cp_cmd |= RxVlan;
1807                 else
1808                         tp->cp_cmd &= ~RxVlan;
1809
1810                 RTL_W16(CPlusCmd, tp->cp_cmd);
1811                 RTL_R16(CPlusCmd);
1812         }
1813         if (changed & NETIF_F_RXALL) {
1814                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1815                 if (features & NETIF_F_RXALL)
1816                         tmp |= (AcceptErr | AcceptRunt);
1817                 RTL_W32(RxConfig, tmp);
1818         }
1819 }
1820
1821 static int rtl8169_set_features(struct net_device *dev,
1822                                 netdev_features_t features)
1823 {
1824         struct rtl8169_private *tp = netdev_priv(dev);
1825
1826         rtl_lock_work(tp);
1827         __rtl8169_set_features(dev, features);
1828         rtl_unlock_work(tp);
1829
1830         return 0;
1831 }
1832
1833
1834 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1835 {
1836         return (vlan_tx_tag_present(skb)) ?
1837                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1838 }
1839
1840 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1841 {
1842         u32 opts2 = le32_to_cpu(desc->opts2);
1843
1844         if (opts2 & RxVlanTag)
1845                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1846 }
1847
1848 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1849 {
1850         struct rtl8169_private *tp = netdev_priv(dev);
1851         void __iomem *ioaddr = tp->mmio_addr;
1852         u32 status;
1853
1854         cmd->supported =
1855                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1856         cmd->port = PORT_FIBRE;
1857         cmd->transceiver = XCVR_INTERNAL;
1858
1859         status = RTL_R32(TBICSR);
1860         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1861         cmd->autoneg = !!(status & TBINwEnable);
1862
1863         ethtool_cmd_speed_set(cmd, SPEED_1000);
1864         cmd->duplex = DUPLEX_FULL; /* Always set */
1865
1866         return 0;
1867 }
1868
1869 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1870 {
1871         struct rtl8169_private *tp = netdev_priv(dev);
1872
1873         return mii_ethtool_gset(&tp->mii, cmd);
1874 }
1875
1876 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1877 {
1878         struct rtl8169_private *tp = netdev_priv(dev);
1879         int rc;
1880
1881         rtl_lock_work(tp);
1882         rc = tp->get_settings(dev, cmd);
1883         rtl_unlock_work(tp);
1884
1885         return rc;
1886 }
1887
1888 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1889                              void *p)
1890 {
1891         struct rtl8169_private *tp = netdev_priv(dev);
1892
1893         if (regs->len > R8169_REGS_SIZE)
1894                 regs->len = R8169_REGS_SIZE;
1895
1896         rtl_lock_work(tp);
1897         memcpy_fromio(p, tp->mmio_addr, regs->len);
1898         rtl_unlock_work(tp);
1899 }
1900
1901 static u32 rtl8169_get_msglevel(struct net_device *dev)
1902 {
1903         struct rtl8169_private *tp = netdev_priv(dev);
1904
1905         return tp->msg_enable;
1906 }
1907
1908 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1909 {
1910         struct rtl8169_private *tp = netdev_priv(dev);
1911
1912         tp->msg_enable = value;
1913 }
1914
1915 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1916         "tx_packets",
1917         "rx_packets",
1918         "tx_errors",
1919         "rx_errors",
1920         "rx_missed",
1921         "align_errors",
1922         "tx_single_collisions",
1923         "tx_multi_collisions",
1924         "unicast",
1925         "broadcast",
1926         "multicast",
1927         "tx_aborted",
1928         "tx_underrun",
1929 };
1930
1931 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1932 {
1933         switch (sset) {
1934         case ETH_SS_STATS:
1935                 return ARRAY_SIZE(rtl8169_gstrings);
1936         default:
1937                 return -EOPNOTSUPP;
1938         }
1939 }
1940
1941 DECLARE_RTL_COND(rtl_counters_cond)
1942 {
1943         void __iomem *ioaddr = tp->mmio_addr;
1944
1945         return RTL_R32(CounterAddrLow) & CounterDump;
1946 }
1947
1948 static void rtl8169_update_counters(struct net_device *dev)
1949 {
1950         struct rtl8169_private *tp = netdev_priv(dev);
1951         void __iomem *ioaddr = tp->mmio_addr;
1952         struct device *d = &tp->pci_dev->dev;
1953         struct rtl8169_counters *counters;
1954         dma_addr_t paddr;
1955         u32 cmd;
1956
1957         /*
1958          * Some chips are unable to dump tally counters when the receiver
1959          * is disabled.
1960          */
1961         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1962                 return;
1963
1964         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1965         if (!counters)
1966                 return;
1967
1968         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1969         cmd = (u64)paddr & DMA_BIT_MASK(32);
1970         RTL_W32(CounterAddrLow, cmd);
1971         RTL_W32(CounterAddrLow, cmd | CounterDump);
1972
1973         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1974                 memcpy(&tp->counters, counters, sizeof(*counters));
1975
1976         RTL_W32(CounterAddrLow, 0);
1977         RTL_W32(CounterAddrHigh, 0);
1978
1979         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1980 }
1981
1982 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1983                                       struct ethtool_stats *stats, u64 *data)
1984 {
1985         struct rtl8169_private *tp = netdev_priv(dev);
1986
1987         ASSERT_RTNL();
1988
1989         rtl8169_update_counters(dev);
1990
1991         data[0] = le64_to_cpu(tp->counters.tx_packets);
1992         data[1] = le64_to_cpu(tp->counters.rx_packets);
1993         data[2] = le64_to_cpu(tp->counters.tx_errors);
1994         data[3] = le32_to_cpu(tp->counters.rx_errors);
1995         data[4] = le16_to_cpu(tp->counters.rx_missed);
1996         data[5] = le16_to_cpu(tp->counters.align_errors);
1997         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1998         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1999         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2000         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2001         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2002         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2003         data[12] = le16_to_cpu(tp->counters.tx_underun);
2004 }
2005
2006 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2007 {
2008         switch(stringset) {
2009         case ETH_SS_STATS:
2010                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2011                 break;
2012         }
2013 }
2014
2015 static const struct ethtool_ops rtl8169_ethtool_ops = {
2016         .get_drvinfo            = rtl8169_get_drvinfo,
2017         .get_regs_len           = rtl8169_get_regs_len,
2018         .get_link               = ethtool_op_get_link,
2019         .get_settings           = rtl8169_get_settings,
2020         .set_settings           = rtl8169_set_settings,
2021         .get_msglevel           = rtl8169_get_msglevel,
2022         .set_msglevel           = rtl8169_set_msglevel,
2023         .get_regs               = rtl8169_get_regs,
2024         .get_wol                = rtl8169_get_wol,
2025         .set_wol                = rtl8169_set_wol,
2026         .get_strings            = rtl8169_get_strings,
2027         .get_sset_count         = rtl8169_get_sset_count,
2028         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2029         .get_ts_info            = ethtool_op_get_ts_info,
2030 };
2031
2032 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2033                                     struct net_device *dev, u8 default_version)
2034 {
2035         void __iomem *ioaddr = tp->mmio_addr;
2036         /*
2037          * The driver currently handles the 8168Bf and the 8168Be identically
2038          * but they can be identified more specifically through the test below
2039          * if needed:
2040          *
2041          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2042          *
2043          * Same thing for the 8101Eb and the 8101Ec:
2044          *
2045          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2046          */
2047         static const struct rtl_mac_info {
2048                 u32 mask;
2049                 u32 val;
2050                 int mac_version;
2051         } mac_info[] = {
2052                 /* 8168G family. */
2053                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2054                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2055                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2056
2057                 /* 8168F family. */
2058                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2059                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2060                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2061
2062                 /* 8168E family. */
2063                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2064                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2065                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2066                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2067
2068                 /* 8168D family. */
2069                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2070                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2071                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2072
2073                 /* 8168DP family. */
2074                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2075                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2076                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2077
2078                 /* 8168C family. */
2079                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2080                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2081                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2082                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2083                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2084                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2085                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2086                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2087                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2088
2089                 /* 8168B family. */
2090                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2091                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2092                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2093                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2094
2095                 /* 8101 family. */
2096                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2097                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2098                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2099                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2100                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2101                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2102                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2103                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2104                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2105                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2106                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2107                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2108                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2109                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2110                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2111                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2112                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2113                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2114                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2115                 /* FIXME: where did these entries come from ? -- FR */
2116                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2117                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2118
2119                 /* 8110 family. */
2120                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2121                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2122                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2123                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2124                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2125                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2126
2127                 /* Catch-all */
2128                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2129         };
2130         const struct rtl_mac_info *p = mac_info;
2131         u32 reg;
2132
2133         reg = RTL_R32(TxConfig);
2134         while ((reg & p->mask) != p->val)
2135                 p++;
2136         tp->mac_version = p->mac_version;
2137
2138         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2139                 netif_notice(tp, probe, dev,
2140                              "unknown MAC, using family default\n");
2141                 tp->mac_version = default_version;
2142         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2143                 tp->mac_version = tp->mii.supports_gmii ?
2144                                   RTL_GIGA_MAC_VER_42 :
2145                                   RTL_GIGA_MAC_VER_43;
2146         }
2147 }
2148
2149 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2150 {
2151         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2152 }
2153
2154 struct phy_reg {
2155         u16 reg;
2156         u16 val;
2157 };
2158
2159 static void rtl_writephy_batch(struct rtl8169_private *tp,
2160                                const struct phy_reg *regs, int len)
2161 {
2162         while (len-- > 0) {
2163                 rtl_writephy(tp, regs->reg, regs->val);
2164                 regs++;
2165         }
2166 }
2167
2168 #define PHY_READ                0x00000000
2169 #define PHY_DATA_OR             0x10000000
2170 #define PHY_DATA_AND            0x20000000
2171 #define PHY_BJMPN               0x30000000
2172 #define PHY_MDIO_CHG            0x40000000
2173 #define PHY_CLEAR_READCOUNT     0x70000000
2174 #define PHY_WRITE               0x80000000
2175 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2176 #define PHY_COMP_EQ_SKIPN       0xa0000000
2177 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2178 #define PHY_WRITE_PREVIOUS      0xc0000000
2179 #define PHY_SKIPN               0xd0000000
2180 #define PHY_DELAY_MS            0xe0000000
2181
2182 struct fw_info {
2183         u32     magic;
2184         char    version[RTL_VER_SIZE];
2185         __le32  fw_start;
2186         __le32  fw_len;
2187         u8      chksum;
2188 } __packed;
2189
2190 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2191
2192 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2193 {
2194         const struct firmware *fw = rtl_fw->fw;
2195         struct fw_info *fw_info = (struct fw_info *)fw->data;
2196         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2197         char *version = rtl_fw->version;
2198         bool rc = false;
2199
2200         if (fw->size < FW_OPCODE_SIZE)
2201                 goto out;
2202
2203         if (!fw_info->magic) {
2204                 size_t i, size, start;
2205                 u8 checksum = 0;
2206
2207                 if (fw->size < sizeof(*fw_info))
2208                         goto out;
2209
2210                 for (i = 0; i < fw->size; i++)
2211                         checksum += fw->data[i];
2212                 if (checksum != 0)
2213                         goto out;
2214
2215                 start = le32_to_cpu(fw_info->fw_start);
2216                 if (start > fw->size)
2217                         goto out;
2218
2219                 size = le32_to_cpu(fw_info->fw_len);
2220                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2221                         goto out;
2222
2223                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2224
2225                 pa->code = (__le32 *)(fw->data + start);
2226                 pa->size = size;
2227         } else {
2228                 if (fw->size % FW_OPCODE_SIZE)
2229                         goto out;
2230
2231                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2232
2233                 pa->code = (__le32 *)fw->data;
2234                 pa->size = fw->size / FW_OPCODE_SIZE;
2235         }
2236         version[RTL_VER_SIZE - 1] = 0;
2237
2238         rc = true;
2239 out:
2240         return rc;
2241 }
2242
2243 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2244                            struct rtl_fw_phy_action *pa)
2245 {
2246         bool rc = false;
2247         size_t index;
2248
2249         for (index = 0; index < pa->size; index++) {
2250                 u32 action = le32_to_cpu(pa->code[index]);
2251                 u32 regno = (action & 0x0fff0000) >> 16;
2252
2253                 switch(action & 0xf0000000) {
2254                 case PHY_READ:
2255                 case PHY_DATA_OR:
2256                 case PHY_DATA_AND:
2257                 case PHY_MDIO_CHG:
2258                 case PHY_CLEAR_READCOUNT:
2259                 case PHY_WRITE:
2260                 case PHY_WRITE_PREVIOUS:
2261                 case PHY_DELAY_MS:
2262                         break;
2263
2264                 case PHY_BJMPN:
2265                         if (regno > index) {
2266                                 netif_err(tp, ifup, tp->dev,
2267                                           "Out of range of firmware\n");
2268                                 goto out;
2269                         }
2270                         break;
2271                 case PHY_READCOUNT_EQ_SKIP:
2272                         if (index + 2 >= pa->size) {
2273                                 netif_err(tp, ifup, tp->dev,
2274                                           "Out of range of firmware\n");
2275                                 goto out;
2276                         }
2277                         break;
2278                 case PHY_COMP_EQ_SKIPN:
2279                 case PHY_COMP_NEQ_SKIPN:
2280                 case PHY_SKIPN:
2281                         if (index + 1 + regno >= pa->size) {
2282                                 netif_err(tp, ifup, tp->dev,
2283                                           "Out of range of firmware\n");
2284                                 goto out;
2285                         }
2286                         break;
2287
2288                 default:
2289                         netif_err(tp, ifup, tp->dev,
2290                                   "Invalid action 0x%08x\n", action);
2291                         goto out;
2292                 }
2293         }
2294         rc = true;
2295 out:
2296         return rc;
2297 }
2298
2299 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2300 {
2301         struct net_device *dev = tp->dev;
2302         int rc = -EINVAL;
2303
2304         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2305                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2306                 goto out;
2307         }
2308
2309         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2310                 rc = 0;
2311 out:
2312         return rc;
2313 }
2314
2315 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2316 {
2317         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2318         struct mdio_ops org, *ops = &tp->mdio_ops;
2319         u32 predata, count;
2320         size_t index;
2321
2322         predata = count = 0;
2323         org.write = ops->write;
2324         org.read = ops->read;
2325
2326         for (index = 0; index < pa->size; ) {
2327                 u32 action = le32_to_cpu(pa->code[index]);
2328                 u32 data = action & 0x0000ffff;
2329                 u32 regno = (action & 0x0fff0000) >> 16;
2330
2331                 if (!action)
2332                         break;
2333
2334                 switch(action & 0xf0000000) {
2335                 case PHY_READ:
2336                         predata = rtl_readphy(tp, regno);
2337                         count++;
2338                         index++;
2339                         break;
2340                 case PHY_DATA_OR:
2341                         predata |= data;
2342                         index++;
2343                         break;
2344                 case PHY_DATA_AND:
2345                         predata &= data;
2346                         index++;
2347                         break;
2348                 case PHY_BJMPN:
2349                         index -= regno;
2350                         break;
2351                 case PHY_MDIO_CHG:
2352                         if (data == 0) {
2353                                 ops->write = org.write;
2354                                 ops->read = org.read;
2355                         } else if (data == 1) {
2356                                 ops->write = mac_mcu_write;
2357                                 ops->read = mac_mcu_read;
2358                         }
2359
2360                         index++;
2361                         break;
2362                 case PHY_CLEAR_READCOUNT:
2363                         count = 0;
2364                         index++;
2365                         break;
2366                 case PHY_WRITE:
2367                         rtl_writephy(tp, regno, data);
2368                         index++;
2369                         break;
2370                 case PHY_READCOUNT_EQ_SKIP:
2371                         index += (count == data) ? 2 : 1;
2372                         break;
2373                 case PHY_COMP_EQ_SKIPN:
2374                         if (predata == data)
2375                                 index += regno;
2376                         index++;
2377                         break;
2378                 case PHY_COMP_NEQ_SKIPN:
2379                         if (predata != data)
2380                                 index += regno;
2381                         index++;
2382                         break;
2383                 case PHY_WRITE_PREVIOUS:
2384                         rtl_writephy(tp, regno, predata);
2385                         index++;
2386                         break;
2387                 case PHY_SKIPN:
2388                         index += regno + 1;
2389                         break;
2390                 case PHY_DELAY_MS:
2391                         mdelay(data);
2392                         index++;
2393                         break;
2394
2395                 default:
2396                         BUG();
2397                 }
2398         }
2399
2400         ops->write = org.write;
2401         ops->read = org.read;
2402 }
2403
2404 static void rtl_release_firmware(struct rtl8169_private *tp)
2405 {
2406         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2407                 release_firmware(tp->rtl_fw->fw);
2408                 kfree(tp->rtl_fw);
2409         }
2410         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2411 }
2412
2413 static void rtl_apply_firmware(struct rtl8169_private *tp)
2414 {
2415         struct rtl_fw *rtl_fw = tp->rtl_fw;
2416
2417         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2418         if (!IS_ERR_OR_NULL(rtl_fw))
2419                 rtl_phy_write_fw(tp, rtl_fw);
2420 }
2421
2422 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2423 {
2424         if (rtl_readphy(tp, reg) != val)
2425                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2426         else
2427                 rtl_apply_firmware(tp);
2428 }
2429
2430 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2431 {
2432         static const struct phy_reg phy_reg_init[] = {
2433                 { 0x1f, 0x0001 },
2434                 { 0x06, 0x006e },
2435                 { 0x08, 0x0708 },
2436                 { 0x15, 0x4000 },
2437                 { 0x18, 0x65c7 },
2438
2439                 { 0x1f, 0x0001 },
2440                 { 0x03, 0x00a1 },
2441                 { 0x02, 0x0008 },
2442                 { 0x01, 0x0120 },
2443                 { 0x00, 0x1000 },
2444                 { 0x04, 0x0800 },
2445                 { 0x04, 0x0000 },
2446
2447                 { 0x03, 0xff41 },
2448                 { 0x02, 0xdf60 },
2449                 { 0x01, 0x0140 },
2450                 { 0x00, 0x0077 },
2451                 { 0x04, 0x7800 },
2452                 { 0x04, 0x7000 },
2453
2454                 { 0x03, 0x802f },
2455                 { 0x02, 0x4f02 },
2456                 { 0x01, 0x0409 },
2457                 { 0x00, 0xf0f9 },
2458                 { 0x04, 0x9800 },
2459                 { 0x04, 0x9000 },
2460
2461                 { 0x03, 0xdf01 },
2462                 { 0x02, 0xdf20 },
2463                 { 0x01, 0xff95 },
2464                 { 0x00, 0xba00 },
2465                 { 0x04, 0xa800 },
2466                 { 0x04, 0xa000 },
2467
2468                 { 0x03, 0xff41 },
2469                 { 0x02, 0xdf20 },
2470                 { 0x01, 0x0140 },
2471                 { 0x00, 0x00bb },
2472                 { 0x04, 0xb800 },
2473                 { 0x04, 0xb000 },
2474
2475                 { 0x03, 0xdf41 },
2476                 { 0x02, 0xdc60 },
2477                 { 0x01, 0x6340 },
2478                 { 0x00, 0x007d },
2479                 { 0x04, 0xd800 },
2480                 { 0x04, 0xd000 },
2481
2482                 { 0x03, 0xdf01 },
2483                 { 0x02, 0xdf20 },
2484                 { 0x01, 0x100a },
2485                 { 0x00, 0xa0ff },
2486                 { 0x04, 0xf800 },
2487                 { 0x04, 0xf000 },
2488
2489                 { 0x1f, 0x0000 },
2490                 { 0x0b, 0x0000 },
2491                 { 0x00, 0x9200 }
2492         };
2493
2494         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2495 }
2496
2497 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2498 {
2499         static const struct phy_reg phy_reg_init[] = {
2500                 { 0x1f, 0x0002 },
2501                 { 0x01, 0x90d0 },
2502                 { 0x1f, 0x0000 }
2503         };
2504
2505         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2506 }
2507
2508 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2509 {
2510         struct pci_dev *pdev = tp->pci_dev;
2511
2512         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2513             (pdev->subsystem_device != 0xe000))
2514                 return;
2515
2516         rtl_writephy(tp, 0x1f, 0x0001);
2517         rtl_writephy(tp, 0x10, 0xf01b);
2518         rtl_writephy(tp, 0x1f, 0x0000);
2519 }
2520
2521 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2522 {
2523         static const struct phy_reg phy_reg_init[] = {
2524                 { 0x1f, 0x0001 },
2525                 { 0x04, 0x0000 },
2526                 { 0x03, 0x00a1 },
2527                 { 0x02, 0x0008 },
2528                 { 0x01, 0x0120 },
2529                 { 0x00, 0x1000 },
2530                 { 0x04, 0x0800 },
2531                 { 0x04, 0x9000 },
2532                 { 0x03, 0x802f },
2533                 { 0x02, 0x4f02 },
2534                 { 0x01, 0x0409 },
2535                 { 0x00, 0xf099 },
2536                 { 0x04, 0x9800 },
2537                 { 0x04, 0xa000 },
2538                 { 0x03, 0xdf01 },
2539                 { 0x02, 0xdf20 },
2540                 { 0x01, 0xff95 },
2541                 { 0x00, 0xba00 },
2542                 { 0x04, 0xa800 },
2543                 { 0x04, 0xf000 },
2544                 { 0x03, 0xdf01 },
2545                 { 0x02, 0xdf20 },
2546                 { 0x01, 0x101a },
2547                 { 0x00, 0xa0ff },
2548                 { 0x04, 0xf800 },
2549                 { 0x04, 0x0000 },
2550                 { 0x1f, 0x0000 },
2551
2552                 { 0x1f, 0x0001 },
2553                 { 0x10, 0xf41b },
2554                 { 0x14, 0xfb54 },
2555                 { 0x18, 0xf5c7 },
2556                 { 0x1f, 0x0000 },
2557
2558                 { 0x1f, 0x0001 },
2559                 { 0x17, 0x0cc0 },
2560                 { 0x1f, 0x0000 }
2561         };
2562
2563         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2564
2565         rtl8169scd_hw_phy_config_quirk(tp);
2566 }
2567
2568 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2569 {
2570         static const struct phy_reg phy_reg_init[] = {
2571                 { 0x1f, 0x0001 },
2572                 { 0x04, 0x0000 },
2573                 { 0x03, 0x00a1 },
2574                 { 0x02, 0x0008 },
2575                 { 0x01, 0x0120 },
2576                 { 0x00, 0x1000 },
2577                 { 0x04, 0x0800 },
2578                 { 0x04, 0x9000 },
2579                 { 0x03, 0x802f },
2580                 { 0x02, 0x4f02 },
2581                 { 0x01, 0x0409 },
2582                 { 0x00, 0xf099 },
2583                 { 0x04, 0x9800 },
2584                 { 0x04, 0xa000 },
2585                 { 0x03, 0xdf01 },
2586                 { 0x02, 0xdf20 },
2587                 { 0x01, 0xff95 },
2588                 { 0x00, 0xba00 },
2589                 { 0x04, 0xa800 },
2590                 { 0x04, 0xf000 },
2591                 { 0x03, 0xdf01 },
2592                 { 0x02, 0xdf20 },
2593                 { 0x01, 0x101a },
2594                 { 0x00, 0xa0ff },
2595                 { 0x04, 0xf800 },
2596                 { 0x04, 0x0000 },
2597                 { 0x1f, 0x0000 },
2598
2599                 { 0x1f, 0x0001 },
2600                 { 0x0b, 0x8480 },
2601                 { 0x1f, 0x0000 },
2602
2603                 { 0x1f, 0x0001 },
2604                 { 0x18, 0x67c7 },
2605                 { 0x04, 0x2000 },
2606                 { 0x03, 0x002f },
2607                 { 0x02, 0x4360 },
2608                 { 0x01, 0x0109 },
2609                 { 0x00, 0x3022 },
2610                 { 0x04, 0x2800 },
2611                 { 0x1f, 0x0000 },
2612
2613                 { 0x1f, 0x0001 },
2614                 { 0x17, 0x0cc0 },
2615                 { 0x1f, 0x0000 }
2616         };
2617
2618         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2619 }
2620
2621 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2622 {
2623         static const struct phy_reg phy_reg_init[] = {
2624                 { 0x10, 0xf41b },
2625                 { 0x1f, 0x0000 }
2626         };
2627
2628         rtl_writephy(tp, 0x1f, 0x0001);
2629         rtl_patchphy(tp, 0x16, 1 << 0);
2630
2631         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2632 }
2633
2634 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2635 {
2636         static const struct phy_reg phy_reg_init[] = {
2637                 { 0x1f, 0x0001 },
2638                 { 0x10, 0xf41b },
2639                 { 0x1f, 0x0000 }
2640         };
2641
2642         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2643 }
2644
2645 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2646 {
2647         static const struct phy_reg phy_reg_init[] = {
2648                 { 0x1f, 0x0000 },
2649                 { 0x1d, 0x0f00 },
2650                 { 0x1f, 0x0002 },
2651                 { 0x0c, 0x1ec8 },
2652                 { 0x1f, 0x0000 }
2653         };
2654
2655         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2656 }
2657
2658 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2659 {
2660         static const struct phy_reg phy_reg_init[] = {
2661                 { 0x1f, 0x0001 },
2662                 { 0x1d, 0x3d98 },
2663                 { 0x1f, 0x0000 }
2664         };
2665
2666         rtl_writephy(tp, 0x1f, 0x0000);
2667         rtl_patchphy(tp, 0x14, 1 << 5);
2668         rtl_patchphy(tp, 0x0d, 1 << 5);
2669
2670         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2671 }
2672
2673 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2674 {
2675         static const struct phy_reg phy_reg_init[] = {
2676                 { 0x1f, 0x0001 },
2677                 { 0x12, 0x2300 },
2678                 { 0x1f, 0x0002 },
2679                 { 0x00, 0x88d4 },
2680                 { 0x01, 0x82b1 },
2681                 { 0x03, 0x7002 },
2682                 { 0x08, 0x9e30 },
2683                 { 0x09, 0x01f0 },
2684                 { 0x0a, 0x5500 },
2685                 { 0x0c, 0x00c8 },
2686                 { 0x1f, 0x0003 },
2687                 { 0x12, 0xc096 },
2688                 { 0x16, 0x000a },
2689                 { 0x1f, 0x0000 },
2690                 { 0x1f, 0x0000 },
2691                 { 0x09, 0x2000 },
2692                 { 0x09, 0x0000 }
2693         };
2694
2695         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2696
2697         rtl_patchphy(tp, 0x14, 1 << 5);
2698         rtl_patchphy(tp, 0x0d, 1 << 5);
2699         rtl_writephy(tp, 0x1f, 0x0000);
2700 }
2701
2702 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2703 {
2704         static const struct phy_reg phy_reg_init[] = {
2705                 { 0x1f, 0x0001 },
2706                 { 0x12, 0x2300 },
2707                 { 0x03, 0x802f },
2708                 { 0x02, 0x4f02 },
2709                 { 0x01, 0x0409 },
2710                 { 0x00, 0xf099 },
2711                 { 0x04, 0x9800 },
2712                 { 0x04, 0x9000 },
2713                 { 0x1d, 0x3d98 },
2714                 { 0x1f, 0x0002 },
2715                 { 0x0c, 0x7eb8 },
2716                 { 0x06, 0x0761 },
2717                 { 0x1f, 0x0003 },
2718                 { 0x16, 0x0f0a },
2719                 { 0x1f, 0x0000 }
2720         };
2721
2722         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2723
2724         rtl_patchphy(tp, 0x16, 1 << 0);
2725         rtl_patchphy(tp, 0x14, 1 << 5);
2726         rtl_patchphy(tp, 0x0d, 1 << 5);
2727         rtl_writephy(tp, 0x1f, 0x0000);
2728 }
2729
2730 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2731 {
2732         static const struct phy_reg phy_reg_init[] = {
2733                 { 0x1f, 0x0001 },
2734                 { 0x12, 0x2300 },
2735                 { 0x1d, 0x3d98 },
2736                 { 0x1f, 0x0002 },
2737                 { 0x0c, 0x7eb8 },
2738                 { 0x06, 0x5461 },
2739                 { 0x1f, 0x0003 },
2740                 { 0x16, 0x0f0a },
2741                 { 0x1f, 0x0000 }
2742         };
2743
2744         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2745
2746         rtl_patchphy(tp, 0x16, 1 << 0);
2747         rtl_patchphy(tp, 0x14, 1 << 5);
2748         rtl_patchphy(tp, 0x0d, 1 << 5);
2749         rtl_writephy(tp, 0x1f, 0x0000);
2750 }
2751
2752 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2753 {
2754         rtl8168c_3_hw_phy_config(tp);
2755 }
2756
2757 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2758 {
2759         static const struct phy_reg phy_reg_init_0[] = {
2760                 /* Channel Estimation */
2761                 { 0x1f, 0x0001 },
2762                 { 0x06, 0x4064 },
2763                 { 0x07, 0x2863 },
2764                 { 0x08, 0x059c },
2765                 { 0x09, 0x26b4 },
2766                 { 0x0a, 0x6a19 },
2767                 { 0x0b, 0xdcc8 },
2768                 { 0x10, 0xf06d },
2769                 { 0x14, 0x7f68 },
2770                 { 0x18, 0x7fd9 },
2771                 { 0x1c, 0xf0ff },
2772                 { 0x1d, 0x3d9c },
2773                 { 0x1f, 0x0003 },
2774                 { 0x12, 0xf49f },
2775                 { 0x13, 0x070b },
2776                 { 0x1a, 0x05ad },
2777                 { 0x14, 0x94c0 },
2778
2779                 /*
2780                  * Tx Error Issue
2781                  * Enhance line driver power
2782                  */
2783                 { 0x1f, 0x0002 },
2784                 { 0x06, 0x5561 },
2785                 { 0x1f, 0x0005 },
2786                 { 0x05, 0x8332 },
2787                 { 0x06, 0x5561 },
2788
2789                 /*
2790                  * Can not link to 1Gbps with bad cable
2791                  * Decrease SNR threshold form 21.07dB to 19.04dB
2792                  */
2793                 { 0x1f, 0x0001 },
2794                 { 0x17, 0x0cc0 },
2795
2796                 { 0x1f, 0x0000 },
2797                 { 0x0d, 0xf880 }
2798         };
2799
2800         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2801
2802         /*
2803          * Rx Error Issue
2804          * Fine Tune Switching regulator parameter
2805          */
2806         rtl_writephy(tp, 0x1f, 0x0002);
2807         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2808         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2809
2810         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2811                 static const struct phy_reg phy_reg_init[] = {
2812                         { 0x1f, 0x0002 },
2813                         { 0x05, 0x669a },
2814                         { 0x1f, 0x0005 },
2815                         { 0x05, 0x8330 },
2816                         { 0x06, 0x669a },
2817                         { 0x1f, 0x0002 }
2818                 };
2819                 int val;
2820
2821                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2822
2823                 val = rtl_readphy(tp, 0x0d);
2824
2825                 if ((val & 0x00ff) != 0x006c) {
2826                         static const u32 set[] = {
2827                                 0x0065, 0x0066, 0x0067, 0x0068,
2828                                 0x0069, 0x006a, 0x006b, 0x006c
2829                         };
2830                         int i;
2831
2832                         rtl_writephy(tp, 0x1f, 0x0002);
2833
2834                         val &= 0xff00;
2835                         for (i = 0; i < ARRAY_SIZE(set); i++)
2836                                 rtl_writephy(tp, 0x0d, val | set[i]);
2837                 }
2838         } else {
2839                 static const struct phy_reg phy_reg_init[] = {
2840                         { 0x1f, 0x0002 },
2841                         { 0x05, 0x6662 },
2842                         { 0x1f, 0x0005 },
2843                         { 0x05, 0x8330 },
2844                         { 0x06, 0x6662 }
2845                 };
2846
2847                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2848         }
2849
2850         /* RSET couple improve */
2851         rtl_writephy(tp, 0x1f, 0x0002);
2852         rtl_patchphy(tp, 0x0d, 0x0300);
2853         rtl_patchphy(tp, 0x0f, 0x0010);
2854
2855         /* Fine tune PLL performance */
2856         rtl_writephy(tp, 0x1f, 0x0002);
2857         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2858         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2859
2860         rtl_writephy(tp, 0x1f, 0x0005);
2861         rtl_writephy(tp, 0x05, 0x001b);
2862
2863         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2864
2865         rtl_writephy(tp, 0x1f, 0x0000);
2866 }
2867
2868 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2869 {
2870         static const struct phy_reg phy_reg_init_0[] = {
2871                 /* Channel Estimation */
2872                 { 0x1f, 0x0001 },
2873                 { 0x06, 0x4064 },
2874                 { 0x07, 0x2863 },
2875                 { 0x08, 0x059c },
2876                 { 0x09, 0x26b4 },
2877                 { 0x0a, 0x6a19 },
2878                 { 0x0b, 0xdcc8 },
2879                 { 0x10, 0xf06d },
2880                 { 0x14, 0x7f68 },
2881                 { 0x18, 0x7fd9 },
2882                 { 0x1c, 0xf0ff },
2883                 { 0x1d, 0x3d9c },
2884                 { 0x1f, 0x0003 },
2885                 { 0x12, 0xf49f },
2886                 { 0x13, 0x070b },
2887                 { 0x1a, 0x05ad },
2888                 { 0x14, 0x94c0 },
2889
2890                 /*
2891                  * Tx Error Issue
2892                  * Enhance line driver power
2893                  */
2894                 { 0x1f, 0x0002 },
2895                 { 0x06, 0x5561 },
2896                 { 0x1f, 0x0005 },
2897                 { 0x05, 0x8332 },
2898                 { 0x06, 0x5561 },
2899
2900                 /*
2901                  * Can not link to 1Gbps with bad cable
2902                  * Decrease SNR threshold form 21.07dB to 19.04dB
2903                  */
2904                 { 0x1f, 0x0001 },
2905                 { 0x17, 0x0cc0 },
2906
2907                 { 0x1f, 0x0000 },
2908                 { 0x0d, 0xf880 }
2909         };
2910
2911         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2912
2913         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2914                 static const struct phy_reg phy_reg_init[] = {
2915                         { 0x1f, 0x0002 },
2916                         { 0x05, 0x669a },
2917                         { 0x1f, 0x0005 },
2918                         { 0x05, 0x8330 },
2919                         { 0x06, 0x669a },
2920
2921                         { 0x1f, 0x0002 }
2922                 };
2923                 int val;
2924
2925                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2926
2927                 val = rtl_readphy(tp, 0x0d);
2928                 if ((val & 0x00ff) != 0x006c) {
2929                         static const u32 set[] = {
2930                                 0x0065, 0x0066, 0x0067, 0x0068,
2931                                 0x0069, 0x006a, 0x006b, 0x006c
2932                         };
2933                         int i;
2934
2935                         rtl_writephy(tp, 0x1f, 0x0002);
2936
2937                         val &= 0xff00;
2938                         for (i = 0; i < ARRAY_SIZE(set); i++)
2939                                 rtl_writephy(tp, 0x0d, val | set[i]);
2940                 }
2941         } else {
2942                 static const struct phy_reg phy_reg_init[] = {
2943                         { 0x1f, 0x0002 },
2944                         { 0x05, 0x2642 },
2945                         { 0x1f, 0x0005 },
2946                         { 0x05, 0x8330 },
2947                         { 0x06, 0x2642 }
2948                 };
2949
2950                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2951         }
2952
2953         /* Fine tune PLL performance */
2954         rtl_writephy(tp, 0x1f, 0x0002);
2955         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2956         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2957
2958         /* Switching regulator Slew rate */
2959         rtl_writephy(tp, 0x1f, 0x0002);
2960         rtl_patchphy(tp, 0x0f, 0x0017);
2961
2962         rtl_writephy(tp, 0x1f, 0x0005);
2963         rtl_writephy(tp, 0x05, 0x001b);
2964
2965         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2966
2967         rtl_writephy(tp, 0x1f, 0x0000);
2968 }
2969
2970 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2971 {
2972         static const struct phy_reg phy_reg_init[] = {
2973                 { 0x1f, 0x0002 },
2974                 { 0x10, 0x0008 },
2975                 { 0x0d, 0x006c },
2976
2977                 { 0x1f, 0x0000 },
2978                 { 0x0d, 0xf880 },
2979
2980                 { 0x1f, 0x0001 },
2981                 { 0x17, 0x0cc0 },
2982
2983                 { 0x1f, 0x0001 },
2984                 { 0x0b, 0xa4d8 },
2985                 { 0x09, 0x281c },
2986                 { 0x07, 0x2883 },
2987                 { 0x0a, 0x6b35 },
2988                 { 0x1d, 0x3da4 },
2989                 { 0x1c, 0xeffd },
2990                 { 0x14, 0x7f52 },
2991                 { 0x18, 0x7fc6 },
2992                 { 0x08, 0x0601 },
2993                 { 0x06, 0x4063 },
2994                 { 0x10, 0xf074 },
2995                 { 0x1f, 0x0003 },
2996                 { 0x13, 0x0789 },
2997                 { 0x12, 0xf4bd },
2998                 { 0x1a, 0x04fd },
2999                 { 0x14, 0x84b0 },
3000                 { 0x1f, 0x0000 },
3001                 { 0x00, 0x9200 },
3002
3003                 { 0x1f, 0x0005 },
3004                 { 0x01, 0x0340 },
3005                 { 0x1f, 0x0001 },
3006                 { 0x04, 0x4000 },
3007                 { 0x03, 0x1d21 },
3008                 { 0x02, 0x0c32 },
3009                 { 0x01, 0x0200 },
3010                 { 0x00, 0x5554 },
3011                 { 0x04, 0x4800 },
3012                 { 0x04, 0x4000 },
3013                 { 0x04, 0xf000 },
3014                 { 0x03, 0xdf01 },
3015                 { 0x02, 0xdf20 },
3016                 { 0x01, 0x101a },
3017                 { 0x00, 0xa0ff },
3018                 { 0x04, 0xf800 },
3019                 { 0x04, 0xf000 },
3020                 { 0x1f, 0x0000 },
3021
3022                 { 0x1f, 0x0007 },
3023                 { 0x1e, 0x0023 },
3024                 { 0x16, 0x0000 },
3025                 { 0x1f, 0x0000 }
3026         };
3027
3028         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3029 }
3030
3031 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3032 {
3033         static const struct phy_reg phy_reg_init[] = {
3034                 { 0x1f, 0x0001 },
3035                 { 0x17, 0x0cc0 },
3036
3037                 { 0x1f, 0x0007 },
3038                 { 0x1e, 0x002d },
3039                 { 0x18, 0x0040 },
3040                 { 0x1f, 0x0000 }
3041         };
3042
3043         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3044         rtl_patchphy(tp, 0x0d, 1 << 5);
3045 }
3046
3047 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3048 {
3049         static const struct phy_reg phy_reg_init[] = {
3050                 /* Enable Delay cap */
3051                 { 0x1f, 0x0005 },
3052                 { 0x05, 0x8b80 },
3053                 { 0x06, 0xc896 },
3054                 { 0x1f, 0x0000 },
3055
3056                 /* Channel estimation fine tune */
3057                 { 0x1f, 0x0001 },
3058                 { 0x0b, 0x6c20 },
3059                 { 0x07, 0x2872 },
3060                 { 0x1c, 0xefff },
3061                 { 0x1f, 0x0003 },
3062                 { 0x14, 0x6420 },
3063                 { 0x1f, 0x0000 },
3064
3065                 /* Update PFM & 10M TX idle timer */
3066                 { 0x1f, 0x0007 },
3067                 { 0x1e, 0x002f },
3068                 { 0x15, 0x1919 },
3069                 { 0x1f, 0x0000 },
3070
3071                 { 0x1f, 0x0007 },
3072                 { 0x1e, 0x00ac },
3073                 { 0x18, 0x0006 },
3074                 { 0x1f, 0x0000 }
3075         };
3076
3077         rtl_apply_firmware(tp);
3078
3079         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3080
3081         /* DCO enable for 10M IDLE Power */
3082         rtl_writephy(tp, 0x1f, 0x0007);
3083         rtl_writephy(tp, 0x1e, 0x0023);
3084         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3085         rtl_writephy(tp, 0x1f, 0x0000);
3086
3087         /* For impedance matching */
3088         rtl_writephy(tp, 0x1f, 0x0002);
3089         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3090         rtl_writephy(tp, 0x1f, 0x0000);
3091
3092         /* PHY auto speed down */
3093         rtl_writephy(tp, 0x1f, 0x0007);
3094         rtl_writephy(tp, 0x1e, 0x002d);
3095         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3096         rtl_writephy(tp, 0x1f, 0x0000);
3097         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3098
3099         rtl_writephy(tp, 0x1f, 0x0005);
3100         rtl_writephy(tp, 0x05, 0x8b86);
3101         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3102         rtl_writephy(tp, 0x1f, 0x0000);
3103
3104         rtl_writephy(tp, 0x1f, 0x0005);
3105         rtl_writephy(tp, 0x05, 0x8b85);
3106         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3107         rtl_writephy(tp, 0x1f, 0x0007);
3108         rtl_writephy(tp, 0x1e, 0x0020);
3109         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3110         rtl_writephy(tp, 0x1f, 0x0006);
3111         rtl_writephy(tp, 0x00, 0x5a00);
3112         rtl_writephy(tp, 0x1f, 0x0000);
3113         rtl_writephy(tp, 0x0d, 0x0007);
3114         rtl_writephy(tp, 0x0e, 0x003c);
3115         rtl_writephy(tp, 0x0d, 0x4007);
3116         rtl_writephy(tp, 0x0e, 0x0000);
3117         rtl_writephy(tp, 0x0d, 0x0000);
3118 }
3119
3120 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3121 {
3122         const u16 w[] = {
3123                 addr[0] | (addr[1] << 8),
3124                 addr[2] | (addr[3] << 8),
3125                 addr[4] | (addr[5] << 8)
3126         };
3127         const struct exgmac_reg e[] = {
3128                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3129                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3130                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3131                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3132         };
3133
3134         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3135 }
3136
3137 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3138 {
3139         static const struct phy_reg phy_reg_init[] = {
3140                 /* Enable Delay cap */
3141                 { 0x1f, 0x0004 },
3142                 { 0x1f, 0x0007 },
3143                 { 0x1e, 0x00ac },
3144                 { 0x18, 0x0006 },
3145                 { 0x1f, 0x0002 },
3146                 { 0x1f, 0x0000 },
3147                 { 0x1f, 0x0000 },
3148
3149                 /* Channel estimation fine tune */
3150                 { 0x1f, 0x0003 },
3151                 { 0x09, 0xa20f },
3152                 { 0x1f, 0x0000 },
3153                 { 0x1f, 0x0000 },
3154
3155                 /* Green Setting */
3156                 { 0x1f, 0x0005 },
3157                 { 0x05, 0x8b5b },
3158                 { 0x06, 0x9222 },
3159                 { 0x05, 0x8b6d },
3160                 { 0x06, 0x8000 },
3161                 { 0x05, 0x8b76 },
3162                 { 0x06, 0x8000 },
3163                 { 0x1f, 0x0000 }
3164         };
3165
3166         rtl_apply_firmware(tp);
3167
3168         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3169
3170         /* For 4-corner performance improve */
3171         rtl_writephy(tp, 0x1f, 0x0005);
3172         rtl_writephy(tp, 0x05, 0x8b80);
3173         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3174         rtl_writephy(tp, 0x1f, 0x0000);
3175
3176         /* PHY auto speed down */
3177         rtl_writephy(tp, 0x1f, 0x0004);
3178         rtl_writephy(tp, 0x1f, 0x0007);
3179         rtl_writephy(tp, 0x1e, 0x002d);
3180         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3181         rtl_writephy(tp, 0x1f, 0x0002);
3182         rtl_writephy(tp, 0x1f, 0x0000);
3183         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3184
3185         /* improve 10M EEE waveform */
3186         rtl_writephy(tp, 0x1f, 0x0005);
3187         rtl_writephy(tp, 0x05, 0x8b86);
3188         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3189         rtl_writephy(tp, 0x1f, 0x0000);
3190
3191         /* Improve 2-pair detection performance */
3192         rtl_writephy(tp, 0x1f, 0x0005);
3193         rtl_writephy(tp, 0x05, 0x8b85);
3194         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3195         rtl_writephy(tp, 0x1f, 0x0000);
3196
3197         /* EEE setting */
3198         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3199         rtl_writephy(tp, 0x1f, 0x0005);
3200         rtl_writephy(tp, 0x05, 0x8b85);
3201         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3202         rtl_writephy(tp, 0x1f, 0x0004);
3203         rtl_writephy(tp, 0x1f, 0x0007);
3204         rtl_writephy(tp, 0x1e, 0x0020);
3205         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3206         rtl_writephy(tp, 0x1f, 0x0002);
3207         rtl_writephy(tp, 0x1f, 0x0000);
3208         rtl_writephy(tp, 0x0d, 0x0007);
3209         rtl_writephy(tp, 0x0e, 0x003c);
3210         rtl_writephy(tp, 0x0d, 0x4007);
3211         rtl_writephy(tp, 0x0e, 0x0000);
3212         rtl_writephy(tp, 0x0d, 0x0000);
3213
3214         /* Green feature */
3215         rtl_writephy(tp, 0x1f, 0x0003);
3216         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3217         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3218         rtl_writephy(tp, 0x1f, 0x0000);
3219
3220         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3221         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3222 }
3223
3224 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3225 {
3226         /* For 4-corner performance improve */
3227         rtl_writephy(tp, 0x1f, 0x0005);
3228         rtl_writephy(tp, 0x05, 0x8b80);
3229         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3230         rtl_writephy(tp, 0x1f, 0x0000);
3231
3232         /* PHY auto speed down */
3233         rtl_writephy(tp, 0x1f, 0x0007);
3234         rtl_writephy(tp, 0x1e, 0x002d);
3235         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3236         rtl_writephy(tp, 0x1f, 0x0000);
3237         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3238
3239         /* Improve 10M EEE waveform */
3240         rtl_writephy(tp, 0x1f, 0x0005);
3241         rtl_writephy(tp, 0x05, 0x8b86);
3242         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3243         rtl_writephy(tp, 0x1f, 0x0000);
3244 }
3245
3246 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3247 {
3248         static const struct phy_reg phy_reg_init[] = {
3249                 /* Channel estimation fine tune */
3250                 { 0x1f, 0x0003 },
3251                 { 0x09, 0xa20f },
3252                 { 0x1f, 0x0000 },
3253
3254                 /* Modify green table for giga & fnet */
3255                 { 0x1f, 0x0005 },
3256                 { 0x05, 0x8b55 },
3257                 { 0x06, 0x0000 },
3258                 { 0x05, 0x8b5e },
3259                 { 0x06, 0x0000 },
3260                 { 0x05, 0x8b67 },
3261                 { 0x06, 0x0000 },
3262                 { 0x05, 0x8b70 },
3263                 { 0x06, 0x0000 },
3264                 { 0x1f, 0x0000 },
3265                 { 0x1f, 0x0007 },
3266                 { 0x1e, 0x0078 },
3267                 { 0x17, 0x0000 },
3268                 { 0x19, 0x00fb },
3269                 { 0x1f, 0x0000 },
3270
3271                 /* Modify green table for 10M */
3272                 { 0x1f, 0x0005 },
3273                 { 0x05, 0x8b79 },
3274                 { 0x06, 0xaa00 },
3275                 { 0x1f, 0x0000 },
3276
3277                 /* Disable hiimpedance detection (RTCT) */
3278                 { 0x1f, 0x0003 },
3279                 { 0x01, 0x328a },
3280                 { 0x1f, 0x0000 }
3281         };
3282
3283         rtl_apply_firmware(tp);
3284
3285         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3286
3287         rtl8168f_hw_phy_config(tp);
3288
3289         /* Improve 2-pair detection performance */
3290         rtl_writephy(tp, 0x1f, 0x0005);
3291         rtl_writephy(tp, 0x05, 0x8b85);
3292         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3293         rtl_writephy(tp, 0x1f, 0x0000);
3294 }
3295
3296 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3297 {
3298         rtl_apply_firmware(tp);
3299
3300         rtl8168f_hw_phy_config(tp);
3301 }
3302
3303 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3304 {
3305         static const struct phy_reg phy_reg_init[] = {
3306                 /* Channel estimation fine tune */
3307                 { 0x1f, 0x0003 },
3308                 { 0x09, 0xa20f },
3309                 { 0x1f, 0x0000 },
3310
3311                 /* Modify green table for giga & fnet */
3312                 { 0x1f, 0x0005 },
3313                 { 0x05, 0x8b55 },
3314                 { 0x06, 0x0000 },
3315                 { 0x05, 0x8b5e },
3316                 { 0x06, 0x0000 },
3317                 { 0x05, 0x8b67 },
3318                 { 0x06, 0x0000 },
3319                 { 0x05, 0x8b70 },
3320                 { 0x06, 0x0000 },
3321                 { 0x1f, 0x0000 },
3322                 { 0x1f, 0x0007 },
3323                 { 0x1e, 0x0078 },
3324                 { 0x17, 0x0000 },
3325                 { 0x19, 0x00aa },
3326                 { 0x1f, 0x0000 },
3327
3328                 /* Modify green table for 10M */
3329                 { 0x1f, 0x0005 },
3330                 { 0x05, 0x8b79 },
3331                 { 0x06, 0xaa00 },
3332                 { 0x1f, 0x0000 },
3333
3334                 /* Disable hiimpedance detection (RTCT) */
3335                 { 0x1f, 0x0003 },
3336                 { 0x01, 0x328a },
3337                 { 0x1f, 0x0000 }
3338         };
3339
3340
3341         rtl_apply_firmware(tp);
3342
3343         rtl8168f_hw_phy_config(tp);
3344
3345         /* Improve 2-pair detection performance */
3346         rtl_writephy(tp, 0x1f, 0x0005);
3347         rtl_writephy(tp, 0x05, 0x8b85);
3348         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3349         rtl_writephy(tp, 0x1f, 0x0000);
3350
3351         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3352
3353         /* Modify green table for giga */
3354         rtl_writephy(tp, 0x1f, 0x0005);
3355         rtl_writephy(tp, 0x05, 0x8b54);
3356         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3357         rtl_writephy(tp, 0x05, 0x8b5d);
3358         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3359         rtl_writephy(tp, 0x05, 0x8a7c);
3360         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3361         rtl_writephy(tp, 0x05, 0x8a7f);
3362         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3363         rtl_writephy(tp, 0x05, 0x8a82);
3364         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3365         rtl_writephy(tp, 0x05, 0x8a85);
3366         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3367         rtl_writephy(tp, 0x05, 0x8a88);
3368         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3369         rtl_writephy(tp, 0x1f, 0x0000);
3370
3371         /* uc same-seed solution */
3372         rtl_writephy(tp, 0x1f, 0x0005);
3373         rtl_writephy(tp, 0x05, 0x8b85);
3374         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3375         rtl_writephy(tp, 0x1f, 0x0000);
3376
3377         /* eee setting */
3378         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3379         rtl_writephy(tp, 0x1f, 0x0005);
3380         rtl_writephy(tp, 0x05, 0x8b85);
3381         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3382         rtl_writephy(tp, 0x1f, 0x0004);
3383         rtl_writephy(tp, 0x1f, 0x0007);
3384         rtl_writephy(tp, 0x1e, 0x0020);
3385         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3386         rtl_writephy(tp, 0x1f, 0x0000);
3387         rtl_writephy(tp, 0x0d, 0x0007);
3388         rtl_writephy(tp, 0x0e, 0x003c);
3389         rtl_writephy(tp, 0x0d, 0x4007);
3390         rtl_writephy(tp, 0x0e, 0x0000);
3391         rtl_writephy(tp, 0x0d, 0x0000);
3392
3393         /* Green feature */
3394         rtl_writephy(tp, 0x1f, 0x0003);
3395         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3396         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3397         rtl_writephy(tp, 0x1f, 0x0000);
3398 }
3399
3400 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3401 {
3402         rtl_apply_firmware(tp);
3403
3404         rtl_writephy(tp, 0x1f, 0x0a46);
3405         if (rtl_readphy(tp, 0x10) & 0x0100) {
3406                 rtl_writephy(tp, 0x1f, 0x0bcc);
3407                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3408         } else {
3409                 rtl_writephy(tp, 0x1f, 0x0bcc);
3410                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3411         }
3412
3413         rtl_writephy(tp, 0x1f, 0x0a46);
3414         if (rtl_readphy(tp, 0x13) & 0x0100) {
3415                 rtl_writephy(tp, 0x1f, 0x0c41);
3416                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3417         } else {
3418                 rtl_writephy(tp, 0x1f, 0x0c41);
3419                 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3420         }
3421
3422         /* Enable PHY auto speed down */
3423         rtl_writephy(tp, 0x1f, 0x0a44);
3424         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3425
3426         rtl_writephy(tp, 0x1f, 0x0bcc);
3427         rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3428         rtl_writephy(tp, 0x1f, 0x0a44);
3429         rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3430         rtl_writephy(tp, 0x1f, 0x0a43);
3431         rtl_writephy(tp, 0x13, 0x8084);
3432         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3433         rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3434
3435         /* EEE auto-fallback function */
3436         rtl_writephy(tp, 0x1f, 0x0a4b);
3437         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3438
3439         /* Enable UC LPF tune function */
3440         rtl_writephy(tp, 0x1f, 0x0a43);
3441         rtl_writephy(tp, 0x13, 0x8012);
3442         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3443
3444         rtl_writephy(tp, 0x1f, 0x0c42);
3445         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3446
3447         /* Improve SWR Efficiency */
3448         rtl_writephy(tp, 0x1f, 0x0bcd);
3449         rtl_writephy(tp, 0x14, 0x5065);
3450         rtl_writephy(tp, 0x14, 0xd065);
3451         rtl_writephy(tp, 0x1f, 0x0bc8);
3452         rtl_writephy(tp, 0x11, 0x5655);
3453         rtl_writephy(tp, 0x1f, 0x0bcd);
3454         rtl_writephy(tp, 0x14, 0x1065);
3455         rtl_writephy(tp, 0x14, 0x9065);
3456         rtl_writephy(tp, 0x14, 0x1065);
3457
3458         rtl_writephy(tp, 0x1f, 0x0000);
3459 }
3460
3461 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3462 {
3463         rtl_apply_firmware(tp);
3464 }
3465
3466 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3467 {
3468         static const struct phy_reg phy_reg_init[] = {
3469                 { 0x1f, 0x0003 },
3470                 { 0x08, 0x441d },
3471                 { 0x01, 0x9100 },
3472                 { 0x1f, 0x0000 }
3473         };
3474
3475         rtl_writephy(tp, 0x1f, 0x0000);
3476         rtl_patchphy(tp, 0x11, 1 << 12);
3477         rtl_patchphy(tp, 0x19, 1 << 13);
3478         rtl_patchphy(tp, 0x10, 1 << 15);
3479
3480         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3481 }
3482
3483 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3484 {
3485         static const struct phy_reg phy_reg_init[] = {
3486                 { 0x1f, 0x0005 },
3487                 { 0x1a, 0x0000 },
3488                 { 0x1f, 0x0000 },
3489
3490                 { 0x1f, 0x0004 },
3491                 { 0x1c, 0x0000 },
3492                 { 0x1f, 0x0000 },
3493
3494                 { 0x1f, 0x0001 },
3495                 { 0x15, 0x7701 },
3496                 { 0x1f, 0x0000 }
3497         };
3498
3499         /* Disable ALDPS before ram code */
3500         rtl_writephy(tp, 0x1f, 0x0000);
3501         rtl_writephy(tp, 0x18, 0x0310);
3502         msleep(100);
3503
3504         rtl_apply_firmware(tp);
3505
3506         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3507 }
3508
3509 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3510 {
3511         /* Disable ALDPS before setting firmware */
3512         rtl_writephy(tp, 0x1f, 0x0000);
3513         rtl_writephy(tp, 0x18, 0x0310);
3514         msleep(20);
3515
3516         rtl_apply_firmware(tp);
3517
3518         /* EEE setting */
3519         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3520         rtl_writephy(tp, 0x1f, 0x0004);
3521         rtl_writephy(tp, 0x10, 0x401f);
3522         rtl_writephy(tp, 0x19, 0x7030);
3523         rtl_writephy(tp, 0x1f, 0x0000);
3524 }
3525
3526 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3527 {
3528         static const struct phy_reg phy_reg_init[] = {
3529                 { 0x1f, 0x0004 },
3530                 { 0x10, 0xc07f },
3531                 { 0x19, 0x7030 },
3532                 { 0x1f, 0x0000 }
3533         };
3534
3535         /* Disable ALDPS before ram code */
3536         rtl_writephy(tp, 0x1f, 0x0000);
3537         rtl_writephy(tp, 0x18, 0x0310);
3538         msleep(100);
3539
3540         rtl_apply_firmware(tp);
3541
3542         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3543         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3544
3545         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3546 }
3547
3548 static void rtl_hw_phy_config(struct net_device *dev)
3549 {
3550         struct rtl8169_private *tp = netdev_priv(dev);
3551
3552         rtl8169_print_mac_version(tp);
3553
3554         switch (tp->mac_version) {
3555         case RTL_GIGA_MAC_VER_01:
3556                 break;
3557         case RTL_GIGA_MAC_VER_02:
3558         case RTL_GIGA_MAC_VER_03:
3559                 rtl8169s_hw_phy_config(tp);
3560                 break;
3561         case RTL_GIGA_MAC_VER_04:
3562                 rtl8169sb_hw_phy_config(tp);
3563                 break;
3564         case RTL_GIGA_MAC_VER_05:
3565                 rtl8169scd_hw_phy_config(tp);
3566                 break;
3567         case RTL_GIGA_MAC_VER_06:
3568                 rtl8169sce_hw_phy_config(tp);
3569                 break;
3570         case RTL_GIGA_MAC_VER_07:
3571         case RTL_GIGA_MAC_VER_08:
3572         case RTL_GIGA_MAC_VER_09:
3573                 rtl8102e_hw_phy_config(tp);
3574                 break;
3575         case RTL_GIGA_MAC_VER_11:
3576                 rtl8168bb_hw_phy_config(tp);
3577                 break;
3578         case RTL_GIGA_MAC_VER_12:
3579                 rtl8168bef_hw_phy_config(tp);
3580                 break;
3581         case RTL_GIGA_MAC_VER_17:
3582                 rtl8168bef_hw_phy_config(tp);
3583                 break;
3584         case RTL_GIGA_MAC_VER_18:
3585                 rtl8168cp_1_hw_phy_config(tp);
3586                 break;
3587         case RTL_GIGA_MAC_VER_19:
3588                 rtl8168c_1_hw_phy_config(tp);
3589                 break;
3590         case RTL_GIGA_MAC_VER_20:
3591                 rtl8168c_2_hw_phy_config(tp);
3592                 break;
3593         case RTL_GIGA_MAC_VER_21:
3594                 rtl8168c_3_hw_phy_config(tp);
3595                 break;
3596         case RTL_GIGA_MAC_VER_22:
3597                 rtl8168c_4_hw_phy_config(tp);
3598                 break;
3599         case RTL_GIGA_MAC_VER_23:
3600         case RTL_GIGA_MAC_VER_24:
3601                 rtl8168cp_2_hw_phy_config(tp);
3602                 break;
3603         case RTL_GIGA_MAC_VER_25:
3604                 rtl8168d_1_hw_phy_config(tp);
3605                 break;
3606         case RTL_GIGA_MAC_VER_26:
3607                 rtl8168d_2_hw_phy_config(tp);
3608                 break;
3609         case RTL_GIGA_MAC_VER_27:
3610                 rtl8168d_3_hw_phy_config(tp);
3611                 break;
3612         case RTL_GIGA_MAC_VER_28:
3613                 rtl8168d_4_hw_phy_config(tp);
3614                 break;
3615         case RTL_GIGA_MAC_VER_29:
3616         case RTL_GIGA_MAC_VER_30:
3617                 rtl8105e_hw_phy_config(tp);
3618                 break;
3619         case RTL_GIGA_MAC_VER_31:
3620                 /* None. */
3621                 break;
3622         case RTL_GIGA_MAC_VER_32:
3623         case RTL_GIGA_MAC_VER_33:
3624                 rtl8168e_1_hw_phy_config(tp);
3625                 break;
3626         case RTL_GIGA_MAC_VER_34:
3627                 rtl8168e_2_hw_phy_config(tp);
3628                 break;
3629         case RTL_GIGA_MAC_VER_35:
3630                 rtl8168f_1_hw_phy_config(tp);
3631                 break;
3632         case RTL_GIGA_MAC_VER_36:
3633                 rtl8168f_2_hw_phy_config(tp);
3634                 break;
3635
3636         case RTL_GIGA_MAC_VER_37:
3637                 rtl8402_hw_phy_config(tp);
3638                 break;
3639
3640         case RTL_GIGA_MAC_VER_38:
3641                 rtl8411_hw_phy_config(tp);
3642                 break;
3643
3644         case RTL_GIGA_MAC_VER_39:
3645                 rtl8106e_hw_phy_config(tp);
3646                 break;
3647
3648         case RTL_GIGA_MAC_VER_40:
3649                 rtl8168g_1_hw_phy_config(tp);
3650                 break;
3651         case RTL_GIGA_MAC_VER_42:
3652         case RTL_GIGA_MAC_VER_43:
3653                 rtl8168g_2_hw_phy_config(tp);
3654                 break;
3655
3656         case RTL_GIGA_MAC_VER_41:
3657         default:
3658                 break;
3659         }
3660 }
3661
3662 static void rtl_phy_work(struct rtl8169_private *tp)
3663 {
3664         struct timer_list *timer = &tp->timer;
3665         void __iomem *ioaddr = tp->mmio_addr;
3666         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3667
3668         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3669
3670         if (tp->phy_reset_pending(tp)) {
3671                 /*
3672                  * A busy loop could burn quite a few cycles on nowadays CPU.
3673                  * Let's delay the execution of the timer for a few ticks.
3674                  */
3675                 timeout = HZ/10;
3676                 goto out_mod_timer;
3677         }
3678
3679         if (tp->link_ok(ioaddr))
3680                 return;
3681
3682         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3683
3684         tp->phy_reset_enable(tp);
3685
3686 out_mod_timer:
3687         mod_timer(timer, jiffies + timeout);
3688 }
3689
3690 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3691 {
3692         if (!test_and_set_bit(flag, tp->wk.flags))
3693                 schedule_work(&tp->wk.work);
3694 }
3695
3696 static void rtl8169_phy_timer(unsigned long __opaque)
3697 {
3698         struct net_device *dev = (struct net_device *)__opaque;
3699         struct rtl8169_private *tp = netdev_priv(dev);
3700
3701         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3702 }
3703
3704 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3705                                   void __iomem *ioaddr)
3706 {
3707         iounmap(ioaddr);
3708         pci_release_regions(pdev);
3709         pci_clear_mwi(pdev);
3710         pci_disable_device(pdev);
3711         free_netdev(dev);
3712 }
3713
3714 DECLARE_RTL_COND(rtl_phy_reset_cond)
3715 {
3716         return tp->phy_reset_pending(tp);
3717 }
3718
3719 static void rtl8169_phy_reset(struct net_device *dev,
3720                               struct rtl8169_private *tp)
3721 {
3722         tp->phy_reset_enable(tp);
3723         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3724 }
3725
3726 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3727 {
3728         void __iomem *ioaddr = tp->mmio_addr;
3729
3730         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3731             (RTL_R8(PHYstatus) & TBI_Enable);
3732 }
3733
3734 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3735 {
3736         void __iomem *ioaddr = tp->mmio_addr;
3737
3738         rtl_hw_phy_config(dev);
3739
3740         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3741                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3742                 RTL_W8(0x82, 0x01);
3743         }
3744
3745         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3746
3747         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3748                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3749
3750         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3751                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3752                 RTL_W8(0x82, 0x01);
3753                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3754                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3755         }
3756
3757         rtl8169_phy_reset(dev, tp);
3758
3759         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3760                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3761                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3762                           (tp->mii.supports_gmii ?
3763                            ADVERTISED_1000baseT_Half |
3764                            ADVERTISED_1000baseT_Full : 0));
3765
3766         if (rtl_tbi_enabled(tp))
3767                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3768 }
3769
3770 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3771 {
3772         void __iomem *ioaddr = tp->mmio_addr;
3773
3774         rtl_lock_work(tp);
3775
3776         RTL_W8(Cfg9346, Cfg9346_Unlock);
3777
3778         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3779         RTL_R32(MAC4);
3780
3781         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3782         RTL_R32(MAC0);
3783
3784         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3785                 rtl_rar_exgmac_set(tp, addr);
3786
3787         RTL_W8(Cfg9346, Cfg9346_Lock);
3788
3789         rtl_unlock_work(tp);
3790 }
3791
3792 static int rtl_set_mac_address(struct net_device *dev, void *p)
3793 {
3794         struct rtl8169_private *tp = netdev_priv(dev);
3795         struct sockaddr *addr = p;
3796
3797         if (!is_valid_ether_addr(addr->sa_data))
3798                 return -EADDRNOTAVAIL;
3799
3800         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3801
3802         rtl_rar_set(tp, dev->dev_addr);
3803
3804         return 0;
3805 }
3806
3807 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3808 {
3809         struct rtl8169_private *tp = netdev_priv(dev);
3810         struct mii_ioctl_data *data = if_mii(ifr);
3811
3812         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3813 }
3814
3815 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3816                           struct mii_ioctl_data *data, int cmd)
3817 {
3818         switch (cmd) {
3819         case SIOCGMIIPHY:
3820                 data->phy_id = 32; /* Internal PHY */
3821                 return 0;
3822
3823         case SIOCGMIIREG:
3824                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3825                 return 0;
3826
3827         case SIOCSMIIREG:
3828                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3829                 return 0;
3830         }
3831         return -EOPNOTSUPP;
3832 }
3833
3834 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3835 {
3836         return -EOPNOTSUPP;
3837 }
3838
3839 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3840 {
3841         if (tp->features & RTL_FEATURE_MSI) {
3842                 pci_disable_msi(pdev);
3843                 tp->features &= ~RTL_FEATURE_MSI;
3844         }
3845 }
3846
3847 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3848 {
3849         struct mdio_ops *ops = &tp->mdio_ops;
3850
3851         switch (tp->mac_version) {
3852         case RTL_GIGA_MAC_VER_27:
3853                 ops->write      = r8168dp_1_mdio_write;
3854                 ops->read       = r8168dp_1_mdio_read;
3855                 break;
3856         case RTL_GIGA_MAC_VER_28:
3857         case RTL_GIGA_MAC_VER_31:
3858                 ops->write      = r8168dp_2_mdio_write;
3859                 ops->read       = r8168dp_2_mdio_read;
3860                 break;
3861         case RTL_GIGA_MAC_VER_40:
3862         case RTL_GIGA_MAC_VER_41:
3863         case RTL_GIGA_MAC_VER_42:
3864         case RTL_GIGA_MAC_VER_43:
3865                 ops->write      = r8168g_mdio_write;
3866                 ops->read       = r8168g_mdio_read;
3867                 break;
3868         default:
3869                 ops->write      = r8169_mdio_write;
3870                 ops->read       = r8169_mdio_read;
3871                 break;
3872         }
3873 }
3874
3875 static void rtl_speed_down(struct rtl8169_private *tp)
3876 {
3877         u32 adv;
3878         int lpa;
3879
3880         rtl_writephy(tp, 0x1f, 0x0000);
3881         lpa = rtl_readphy(tp, MII_LPA);
3882
3883         if (lpa & (LPA_10HALF | LPA_10FULL))
3884                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3885         else if (lpa & (LPA_100HALF | LPA_100FULL))
3886                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3887                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3888         else
3889                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3890                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3891                       (tp->mii.supports_gmii ?
3892                        ADVERTISED_1000baseT_Half |
3893                        ADVERTISED_1000baseT_Full : 0);
3894
3895         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3896                           adv);
3897 }
3898
3899 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3900 {
3901         void __iomem *ioaddr = tp->mmio_addr;
3902
3903         switch (tp->mac_version) {
3904         case RTL_GIGA_MAC_VER_25:
3905         case RTL_GIGA_MAC_VER_26:
3906         case RTL_GIGA_MAC_VER_29:
3907         case RTL_GIGA_MAC_VER_30:
3908         case RTL_GIGA_MAC_VER_32:
3909         case RTL_GIGA_MAC_VER_33:
3910         case RTL_GIGA_MAC_VER_34:
3911         case RTL_GIGA_MAC_VER_37:
3912         case RTL_GIGA_MAC_VER_38:
3913         case RTL_GIGA_MAC_VER_39:
3914         case RTL_GIGA_MAC_VER_40:
3915         case RTL_GIGA_MAC_VER_41:
3916         case RTL_GIGA_MAC_VER_42:
3917         case RTL_GIGA_MAC_VER_43:
3918                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3919                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3920                 break;
3921         default:
3922                 break;
3923         }
3924 }
3925
3926 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3927 {
3928         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3929                 return false;
3930
3931         rtl_speed_down(tp);
3932         rtl_wol_suspend_quirk(tp);
3933
3934         return true;
3935 }
3936
3937 static void r810x_phy_power_down(struct rtl8169_private *tp)
3938 {
3939         rtl_writephy(tp, 0x1f, 0x0000);
3940         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3941 }
3942
3943 static void r810x_phy_power_up(struct rtl8169_private *tp)
3944 {
3945         rtl_writephy(tp, 0x1f, 0x0000);
3946         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3947 }
3948
3949 static void r810x_pll_power_down(struct rtl8169_private *tp)
3950 {
3951         void __iomem *ioaddr = tp->mmio_addr;
3952
3953         if (rtl_wol_pll_power_down(tp))
3954                 return;
3955
3956         r810x_phy_power_down(tp);
3957
3958         switch (tp->mac_version) {
3959         case RTL_GIGA_MAC_VER_07:
3960         case RTL_GIGA_MAC_VER_08:
3961         case RTL_GIGA_MAC_VER_09:
3962         case RTL_GIGA_MAC_VER_10:
3963         case RTL_GIGA_MAC_VER_13:
3964         case RTL_GIGA_MAC_VER_16:
3965                 break;
3966         default:
3967                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3968                 break;
3969         }
3970 }
3971
3972 static void r810x_pll_power_up(struct rtl8169_private *tp)
3973 {
3974         void __iomem *ioaddr = tp->mmio_addr;
3975
3976         r810x_phy_power_up(tp);
3977
3978         switch (tp->mac_version) {
3979         case RTL_GIGA_MAC_VER_07:
3980         case RTL_GIGA_MAC_VER_08:
3981         case RTL_GIGA_MAC_VER_09:
3982         case RTL_GIGA_MAC_VER_10:
3983         case RTL_GIGA_MAC_VER_13:
3984         case RTL_GIGA_MAC_VER_16:
3985                 break;
3986         default:
3987                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3988                 break;
3989         }
3990 }
3991
3992 static void r8168_phy_power_up(struct rtl8169_private *tp)
3993 {
3994         rtl_writephy(tp, 0x1f, 0x0000);
3995         switch (tp->mac_version) {
3996         case RTL_GIGA_MAC_VER_11:
3997         case RTL_GIGA_MAC_VER_12:
3998         case RTL_GIGA_MAC_VER_17:
3999         case RTL_GIGA_MAC_VER_18:
4000         case RTL_GIGA_MAC_VER_19:
4001         case RTL_GIGA_MAC_VER_20:
4002         case RTL_GIGA_MAC_VER_21:
4003         case RTL_GIGA_MAC_VER_22:
4004         case RTL_GIGA_MAC_VER_23:
4005         case RTL_GIGA_MAC_VER_24:
4006         case RTL_GIGA_MAC_VER_25:
4007         case RTL_GIGA_MAC_VER_26:
4008         case RTL_GIGA_MAC_VER_27:
4009         case RTL_GIGA_MAC_VER_28:
4010         case RTL_GIGA_MAC_VER_31:
4011                 rtl_writephy(tp, 0x0e, 0x0000);
4012                 break;
4013         default:
4014                 break;
4015         }
4016         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4017 }
4018
4019 static void r8168_phy_power_down(struct rtl8169_private *tp)
4020 {
4021         rtl_writephy(tp, 0x1f, 0x0000);
4022         switch (tp->mac_version) {
4023         case RTL_GIGA_MAC_VER_32:
4024         case RTL_GIGA_MAC_VER_33:
4025         case RTL_GIGA_MAC_VER_40:
4026         case RTL_GIGA_MAC_VER_41:
4027                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4028                 break;
4029
4030         case RTL_GIGA_MAC_VER_11:
4031         case RTL_GIGA_MAC_VER_12:
4032         case RTL_GIGA_MAC_VER_17:
4033         case RTL_GIGA_MAC_VER_18:
4034         case RTL_GIGA_MAC_VER_19:
4035         case RTL_GIGA_MAC_VER_20:
4036         case RTL_GIGA_MAC_VER_21:
4037         case RTL_GIGA_MAC_VER_22:
4038         case RTL_GIGA_MAC_VER_23:
4039         case RTL_GIGA_MAC_VER_24:
4040         case RTL_GIGA_MAC_VER_25:
4041         case RTL_GIGA_MAC_VER_26:
4042         case RTL_GIGA_MAC_VER_27:
4043         case RTL_GIGA_MAC_VER_28:
4044         case RTL_GIGA_MAC_VER_31:
4045                 rtl_writephy(tp, 0x0e, 0x0200);
4046         default:
4047                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4048                 break;
4049         }
4050 }
4051
4052 static void r8168_pll_power_down(struct rtl8169_private *tp)
4053 {
4054         void __iomem *ioaddr = tp->mmio_addr;
4055
4056         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4057              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4058              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4059             r8168dp_check_dash(tp)) {
4060                 return;
4061         }
4062
4063         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4064              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4065             (RTL_R16(CPlusCmd) & ASF)) {
4066                 return;
4067         }
4068
4069         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4070             tp->mac_version == RTL_GIGA_MAC_VER_33)
4071                 rtl_ephy_write(tp, 0x19, 0xff64);
4072
4073         if (rtl_wol_pll_power_down(tp))
4074                 return;
4075
4076         r8168_phy_power_down(tp);
4077
4078         switch (tp->mac_version) {
4079         case RTL_GIGA_MAC_VER_25:
4080         case RTL_GIGA_MAC_VER_26:
4081         case RTL_GIGA_MAC_VER_27:
4082         case RTL_GIGA_MAC_VER_28:
4083         case RTL_GIGA_MAC_VER_31:
4084         case RTL_GIGA_MAC_VER_32:
4085         case RTL_GIGA_MAC_VER_33:
4086                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4087                 break;
4088         case RTL_GIGA_MAC_VER_40:
4089         case RTL_GIGA_MAC_VER_41:
4090                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4091                              0xfc000000, ERIAR_EXGMAC);
4092                 break;
4093         }
4094 }
4095
4096 static void r8168_pll_power_up(struct rtl8169_private *tp)
4097 {
4098         void __iomem *ioaddr = tp->mmio_addr;
4099
4100         switch (tp->mac_version) {
4101         case RTL_GIGA_MAC_VER_25:
4102         case RTL_GIGA_MAC_VER_26:
4103         case RTL_GIGA_MAC_VER_27:
4104         case RTL_GIGA_MAC_VER_28:
4105         case RTL_GIGA_MAC_VER_31:
4106         case RTL_GIGA_MAC_VER_32:
4107         case RTL_GIGA_MAC_VER_33:
4108                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4109                 break;
4110         case RTL_GIGA_MAC_VER_40:
4111         case RTL_GIGA_MAC_VER_41:
4112                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4113                              0x00000000, ERIAR_EXGMAC);
4114                 break;
4115         }
4116
4117         r8168_phy_power_up(tp);
4118 }
4119
4120 static void rtl_generic_op(struct rtl8169_private *tp,
4121                            void (*op)(struct rtl8169_private *))
4122 {
4123         if (op)
4124                 op(tp);
4125 }
4126
4127 static void rtl_pll_power_down(struct rtl8169_private *tp)
4128 {
4129         rtl_generic_op(tp, tp->pll_power_ops.down);
4130 }
4131
4132 static void rtl_pll_power_up(struct rtl8169_private *tp)
4133 {
4134         rtl_generic_op(tp, tp->pll_power_ops.up);
4135 }
4136
4137 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4138 {
4139         struct pll_power_ops *ops = &tp->pll_power_ops;
4140
4141         switch (tp->mac_version) {
4142         case RTL_GIGA_MAC_VER_07:
4143         case RTL_GIGA_MAC_VER_08:
4144         case RTL_GIGA_MAC_VER_09:
4145         case RTL_GIGA_MAC_VER_10:
4146         case RTL_GIGA_MAC_VER_16:
4147         case RTL_GIGA_MAC_VER_29:
4148         case RTL_GIGA_MAC_VER_30:
4149         case RTL_GIGA_MAC_VER_37:
4150         case RTL_GIGA_MAC_VER_39:
4151         case RTL_GIGA_MAC_VER_43:
4152                 ops->down       = r810x_pll_power_down;
4153                 ops->up         = r810x_pll_power_up;
4154                 break;
4155
4156         case RTL_GIGA_MAC_VER_11:
4157         case RTL_GIGA_MAC_VER_12:
4158         case RTL_GIGA_MAC_VER_17:
4159         case RTL_GIGA_MAC_VER_18:
4160         case RTL_GIGA_MAC_VER_19:
4161         case RTL_GIGA_MAC_VER_20:
4162         case RTL_GIGA_MAC_VER_21:
4163         case RTL_GIGA_MAC_VER_22:
4164         case RTL_GIGA_MAC_VER_23:
4165         case RTL_GIGA_MAC_VER_24:
4166         case RTL_GIGA_MAC_VER_25:
4167         case RTL_GIGA_MAC_VER_26:
4168         case RTL_GIGA_MAC_VER_27:
4169         case RTL_GIGA_MAC_VER_28:
4170         case RTL_GIGA_MAC_VER_31:
4171         case RTL_GIGA_MAC_VER_32:
4172         case RTL_GIGA_MAC_VER_33:
4173         case RTL_GIGA_MAC_VER_34:
4174         case RTL_GIGA_MAC_VER_35:
4175         case RTL_GIGA_MAC_VER_36:
4176         case RTL_GIGA_MAC_VER_38:
4177         case RTL_GIGA_MAC_VER_40:
4178         case RTL_GIGA_MAC_VER_41:
4179         case RTL_GIGA_MAC_VER_42:
4180                 ops->down       = r8168_pll_power_down;
4181                 ops->up         = r8168_pll_power_up;
4182                 break;
4183
4184         default:
4185                 ops->down       = NULL;
4186                 ops->up         = NULL;
4187                 break;
4188         }
4189 }
4190
4191 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4192 {
4193         void __iomem *ioaddr = tp->mmio_addr;
4194
4195         switch (tp->mac_version) {
4196         case RTL_GIGA_MAC_VER_01:
4197         case RTL_GIGA_MAC_VER_02:
4198         case RTL_GIGA_MAC_VER_03:
4199         case RTL_GIGA_MAC_VER_04:
4200         case RTL_GIGA_MAC_VER_05:
4201         case RTL_GIGA_MAC_VER_06:
4202         case RTL_GIGA_MAC_VER_10:
4203         case RTL_GIGA_MAC_VER_11:
4204         case RTL_GIGA_MAC_VER_12:
4205         case RTL_GIGA_MAC_VER_13:
4206         case RTL_GIGA_MAC_VER_14:
4207         case RTL_GIGA_MAC_VER_15:
4208         case RTL_GIGA_MAC_VER_16:
4209         case RTL_GIGA_MAC_VER_17:
4210                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4211                 break;
4212         case RTL_GIGA_MAC_VER_18:
4213         case RTL_GIGA_MAC_VER_19:
4214         case RTL_GIGA_MAC_VER_20:
4215         case RTL_GIGA_MAC_VER_21:
4216         case RTL_GIGA_MAC_VER_22:
4217         case RTL_GIGA_MAC_VER_23:
4218         case RTL_GIGA_MAC_VER_24:
4219         case RTL_GIGA_MAC_VER_34:
4220                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4221                 break;
4222         case RTL_GIGA_MAC_VER_40:
4223         case RTL_GIGA_MAC_VER_41:
4224         case RTL_GIGA_MAC_VER_42:
4225         case RTL_GIGA_MAC_VER_43:
4226                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4227                 break;
4228         default:
4229                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4230                 break;
4231         }
4232 }
4233
4234 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4235 {
4236         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4237 }
4238
4239 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4240 {
4241         void __iomem *ioaddr = tp->mmio_addr;
4242
4243         RTL_W8(Cfg9346, Cfg9346_Unlock);
4244         rtl_generic_op(tp, tp->jumbo_ops.enable);
4245         RTL_W8(Cfg9346, Cfg9346_Lock);
4246 }
4247
4248 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4249 {
4250         void __iomem *ioaddr = tp->mmio_addr;
4251
4252         RTL_W8(Cfg9346, Cfg9346_Unlock);
4253         rtl_generic_op(tp, tp->jumbo_ops.disable);
4254         RTL_W8(Cfg9346, Cfg9346_Lock);
4255 }
4256
4257 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4258 {
4259         void __iomem *ioaddr = tp->mmio_addr;
4260
4261         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4262         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4263         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4264 }
4265
4266 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4267 {
4268         void __iomem *ioaddr = tp->mmio_addr;
4269
4270         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4271         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4272         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4273 }
4274
4275 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4276 {
4277         void __iomem *ioaddr = tp->mmio_addr;
4278
4279         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4280 }
4281
4282 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4283 {
4284         void __iomem *ioaddr = tp->mmio_addr;
4285
4286         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4287 }
4288
4289 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4290 {
4291         void __iomem *ioaddr = tp->mmio_addr;
4292
4293         RTL_W8(MaxTxPacketSize, 0x3f);
4294         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4295         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4296         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4297 }
4298
4299 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4300 {
4301         void __iomem *ioaddr = tp->mmio_addr;
4302
4303         RTL_W8(MaxTxPacketSize, 0x0c);
4304         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4305         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4306         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4307 }
4308
4309 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4310 {
4311         rtl_tx_performance_tweak(tp->pci_dev,
4312                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4313 }
4314
4315 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4316 {
4317         rtl_tx_performance_tweak(tp->pci_dev,
4318                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4319 }
4320
4321 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4322 {
4323         void __iomem *ioaddr = tp->mmio_addr;
4324
4325         r8168b_0_hw_jumbo_enable(tp);
4326
4327         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4328 }
4329
4330 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4331 {
4332         void __iomem *ioaddr = tp->mmio_addr;
4333
4334         r8168b_0_hw_jumbo_disable(tp);
4335
4336         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4337 }
4338
4339 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4340 {
4341         struct jumbo_ops *ops = &tp->jumbo_ops;
4342
4343         switch (tp->mac_version) {
4344         case RTL_GIGA_MAC_VER_11:
4345                 ops->disable    = r8168b_0_hw_jumbo_disable;
4346                 ops->enable     = r8168b_0_hw_jumbo_enable;
4347                 break;
4348         case RTL_GIGA_MAC_VER_12:
4349         case RTL_GIGA_MAC_VER_17:
4350                 ops->disable    = r8168b_1_hw_jumbo_disable;
4351                 ops->enable     = r8168b_1_hw_jumbo_enable;
4352                 break;
4353         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4354         case RTL_GIGA_MAC_VER_19:
4355         case RTL_GIGA_MAC_VER_20:
4356         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4357         case RTL_GIGA_MAC_VER_22:
4358         case RTL_GIGA_MAC_VER_23:
4359         case RTL_GIGA_MAC_VER_24:
4360         case RTL_GIGA_MAC_VER_25:
4361         case RTL_GIGA_MAC_VER_26:
4362                 ops->disable    = r8168c_hw_jumbo_disable;
4363                 ops->enable     = r8168c_hw_jumbo_enable;
4364                 break;
4365         case RTL_GIGA_MAC_VER_27:
4366         case RTL_GIGA_MAC_VER_28:
4367                 ops->disable    = r8168dp_hw_jumbo_disable;
4368                 ops->enable     = r8168dp_hw_jumbo_enable;
4369                 break;
4370         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4371         case RTL_GIGA_MAC_VER_32:
4372         case RTL_GIGA_MAC_VER_33:
4373         case RTL_GIGA_MAC_VER_34:
4374                 ops->disable    = r8168e_hw_jumbo_disable;
4375                 ops->enable     = r8168e_hw_jumbo_enable;
4376                 break;
4377
4378         /*
4379          * No action needed for jumbo frames with 8169.
4380          * No jumbo for 810x at all.
4381          */
4382         case RTL_GIGA_MAC_VER_40:
4383         case RTL_GIGA_MAC_VER_41:
4384         case RTL_GIGA_MAC_VER_42:
4385         case RTL_GIGA_MAC_VER_43:
4386         default:
4387                 ops->disable    = NULL;
4388                 ops->enable     = NULL;
4389                 break;
4390         }
4391 }
4392
4393 DECLARE_RTL_COND(rtl_chipcmd_cond)
4394 {
4395         void __iomem *ioaddr = tp->mmio_addr;
4396
4397         return RTL_R8(ChipCmd) & CmdReset;
4398 }
4399
4400 static void rtl_hw_reset(struct rtl8169_private *tp)
4401 {
4402         void __iomem *ioaddr = tp->mmio_addr;
4403
4404         RTL_W8(ChipCmd, CmdReset);
4405
4406         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4407 }
4408
4409 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4410 {
4411         struct rtl_fw *rtl_fw;
4412         const char *name;
4413         int rc = -ENOMEM;
4414
4415         name = rtl_lookup_firmware_name(tp);
4416         if (!name)
4417                 goto out_no_firmware;
4418
4419         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4420         if (!rtl_fw)
4421                 goto err_warn;
4422
4423         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4424         if (rc < 0)
4425                 goto err_free;
4426
4427         rc = rtl_check_firmware(tp, rtl_fw);
4428         if (rc < 0)
4429                 goto err_release_firmware;
4430
4431         tp->rtl_fw = rtl_fw;
4432 out:
4433         return;
4434
4435 err_release_firmware:
4436         release_firmware(rtl_fw->fw);
4437 err_free:
4438         kfree(rtl_fw);
4439 err_warn:
4440         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4441                    name, rc);
4442 out_no_firmware:
4443         tp->rtl_fw = NULL;
4444         goto out;
4445 }
4446
4447 static void rtl_request_firmware(struct rtl8169_private *tp)
4448 {
4449         if (IS_ERR(tp->rtl_fw))
4450                 rtl_request_uncached_firmware(tp);
4451 }
4452
4453 static void rtl_rx_close(struct rtl8169_private *tp)
4454 {
4455         void __iomem *ioaddr = tp->mmio_addr;
4456
4457         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4458 }
4459
4460 DECLARE_RTL_COND(rtl_npq_cond)
4461 {
4462         void __iomem *ioaddr = tp->mmio_addr;
4463
4464         return RTL_R8(TxPoll) & NPQ;
4465 }
4466
4467 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4468 {
4469         void __iomem *ioaddr = tp->mmio_addr;
4470
4471         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4472 }
4473
4474 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4475 {
4476         void __iomem *ioaddr = tp->mmio_addr;
4477
4478         /* Disable interrupts */
4479         rtl8169_irq_mask_and_ack(tp);
4480
4481         rtl_rx_close(tp);
4482
4483         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4484             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4485             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4486                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4487         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4488                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4489                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4490                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4491                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4492                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4493                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4494                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4495                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4496                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4497                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4498         } else {
4499                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4500                 udelay(100);
4501         }
4502
4503         rtl_hw_reset(tp);
4504 }
4505
4506 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4507 {
4508         void __iomem *ioaddr = tp->mmio_addr;
4509
4510         /* Set DMA burst size and Interframe Gap Time */
4511         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4512                 (InterFrameGap << TxInterFrameGapShift));
4513 }
4514
4515 static void rtl_hw_start(struct net_device *dev)
4516 {
4517         struct rtl8169_private *tp = netdev_priv(dev);
4518
4519         tp->hw_start(dev);
4520
4521         rtl_irq_enable_all(tp);
4522 }
4523
4524 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4525                                          void __iomem *ioaddr)
4526 {
4527         /*
4528          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4529          * register to be written before TxDescAddrLow to work.
4530          * Switching from MMIO to I/O access fixes the issue as well.
4531          */
4532         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4533         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4534         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4535         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4536 }
4537
4538 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4539 {
4540         u16 cmd;
4541
4542         cmd = RTL_R16(CPlusCmd);
4543         RTL_W16(CPlusCmd, cmd);
4544         return cmd;
4545 }
4546
4547 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4548 {
4549         /* Low hurts. Let's disable the filtering. */
4550         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4551 }
4552
4553 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4554 {
4555         static const struct rtl_cfg2_info {
4556                 u32 mac_version;
4557                 u32 clk;
4558                 u32 val;
4559         } cfg2_info [] = {
4560                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4561                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4562                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4563                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4564         };
4565         const struct rtl_cfg2_info *p = cfg2_info;
4566         unsigned int i;
4567         u32 clk;
4568
4569         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4570         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4571                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4572                         RTL_W32(0x7c, p->val);
4573                         break;
4574                 }
4575         }
4576 }
4577
4578 static void rtl_set_rx_mode(struct net_device *dev)
4579 {
4580         struct rtl8169_private *tp = netdev_priv(dev);
4581         void __iomem *ioaddr = tp->mmio_addr;
4582         u32 mc_filter[2];       /* Multicast hash filter */
4583         int rx_mode;
4584         u32 tmp = 0;
4585
4586         if (dev->flags & IFF_PROMISC) {
4587                 /* Unconditionally log net taps. */
4588                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4589                 rx_mode =
4590                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4591                     AcceptAllPhys;
4592                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4593         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4594                    (dev->flags & IFF_ALLMULTI)) {
4595                 /* Too many to filter perfectly -- accept all multicasts. */
4596                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4597                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4598         } else {
4599                 struct netdev_hw_addr *ha;
4600
4601                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4602                 mc_filter[1] = mc_filter[0] = 0;
4603                 netdev_for_each_mc_addr(ha, dev) {
4604                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4605                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4606                         rx_mode |= AcceptMulticast;
4607                 }
4608         }
4609
4610         if (dev->features & NETIF_F_RXALL)
4611                 rx_mode |= (AcceptErr | AcceptRunt);
4612
4613         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4614
4615         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4616                 u32 data = mc_filter[0];
4617
4618                 mc_filter[0] = swab32(mc_filter[1]);
4619                 mc_filter[1] = swab32(data);
4620         }
4621
4622         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4623                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4624
4625         RTL_W32(MAR0 + 4, mc_filter[1]);
4626         RTL_W32(MAR0 + 0, mc_filter[0]);
4627
4628         RTL_W32(RxConfig, tmp);
4629 }
4630
4631 static void rtl_hw_start_8169(struct net_device *dev)
4632 {
4633         struct rtl8169_private *tp = netdev_priv(dev);
4634         void __iomem *ioaddr = tp->mmio_addr;
4635         struct pci_dev *pdev = tp->pci_dev;
4636
4637         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4638                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4639                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4640         }
4641
4642         RTL_W8(Cfg9346, Cfg9346_Unlock);
4643         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4644             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4645             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4646             tp->mac_version == RTL_GIGA_MAC_VER_04)
4647                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4648
4649         rtl_init_rxcfg(tp);
4650
4651         RTL_W8(EarlyTxThres, NoEarlyTx);
4652
4653         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4654
4655         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4656             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4657             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4658             tp->mac_version == RTL_GIGA_MAC_VER_04)
4659                 rtl_set_rx_tx_config_registers(tp);
4660
4661         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4662
4663         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4664             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4665                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4666                         "Bit-3 and bit-14 MUST be 1\n");
4667                 tp->cp_cmd |= (1 << 14);
4668         }
4669
4670         RTL_W16(CPlusCmd, tp->cp_cmd);
4671
4672         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4673
4674         /*
4675          * Undocumented corner. Supposedly:
4676          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4677          */
4678         RTL_W16(IntrMitigate, 0x0000);
4679
4680         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4681
4682         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4683             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4684             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4685             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4686                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4687                 rtl_set_rx_tx_config_registers(tp);
4688         }
4689
4690         RTL_W8(Cfg9346, Cfg9346_Lock);
4691
4692         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4693         RTL_R8(IntrMask);
4694
4695         RTL_W32(RxMissed, 0);
4696
4697         rtl_set_rx_mode(dev);
4698
4699         /* no early-rx interrupts */
4700         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4701 }
4702
4703 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4704 {
4705         if (tp->csi_ops.write)
4706                 tp->csi_ops.write(tp, addr, value);
4707 }
4708
4709 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4710 {
4711         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4712 }
4713
4714 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4715 {
4716         u32 csi;
4717
4718         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4719         rtl_csi_write(tp, 0x070c, csi | bits);
4720 }
4721
4722 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4723 {
4724         rtl_csi_access_enable(tp, 0x17000000);
4725 }
4726
4727 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4728 {
4729         rtl_csi_access_enable(tp, 0x27000000);
4730 }
4731
4732 DECLARE_RTL_COND(rtl_csiar_cond)
4733 {
4734         void __iomem *ioaddr = tp->mmio_addr;
4735
4736         return RTL_R32(CSIAR) & CSIAR_FLAG;
4737 }
4738
4739 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4740 {
4741         void __iomem *ioaddr = tp->mmio_addr;
4742
4743         RTL_W32(CSIDR, value);
4744         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4745                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4746
4747         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4748 }
4749
4750 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4751 {
4752         void __iomem *ioaddr = tp->mmio_addr;
4753
4754         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4755                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4756
4757         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4758                 RTL_R32(CSIDR) : ~0;
4759 }
4760
4761 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4762 {
4763         void __iomem *ioaddr = tp->mmio_addr;
4764
4765         RTL_W32(CSIDR, value);
4766         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4767                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4768                 CSIAR_FUNC_NIC);
4769
4770         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4771 }
4772
4773 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4774 {
4775         void __iomem *ioaddr = tp->mmio_addr;
4776
4777         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4778                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4779
4780         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4781                 RTL_R32(CSIDR) : ~0;
4782 }
4783
4784 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4785 {
4786         struct csi_ops *ops = &tp->csi_ops;
4787
4788         switch (tp->mac_version) {
4789         case RTL_GIGA_MAC_VER_01:
4790         case RTL_GIGA_MAC_VER_02:
4791         case RTL_GIGA_MAC_VER_03:
4792         case RTL_GIGA_MAC_VER_04:
4793         case RTL_GIGA_MAC_VER_05:
4794         case RTL_GIGA_MAC_VER_06:
4795         case RTL_GIGA_MAC_VER_10:
4796         case RTL_GIGA_MAC_VER_11:
4797         case RTL_GIGA_MAC_VER_12:
4798         case RTL_GIGA_MAC_VER_13:
4799         case RTL_GIGA_MAC_VER_14:
4800         case RTL_GIGA_MAC_VER_15:
4801         case RTL_GIGA_MAC_VER_16:
4802         case RTL_GIGA_MAC_VER_17:
4803                 ops->write      = NULL;
4804                 ops->read       = NULL;
4805                 break;
4806
4807         case RTL_GIGA_MAC_VER_37:
4808         case RTL_GIGA_MAC_VER_38:
4809                 ops->write      = r8402_csi_write;
4810                 ops->read       = r8402_csi_read;
4811                 break;
4812
4813         default:
4814                 ops->write      = r8169_csi_write;
4815                 ops->read       = r8169_csi_read;
4816                 break;
4817         }
4818 }
4819
4820 struct ephy_info {
4821         unsigned int offset;
4822         u16 mask;
4823         u16 bits;
4824 };
4825
4826 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4827                           int len)
4828 {
4829         u16 w;
4830
4831         while (len-- > 0) {
4832                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4833                 rtl_ephy_write(tp, e->offset, w);
4834                 e++;
4835         }
4836 }
4837
4838 static void rtl_disable_clock_request(struct pci_dev *pdev)
4839 {
4840         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4841                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4842 }
4843
4844 static void rtl_enable_clock_request(struct pci_dev *pdev)
4845 {
4846         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4847                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4848 }
4849
4850 #define R8168_CPCMD_QUIRK_MASK (\
4851         EnableBist | \
4852         Mac_dbgo_oe | \
4853         Force_half_dup | \
4854         Force_rxflow_en | \
4855         Force_txflow_en | \
4856         Cxpl_dbg_sel | \
4857         ASF | \
4858         PktCntrDisable | \
4859         Mac_dbgo_sel)
4860
4861 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4862 {
4863         void __iomem *ioaddr = tp->mmio_addr;
4864         struct pci_dev *pdev = tp->pci_dev;
4865
4866         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4867
4868         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4869
4870         if (tp->dev->mtu <= ETH_DATA_LEN) {
4871                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4872                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4873         }
4874 }
4875
4876 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4877 {
4878         void __iomem *ioaddr = tp->mmio_addr;
4879
4880         rtl_hw_start_8168bb(tp);
4881
4882         RTL_W8(MaxTxPacketSize, TxPacketMax);
4883
4884         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4885 }
4886
4887 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4888 {
4889         void __iomem *ioaddr = tp->mmio_addr;
4890         struct pci_dev *pdev = tp->pci_dev;
4891
4892         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4893
4894         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4895
4896         if (tp->dev->mtu <= ETH_DATA_LEN)
4897                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4898
4899         rtl_disable_clock_request(pdev);
4900
4901         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4902 }
4903
4904 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4905 {
4906         static const struct ephy_info e_info_8168cp[] = {
4907                 { 0x01, 0,      0x0001 },
4908                 { 0x02, 0x0800, 0x1000 },
4909                 { 0x03, 0,      0x0042 },
4910                 { 0x06, 0x0080, 0x0000 },
4911                 { 0x07, 0,      0x2000 }
4912         };
4913
4914         rtl_csi_access_enable_2(tp);
4915
4916         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4917
4918         __rtl_hw_start_8168cp(tp);
4919 }
4920
4921 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4922 {
4923         void __iomem *ioaddr = tp->mmio_addr;
4924         struct pci_dev *pdev = tp->pci_dev;
4925
4926         rtl_csi_access_enable_2(tp);
4927
4928         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4929
4930         if (tp->dev->mtu <= ETH_DATA_LEN)
4931                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4932
4933         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4934 }
4935
4936 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4937 {
4938         void __iomem *ioaddr = tp->mmio_addr;
4939         struct pci_dev *pdev = tp->pci_dev;
4940
4941         rtl_csi_access_enable_2(tp);
4942
4943         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4944
4945         /* Magic. */
4946         RTL_W8(DBG_REG, 0x20);
4947
4948         RTL_W8(MaxTxPacketSize, TxPacketMax);
4949
4950         if (tp->dev->mtu <= ETH_DATA_LEN)
4951                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4952
4953         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4954 }
4955
4956 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4957 {
4958         void __iomem *ioaddr = tp->mmio_addr;
4959         static const struct ephy_info e_info_8168c_1[] = {
4960                 { 0x02, 0x0800, 0x1000 },
4961                 { 0x03, 0,      0x0002 },
4962                 { 0x06, 0x0080, 0x0000 }
4963         };
4964
4965         rtl_csi_access_enable_2(tp);
4966
4967         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4968
4969         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4970
4971         __rtl_hw_start_8168cp(tp);
4972 }
4973
4974 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4975 {
4976         static const struct ephy_info e_info_8168c_2[] = {
4977                 { 0x01, 0,      0x0001 },
4978                 { 0x03, 0x0400, 0x0220 }
4979         };
4980
4981         rtl_csi_access_enable_2(tp);
4982
4983         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4984
4985         __rtl_hw_start_8168cp(tp);
4986 }
4987
4988 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4989 {
4990         rtl_hw_start_8168c_2(tp);
4991 }
4992
4993 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4994 {
4995         rtl_csi_access_enable_2(tp);
4996
4997         __rtl_hw_start_8168cp(tp);
4998 }
4999
5000 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5001 {
5002         void __iomem *ioaddr = tp->mmio_addr;
5003         struct pci_dev *pdev = tp->pci_dev;
5004
5005         rtl_csi_access_enable_2(tp);
5006
5007         rtl_disable_clock_request(pdev);
5008
5009         RTL_W8(MaxTxPacketSize, TxPacketMax);
5010
5011         if (tp->dev->mtu <= ETH_DATA_LEN)
5012                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5013
5014         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5015 }
5016
5017 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5018 {
5019         void __iomem *ioaddr = tp->mmio_addr;
5020         struct pci_dev *pdev = tp->pci_dev;
5021
5022         rtl_csi_access_enable_1(tp);
5023
5024         if (tp->dev->mtu <= ETH_DATA_LEN)
5025                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5026
5027         RTL_W8(MaxTxPacketSize, TxPacketMax);
5028
5029         rtl_disable_clock_request(pdev);
5030 }
5031
5032 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5033 {
5034         void __iomem *ioaddr = tp->mmio_addr;
5035         struct pci_dev *pdev = tp->pci_dev;
5036         static const struct ephy_info e_info_8168d_4[] = {
5037                 { 0x0b, ~0,     0x48 },
5038                 { 0x19, 0x20,   0x50 },
5039                 { 0x0c, ~0,     0x20 }
5040         };
5041         int i;
5042
5043         rtl_csi_access_enable_1(tp);
5044
5045         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5046
5047         RTL_W8(MaxTxPacketSize, TxPacketMax);
5048
5049         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5050                 const struct ephy_info *e = e_info_8168d_4 + i;
5051                 u16 w;
5052
5053                 w = rtl_ephy_read(tp, e->offset);
5054                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5055         }
5056
5057         rtl_enable_clock_request(pdev);
5058 }
5059
5060 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5061 {
5062         void __iomem *ioaddr = tp->mmio_addr;
5063         struct pci_dev *pdev = tp->pci_dev;
5064         static const struct ephy_info e_info_8168e_1[] = {
5065                 { 0x00, 0x0200, 0x0100 },
5066                 { 0x00, 0x0000, 0x0004 },
5067                 { 0x06, 0x0002, 0x0001 },
5068                 { 0x06, 0x0000, 0x0030 },
5069                 { 0x07, 0x0000, 0x2000 },
5070                 { 0x00, 0x0000, 0x0020 },
5071                 { 0x03, 0x5800, 0x2000 },
5072                 { 0x03, 0x0000, 0x0001 },
5073                 { 0x01, 0x0800, 0x1000 },
5074                 { 0x07, 0x0000, 0x4000 },
5075                 { 0x1e, 0x0000, 0x2000 },
5076                 { 0x19, 0xffff, 0xfe6c },
5077                 { 0x0a, 0x0000, 0x0040 }
5078         };
5079
5080         rtl_csi_access_enable_2(tp);
5081
5082         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5083
5084         if (tp->dev->mtu <= ETH_DATA_LEN)
5085                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5086
5087         RTL_W8(MaxTxPacketSize, TxPacketMax);
5088
5089         rtl_disable_clock_request(pdev);
5090
5091         /* Reset tx FIFO pointer */
5092         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5093         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5094
5095         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5096 }
5097
5098 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5099 {
5100         void __iomem *ioaddr = tp->mmio_addr;
5101         struct pci_dev *pdev = tp->pci_dev;
5102         static const struct ephy_info e_info_8168e_2[] = {
5103                 { 0x09, 0x0000, 0x0080 },
5104                 { 0x19, 0x0000, 0x0224 }
5105         };
5106
5107         rtl_csi_access_enable_1(tp);
5108
5109         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5110
5111         if (tp->dev->mtu <= ETH_DATA_LEN)
5112                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5113
5114         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5115         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5116         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5117         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5118         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5119         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5120         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5121         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5122
5123         RTL_W8(MaxTxPacketSize, EarlySize);
5124
5125         rtl_disable_clock_request(pdev);
5126
5127         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5128         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5129
5130         /* Adjust EEE LED frequency */
5131         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5132
5133         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5134         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5135         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5136 }
5137
5138 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5139 {
5140         void __iomem *ioaddr = tp->mmio_addr;
5141         struct pci_dev *pdev = tp->pci_dev;
5142
5143         rtl_csi_access_enable_2(tp);
5144
5145         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5146
5147         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5148         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5149         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5150         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5151         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5152         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5153         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5154         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5155         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5156         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5157
5158         RTL_W8(MaxTxPacketSize, EarlySize);
5159
5160         rtl_disable_clock_request(pdev);
5161
5162         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5163         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5164         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5165         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5166         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5167 }
5168
5169 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5170 {
5171         void __iomem *ioaddr = tp->mmio_addr;
5172         static const struct ephy_info e_info_8168f_1[] = {
5173                 { 0x06, 0x00c0, 0x0020 },
5174                 { 0x08, 0x0001, 0x0002 },
5175                 { 0x09, 0x0000, 0x0080 },
5176                 { 0x19, 0x0000, 0x0224 }
5177         };
5178
5179         rtl_hw_start_8168f(tp);
5180
5181         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5182
5183         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5184
5185         /* Adjust EEE LED frequency */
5186         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5187 }
5188
5189 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5190 {
5191         static const struct ephy_info e_info_8168f_1[] = {
5192                 { 0x06, 0x00c0, 0x0020 },
5193                 { 0x0f, 0xffff, 0x5200 },
5194                 { 0x1e, 0x0000, 0x4000 },
5195                 { 0x19, 0x0000, 0x0224 }
5196         };
5197
5198         rtl_hw_start_8168f(tp);
5199
5200         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5201
5202         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5203 }
5204
5205 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5206 {
5207         void __iomem *ioaddr = tp->mmio_addr;
5208         struct pci_dev *pdev = tp->pci_dev;
5209
5210         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5211
5212         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5213         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5214         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5215         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5216
5217         rtl_csi_access_enable_1(tp);
5218
5219         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5220
5221         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5222         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5223         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5224
5225         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5226         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5227         RTL_W8(MaxTxPacketSize, EarlySize);
5228
5229         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5230         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5231
5232         /* Adjust EEE LED frequency */
5233         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5234
5235         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5236         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5237 }
5238
5239 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5240 {
5241         void __iomem *ioaddr = tp->mmio_addr;
5242         static const struct ephy_info e_info_8168g_2[] = {
5243                 { 0x00, 0x0000, 0x0008 },
5244                 { 0x0c, 0x3df0, 0x0200 },
5245                 { 0x19, 0xffff, 0xfc00 },
5246                 { 0x1e, 0xffff, 0x20eb }
5247         };
5248
5249         rtl_hw_start_8168g_1(tp);
5250
5251         /* disable aspm and clock request before access ephy */
5252         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5253         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5254         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5255 }
5256
5257 static void rtl_hw_start_8168(struct net_device *dev)
5258 {
5259         struct rtl8169_private *tp = netdev_priv(dev);
5260         void __iomem *ioaddr = tp->mmio_addr;
5261
5262         RTL_W8(Cfg9346, Cfg9346_Unlock);
5263
5264         RTL_W8(MaxTxPacketSize, TxPacketMax);
5265
5266         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5267
5268         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5269
5270         RTL_W16(CPlusCmd, tp->cp_cmd);
5271
5272         RTL_W16(IntrMitigate, 0x5151);
5273
5274         /* Work around for RxFIFO overflow. */
5275         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5276                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5277                 tp->event_slow &= ~RxOverflow;
5278         }
5279
5280         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5281
5282         rtl_set_rx_tx_config_registers(tp);
5283
5284         RTL_R8(IntrMask);
5285
5286         switch (tp->mac_version) {
5287         case RTL_GIGA_MAC_VER_11:
5288                 rtl_hw_start_8168bb(tp);
5289                 break;
5290
5291         case RTL_GIGA_MAC_VER_12:
5292         case RTL_GIGA_MAC_VER_17:
5293                 rtl_hw_start_8168bef(tp);
5294                 break;
5295
5296         case RTL_GIGA_MAC_VER_18:
5297                 rtl_hw_start_8168cp_1(tp);
5298                 break;
5299
5300         case RTL_GIGA_MAC_VER_19:
5301                 rtl_hw_start_8168c_1(tp);
5302                 break;
5303
5304         case RTL_GIGA_MAC_VER_20:
5305                 rtl_hw_start_8168c_2(tp);
5306                 break;
5307
5308         case RTL_GIGA_MAC_VER_21:
5309                 rtl_hw_start_8168c_3(tp);
5310                 break;
5311
5312         case RTL_GIGA_MAC_VER_22:
5313                 rtl_hw_start_8168c_4(tp);
5314                 break;
5315
5316         case RTL_GIGA_MAC_VER_23:
5317                 rtl_hw_start_8168cp_2(tp);
5318                 break;
5319
5320         case RTL_GIGA_MAC_VER_24:
5321                 rtl_hw_start_8168cp_3(tp);
5322                 break;
5323
5324         case RTL_GIGA_MAC_VER_25:
5325         case RTL_GIGA_MAC_VER_26:
5326         case RTL_GIGA_MAC_VER_27:
5327                 rtl_hw_start_8168d(tp);
5328                 break;
5329
5330         case RTL_GIGA_MAC_VER_28:
5331                 rtl_hw_start_8168d_4(tp);
5332                 break;
5333
5334         case RTL_GIGA_MAC_VER_31:
5335                 rtl_hw_start_8168dp(tp);
5336                 break;
5337
5338         case RTL_GIGA_MAC_VER_32:
5339         case RTL_GIGA_MAC_VER_33:
5340                 rtl_hw_start_8168e_1(tp);
5341                 break;
5342         case RTL_GIGA_MAC_VER_34:
5343                 rtl_hw_start_8168e_2(tp);
5344                 break;
5345
5346         case RTL_GIGA_MAC_VER_35:
5347         case RTL_GIGA_MAC_VER_36:
5348                 rtl_hw_start_8168f_1(tp);
5349                 break;
5350
5351         case RTL_GIGA_MAC_VER_38:
5352                 rtl_hw_start_8411(tp);
5353                 break;
5354
5355         case RTL_GIGA_MAC_VER_40:
5356         case RTL_GIGA_MAC_VER_41:
5357                 rtl_hw_start_8168g_1(tp);
5358                 break;
5359         case RTL_GIGA_MAC_VER_42:
5360                 rtl_hw_start_8168g_2(tp);
5361                 break;
5362
5363         default:
5364                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5365                         dev->name, tp->mac_version);
5366                 break;
5367         }
5368
5369         RTL_W8(Cfg9346, Cfg9346_Lock);
5370
5371         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5372
5373         rtl_set_rx_mode(dev);
5374
5375         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5376 }
5377
5378 #define R810X_CPCMD_QUIRK_MASK (\
5379         EnableBist | \
5380         Mac_dbgo_oe | \
5381         Force_half_dup | \
5382         Force_rxflow_en | \
5383         Force_txflow_en | \
5384         Cxpl_dbg_sel | \
5385         ASF | \
5386         PktCntrDisable | \
5387         Mac_dbgo_sel)
5388
5389 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5390 {
5391         void __iomem *ioaddr = tp->mmio_addr;
5392         struct pci_dev *pdev = tp->pci_dev;
5393         static const struct ephy_info e_info_8102e_1[] = {
5394                 { 0x01, 0, 0x6e65 },
5395                 { 0x02, 0, 0x091f },
5396                 { 0x03, 0, 0xc2f9 },
5397                 { 0x06, 0, 0xafb5 },
5398                 { 0x07, 0, 0x0e00 },
5399                 { 0x19, 0, 0xec80 },
5400                 { 0x01, 0, 0x2e65 },
5401                 { 0x01, 0, 0x6e65 }
5402         };
5403         u8 cfg1;
5404
5405         rtl_csi_access_enable_2(tp);
5406
5407         RTL_W8(DBG_REG, FIX_NAK_1);
5408
5409         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5410
5411         RTL_W8(Config1,
5412                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5413         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5414
5415         cfg1 = RTL_R8(Config1);
5416         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5417                 RTL_W8(Config1, cfg1 & ~LEDS0);
5418
5419         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5420 }
5421
5422 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5423 {
5424         void __iomem *ioaddr = tp->mmio_addr;
5425         struct pci_dev *pdev = tp->pci_dev;
5426
5427         rtl_csi_access_enable_2(tp);
5428
5429         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5430
5431         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5432         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5433 }
5434
5435 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5436 {
5437         rtl_hw_start_8102e_2(tp);
5438
5439         rtl_ephy_write(tp, 0x03, 0xc2f9);
5440 }
5441
5442 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5443 {
5444         void __iomem *ioaddr = tp->mmio_addr;
5445         static const struct ephy_info e_info_8105e_1[] = {
5446                 { 0x07, 0, 0x4000 },
5447                 { 0x19, 0, 0x0200 },
5448                 { 0x19, 0, 0x0020 },
5449                 { 0x1e, 0, 0x2000 },
5450                 { 0x03, 0, 0x0001 },
5451                 { 0x19, 0, 0x0100 },
5452                 { 0x19, 0, 0x0004 },
5453                 { 0x0a, 0, 0x0020 }
5454         };
5455
5456         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5457         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5458
5459         /* Disable Early Tally Counter */
5460         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5461
5462         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5463         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5464
5465         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5466 }
5467
5468 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5469 {
5470         rtl_hw_start_8105e_1(tp);
5471         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5472 }
5473
5474 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5475 {
5476         void __iomem *ioaddr = tp->mmio_addr;
5477         static const struct ephy_info e_info_8402[] = {
5478                 { 0x19, 0xffff, 0xff64 },
5479                 { 0x1e, 0, 0x4000 }
5480         };
5481
5482         rtl_csi_access_enable_2(tp);
5483
5484         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5485         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5486
5487         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5488         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5489
5490         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5491
5492         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5493
5494         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5495         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5496         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5497         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5498         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5499         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5500         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5501 }
5502
5503 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5504 {
5505         void __iomem *ioaddr = tp->mmio_addr;
5506
5507         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5508         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5509
5510         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5511         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5512         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5513 }
5514
5515 static void rtl_hw_start_8101(struct net_device *dev)
5516 {
5517         struct rtl8169_private *tp = netdev_priv(dev);
5518         void __iomem *ioaddr = tp->mmio_addr;
5519         struct pci_dev *pdev = tp->pci_dev;
5520
5521         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5522                 tp->event_slow &= ~RxFIFOOver;
5523
5524         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5525             tp->mac_version == RTL_GIGA_MAC_VER_16)
5526                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5527                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5528
5529         RTL_W8(Cfg9346, Cfg9346_Unlock);
5530
5531         RTL_W8(MaxTxPacketSize, TxPacketMax);
5532
5533         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5534
5535         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5536         RTL_W16(CPlusCmd, tp->cp_cmd);
5537
5538         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5539
5540         rtl_set_rx_tx_config_registers(tp);
5541
5542         switch (tp->mac_version) {
5543         case RTL_GIGA_MAC_VER_07:
5544                 rtl_hw_start_8102e_1(tp);
5545                 break;
5546
5547         case RTL_GIGA_MAC_VER_08:
5548                 rtl_hw_start_8102e_3(tp);
5549                 break;
5550
5551         case RTL_GIGA_MAC_VER_09:
5552                 rtl_hw_start_8102e_2(tp);
5553                 break;
5554
5555         case RTL_GIGA_MAC_VER_29:
5556                 rtl_hw_start_8105e_1(tp);
5557                 break;
5558         case RTL_GIGA_MAC_VER_30:
5559                 rtl_hw_start_8105e_2(tp);
5560                 break;
5561
5562         case RTL_GIGA_MAC_VER_37:
5563                 rtl_hw_start_8402(tp);
5564                 break;
5565
5566         case RTL_GIGA_MAC_VER_39:
5567                 rtl_hw_start_8106(tp);
5568                 break;
5569         case RTL_GIGA_MAC_VER_43:
5570                 rtl_hw_start_8168g_2(tp);
5571                 break;
5572         }
5573
5574         RTL_W8(Cfg9346, Cfg9346_Lock);
5575
5576         RTL_W16(IntrMitigate, 0x0000);
5577
5578         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5579
5580         rtl_set_rx_mode(dev);
5581
5582         RTL_R8(IntrMask);
5583
5584         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5585 }
5586
5587 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5588 {
5589         struct rtl8169_private *tp = netdev_priv(dev);
5590
5591         if (new_mtu < ETH_ZLEN ||
5592             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5593                 return -EINVAL;
5594
5595         if (new_mtu > ETH_DATA_LEN)
5596                 rtl_hw_jumbo_enable(tp);
5597         else
5598                 rtl_hw_jumbo_disable(tp);
5599
5600         dev->mtu = new_mtu;
5601         netdev_update_features(dev);
5602
5603         return 0;
5604 }
5605
5606 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5607 {
5608         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5609         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5610 }
5611
5612 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5613                                      void **data_buff, struct RxDesc *desc)
5614 {
5615         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5616                          DMA_FROM_DEVICE);
5617
5618         kfree(*data_buff);
5619         *data_buff = NULL;
5620         rtl8169_make_unusable_by_asic(desc);
5621 }
5622
5623 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5624 {
5625         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5626
5627         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5628 }
5629
5630 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5631                                        u32 rx_buf_sz)
5632 {
5633         desc->addr = cpu_to_le64(mapping);
5634         wmb();
5635         rtl8169_mark_to_asic(desc, rx_buf_sz);
5636 }
5637
5638 static inline void *rtl8169_align(void *data)
5639 {
5640         return (void *)ALIGN((long)data, 16);
5641 }
5642
5643 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5644                                              struct RxDesc *desc)
5645 {
5646         void *data;
5647         dma_addr_t mapping;
5648         struct device *d = &tp->pci_dev->dev;
5649         struct net_device *dev = tp->dev;
5650         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5651
5652         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5653         if (!data)
5654                 return NULL;
5655
5656         if (rtl8169_align(data) != data) {
5657                 kfree(data);
5658                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5659                 if (!data)
5660                         return NULL;
5661         }
5662
5663         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5664                                  DMA_FROM_DEVICE);
5665         if (unlikely(dma_mapping_error(d, mapping))) {
5666                 if (net_ratelimit())
5667                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5668                 goto err_out;
5669         }
5670
5671         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5672         return data;
5673
5674 err_out:
5675         kfree(data);
5676         return NULL;
5677 }
5678
5679 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5680 {
5681         unsigned int i;
5682
5683         for (i = 0; i < NUM_RX_DESC; i++) {
5684                 if (tp->Rx_databuff[i]) {
5685                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5686                                             tp->RxDescArray + i);
5687                 }
5688         }
5689 }
5690
5691 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5692 {
5693         desc->opts1 |= cpu_to_le32(RingEnd);
5694 }
5695
5696 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5697 {
5698         unsigned int i;
5699
5700         for (i = 0; i < NUM_RX_DESC; i++) {
5701                 void *data;
5702
5703                 if (tp->Rx_databuff[i])
5704                         continue;
5705
5706                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5707                 if (!data) {
5708                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5709                         goto err_out;
5710                 }
5711                 tp->Rx_databuff[i] = data;
5712         }
5713
5714         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5715         return 0;
5716
5717 err_out:
5718         rtl8169_rx_clear(tp);
5719         return -ENOMEM;
5720 }
5721
5722 static int rtl8169_init_ring(struct net_device *dev)
5723 {
5724         struct rtl8169_private *tp = netdev_priv(dev);
5725
5726         rtl8169_init_ring_indexes(tp);
5727
5728         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5729         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5730
5731         return rtl8169_rx_fill(tp);
5732 }
5733
5734 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5735                                  struct TxDesc *desc)
5736 {
5737         unsigned int len = tx_skb->len;
5738
5739         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5740
5741         desc->opts1 = 0x00;
5742         desc->opts2 = 0x00;
5743         desc->addr = 0x00;
5744         tx_skb->len = 0;
5745 }
5746
5747 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5748                                    unsigned int n)
5749 {
5750         unsigned int i;
5751
5752         for (i = 0; i < n; i++) {
5753                 unsigned int entry = (start + i) % NUM_TX_DESC;
5754                 struct ring_info *tx_skb = tp->tx_skb + entry;
5755                 unsigned int len = tx_skb->len;
5756
5757                 if (len) {
5758                         struct sk_buff *skb = tx_skb->skb;
5759
5760                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5761                                              tp->TxDescArray + entry);
5762                         if (skb) {
5763                                 tp->dev->stats.tx_dropped++;
5764                                 dev_kfree_skb(skb);
5765                                 tx_skb->skb = NULL;
5766                         }
5767                 }
5768         }
5769 }
5770
5771 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5772 {
5773         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5774         tp->cur_tx = tp->dirty_tx = 0;
5775 }
5776
5777 static void rtl_reset_work(struct rtl8169_private *tp)
5778 {
5779         struct net_device *dev = tp->dev;
5780         int i;
5781
5782         napi_disable(&tp->napi);
5783         netif_stop_queue(dev);
5784         synchronize_sched();
5785
5786         rtl8169_hw_reset(tp);
5787
5788         for (i = 0; i < NUM_RX_DESC; i++)
5789                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5790
5791         rtl8169_tx_clear(tp);
5792         rtl8169_init_ring_indexes(tp);
5793
5794         napi_enable(&tp->napi);
5795         rtl_hw_start(dev);
5796         netif_wake_queue(dev);
5797         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5798 }
5799
5800 static void rtl8169_tx_timeout(struct net_device *dev)
5801 {
5802         struct rtl8169_private *tp = netdev_priv(dev);
5803
5804         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5805 }
5806
5807 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5808                               u32 *opts)
5809 {
5810         struct skb_shared_info *info = skb_shinfo(skb);
5811         unsigned int cur_frag, entry;
5812         struct TxDesc * uninitialized_var(txd);
5813         struct device *d = &tp->pci_dev->dev;
5814
5815         entry = tp->cur_tx;
5816         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5817                 const skb_frag_t *frag = info->frags + cur_frag;
5818                 dma_addr_t mapping;
5819                 u32 status, len;
5820                 void *addr;
5821
5822                 entry = (entry + 1) % NUM_TX_DESC;
5823
5824                 txd = tp->TxDescArray + entry;
5825                 len = skb_frag_size(frag);
5826                 addr = skb_frag_address(frag);
5827                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5828                 if (unlikely(dma_mapping_error(d, mapping))) {
5829                         if (net_ratelimit())
5830                                 netif_err(tp, drv, tp->dev,
5831                                           "Failed to map TX fragments DMA!\n");
5832                         goto err_out;
5833                 }
5834
5835                 /* Anti gcc 2.95.3 bugware (sic) */
5836                 status = opts[0] | len |
5837                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5838
5839                 txd->opts1 = cpu_to_le32(status);
5840                 txd->opts2 = cpu_to_le32(opts[1]);
5841                 txd->addr = cpu_to_le64(mapping);
5842
5843                 tp->tx_skb[entry].len = len;
5844         }
5845
5846         if (cur_frag) {
5847                 tp->tx_skb[entry].skb = skb;
5848                 txd->opts1 |= cpu_to_le32(LastFrag);
5849         }
5850
5851         return cur_frag;
5852
5853 err_out:
5854         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5855         return -EIO;
5856 }
5857
5858 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5859                                     struct sk_buff *skb, u32 *opts)
5860 {
5861         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5862         u32 mss = skb_shinfo(skb)->gso_size;
5863         int offset = info->opts_offset;
5864
5865         if (mss) {
5866                 opts[0] |= TD_LSO;
5867                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5868         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5869                 const struct iphdr *ip = ip_hdr(skb);
5870
5871                 if (ip->protocol == IPPROTO_TCP)
5872                         opts[offset] |= info->checksum.tcp;
5873                 else if (ip->protocol == IPPROTO_UDP)
5874                         opts[offset] |= info->checksum.udp;
5875                 else
5876                         WARN_ON_ONCE(1);
5877         }
5878 }
5879
5880 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5881                                       struct net_device *dev)
5882 {
5883         struct rtl8169_private *tp = netdev_priv(dev);
5884         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5885         struct TxDesc *txd = tp->TxDescArray + entry;
5886         void __iomem *ioaddr = tp->mmio_addr;
5887         struct device *d = &tp->pci_dev->dev;
5888         dma_addr_t mapping;
5889         u32 status, len;
5890         u32 opts[2];
5891         int frags;
5892
5893         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5894                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5895                 goto err_stop_0;
5896         }
5897
5898         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5899                 goto err_stop_0;
5900
5901         len = skb_headlen(skb);
5902         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5903         if (unlikely(dma_mapping_error(d, mapping))) {
5904                 if (net_ratelimit())
5905                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5906                 goto err_dma_0;
5907         }
5908
5909         tp->tx_skb[entry].len = len;
5910         txd->addr = cpu_to_le64(mapping);
5911
5912         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5913         opts[0] = DescOwn;
5914
5915         rtl8169_tso_csum(tp, skb, opts);
5916
5917         frags = rtl8169_xmit_frags(tp, skb, opts);
5918         if (frags < 0)
5919                 goto err_dma_1;
5920         else if (frags)
5921                 opts[0] |= FirstFrag;
5922         else {
5923                 opts[0] |= FirstFrag | LastFrag;
5924                 tp->tx_skb[entry].skb = skb;
5925         }
5926
5927         txd->opts2 = cpu_to_le32(opts[1]);
5928
5929         skb_tx_timestamp(skb);
5930
5931         wmb();
5932
5933         /* Anti gcc 2.95.3 bugware (sic) */
5934         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5935         txd->opts1 = cpu_to_le32(status);
5936
5937         tp->cur_tx += frags + 1;
5938
5939         wmb();
5940
5941         RTL_W8(TxPoll, NPQ);
5942
5943         mmiowb();
5944
5945         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5946                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5947                  * not miss a ring update when it notices a stopped queue.
5948                  */
5949                 smp_wmb();
5950                 netif_stop_queue(dev);
5951                 /* Sync with rtl_tx:
5952                  * - publish queue status and cur_tx ring index (write barrier)
5953                  * - refresh dirty_tx ring index (read barrier).
5954                  * May the current thread have a pessimistic view of the ring
5955                  * status and forget to wake up queue, a racing rtl_tx thread
5956                  * can't.
5957                  */
5958                 smp_mb();
5959                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5960                         netif_wake_queue(dev);
5961         }
5962
5963         return NETDEV_TX_OK;
5964
5965 err_dma_1:
5966         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5967 err_dma_0:
5968         dev_kfree_skb(skb);
5969         dev->stats.tx_dropped++;
5970         return NETDEV_TX_OK;
5971
5972 err_stop_0:
5973         netif_stop_queue(dev);
5974         dev->stats.tx_dropped++;
5975         return NETDEV_TX_BUSY;
5976 }
5977
5978 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5979 {
5980         struct rtl8169_private *tp = netdev_priv(dev);
5981         struct pci_dev *pdev = tp->pci_dev;
5982         u16 pci_status, pci_cmd;
5983
5984         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5985         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5986
5987         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5988                   pci_cmd, pci_status);
5989
5990         /*
5991          * The recovery sequence below admits a very elaborated explanation:
5992          * - it seems to work;
5993          * - I did not see what else could be done;
5994          * - it makes iop3xx happy.
5995          *
5996          * Feel free to adjust to your needs.
5997          */
5998         if (pdev->broken_parity_status)
5999                 pci_cmd &= ~PCI_COMMAND_PARITY;
6000         else
6001                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6002
6003         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6004
6005         pci_write_config_word(pdev, PCI_STATUS,
6006                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6007                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6008                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6009
6010         /* The infamous DAC f*ckup only happens at boot time */
6011         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6012                 void __iomem *ioaddr = tp->mmio_addr;
6013
6014                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6015                 tp->cp_cmd &= ~PCIDAC;
6016                 RTL_W16(CPlusCmd, tp->cp_cmd);
6017                 dev->features &= ~NETIF_F_HIGHDMA;
6018         }
6019
6020         rtl8169_hw_reset(tp);
6021
6022         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6023 }
6024
6025 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6026 {
6027         unsigned int dirty_tx, tx_left;
6028
6029         dirty_tx = tp->dirty_tx;
6030         smp_rmb();
6031         tx_left = tp->cur_tx - dirty_tx;
6032
6033         while (tx_left > 0) {
6034                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6035                 struct ring_info *tx_skb = tp->tx_skb + entry;
6036                 u32 status;
6037
6038                 rmb();
6039                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6040                 if (status & DescOwn)
6041                         break;
6042
6043                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6044                                      tp->TxDescArray + entry);
6045                 if (status & LastFrag) {
6046                         u64_stats_update_begin(&tp->tx_stats.syncp);
6047                         tp->tx_stats.packets++;
6048                         tp->tx_stats.bytes += tx_skb->skb->len;
6049                         u64_stats_update_end(&tp->tx_stats.syncp);
6050                         dev_kfree_skb(tx_skb->skb);
6051                         tx_skb->skb = NULL;
6052                 }
6053                 dirty_tx++;
6054                 tx_left--;
6055         }
6056
6057         if (tp->dirty_tx != dirty_tx) {
6058                 tp->dirty_tx = dirty_tx;
6059                 /* Sync with rtl8169_start_xmit:
6060                  * - publish dirty_tx ring index (write barrier)
6061                  * - refresh cur_tx ring index and queue status (read barrier)
6062                  * May the current thread miss the stopped queue condition,
6063                  * a racing xmit thread can only have a right view of the
6064                  * ring status.
6065                  */
6066                 smp_mb();
6067                 if (netif_queue_stopped(dev) &&
6068                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6069                         netif_wake_queue(dev);
6070                 }
6071                 /*
6072                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6073                  * too close. Let's kick an extra TxPoll request when a burst
6074                  * of start_xmit activity is detected (if it is not detected,
6075                  * it is slow enough). -- FR
6076                  */
6077                 if (tp->cur_tx != dirty_tx) {
6078                         void __iomem *ioaddr = tp->mmio_addr;
6079
6080                         RTL_W8(TxPoll, NPQ);
6081                 }
6082         }
6083 }
6084
6085 static inline int rtl8169_fragmented_frame(u32 status)
6086 {
6087         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6088 }
6089
6090 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6091 {
6092         u32 status = opts1 & RxProtoMask;
6093
6094         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6095             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6096                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6097         else
6098                 skb_checksum_none_assert(skb);
6099 }
6100
6101 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6102                                            struct rtl8169_private *tp,
6103                                            int pkt_size,
6104                                            dma_addr_t addr)
6105 {
6106         struct sk_buff *skb;
6107         struct device *d = &tp->pci_dev->dev;
6108
6109         data = rtl8169_align(data);
6110         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6111         prefetch(data);
6112         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6113         if (skb)
6114                 memcpy(skb->data, data, pkt_size);
6115         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6116
6117         return skb;
6118 }
6119
6120 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6121 {
6122         unsigned int cur_rx, rx_left;
6123         unsigned int count;
6124
6125         cur_rx = tp->cur_rx;
6126
6127         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6128                 unsigned int entry = cur_rx % NUM_RX_DESC;
6129                 struct RxDesc *desc = tp->RxDescArray + entry;
6130                 u32 status;
6131
6132                 rmb();
6133                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6134
6135                 if (status & DescOwn)
6136                         break;
6137                 if (unlikely(status & RxRES)) {
6138                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6139                                    status);
6140                         dev->stats.rx_errors++;
6141                         if (status & (RxRWT | RxRUNT))
6142                                 dev->stats.rx_length_errors++;
6143                         if (status & RxCRC)
6144                                 dev->stats.rx_crc_errors++;
6145                         if (status & RxFOVF) {
6146                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6147                                 dev->stats.rx_fifo_errors++;
6148                         }
6149                         if ((status & (RxRUNT | RxCRC)) &&
6150                             !(status & (RxRWT | RxFOVF)) &&
6151                             (dev->features & NETIF_F_RXALL))
6152                                 goto process_pkt;
6153                 } else {
6154                         struct sk_buff *skb;
6155                         dma_addr_t addr;
6156                         int pkt_size;
6157
6158 process_pkt:
6159                         addr = le64_to_cpu(desc->addr);
6160                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6161                                 pkt_size = (status & 0x00003fff) - 4;
6162                         else
6163                                 pkt_size = status & 0x00003fff;
6164
6165                         /*
6166                          * The driver does not support incoming fragmented
6167                          * frames. They are seen as a symptom of over-mtu
6168                          * sized frames.
6169                          */
6170                         if (unlikely(rtl8169_fragmented_frame(status))) {
6171                                 dev->stats.rx_dropped++;
6172                                 dev->stats.rx_length_errors++;
6173                                 goto release_descriptor;
6174                         }
6175
6176                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6177                                                   tp, pkt_size, addr);
6178                         if (!skb) {
6179                                 dev->stats.rx_dropped++;
6180                                 goto release_descriptor;
6181                         }
6182
6183                         rtl8169_rx_csum(skb, status);
6184                         skb_put(skb, pkt_size);
6185                         skb->protocol = eth_type_trans(skb, dev);
6186
6187                         rtl8169_rx_vlan_tag(desc, skb);
6188
6189                         napi_gro_receive(&tp->napi, skb);
6190
6191                         u64_stats_update_begin(&tp->rx_stats.syncp);
6192                         tp->rx_stats.packets++;
6193                         tp->rx_stats.bytes += pkt_size;
6194                         u64_stats_update_end(&tp->rx_stats.syncp);
6195                 }
6196 release_descriptor:
6197                 desc->opts2 = 0;
6198                 wmb();
6199                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6200         }
6201
6202         count = cur_rx - tp->cur_rx;
6203         tp->cur_rx = cur_rx;
6204
6205         return count;
6206 }
6207
6208 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6209 {
6210         struct net_device *dev = dev_instance;
6211         struct rtl8169_private *tp = netdev_priv(dev);
6212         int handled = 0;
6213         u16 status;
6214
6215         status = rtl_get_events(tp);
6216         if (status && status != 0xffff) {
6217                 status &= RTL_EVENT_NAPI | tp->event_slow;
6218                 if (status) {
6219                         handled = 1;
6220
6221                         rtl_irq_disable(tp);
6222                         napi_schedule(&tp->napi);
6223                 }
6224         }
6225         return IRQ_RETVAL(handled);
6226 }
6227
6228 /*
6229  * Workqueue context.
6230  */
6231 static void rtl_slow_event_work(struct rtl8169_private *tp)
6232 {
6233         struct net_device *dev = tp->dev;
6234         u16 status;
6235
6236         status = rtl_get_events(tp) & tp->event_slow;
6237         rtl_ack_events(tp, status);
6238
6239         if (unlikely(status & RxFIFOOver)) {
6240                 switch (tp->mac_version) {
6241                 /* Work around for rx fifo overflow */
6242                 case RTL_GIGA_MAC_VER_11:
6243                         netif_stop_queue(dev);
6244                         /* XXX - Hack alert. See rtl_task(). */
6245                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6246                 default:
6247                         break;
6248                 }
6249         }
6250
6251         if (unlikely(status & SYSErr))
6252                 rtl8169_pcierr_interrupt(dev);
6253
6254         if (status & LinkChg)
6255                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6256
6257         rtl_irq_enable_all(tp);
6258 }
6259
6260 static void rtl_task(struct work_struct *work)
6261 {
6262         static const struct {
6263                 int bitnr;
6264                 void (*action)(struct rtl8169_private *);
6265         } rtl_work[] = {
6266                 /* XXX - keep rtl_slow_event_work() as first element. */
6267                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6268                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6269                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6270         };
6271         struct rtl8169_private *tp =
6272                 container_of(work, struct rtl8169_private, wk.work);
6273         struct net_device *dev = tp->dev;
6274         int i;
6275
6276         rtl_lock_work(tp);
6277
6278         if (!netif_running(dev) ||
6279             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6280                 goto out_unlock;
6281
6282         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6283                 bool pending;
6284
6285                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6286                 if (pending)
6287                         rtl_work[i].action(tp);
6288         }
6289
6290 out_unlock:
6291         rtl_unlock_work(tp);
6292 }
6293
6294 static int rtl8169_poll(struct napi_struct *napi, int budget)
6295 {
6296         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6297         struct net_device *dev = tp->dev;
6298         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6299         int work_done= 0;
6300         u16 status;
6301
6302         status = rtl_get_events(tp);
6303         rtl_ack_events(tp, status & ~tp->event_slow);
6304
6305         if (status & RTL_EVENT_NAPI_RX)
6306                 work_done = rtl_rx(dev, tp, (u32) budget);
6307
6308         if (status & RTL_EVENT_NAPI_TX)
6309                 rtl_tx(dev, tp);
6310
6311         if (status & tp->event_slow) {
6312                 enable_mask &= ~tp->event_slow;
6313
6314                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6315         }
6316
6317         if (work_done < budget) {
6318                 napi_complete(napi);
6319
6320                 rtl_irq_enable(tp, enable_mask);
6321                 mmiowb();
6322         }
6323
6324         return work_done;
6325 }
6326
6327 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6328 {
6329         struct rtl8169_private *tp = netdev_priv(dev);
6330
6331         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6332                 return;
6333
6334         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6335         RTL_W32(RxMissed, 0);
6336 }
6337
6338 static void rtl8169_down(struct net_device *dev)
6339 {
6340         struct rtl8169_private *tp = netdev_priv(dev);
6341         void __iomem *ioaddr = tp->mmio_addr;
6342
6343         del_timer_sync(&tp->timer);
6344
6345         napi_disable(&tp->napi);
6346         netif_stop_queue(dev);
6347
6348         rtl8169_hw_reset(tp);
6349         /*
6350          * At this point device interrupts can not be enabled in any function,
6351          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6352          * and napi is disabled (rtl8169_poll).
6353          */
6354         rtl8169_rx_missed(dev, ioaddr);
6355
6356         /* Give a racing hard_start_xmit a few cycles to complete. */
6357         synchronize_sched();
6358
6359         rtl8169_tx_clear(tp);
6360
6361         rtl8169_rx_clear(tp);
6362
6363         rtl_pll_power_down(tp);
6364 }
6365
6366 static int rtl8169_close(struct net_device *dev)
6367 {
6368         struct rtl8169_private *tp = netdev_priv(dev);
6369         struct pci_dev *pdev = tp->pci_dev;
6370
6371         pm_runtime_get_sync(&pdev->dev);
6372
6373         /* Update counters before going down */
6374         rtl8169_update_counters(dev);
6375
6376         rtl_lock_work(tp);
6377         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6378
6379         rtl8169_down(dev);
6380         rtl_unlock_work(tp);
6381
6382         free_irq(pdev->irq, dev);
6383
6384         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6385                           tp->RxPhyAddr);
6386         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6387                           tp->TxPhyAddr);
6388         tp->TxDescArray = NULL;
6389         tp->RxDescArray = NULL;
6390
6391         pm_runtime_put_sync(&pdev->dev);
6392
6393         return 0;
6394 }
6395
6396 #ifdef CONFIG_NET_POLL_CONTROLLER
6397 static void rtl8169_netpoll(struct net_device *dev)
6398 {
6399         struct rtl8169_private *tp = netdev_priv(dev);
6400
6401         rtl8169_interrupt(tp->pci_dev->irq, dev);
6402 }
6403 #endif
6404
6405 static int rtl_open(struct net_device *dev)
6406 {
6407         struct rtl8169_private *tp = netdev_priv(dev);
6408         void __iomem *ioaddr = tp->mmio_addr;
6409         struct pci_dev *pdev = tp->pci_dev;
6410         int retval = -ENOMEM;
6411
6412         pm_runtime_get_sync(&pdev->dev);
6413
6414         /*
6415          * Rx and Tx descriptors needs 256 bytes alignment.
6416          * dma_alloc_coherent provides more.
6417          */
6418         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6419                                              &tp->TxPhyAddr, GFP_KERNEL);
6420         if (!tp->TxDescArray)
6421                 goto err_pm_runtime_put;
6422
6423         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6424                                              &tp->RxPhyAddr, GFP_KERNEL);
6425         if (!tp->RxDescArray)
6426                 goto err_free_tx_0;
6427
6428         retval = rtl8169_init_ring(dev);
6429         if (retval < 0)
6430                 goto err_free_rx_1;
6431
6432         INIT_WORK(&tp->wk.work, rtl_task);
6433
6434         smp_mb();
6435
6436         rtl_request_firmware(tp);
6437
6438         retval = request_irq(pdev->irq, rtl8169_interrupt,
6439                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6440                              dev->name, dev);
6441         if (retval < 0)
6442                 goto err_release_fw_2;
6443
6444         rtl_lock_work(tp);
6445
6446         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6447
6448         napi_enable(&tp->napi);
6449
6450         rtl8169_init_phy(dev, tp);
6451
6452         __rtl8169_set_features(dev, dev->features);
6453
6454         rtl_pll_power_up(tp);
6455
6456         rtl_hw_start(dev);
6457
6458         netif_start_queue(dev);
6459
6460         rtl_unlock_work(tp);
6461
6462         tp->saved_wolopts = 0;
6463         pm_runtime_put_noidle(&pdev->dev);
6464
6465         rtl8169_check_link_status(dev, tp, ioaddr);
6466 out:
6467         return retval;
6468
6469 err_release_fw_2:
6470         rtl_release_firmware(tp);
6471         rtl8169_rx_clear(tp);
6472 err_free_rx_1:
6473         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6474                           tp->RxPhyAddr);
6475         tp->RxDescArray = NULL;
6476 err_free_tx_0:
6477         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6478                           tp->TxPhyAddr);
6479         tp->TxDescArray = NULL;
6480 err_pm_runtime_put:
6481         pm_runtime_put_noidle(&pdev->dev);
6482         goto out;
6483 }
6484
6485 static struct rtnl_link_stats64 *
6486 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6487 {
6488         struct rtl8169_private *tp = netdev_priv(dev);
6489         void __iomem *ioaddr = tp->mmio_addr;
6490         unsigned int start;
6491
6492         if (netif_running(dev))
6493                 rtl8169_rx_missed(dev, ioaddr);
6494
6495         do {
6496                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6497                 stats->rx_packets = tp->rx_stats.packets;
6498                 stats->rx_bytes = tp->rx_stats.bytes;
6499         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6500
6501
6502         do {
6503                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6504                 stats->tx_packets = tp->tx_stats.packets;
6505                 stats->tx_bytes = tp->tx_stats.bytes;
6506         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6507
6508         stats->rx_dropped       = dev->stats.rx_dropped;
6509         stats->tx_dropped       = dev->stats.tx_dropped;
6510         stats->rx_length_errors = dev->stats.rx_length_errors;
6511         stats->rx_errors        = dev->stats.rx_errors;
6512         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6513         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6514         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6515
6516         return stats;
6517 }
6518
6519 static void rtl8169_net_suspend(struct net_device *dev)
6520 {
6521         struct rtl8169_private *tp = netdev_priv(dev);
6522
6523         if (!netif_running(dev))
6524                 return;
6525
6526         netif_device_detach(dev);
6527         netif_stop_queue(dev);
6528
6529         rtl_lock_work(tp);
6530         napi_disable(&tp->napi);
6531         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6532         rtl_unlock_work(tp);
6533
6534         rtl_pll_power_down(tp);
6535 }
6536
6537 #ifdef CONFIG_PM
6538
6539 static int rtl8169_suspend(struct device *device)
6540 {
6541         struct pci_dev *pdev = to_pci_dev(device);
6542         struct net_device *dev = pci_get_drvdata(pdev);
6543
6544         rtl8169_net_suspend(dev);
6545
6546         return 0;
6547 }
6548
6549 static void __rtl8169_resume(struct net_device *dev)
6550 {
6551         struct rtl8169_private *tp = netdev_priv(dev);
6552
6553         netif_device_attach(dev);
6554
6555         rtl_pll_power_up(tp);
6556
6557         rtl_lock_work(tp);
6558         napi_enable(&tp->napi);
6559         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6560         rtl_unlock_work(tp);
6561
6562         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6563 }
6564
6565 static int rtl8169_resume(struct device *device)
6566 {
6567         struct pci_dev *pdev = to_pci_dev(device);
6568         struct net_device *dev = pci_get_drvdata(pdev);
6569         struct rtl8169_private *tp = netdev_priv(dev);
6570
6571         rtl8169_init_phy(dev, tp);
6572
6573         if (netif_running(dev))
6574                 __rtl8169_resume(dev);
6575
6576         return 0;
6577 }
6578
6579 static int rtl8169_runtime_suspend(struct device *device)
6580 {
6581         struct pci_dev *pdev = to_pci_dev(device);
6582         struct net_device *dev = pci_get_drvdata(pdev);
6583         struct rtl8169_private *tp = netdev_priv(dev);
6584
6585         if (!tp->TxDescArray)
6586                 return 0;
6587
6588         rtl_lock_work(tp);
6589         tp->saved_wolopts = __rtl8169_get_wol(tp);
6590         __rtl8169_set_wol(tp, WAKE_ANY);
6591         rtl_unlock_work(tp);
6592
6593         rtl8169_net_suspend(dev);
6594
6595         return 0;
6596 }
6597
6598 static int rtl8169_runtime_resume(struct device *device)
6599 {
6600         struct pci_dev *pdev = to_pci_dev(device);
6601         struct net_device *dev = pci_get_drvdata(pdev);
6602         struct rtl8169_private *tp = netdev_priv(dev);
6603
6604         if (!tp->TxDescArray)
6605                 return 0;
6606
6607         rtl_lock_work(tp);
6608         __rtl8169_set_wol(tp, tp->saved_wolopts);
6609         tp->saved_wolopts = 0;
6610         rtl_unlock_work(tp);
6611
6612         rtl8169_init_phy(dev, tp);
6613
6614         __rtl8169_resume(dev);
6615
6616         return 0;
6617 }
6618
6619 static int rtl8169_runtime_idle(struct device *device)
6620 {
6621         struct pci_dev *pdev = to_pci_dev(device);
6622         struct net_device *dev = pci_get_drvdata(pdev);
6623         struct rtl8169_private *tp = netdev_priv(dev);
6624
6625         return tp->TxDescArray ? -EBUSY : 0;
6626 }
6627
6628 static const struct dev_pm_ops rtl8169_pm_ops = {
6629         .suspend                = rtl8169_suspend,
6630         .resume                 = rtl8169_resume,
6631         .freeze                 = rtl8169_suspend,
6632         .thaw                   = rtl8169_resume,
6633         .poweroff               = rtl8169_suspend,
6634         .restore                = rtl8169_resume,
6635         .runtime_suspend        = rtl8169_runtime_suspend,
6636         .runtime_resume         = rtl8169_runtime_resume,
6637         .runtime_idle           = rtl8169_runtime_idle,
6638 };
6639
6640 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6641
6642 #else /* !CONFIG_PM */
6643
6644 #define RTL8169_PM_OPS  NULL
6645
6646 #endif /* !CONFIG_PM */
6647
6648 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6649 {
6650         void __iomem *ioaddr = tp->mmio_addr;
6651
6652         /* WoL fails with 8168b when the receiver is disabled. */
6653         switch (tp->mac_version) {
6654         case RTL_GIGA_MAC_VER_11:
6655         case RTL_GIGA_MAC_VER_12:
6656         case RTL_GIGA_MAC_VER_17:
6657                 pci_clear_master(tp->pci_dev);
6658
6659                 RTL_W8(ChipCmd, CmdRxEnb);
6660                 /* PCI commit */
6661                 RTL_R8(ChipCmd);
6662                 break;
6663         default:
6664                 break;
6665         }
6666 }
6667
6668 static void rtl_shutdown(struct pci_dev *pdev)
6669 {
6670         struct net_device *dev = pci_get_drvdata(pdev);
6671         struct rtl8169_private *tp = netdev_priv(dev);
6672         struct device *d = &pdev->dev;
6673
6674         pm_runtime_get_sync(d);
6675
6676         rtl8169_net_suspend(dev);
6677
6678         /* Restore original MAC address */
6679         rtl_rar_set(tp, dev->perm_addr);
6680
6681         rtl8169_hw_reset(tp);
6682
6683         if (system_state == SYSTEM_POWER_OFF) {
6684                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6685                         rtl_wol_suspend_quirk(tp);
6686                         rtl_wol_shutdown_quirk(tp);
6687                 }
6688
6689                 pci_wake_from_d3(pdev, true);
6690                 pci_set_power_state(pdev, PCI_D3hot);
6691         }
6692
6693         pm_runtime_put_noidle(d);
6694 }
6695
6696 static void rtl_remove_one(struct pci_dev *pdev)
6697 {
6698         struct net_device *dev = pci_get_drvdata(pdev);
6699         struct rtl8169_private *tp = netdev_priv(dev);
6700
6701         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6702             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6703             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6704                 rtl8168_driver_stop(tp);
6705         }
6706
6707         cancel_work_sync(&tp->wk.work);
6708
6709         netif_napi_del(&tp->napi);
6710
6711         unregister_netdev(dev);
6712
6713         rtl_release_firmware(tp);
6714
6715         if (pci_dev_run_wake(pdev))
6716                 pm_runtime_get_noresume(&pdev->dev);
6717
6718         /* restore original MAC address */
6719         rtl_rar_set(tp, dev->perm_addr);
6720
6721         rtl_disable_msi(pdev, tp);
6722         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6723         pci_set_drvdata(pdev, NULL);
6724 }
6725
6726 static const struct net_device_ops rtl_netdev_ops = {
6727         .ndo_open               = rtl_open,
6728         .ndo_stop               = rtl8169_close,
6729         .ndo_get_stats64        = rtl8169_get_stats64,
6730         .ndo_start_xmit         = rtl8169_start_xmit,
6731         .ndo_tx_timeout         = rtl8169_tx_timeout,
6732         .ndo_validate_addr      = eth_validate_addr,
6733         .ndo_change_mtu         = rtl8169_change_mtu,
6734         .ndo_fix_features       = rtl8169_fix_features,
6735         .ndo_set_features       = rtl8169_set_features,
6736         .ndo_set_mac_address    = rtl_set_mac_address,
6737         .ndo_do_ioctl           = rtl8169_ioctl,
6738         .ndo_set_rx_mode        = rtl_set_rx_mode,
6739 #ifdef CONFIG_NET_POLL_CONTROLLER
6740         .ndo_poll_controller    = rtl8169_netpoll,
6741 #endif
6742
6743 };
6744
6745 static const struct rtl_cfg_info {
6746         void (*hw_start)(struct net_device *);
6747         unsigned int region;
6748         unsigned int align;
6749         u16 event_slow;
6750         unsigned features;
6751         u8 default_ver;
6752 } rtl_cfg_infos [] = {
6753         [RTL_CFG_0] = {
6754                 .hw_start       = rtl_hw_start_8169,
6755                 .region         = 1,
6756                 .align          = 0,
6757                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6758                 .features       = RTL_FEATURE_GMII,
6759                 .default_ver    = RTL_GIGA_MAC_VER_01,
6760         },
6761         [RTL_CFG_1] = {
6762                 .hw_start       = rtl_hw_start_8168,
6763                 .region         = 2,
6764                 .align          = 8,
6765                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6766                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6767                 .default_ver    = RTL_GIGA_MAC_VER_11,
6768         },
6769         [RTL_CFG_2] = {
6770                 .hw_start       = rtl_hw_start_8101,
6771                 .region         = 2,
6772                 .align          = 8,
6773                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6774                                   PCSTimeout,
6775                 .features       = RTL_FEATURE_MSI,
6776                 .default_ver    = RTL_GIGA_MAC_VER_13,
6777         }
6778 };
6779
6780 /* Cfg9346_Unlock assumed. */
6781 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6782                             const struct rtl_cfg_info *cfg)
6783 {
6784         void __iomem *ioaddr = tp->mmio_addr;
6785         unsigned msi = 0;
6786         u8 cfg2;
6787
6788         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6789         if (cfg->features & RTL_FEATURE_MSI) {
6790                 if (pci_enable_msi(tp->pci_dev)) {
6791                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6792                 } else {
6793                         cfg2 |= MSIEnable;
6794                         msi = RTL_FEATURE_MSI;
6795                 }
6796         }
6797         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6798                 RTL_W8(Config2, cfg2);
6799         return msi;
6800 }
6801
6802 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6803 {
6804         void __iomem *ioaddr = tp->mmio_addr;
6805
6806         return RTL_R8(MCU) & LINK_LIST_RDY;
6807 }
6808
6809 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6810 {
6811         void __iomem *ioaddr = tp->mmio_addr;
6812
6813         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6814 }
6815
6816 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6817 {
6818         void __iomem *ioaddr = tp->mmio_addr;
6819         u32 data;
6820
6821         tp->ocp_base = OCP_STD_PHY_BASE;
6822
6823         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6824
6825         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6826                 return;
6827
6828         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6829                 return;
6830
6831         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6832         msleep(1);
6833         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6834
6835         data = r8168_mac_ocp_read(tp, 0xe8de);
6836         data &= ~(1 << 14);
6837         r8168_mac_ocp_write(tp, 0xe8de, data);
6838
6839         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6840                 return;
6841
6842         data = r8168_mac_ocp_read(tp, 0xe8de);
6843         data |= (1 << 15);
6844         r8168_mac_ocp_write(tp, 0xe8de, data);
6845
6846         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6847                 return;
6848 }
6849
6850 static void rtl_hw_initialize(struct rtl8169_private *tp)
6851 {
6852         switch (tp->mac_version) {
6853         case RTL_GIGA_MAC_VER_40:
6854         case RTL_GIGA_MAC_VER_41:
6855         case RTL_GIGA_MAC_VER_42:
6856         case RTL_GIGA_MAC_VER_43:
6857                 rtl_hw_init_8168g(tp);
6858                 break;
6859
6860         default:
6861                 break;
6862         }
6863 }
6864
6865 static int
6866 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6867 {
6868         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6869         const unsigned int region = cfg->region;
6870         struct rtl8169_private *tp;
6871         struct mii_if_info *mii;
6872         struct net_device *dev;
6873         void __iomem *ioaddr;
6874         int chipset, i;
6875         int rc;
6876
6877         if (netif_msg_drv(&debug)) {
6878                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6879                        MODULENAME, RTL8169_VERSION);
6880         }
6881
6882         dev = alloc_etherdev(sizeof (*tp));
6883         if (!dev) {
6884                 rc = -ENOMEM;
6885                 goto out;
6886         }
6887
6888         SET_NETDEV_DEV(dev, &pdev->dev);
6889         dev->netdev_ops = &rtl_netdev_ops;
6890         tp = netdev_priv(dev);
6891         tp->dev = dev;
6892         tp->pci_dev = pdev;
6893         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6894
6895         mii = &tp->mii;
6896         mii->dev = dev;
6897         mii->mdio_read = rtl_mdio_read;
6898         mii->mdio_write = rtl_mdio_write;
6899         mii->phy_id_mask = 0x1f;
6900         mii->reg_num_mask = 0x1f;
6901         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6902
6903         /* disable ASPM completely as that cause random device stop working
6904          * problems as well as full system hangs for some PCIe devices users */
6905         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6906                                      PCIE_LINK_STATE_CLKPM);
6907
6908         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6909         rc = pci_enable_device(pdev);
6910         if (rc < 0) {
6911                 netif_err(tp, probe, dev, "enable failure\n");
6912                 goto err_out_free_dev_1;
6913         }
6914
6915         if (pci_set_mwi(pdev) < 0)
6916                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6917
6918         /* make sure PCI base addr 1 is MMIO */
6919         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6920                 netif_err(tp, probe, dev,
6921                           "region #%d not an MMIO resource, aborting\n",
6922                           region);
6923                 rc = -ENODEV;
6924                 goto err_out_mwi_2;
6925         }
6926
6927         /* check for weird/broken PCI region reporting */
6928         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6929                 netif_err(tp, probe, dev,
6930                           "Invalid PCI region size(s), aborting\n");
6931                 rc = -ENODEV;
6932                 goto err_out_mwi_2;
6933         }
6934
6935         rc = pci_request_regions(pdev, MODULENAME);
6936         if (rc < 0) {
6937                 netif_err(tp, probe, dev, "could not request regions\n");
6938                 goto err_out_mwi_2;
6939         }
6940
6941         tp->cp_cmd = RxChkSum;
6942
6943         if ((sizeof(dma_addr_t) > 4) &&
6944             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6945                 tp->cp_cmd |= PCIDAC;
6946                 dev->features |= NETIF_F_HIGHDMA;
6947         } else {
6948                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6949                 if (rc < 0) {
6950                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6951                         goto err_out_free_res_3;
6952                 }
6953         }
6954
6955         /* ioremap MMIO region */
6956         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6957         if (!ioaddr) {
6958                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6959                 rc = -EIO;
6960                 goto err_out_free_res_3;
6961         }
6962         tp->mmio_addr = ioaddr;
6963
6964         if (!pci_is_pcie(pdev))
6965                 netif_info(tp, probe, dev, "not PCI Express\n");
6966
6967         /* Identify chip attached to board */
6968         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6969
6970         rtl_init_rxcfg(tp);
6971
6972         rtl_irq_disable(tp);
6973
6974         rtl_hw_initialize(tp);
6975
6976         rtl_hw_reset(tp);
6977
6978         rtl_ack_events(tp, 0xffff);
6979
6980         pci_set_master(pdev);
6981
6982         /*
6983          * Pretend we are using VLANs; This bypasses a nasty bug where
6984          * Interrupts stop flowing on high load on 8110SCd controllers.
6985          */
6986         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6987                 tp->cp_cmd |= RxVlan;
6988
6989         rtl_init_mdio_ops(tp);
6990         rtl_init_pll_power_ops(tp);
6991         rtl_init_jumbo_ops(tp);
6992         rtl_init_csi_ops(tp);
6993
6994         rtl8169_print_mac_version(tp);
6995
6996         chipset = tp->mac_version;
6997         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6998
6999         RTL_W8(Cfg9346, Cfg9346_Unlock);
7000         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7001         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
7002         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7003                 tp->features |= RTL_FEATURE_WOL;
7004         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7005                 tp->features |= RTL_FEATURE_WOL;
7006         tp->features |= rtl_try_msi(tp, cfg);
7007         RTL_W8(Cfg9346, Cfg9346_Lock);
7008
7009         if (rtl_tbi_enabled(tp)) {
7010                 tp->set_speed = rtl8169_set_speed_tbi;
7011                 tp->get_settings = rtl8169_gset_tbi;
7012                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7013                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7014                 tp->link_ok = rtl8169_tbi_link_ok;
7015                 tp->do_ioctl = rtl_tbi_ioctl;
7016         } else {
7017                 tp->set_speed = rtl8169_set_speed_xmii;
7018                 tp->get_settings = rtl8169_gset_xmii;
7019                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7020                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7021                 tp->link_ok = rtl8169_xmii_link_ok;
7022                 tp->do_ioctl = rtl_xmii_ioctl;
7023         }
7024
7025         mutex_init(&tp->wk.mutex);
7026
7027         /* Get MAC address */
7028         for (i = 0; i < ETH_ALEN; i++)
7029                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7030
7031         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7032         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7033
7034         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7035
7036         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7037          * properly for all devices */
7038         dev->features |= NETIF_F_RXCSUM |
7039                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7040
7041         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7042                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7043         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7044                 NETIF_F_HIGHDMA;
7045
7046         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7047                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7048                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
7049
7050         dev->hw_features |= NETIF_F_RXALL;
7051         dev->hw_features |= NETIF_F_RXFCS;
7052
7053         tp->hw_start = cfg->hw_start;
7054         tp->event_slow = cfg->event_slow;
7055
7056         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7057                 ~(RxBOVF | RxFOVF) : ~0;
7058
7059         init_timer(&tp->timer);
7060         tp->timer.data = (unsigned long) dev;
7061         tp->timer.function = rtl8169_phy_timer;
7062
7063         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7064
7065         rc = register_netdev(dev);
7066         if (rc < 0)
7067                 goto err_out_msi_4;
7068
7069         pci_set_drvdata(pdev, dev);
7070
7071         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7072                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7073                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7074         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7075                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7076                            "tx checksumming: %s]\n",
7077                            rtl_chip_infos[chipset].jumbo_max,
7078                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7079         }
7080
7081         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7082             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7083             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7084                 rtl8168_driver_start(tp);
7085         }
7086
7087         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7088
7089         if (pci_dev_run_wake(pdev))
7090                 pm_runtime_put_noidle(&pdev->dev);
7091
7092         netif_carrier_off(dev);
7093
7094 out:
7095         return rc;
7096
7097 err_out_msi_4:
7098         netif_napi_del(&tp->napi);
7099         rtl_disable_msi(pdev, tp);
7100         iounmap(ioaddr);
7101 err_out_free_res_3:
7102         pci_release_regions(pdev);
7103 err_out_mwi_2:
7104         pci_clear_mwi(pdev);
7105         pci_disable_device(pdev);
7106 err_out_free_dev_1:
7107         free_netdev(dev);
7108         goto out;
7109 }
7110
7111 static struct pci_driver rtl8169_pci_driver = {
7112         .name           = MODULENAME,
7113         .id_table       = rtl8169_pci_tbl,
7114         .probe          = rtl_init_one,
7115         .remove         = rtl_remove_one,
7116         .shutdown       = rtl_shutdown,
7117         .driver.pm      = RTL8169_PM_OPS,
7118 };
7119
7120 module_pci_driver(rtl8169_pci_driver);