2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01 = 0,
161 RTL_GIGA_MAC_NONE = 0xff,
164 enum rtl_tx_desc_version {
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version;
189 } rtl_chip_infos[] = {
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347 static int rx_buf_sz = 16383;
348 static int use_dac = -1;
354 MAC0 = 0, /* Ethernet hardware address. */
356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
371 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
375 #define RX128_INT_EN (1 << 15) /* 8111c and later */
376 #define RX_MULTI_EN (1 << 14) /* 8111c only */
377 #define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
380 #define RX_EARLY_OFF (1 << 11)
381 #define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
390 #define PME_SIGNAL (1 << 5) /* 8168c and later */
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
405 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
409 #define TxPacketMax (8064 >> 7)
410 #define EarlySize 0x27
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
419 FuncForceEvent = 0xfc,
422 enum rtl8110_registers {
428 enum rtl8168_8101_registers {
431 #define CSIAR_FLAG 0x80000000
432 #define CSIAR_WRITE_CMD 0x80000000
433 #define CSIAR_BYTE_ENABLE 0x0f
434 #define CSIAR_BYTE_ENABLE_SHIFT 12
435 #define CSIAR_ADDR_MASK 0x0fff
436 #define CSIAR_FUNC_CARD 0x00000000
437 #define CSIAR_FUNC_SDIO 0x00010000
438 #define CSIAR_FUNC_NIC 0x00020000
439 #define CSIAR_FUNC_NIC2 0x00010000
442 #define EPHYAR_FLAG 0x80000000
443 #define EPHYAR_WRITE_CMD 0x80000000
444 #define EPHYAR_REG_MASK 0x1f
445 #define EPHYAR_REG_SHIFT 16
446 #define EPHYAR_DATA_MASK 0xffff
448 #define PFM_EN (1 << 6)
449 #define TX_10M_PS_EN (1 << 7)
451 #define FIX_NAK_1 (1 << 4)
452 #define FIX_NAK_2 (1 << 3)
455 #define NOW_IS_OOB (1 << 7)
456 #define TX_EMPTY (1 << 5)
457 #define RX_EMPTY (1 << 4)
458 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
459 #define EN_NDP (1 << 3)
460 #define EN_OOB_RESET (1 << 2)
461 #define LINK_LIST_RDY (1 << 1)
463 #define EFUSEAR_FLAG 0x80000000
464 #define EFUSEAR_WRITE_CMD 0x80000000
465 #define EFUSEAR_READ_CMD 0x00000000
466 #define EFUSEAR_REG_MASK 0x03ff
467 #define EFUSEAR_REG_SHIFT 8
468 #define EFUSEAR_DATA_MASK 0xff
470 #define PFM_D3COLD_EN (1 << 6)
473 enum rtl8168_registers {
478 #define ERIAR_FLAG 0x80000000
479 #define ERIAR_WRITE_CMD 0x80000000
480 #define ERIAR_READ_CMD 0x00000000
481 #define ERIAR_ADDR_BYTE_ALIGN 4
482 #define ERIAR_TYPE_SHIFT 16
483 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MASK_SHIFT 12
488 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495 #define OCPDR_WRITE_CMD 0x80000000
496 #define OCPDR_READ_CMD 0x00000000
497 #define OCPDR_REG_MASK 0x7f
498 #define OCPDR_GPHY_REG_SHIFT 16
499 #define OCPDR_DATA_MASK 0xffff
501 #define OCPAR_FLAG 0x80000000
502 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
503 #define OCPAR_GPHY_READ_CMD 0x0000f060
505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
507 #define TXPLA_RST (1 << 29)
508 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
509 #define PWM_EN (1 << 22)
510 #define RXDV_GATED_EN (1 << 19)
511 #define EARLY_TALLY_EN (1 << 16)
514 enum rtl_register_content {
515 /* InterruptStatusBits */
519 TxDescUnavail = 0x0080,
543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
550 Cfg9346_Unlock = 0xc0,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
558 AcceptAllPhys = 0x01,
559 #define RX_CONFIG_ACCEPT_MASK 0x3f
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
565 /* Config1 register p.24 */
568 Speed_down = (1 << 4),
572 PMEnable = (1 << 0), /* Power Management Enable */
574 /* Config2 register p. 25 */
575 ClkReqEn = (1 << 7), /* Clock Request Enable */
576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
590 /* Config5 register p.27 */
591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
595 LanWake = (1 << 1), /* LanWake enable/disable */
596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
597 ASPM_en = (1 << 0), /* ASPM enable */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
627 /* rtl8169_PHYstatus */
638 TBILinkOK = 0x02000000,
640 /* ResetCounterCommand */
643 /* DumpCounterCommand */
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
651 /* First doubleword. */
652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
659 enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662 #define TD_MSS_MAX 0x07ffu /* MSS value */
664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
668 /* 8169, 8168b and 810x except 8102e. */
669 enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
677 /* 8102e, 8168c and beyond. */
678 enum rtl_tx_desc_bit_1 {
679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
682 #define GTTCPHO_SHIFT 18
683 #define GTTCPHO_MAX 0x7fU
685 /* Second doubleword. */
686 #define TCPHO_SHIFT 18
687 #define TCPHO_MAX 0x3ffU
688 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
695 enum rtl_rx_desc_bit {
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
700 #define RxProtoUDP (PID1)
701 #define RxProtoTCP (PID0)
702 #define RxProtoIP (PID1 | PID0)
703 #define RxProtoMask RxProtoIP
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
711 #define RsvdMask 0x3fffc000
728 u8 __pad[sizeof(void *) - sizeof(u32)];
732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
737 struct rtl8169_counters {
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
753 struct rtl8169_tc_offsets {
756 __le32 tx_multi_collision;
761 RTL_FLAG_TASK_ENABLED,
762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
768 struct rtl8169_stats {
771 struct u64_stats_sync syncp;
774 struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
776 struct pci_dev *pci_dev;
777 struct net_device *dev;
778 struct napi_struct napi;
782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
793 struct timer_list timer;
799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
820 void (*phy_reset_enable)(struct rtl8169_private *tp);
821 void (*hw_start)(struct net_device *);
822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
823 unsigned int (*link_ok)(void __iomem *);
824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
830 struct work_struct work;
835 struct mii_if_info mii;
836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
838 struct rtl8169_tc_offsets tc_offset;
843 const struct firmware *fw;
845 #define RTL_VER_SIZE 32
847 char version[RTL_VER_SIZE];
849 struct rtl_fw_phy_action {
854 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
859 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
860 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
861 module_param(use_dac, int, 0);
862 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
863 module_param_named(debug, debug.msg_enable, int, 0);
864 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
865 MODULE_LICENSE("GPL");
866 MODULE_VERSION(RTL8169_VERSION);
867 MODULE_FIRMWARE(FIRMWARE_8168D_1);
868 MODULE_FIRMWARE(FIRMWARE_8168D_2);
869 MODULE_FIRMWARE(FIRMWARE_8168E_1);
870 MODULE_FIRMWARE(FIRMWARE_8168E_2);
871 MODULE_FIRMWARE(FIRMWARE_8168E_3);
872 MODULE_FIRMWARE(FIRMWARE_8105E_1);
873 MODULE_FIRMWARE(FIRMWARE_8168F_1);
874 MODULE_FIRMWARE(FIRMWARE_8168F_2);
875 MODULE_FIRMWARE(FIRMWARE_8402_1);
876 MODULE_FIRMWARE(FIRMWARE_8411_1);
877 MODULE_FIRMWARE(FIRMWARE_8411_2);
878 MODULE_FIRMWARE(FIRMWARE_8106E_1);
879 MODULE_FIRMWARE(FIRMWARE_8106E_2);
880 MODULE_FIRMWARE(FIRMWARE_8168G_2);
881 MODULE_FIRMWARE(FIRMWARE_8168G_3);
882 MODULE_FIRMWARE(FIRMWARE_8168H_1);
883 MODULE_FIRMWARE(FIRMWARE_8168H_2);
884 MODULE_FIRMWARE(FIRMWARE_8107E_1);
885 MODULE_FIRMWARE(FIRMWARE_8107E_2);
887 static void rtl_lock_work(struct rtl8169_private *tp)
889 mutex_lock(&tp->wk.mutex);
892 static void rtl_unlock_work(struct rtl8169_private *tp)
894 mutex_unlock(&tp->wk.mutex);
897 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
904 bool (*check)(struct rtl8169_private *);
908 static void rtl_udelay(unsigned int d)
913 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
919 for (i = 0; i < n; i++) {
921 if (c->check(tp) == high)
924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
929 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
936 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
943 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
950 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
957 #define DECLARE_RTL_COND(name) \
958 static bool name ## _check(struct rtl8169_private *); \
960 static const struct rtl_cond name = { \
961 .check = name ## _check, \
965 static bool name ## _check(struct rtl8169_private *tp)
967 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
976 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
978 void __iomem *ioaddr = tp->mmio_addr;
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
983 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
985 void __iomem *ioaddr = tp->mmio_addr;
987 if (rtl_ocp_reg_failure(tp, reg))
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
995 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
997 void __iomem *ioaddr = tp->mmio_addr;
999 if (rtl_ocp_reg_failure(tp, reg))
1002 RTL_W32(GPHY_OCP, reg << 15);
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1008 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1010 void __iomem *ioaddr = tp->mmio_addr;
1012 if (rtl_ocp_reg_failure(tp, reg))
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1018 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1020 void __iomem *ioaddr = tp->mmio_addr;
1022 if (rtl_ocp_reg_failure(tp, reg))
1025 RTL_W32(OCPDR, reg << 15);
1027 return RTL_R32(OCPDR);
1030 #define OCP_STD_PHY_BASE 0xa400
1032 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1045 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1053 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1056 tp->ocp_base = value << 4;
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1063 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1068 DECLARE_RTL_COND(rtl_phyar_cond)
1070 void __iomem *ioaddr = tp->mmio_addr;
1072 return RTL_R32(PHYAR) & 0x80000000;
1075 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1077 void __iomem *ioaddr = tp->mmio_addr;
1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
1089 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1091 void __iomem *ioaddr = tp->mmio_addr;
1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1108 DECLARE_RTL_COND(rtl_ocpar_cond)
1110 void __iomem *ioaddr = tp->mmio_addr;
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1115 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1117 void __iomem *ioaddr = tp->mmio_addr;
1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1126 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1132 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1134 void __iomem *ioaddr = tp->mmio_addr;
1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1146 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1148 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1153 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1158 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1160 void __iomem *ioaddr = tp->mmio_addr;
1162 r8168dp_2_mdio_start(ioaddr);
1164 r8169_mdio_write(tp, reg, value);
1166 r8168dp_2_mdio_stop(ioaddr);
1169 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1171 void __iomem *ioaddr = tp->mmio_addr;
1174 r8168dp_2_mdio_start(ioaddr);
1176 value = r8169_mdio_read(tp, reg);
1178 r8168dp_2_mdio_stop(ioaddr);
1183 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1185 tp->mdio_ops.write(tp, location, val);
1188 static int rtl_readphy(struct rtl8169_private *tp, int location)
1190 return tp->mdio_ops.read(tp, location);
1193 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1198 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1202 val = rtl_readphy(tp, reg_addr);
1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1206 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1209 struct rtl8169_private *tp = netdev_priv(dev);
1211 rtl_writephy(tp, location, val);
1214 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1216 struct rtl8169_private *tp = netdev_priv(dev);
1218 return rtl_readphy(tp, location);
1221 DECLARE_RTL_COND(rtl_ephyar_cond)
1223 void __iomem *ioaddr = tp->mmio_addr;
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1228 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1230 void __iomem *ioaddr = tp->mmio_addr;
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1240 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1242 void __iomem *ioaddr = tp->mmio_addr;
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1250 DECLARE_RTL_COND(rtl_eriar_cond)
1252 void __iomem *ioaddr = tp->mmio_addr;
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1257 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1260 void __iomem *ioaddr = tp->mmio_addr;
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1269 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1271 void __iomem *ioaddr = tp->mmio_addr;
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
1279 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1288 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1290 void __iomem *ioaddr = tp->mmio_addr;
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1297 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1302 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1319 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1322 void __iomem *ioaddr = tp->mmio_addr;
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1329 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1336 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1355 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1362 #define OOB_CMD_RESET 0x00
1363 #define OOB_CMD_DRIVER_START 0x05
1364 #define OOB_CMD_DRIVER_STOP 0x06
1366 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1371 DECLARE_RTL_COND(rtl_ocp_read_cond)
1375 reg = rtl8168_get_ocp_reg(tp);
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1380 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1385 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1387 void __iomem *ioaddr = tp->mmio_addr;
1389 return RTL_R8(IBISR0) & 0x02;
1392 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1394 void __iomem *ioaddr = tp->mmio_addr;
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1402 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1408 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1415 static void rtl8168_driver_start(struct rtl8169_private *tp)
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1434 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1440 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1442 rtl8168ep_stop_cmac(tp);
1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1448 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1467 static int r8168dp_check_dash(struct rtl8169_private *tp)
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1474 static int r8168ep_check_dash(struct rtl8169_private *tp)
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1479 static int r8168_check_dash(struct rtl8169_private *tp)
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1501 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1502 const struct exgmac_reg *r, int len)
1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1510 DECLARE_RTL_COND(rtl_efusear_cond)
1512 void __iomem *ioaddr = tp->mmio_addr;
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1517 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1519 void __iomem *ioaddr = tp->mmio_addr;
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1527 static u16 rtl_get_events(struct rtl8169_private *tp)
1529 void __iomem *ioaddr = tp->mmio_addr;
1531 return RTL_R16(IntrStatus);
1534 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1536 void __iomem *ioaddr = tp->mmio_addr;
1538 RTL_W16(IntrStatus, bits);
1542 static void rtl_irq_disable(struct rtl8169_private *tp)
1544 void __iomem *ioaddr = tp->mmio_addr;
1546 RTL_W16(IntrMask, 0);
1550 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1552 void __iomem *ioaddr = tp->mmio_addr;
1554 RTL_W16(IntrMask, bits);
1557 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1561 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1566 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1568 void __iomem *ioaddr = tp->mmio_addr;
1570 rtl_irq_disable(tp);
1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1575 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1577 void __iomem *ioaddr = tp->mmio_addr;
1579 return RTL_R32(TBICSR) & TBIReset;
1582 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1587 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1589 return RTL_R32(TBICSR) & TBILinkOk;
1592 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1594 return RTL_R8(PHYstatus) & LinkStatus;
1597 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1599 void __iomem *ioaddr = tp->mmio_addr;
1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1604 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1612 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1617 if (!netif_running(dev))
1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1627 } else if (RTL_R8(PHYstatus) & _100bps) {
1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1638 /* Reset packet filter */
1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1669 static void __rtl8169_check_link_status(struct net_device *dev,
1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1673 if (tp->link_ok(ioaddr)) {
1674 rtl_link_chg_patch(tp);
1675 /* This is to cancel a scheduled suspend if there's one. */
1677 pm_request_resume(&tp->pci_dev->dev);
1678 netif_carrier_on(dev);
1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
1682 netif_carrier_off(dev);
1683 netif_info(tp, ifdown, dev, "link down\n");
1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1689 static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1696 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1698 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1700 void __iomem *ioaddr = tp->mmio_addr;
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
1710 wolopts |= WAKE_PHY;
1711 switch (tp->mac_version) {
1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1738 options = RTL_R8(Config5);
1740 wolopts |= WAKE_UCAST;
1742 wolopts |= WAKE_BCAST;
1744 wolopts |= WAKE_MCAST;
1749 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 struct device *d = &tp->pci_dev->dev;
1754 pm_runtime_get_noresume(d);
1758 wol->supported = WAKE_ANY;
1759 if (pm_runtime_active(d))
1760 wol->wolopts = __rtl8169_get_wol(tp);
1762 wol->wolopts = tp->saved_wolopts;
1764 rtl_unlock_work(tp);
1766 pm_runtime_put_noidle(d);
1769 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1771 void __iomem *ioaddr = tp->mmio_addr;
1772 unsigned int i, tmp;
1773 static const struct {
1778 { WAKE_PHY, Config3, LinkUp },
1779 { WAKE_UCAST, Config5, UWF },
1780 { WAKE_BCAST, Config5, BWF },
1781 { WAKE_MCAST, Config5, MWF },
1782 { WAKE_ANY, Config5, LanWake },
1783 { WAKE_MAGIC, Config3, MagicPacket }
1787 RTL_W8(Cfg9346, Cfg9346_Unlock);
1789 switch (tp->mac_version) {
1790 case RTL_GIGA_MAC_VER_34:
1791 case RTL_GIGA_MAC_VER_35:
1792 case RTL_GIGA_MAC_VER_36:
1793 case RTL_GIGA_MAC_VER_37:
1794 case RTL_GIGA_MAC_VER_38:
1795 case RTL_GIGA_MAC_VER_40:
1796 case RTL_GIGA_MAC_VER_41:
1797 case RTL_GIGA_MAC_VER_42:
1798 case RTL_GIGA_MAC_VER_43:
1799 case RTL_GIGA_MAC_VER_44:
1800 case RTL_GIGA_MAC_VER_45:
1801 case RTL_GIGA_MAC_VER_46:
1802 case RTL_GIGA_MAC_VER_47:
1803 case RTL_GIGA_MAC_VER_48:
1804 case RTL_GIGA_MAC_VER_49:
1805 case RTL_GIGA_MAC_VER_50:
1806 case RTL_GIGA_MAC_VER_51:
1807 tmp = ARRAY_SIZE(cfg) - 1;
1808 if (wolopts & WAKE_MAGIC)
1824 tmp = ARRAY_SIZE(cfg);
1828 for (i = 0; i < tmp; i++) {
1829 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1830 if (wolopts & cfg[i].opt)
1831 options |= cfg[i].mask;
1832 RTL_W8(cfg[i].reg, options);
1835 switch (tp->mac_version) {
1836 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1837 options = RTL_R8(Config1) & ~PMEnable;
1839 options |= PMEnable;
1840 RTL_W8(Config1, options);
1843 options = RTL_R8(Config2) & ~PME_SIGNAL;
1845 options |= PME_SIGNAL;
1846 RTL_W8(Config2, options);
1850 RTL_W8(Cfg9346, Cfg9346_Lock);
1853 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1855 struct rtl8169_private *tp = netdev_priv(dev);
1856 struct device *d = &tp->pci_dev->dev;
1858 pm_runtime_get_noresume(d);
1863 tp->features |= RTL_FEATURE_WOL;
1865 tp->features &= ~RTL_FEATURE_WOL;
1866 if (pm_runtime_active(d))
1867 __rtl8169_set_wol(tp, wol->wolopts);
1869 tp->saved_wolopts = wol->wolopts;
1871 rtl_unlock_work(tp);
1873 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1875 pm_runtime_put_noidle(d);
1880 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1882 return rtl_chip_infos[tp->mac_version].fw_name;
1885 static void rtl8169_get_drvinfo(struct net_device *dev,
1886 struct ethtool_drvinfo *info)
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889 struct rtl_fw *rtl_fw = tp->rtl_fw;
1891 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1892 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1893 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1894 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1895 if (!IS_ERR_OR_NULL(rtl_fw))
1896 strlcpy(info->fw_version, rtl_fw->version,
1897 sizeof(info->fw_version));
1900 static int rtl8169_get_regs_len(struct net_device *dev)
1902 return R8169_REGS_SIZE;
1905 static int rtl8169_set_speed_tbi(struct net_device *dev,
1906 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 void __iomem *ioaddr = tp->mmio_addr;
1913 reg = RTL_R32(TBICSR);
1914 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1915 (duplex == DUPLEX_FULL)) {
1916 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1917 } else if (autoneg == AUTONEG_ENABLE)
1918 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1920 netif_warn(tp, link, dev,
1921 "incorrect speed setting refused in TBI mode\n");
1928 static int rtl8169_set_speed_xmii(struct net_device *dev,
1929 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1931 struct rtl8169_private *tp = netdev_priv(dev);
1932 int giga_ctrl, bmcr;
1935 rtl_writephy(tp, 0x1f, 0x0000);
1937 if (autoneg == AUTONEG_ENABLE) {
1940 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1941 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1942 ADVERTISE_100HALF | ADVERTISE_100FULL);
1944 if (adv & ADVERTISED_10baseT_Half)
1945 auto_nego |= ADVERTISE_10HALF;
1946 if (adv & ADVERTISED_10baseT_Full)
1947 auto_nego |= ADVERTISE_10FULL;
1948 if (adv & ADVERTISED_100baseT_Half)
1949 auto_nego |= ADVERTISE_100HALF;
1950 if (adv & ADVERTISED_100baseT_Full)
1951 auto_nego |= ADVERTISE_100FULL;
1953 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1955 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1956 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1958 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1959 if (tp->mii.supports_gmii) {
1960 if (adv & ADVERTISED_1000baseT_Half)
1961 giga_ctrl |= ADVERTISE_1000HALF;
1962 if (adv & ADVERTISED_1000baseT_Full)
1963 giga_ctrl |= ADVERTISE_1000FULL;
1964 } else if (adv & (ADVERTISED_1000baseT_Half |
1965 ADVERTISED_1000baseT_Full)) {
1966 netif_info(tp, link, dev,
1967 "PHY does not support 1000Mbps\n");
1971 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1973 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1974 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1978 if (speed == SPEED_10)
1980 else if (speed == SPEED_100)
1981 bmcr = BMCR_SPEED100;
1985 if (duplex == DUPLEX_FULL)
1986 bmcr |= BMCR_FULLDPLX;
1989 rtl_writephy(tp, MII_BMCR, bmcr);
1991 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1992 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1993 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1994 rtl_writephy(tp, 0x17, 0x2138);
1995 rtl_writephy(tp, 0x0e, 0x0260);
1997 rtl_writephy(tp, 0x17, 0x2108);
1998 rtl_writephy(tp, 0x0e, 0x0000);
2007 static int rtl8169_set_speed(struct net_device *dev,
2008 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2010 struct rtl8169_private *tp = netdev_priv(dev);
2013 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2017 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2018 (advertising & ADVERTISED_1000baseT_Full) &&
2019 !pci_is_pcie(tp->pci_dev)) {
2020 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2026 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2028 struct rtl8169_private *tp = netdev_priv(dev);
2031 del_timer_sync(&tp->timer);
2034 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2035 cmd->duplex, cmd->advertising);
2036 rtl_unlock_work(tp);
2041 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2042 netdev_features_t features)
2044 struct rtl8169_private *tp = netdev_priv(dev);
2046 if (dev->mtu > TD_MSS_MAX)
2047 features &= ~NETIF_F_ALL_TSO;
2049 if (dev->mtu > JUMBO_1K &&
2050 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2051 features &= ~NETIF_F_IP_CSUM;
2056 static void __rtl8169_set_features(struct net_device *dev,
2057 netdev_features_t features)
2059 struct rtl8169_private *tp = netdev_priv(dev);
2060 void __iomem *ioaddr = tp->mmio_addr;
2063 rx_config = RTL_R32(RxConfig);
2064 if (features & NETIF_F_RXALL)
2065 rx_config |= (AcceptErr | AcceptRunt);
2067 rx_config &= ~(AcceptErr | AcceptRunt);
2069 RTL_W32(RxConfig, rx_config);
2071 if (features & NETIF_F_RXCSUM)
2072 tp->cp_cmd |= RxChkSum;
2074 tp->cp_cmd &= ~RxChkSum;
2076 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2077 tp->cp_cmd |= RxVlan;
2079 tp->cp_cmd &= ~RxVlan;
2081 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2083 RTL_W16(CPlusCmd, tp->cp_cmd);
2087 static int rtl8169_set_features(struct net_device *dev,
2088 netdev_features_t features)
2090 struct rtl8169_private *tp = netdev_priv(dev);
2092 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2095 if (features ^ dev->features)
2096 __rtl8169_set_features(dev, features);
2097 rtl_unlock_work(tp);
2103 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2105 return (skb_vlan_tag_present(skb)) ?
2106 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2109 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2111 u32 opts2 = le32_to_cpu(desc->opts2);
2113 if (opts2 & RxVlanTag)
2114 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2117 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2119 struct rtl8169_private *tp = netdev_priv(dev);
2120 void __iomem *ioaddr = tp->mmio_addr;
2124 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2125 cmd->port = PORT_FIBRE;
2126 cmd->transceiver = XCVR_INTERNAL;
2128 status = RTL_R32(TBICSR);
2129 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2130 cmd->autoneg = !!(status & TBINwEnable);
2132 ethtool_cmd_speed_set(cmd, SPEED_1000);
2133 cmd->duplex = DUPLEX_FULL; /* Always set */
2138 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2140 struct rtl8169_private *tp = netdev_priv(dev);
2142 return mii_ethtool_gset(&tp->mii, cmd);
2145 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2147 struct rtl8169_private *tp = netdev_priv(dev);
2151 rc = tp->get_settings(dev, cmd);
2152 rtl_unlock_work(tp);
2157 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2160 struct rtl8169_private *tp = netdev_priv(dev);
2161 u32 __iomem *data = tp->mmio_addr;
2166 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2167 memcpy_fromio(dw++, data++, 4);
2168 rtl_unlock_work(tp);
2171 static u32 rtl8169_get_msglevel(struct net_device *dev)
2173 struct rtl8169_private *tp = netdev_priv(dev);
2175 return tp->msg_enable;
2178 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2180 struct rtl8169_private *tp = netdev_priv(dev);
2182 tp->msg_enable = value;
2185 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2192 "tx_single_collisions",
2193 "tx_multi_collisions",
2201 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2205 return ARRAY_SIZE(rtl8169_gstrings);
2211 DECLARE_RTL_COND(rtl_counters_cond)
2213 void __iomem *ioaddr = tp->mmio_addr;
2215 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2218 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2220 struct rtl8169_private *tp = netdev_priv(dev);
2221 void __iomem *ioaddr = tp->mmio_addr;
2222 dma_addr_t paddr = tp->counters_phys_addr;
2226 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2227 cmd = (u64)paddr & DMA_BIT_MASK(32);
2228 RTL_W32(CounterAddrLow, cmd);
2229 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2231 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2233 RTL_W32(CounterAddrLow, 0);
2234 RTL_W32(CounterAddrHigh, 0);
2239 static bool rtl8169_reset_counters(struct net_device *dev)
2241 struct rtl8169_private *tp = netdev_priv(dev);
2244 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2247 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2250 return rtl8169_do_counters(dev, CounterReset);
2253 static bool rtl8169_update_counters(struct net_device *dev)
2255 struct rtl8169_private *tp = netdev_priv(dev);
2256 void __iomem *ioaddr = tp->mmio_addr;
2259 * Some chips are unable to dump tally counters when the receiver
2262 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2265 return rtl8169_do_counters(dev, CounterDump);
2268 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2270 struct rtl8169_private *tp = netdev_priv(dev);
2271 struct rtl8169_counters *counters = tp->counters;
2275 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2276 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2277 * reset by a power cycle, while the counter values collected by the
2278 * driver are reset at every driver unload/load cycle.
2280 * To make sure the HW values returned by @get_stats64 match the SW
2281 * values, we collect the initial values at first open(*) and use them
2282 * as offsets to normalize the values returned by @get_stats64.
2284 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2285 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2286 * set at open time by rtl_hw_start.
2289 if (tp->tc_offset.inited)
2292 /* If both, reset and update fail, propagate to caller. */
2293 if (rtl8169_reset_counters(dev))
2296 if (rtl8169_update_counters(dev))
2299 tp->tc_offset.tx_errors = counters->tx_errors;
2300 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2301 tp->tc_offset.tx_aborted = counters->tx_aborted;
2302 tp->tc_offset.inited = true;
2307 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2308 struct ethtool_stats *stats, u64 *data)
2310 struct rtl8169_private *tp = netdev_priv(dev);
2311 struct device *d = &tp->pci_dev->dev;
2312 struct rtl8169_counters *counters = tp->counters;
2316 pm_runtime_get_noresume(d);
2318 if (pm_runtime_active(d))
2319 rtl8169_update_counters(dev);
2321 pm_runtime_put_noidle(d);
2323 data[0] = le64_to_cpu(counters->tx_packets);
2324 data[1] = le64_to_cpu(counters->rx_packets);
2325 data[2] = le64_to_cpu(counters->tx_errors);
2326 data[3] = le32_to_cpu(counters->rx_errors);
2327 data[4] = le16_to_cpu(counters->rx_missed);
2328 data[5] = le16_to_cpu(counters->align_errors);
2329 data[6] = le32_to_cpu(counters->tx_one_collision);
2330 data[7] = le32_to_cpu(counters->tx_multi_collision);
2331 data[8] = le64_to_cpu(counters->rx_unicast);
2332 data[9] = le64_to_cpu(counters->rx_broadcast);
2333 data[10] = le32_to_cpu(counters->rx_multicast);
2334 data[11] = le16_to_cpu(counters->tx_aborted);
2335 data[12] = le16_to_cpu(counters->tx_underun);
2338 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2342 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2347 static int rtl8169_nway_reset(struct net_device *dev)
2349 struct rtl8169_private *tp = netdev_priv(dev);
2351 return mii_nway_restart(&tp->mii);
2354 static const struct ethtool_ops rtl8169_ethtool_ops = {
2355 .get_drvinfo = rtl8169_get_drvinfo,
2356 .get_regs_len = rtl8169_get_regs_len,
2357 .get_link = ethtool_op_get_link,
2358 .get_settings = rtl8169_get_settings,
2359 .set_settings = rtl8169_set_settings,
2360 .get_msglevel = rtl8169_get_msglevel,
2361 .set_msglevel = rtl8169_set_msglevel,
2362 .get_regs = rtl8169_get_regs,
2363 .get_wol = rtl8169_get_wol,
2364 .set_wol = rtl8169_set_wol,
2365 .get_strings = rtl8169_get_strings,
2366 .get_sset_count = rtl8169_get_sset_count,
2367 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2368 .get_ts_info = ethtool_op_get_ts_info,
2369 .nway_reset = rtl8169_nway_reset,
2372 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2373 struct net_device *dev, u8 default_version)
2375 void __iomem *ioaddr = tp->mmio_addr;
2377 * The driver currently handles the 8168Bf and the 8168Be identically
2378 * but they can be identified more specifically through the test below
2381 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2383 * Same thing for the 8101Eb and the 8101Ec:
2385 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2387 static const struct rtl_mac_info {
2392 /* 8168EP family. */
2393 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2394 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2395 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2398 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2399 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2402 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2403 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2404 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2405 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2408 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2409 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2410 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2413 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2414 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2415 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2416 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2419 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2420 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2421 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2423 /* 8168DP family. */
2424 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2425 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2426 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2429 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2430 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2431 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2432 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2433 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2434 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2435 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2436 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2437 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2440 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2441 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2442 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2443 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2446 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2447 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2448 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2449 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2450 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2451 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2452 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2453 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2454 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2455 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2456 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2457 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2458 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2459 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2460 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2461 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2462 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2463 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2464 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2465 /* FIXME: where did these entries come from ? -- FR */
2466 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2467 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2470 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2471 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2472 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2473 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2474 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2475 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2478 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2480 const struct rtl_mac_info *p = mac_info;
2483 reg = RTL_R32(TxConfig);
2484 while ((reg & p->mask) != p->val)
2486 tp->mac_version = p->mac_version;
2488 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2489 netif_notice(tp, probe, dev,
2490 "unknown MAC, using family default\n");
2491 tp->mac_version = default_version;
2492 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2493 tp->mac_version = tp->mii.supports_gmii ?
2494 RTL_GIGA_MAC_VER_42 :
2495 RTL_GIGA_MAC_VER_43;
2496 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2497 tp->mac_version = tp->mii.supports_gmii ?
2498 RTL_GIGA_MAC_VER_45 :
2499 RTL_GIGA_MAC_VER_47;
2500 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2501 tp->mac_version = tp->mii.supports_gmii ?
2502 RTL_GIGA_MAC_VER_46 :
2503 RTL_GIGA_MAC_VER_48;
2507 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2509 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2517 static void rtl_writephy_batch(struct rtl8169_private *tp,
2518 const struct phy_reg *regs, int len)
2521 rtl_writephy(tp, regs->reg, regs->val);
2526 #define PHY_READ 0x00000000
2527 #define PHY_DATA_OR 0x10000000
2528 #define PHY_DATA_AND 0x20000000
2529 #define PHY_BJMPN 0x30000000
2530 #define PHY_MDIO_CHG 0x40000000
2531 #define PHY_CLEAR_READCOUNT 0x70000000
2532 #define PHY_WRITE 0x80000000
2533 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2534 #define PHY_COMP_EQ_SKIPN 0xa0000000
2535 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2536 #define PHY_WRITE_PREVIOUS 0xc0000000
2537 #define PHY_SKIPN 0xd0000000
2538 #define PHY_DELAY_MS 0xe0000000
2542 char version[RTL_VER_SIZE];
2548 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2550 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2552 const struct firmware *fw = rtl_fw->fw;
2553 struct fw_info *fw_info = (struct fw_info *)fw->data;
2554 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2555 char *version = rtl_fw->version;
2558 if (fw->size < FW_OPCODE_SIZE)
2561 if (!fw_info->magic) {
2562 size_t i, size, start;
2565 if (fw->size < sizeof(*fw_info))
2568 for (i = 0; i < fw->size; i++)
2569 checksum += fw->data[i];
2573 start = le32_to_cpu(fw_info->fw_start);
2574 if (start > fw->size)
2577 size = le32_to_cpu(fw_info->fw_len);
2578 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2581 memcpy(version, fw_info->version, RTL_VER_SIZE);
2583 pa->code = (__le32 *)(fw->data + start);
2586 if (fw->size % FW_OPCODE_SIZE)
2589 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2591 pa->code = (__le32 *)fw->data;
2592 pa->size = fw->size / FW_OPCODE_SIZE;
2594 version[RTL_VER_SIZE - 1] = 0;
2601 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2602 struct rtl_fw_phy_action *pa)
2607 for (index = 0; index < pa->size; index++) {
2608 u32 action = le32_to_cpu(pa->code[index]);
2609 u32 regno = (action & 0x0fff0000) >> 16;
2611 switch(action & 0xf0000000) {
2616 case PHY_CLEAR_READCOUNT:
2618 case PHY_WRITE_PREVIOUS:
2623 if (regno > index) {
2624 netif_err(tp, ifup, tp->dev,
2625 "Out of range of firmware\n");
2629 case PHY_READCOUNT_EQ_SKIP:
2630 if (index + 2 >= pa->size) {
2631 netif_err(tp, ifup, tp->dev,
2632 "Out of range of firmware\n");
2636 case PHY_COMP_EQ_SKIPN:
2637 case PHY_COMP_NEQ_SKIPN:
2639 if (index + 1 + regno >= pa->size) {
2640 netif_err(tp, ifup, tp->dev,
2641 "Out of range of firmware\n");
2647 netif_err(tp, ifup, tp->dev,
2648 "Invalid action 0x%08x\n", action);
2657 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2659 struct net_device *dev = tp->dev;
2662 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2663 netif_err(tp, ifup, dev, "invalid firmware\n");
2667 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2673 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2675 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2676 struct mdio_ops org, *ops = &tp->mdio_ops;
2680 predata = count = 0;
2681 org.write = ops->write;
2682 org.read = ops->read;
2684 for (index = 0; index < pa->size; ) {
2685 u32 action = le32_to_cpu(pa->code[index]);
2686 u32 data = action & 0x0000ffff;
2687 u32 regno = (action & 0x0fff0000) >> 16;
2692 switch(action & 0xf0000000) {
2694 predata = rtl_readphy(tp, regno);
2711 ops->write = org.write;
2712 ops->read = org.read;
2713 } else if (data == 1) {
2714 ops->write = mac_mcu_write;
2715 ops->read = mac_mcu_read;
2720 case PHY_CLEAR_READCOUNT:
2725 rtl_writephy(tp, regno, data);
2728 case PHY_READCOUNT_EQ_SKIP:
2729 index += (count == data) ? 2 : 1;
2731 case PHY_COMP_EQ_SKIPN:
2732 if (predata == data)
2736 case PHY_COMP_NEQ_SKIPN:
2737 if (predata != data)
2741 case PHY_WRITE_PREVIOUS:
2742 rtl_writephy(tp, regno, predata);
2758 ops->write = org.write;
2759 ops->read = org.read;
2762 static void rtl_release_firmware(struct rtl8169_private *tp)
2764 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2765 release_firmware(tp->rtl_fw->fw);
2768 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2771 static void rtl_apply_firmware(struct rtl8169_private *tp)
2773 struct rtl_fw *rtl_fw = tp->rtl_fw;
2775 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2776 if (!IS_ERR_OR_NULL(rtl_fw))
2777 rtl_phy_write_fw(tp, rtl_fw);
2780 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2782 if (rtl_readphy(tp, reg) != val)
2783 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2785 rtl_apply_firmware(tp);
2788 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2790 static const struct phy_reg phy_reg_init[] = {
2852 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2855 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2857 static const struct phy_reg phy_reg_init[] = {
2863 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2866 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2868 struct pci_dev *pdev = tp->pci_dev;
2870 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2871 (pdev->subsystem_device != 0xe000))
2874 rtl_writephy(tp, 0x1f, 0x0001);
2875 rtl_writephy(tp, 0x10, 0xf01b);
2876 rtl_writephy(tp, 0x1f, 0x0000);
2879 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2881 static const struct phy_reg phy_reg_init[] = {
2921 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2923 rtl8169scd_hw_phy_config_quirk(tp);
2926 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2928 static const struct phy_reg phy_reg_init[] = {
2976 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2979 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2981 static const struct phy_reg phy_reg_init[] = {
2986 rtl_writephy(tp, 0x1f, 0x0001);
2987 rtl_patchphy(tp, 0x16, 1 << 0);
2989 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2992 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2994 static const struct phy_reg phy_reg_init[] = {
3000 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3003 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3005 static const struct phy_reg phy_reg_init[] = {
3013 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3016 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3018 static const struct phy_reg phy_reg_init[] = {
3024 rtl_writephy(tp, 0x1f, 0x0000);
3025 rtl_patchphy(tp, 0x14, 1 << 5);
3026 rtl_patchphy(tp, 0x0d, 1 << 5);
3028 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3031 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3033 static const struct phy_reg phy_reg_init[] = {
3053 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3055 rtl_patchphy(tp, 0x14, 1 << 5);
3056 rtl_patchphy(tp, 0x0d, 1 << 5);
3057 rtl_writephy(tp, 0x1f, 0x0000);
3060 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3062 static const struct phy_reg phy_reg_init[] = {
3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3082 rtl_patchphy(tp, 0x16, 1 << 0);
3083 rtl_patchphy(tp, 0x14, 1 << 5);
3084 rtl_patchphy(tp, 0x0d, 1 << 5);
3085 rtl_writephy(tp, 0x1f, 0x0000);
3088 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3090 static const struct phy_reg phy_reg_init[] = {
3102 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3104 rtl_patchphy(tp, 0x16, 1 << 0);
3105 rtl_patchphy(tp, 0x14, 1 << 5);
3106 rtl_patchphy(tp, 0x0d, 1 << 5);
3107 rtl_writephy(tp, 0x1f, 0x0000);
3110 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3112 rtl8168c_3_hw_phy_config(tp);
3115 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3117 static const struct phy_reg phy_reg_init_0[] = {
3118 /* Channel Estimation */
3139 * Enhance line driver power
3148 * Can not link to 1Gbps with bad cable
3149 * Decrease SNR threshold form 21.07dB to 19.04dB
3158 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3162 * Fine Tune Switching regulator parameter
3164 rtl_writephy(tp, 0x1f, 0x0002);
3165 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3166 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3168 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3169 static const struct phy_reg phy_reg_init[] = {
3179 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3181 val = rtl_readphy(tp, 0x0d);
3183 if ((val & 0x00ff) != 0x006c) {
3184 static const u32 set[] = {
3185 0x0065, 0x0066, 0x0067, 0x0068,
3186 0x0069, 0x006a, 0x006b, 0x006c
3190 rtl_writephy(tp, 0x1f, 0x0002);
3193 for (i = 0; i < ARRAY_SIZE(set); i++)
3194 rtl_writephy(tp, 0x0d, val | set[i]);
3197 static const struct phy_reg phy_reg_init[] = {
3205 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3208 /* RSET couple improve */
3209 rtl_writephy(tp, 0x1f, 0x0002);
3210 rtl_patchphy(tp, 0x0d, 0x0300);
3211 rtl_patchphy(tp, 0x0f, 0x0010);
3213 /* Fine tune PLL performance */
3214 rtl_writephy(tp, 0x1f, 0x0002);
3215 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3216 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3218 rtl_writephy(tp, 0x1f, 0x0005);
3219 rtl_writephy(tp, 0x05, 0x001b);
3221 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3223 rtl_writephy(tp, 0x1f, 0x0000);
3226 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3228 static const struct phy_reg phy_reg_init_0[] = {
3229 /* Channel Estimation */
3250 * Enhance line driver power
3259 * Can not link to 1Gbps with bad cable
3260 * Decrease SNR threshold form 21.07dB to 19.04dB
3269 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3271 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3272 static const struct phy_reg phy_reg_init[] = {
3283 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3285 val = rtl_readphy(tp, 0x0d);
3286 if ((val & 0x00ff) != 0x006c) {
3287 static const u32 set[] = {
3288 0x0065, 0x0066, 0x0067, 0x0068,
3289 0x0069, 0x006a, 0x006b, 0x006c
3293 rtl_writephy(tp, 0x1f, 0x0002);
3296 for (i = 0; i < ARRAY_SIZE(set); i++)
3297 rtl_writephy(tp, 0x0d, val | set[i]);
3300 static const struct phy_reg phy_reg_init[] = {
3308 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3311 /* Fine tune PLL performance */
3312 rtl_writephy(tp, 0x1f, 0x0002);
3313 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3314 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3316 /* Switching regulator Slew rate */
3317 rtl_writephy(tp, 0x1f, 0x0002);
3318 rtl_patchphy(tp, 0x0f, 0x0017);
3320 rtl_writephy(tp, 0x1f, 0x0005);
3321 rtl_writephy(tp, 0x05, 0x001b);
3323 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3325 rtl_writephy(tp, 0x1f, 0x0000);
3328 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3330 static const struct phy_reg phy_reg_init[] = {
3386 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3389 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3391 static const struct phy_reg phy_reg_init[] = {
3401 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3402 rtl_patchphy(tp, 0x0d, 1 << 5);
3405 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3407 static const struct phy_reg phy_reg_init[] = {
3408 /* Enable Delay cap */
3414 /* Channel estimation fine tune */
3423 /* Update PFM & 10M TX idle timer */
3435 rtl_apply_firmware(tp);
3437 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3439 /* DCO enable for 10M IDLE Power */
3440 rtl_writephy(tp, 0x1f, 0x0007);
3441 rtl_writephy(tp, 0x1e, 0x0023);
3442 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3443 rtl_writephy(tp, 0x1f, 0x0000);
3445 /* For impedance matching */
3446 rtl_writephy(tp, 0x1f, 0x0002);
3447 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3448 rtl_writephy(tp, 0x1f, 0x0000);
3450 /* PHY auto speed down */
3451 rtl_writephy(tp, 0x1f, 0x0007);
3452 rtl_writephy(tp, 0x1e, 0x002d);
3453 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3454 rtl_writephy(tp, 0x1f, 0x0000);
3455 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3457 rtl_writephy(tp, 0x1f, 0x0005);
3458 rtl_writephy(tp, 0x05, 0x8b86);
3459 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3460 rtl_writephy(tp, 0x1f, 0x0000);
3462 rtl_writephy(tp, 0x1f, 0x0005);
3463 rtl_writephy(tp, 0x05, 0x8b85);
3464 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3465 rtl_writephy(tp, 0x1f, 0x0007);
3466 rtl_writephy(tp, 0x1e, 0x0020);
3467 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3468 rtl_writephy(tp, 0x1f, 0x0006);
3469 rtl_writephy(tp, 0x00, 0x5a00);
3470 rtl_writephy(tp, 0x1f, 0x0000);
3471 rtl_writephy(tp, 0x0d, 0x0007);
3472 rtl_writephy(tp, 0x0e, 0x003c);
3473 rtl_writephy(tp, 0x0d, 0x4007);
3474 rtl_writephy(tp, 0x0e, 0x0000);
3475 rtl_writephy(tp, 0x0d, 0x0000);
3478 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3481 addr[0] | (addr[1] << 8),
3482 addr[2] | (addr[3] << 8),
3483 addr[4] | (addr[5] << 8)
3485 const struct exgmac_reg e[] = {
3486 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3487 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3488 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3489 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3492 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3495 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3497 static const struct phy_reg phy_reg_init[] = {
3498 /* Enable Delay cap */
3507 /* Channel estimation fine tune */
3524 rtl_apply_firmware(tp);
3526 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3528 /* For 4-corner performance improve */
3529 rtl_writephy(tp, 0x1f, 0x0005);
3530 rtl_writephy(tp, 0x05, 0x8b80);
3531 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3532 rtl_writephy(tp, 0x1f, 0x0000);
3534 /* PHY auto speed down */
3535 rtl_writephy(tp, 0x1f, 0x0004);
3536 rtl_writephy(tp, 0x1f, 0x0007);
3537 rtl_writephy(tp, 0x1e, 0x002d);
3538 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3539 rtl_writephy(tp, 0x1f, 0x0002);
3540 rtl_writephy(tp, 0x1f, 0x0000);
3541 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3543 /* improve 10M EEE waveform */
3544 rtl_writephy(tp, 0x1f, 0x0005);
3545 rtl_writephy(tp, 0x05, 0x8b86);
3546 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3547 rtl_writephy(tp, 0x1f, 0x0000);
3549 /* Improve 2-pair detection performance */
3550 rtl_writephy(tp, 0x1f, 0x0005);
3551 rtl_writephy(tp, 0x05, 0x8b85);
3552 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3553 rtl_writephy(tp, 0x1f, 0x0000);
3556 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3557 rtl_writephy(tp, 0x1f, 0x0005);
3558 rtl_writephy(tp, 0x05, 0x8b85);
3559 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3560 rtl_writephy(tp, 0x1f, 0x0004);
3561 rtl_writephy(tp, 0x1f, 0x0007);
3562 rtl_writephy(tp, 0x1e, 0x0020);
3563 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3564 rtl_writephy(tp, 0x1f, 0x0002);
3565 rtl_writephy(tp, 0x1f, 0x0000);
3566 rtl_writephy(tp, 0x0d, 0x0007);
3567 rtl_writephy(tp, 0x0e, 0x003c);
3568 rtl_writephy(tp, 0x0d, 0x4007);
3569 rtl_writephy(tp, 0x0e, 0x0000);
3570 rtl_writephy(tp, 0x0d, 0x0000);
3573 rtl_writephy(tp, 0x1f, 0x0003);
3574 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3575 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3576 rtl_writephy(tp, 0x1f, 0x0000);
3578 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3579 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3582 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3584 /* For 4-corner performance improve */
3585 rtl_writephy(tp, 0x1f, 0x0005);
3586 rtl_writephy(tp, 0x05, 0x8b80);
3587 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3588 rtl_writephy(tp, 0x1f, 0x0000);
3590 /* PHY auto speed down */
3591 rtl_writephy(tp, 0x1f, 0x0007);
3592 rtl_writephy(tp, 0x1e, 0x002d);
3593 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3594 rtl_writephy(tp, 0x1f, 0x0000);
3595 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3597 /* Improve 10M EEE waveform */
3598 rtl_writephy(tp, 0x1f, 0x0005);
3599 rtl_writephy(tp, 0x05, 0x8b86);
3600 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3601 rtl_writephy(tp, 0x1f, 0x0000);
3604 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3606 static const struct phy_reg phy_reg_init[] = {
3607 /* Channel estimation fine tune */
3612 /* Modify green table for giga & fnet */
3629 /* Modify green table for 10M */
3635 /* Disable hiimpedance detection (RTCT) */
3641 rtl_apply_firmware(tp);
3643 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3645 rtl8168f_hw_phy_config(tp);
3647 /* Improve 2-pair detection performance */
3648 rtl_writephy(tp, 0x1f, 0x0005);
3649 rtl_writephy(tp, 0x05, 0x8b85);
3650 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3651 rtl_writephy(tp, 0x1f, 0x0000);
3654 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3656 rtl_apply_firmware(tp);
3658 rtl8168f_hw_phy_config(tp);
3661 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3663 static const struct phy_reg phy_reg_init[] = {
3664 /* Channel estimation fine tune */
3669 /* Modify green table for giga & fnet */
3686 /* Modify green table for 10M */
3692 /* Disable hiimpedance detection (RTCT) */
3699 rtl_apply_firmware(tp);
3701 rtl8168f_hw_phy_config(tp);
3703 /* Improve 2-pair detection performance */
3704 rtl_writephy(tp, 0x1f, 0x0005);
3705 rtl_writephy(tp, 0x05, 0x8b85);
3706 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3707 rtl_writephy(tp, 0x1f, 0x0000);
3709 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3711 /* Modify green table for giga */
3712 rtl_writephy(tp, 0x1f, 0x0005);
3713 rtl_writephy(tp, 0x05, 0x8b54);
3714 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3715 rtl_writephy(tp, 0x05, 0x8b5d);
3716 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3717 rtl_writephy(tp, 0x05, 0x8a7c);
3718 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3719 rtl_writephy(tp, 0x05, 0x8a7f);
3720 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3721 rtl_writephy(tp, 0x05, 0x8a82);
3722 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3723 rtl_writephy(tp, 0x05, 0x8a85);
3724 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3725 rtl_writephy(tp, 0x05, 0x8a88);
3726 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3727 rtl_writephy(tp, 0x1f, 0x0000);
3729 /* uc same-seed solution */
3730 rtl_writephy(tp, 0x1f, 0x0005);
3731 rtl_writephy(tp, 0x05, 0x8b85);
3732 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3733 rtl_writephy(tp, 0x1f, 0x0000);
3736 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3737 rtl_writephy(tp, 0x1f, 0x0005);
3738 rtl_writephy(tp, 0x05, 0x8b85);
3739 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3740 rtl_writephy(tp, 0x1f, 0x0004);
3741 rtl_writephy(tp, 0x1f, 0x0007);
3742 rtl_writephy(tp, 0x1e, 0x0020);
3743 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3744 rtl_writephy(tp, 0x1f, 0x0000);
3745 rtl_writephy(tp, 0x0d, 0x0007);
3746 rtl_writephy(tp, 0x0e, 0x003c);
3747 rtl_writephy(tp, 0x0d, 0x4007);
3748 rtl_writephy(tp, 0x0e, 0x0000);
3749 rtl_writephy(tp, 0x0d, 0x0000);
3752 rtl_writephy(tp, 0x1f, 0x0003);
3753 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3754 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3755 rtl_writephy(tp, 0x1f, 0x0000);
3758 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3760 rtl_apply_firmware(tp);
3762 rtl_writephy(tp, 0x1f, 0x0a46);
3763 if (rtl_readphy(tp, 0x10) & 0x0100) {
3764 rtl_writephy(tp, 0x1f, 0x0bcc);
3765 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3767 rtl_writephy(tp, 0x1f, 0x0bcc);
3768 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3771 rtl_writephy(tp, 0x1f, 0x0a46);
3772 if (rtl_readphy(tp, 0x13) & 0x0100) {
3773 rtl_writephy(tp, 0x1f, 0x0c41);
3774 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3776 rtl_writephy(tp, 0x1f, 0x0c41);
3777 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3780 /* Enable PHY auto speed down */
3781 rtl_writephy(tp, 0x1f, 0x0a44);
3782 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3784 rtl_writephy(tp, 0x1f, 0x0bcc);
3785 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3786 rtl_writephy(tp, 0x1f, 0x0a44);
3787 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3788 rtl_writephy(tp, 0x1f, 0x0a43);
3789 rtl_writephy(tp, 0x13, 0x8084);
3790 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3791 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3793 /* EEE auto-fallback function */
3794 rtl_writephy(tp, 0x1f, 0x0a4b);
3795 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3797 /* Enable UC LPF tune function */
3798 rtl_writephy(tp, 0x1f, 0x0a43);
3799 rtl_writephy(tp, 0x13, 0x8012);
3800 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3802 rtl_writephy(tp, 0x1f, 0x0c42);
3803 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3805 /* Improve SWR Efficiency */
3806 rtl_writephy(tp, 0x1f, 0x0bcd);
3807 rtl_writephy(tp, 0x14, 0x5065);
3808 rtl_writephy(tp, 0x14, 0xd065);
3809 rtl_writephy(tp, 0x1f, 0x0bc8);
3810 rtl_writephy(tp, 0x11, 0x5655);
3811 rtl_writephy(tp, 0x1f, 0x0bcd);
3812 rtl_writephy(tp, 0x14, 0x1065);
3813 rtl_writephy(tp, 0x14, 0x9065);
3814 rtl_writephy(tp, 0x14, 0x1065);
3816 /* Check ALDPS bit, disable it if enabled */
3817 rtl_writephy(tp, 0x1f, 0x0a43);
3818 if (rtl_readphy(tp, 0x10) & 0x0004)
3819 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3821 rtl_writephy(tp, 0x1f, 0x0000);
3824 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3826 rtl_apply_firmware(tp);
3829 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3834 rtl_apply_firmware(tp);
3836 /* CHN EST parameters adjust - giga master */
3837 rtl_writephy(tp, 0x1f, 0x0a43);
3838 rtl_writephy(tp, 0x13, 0x809b);
3839 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3840 rtl_writephy(tp, 0x13, 0x80a2);
3841 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3842 rtl_writephy(tp, 0x13, 0x80a4);
3843 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3844 rtl_writephy(tp, 0x13, 0x809c);
3845 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3846 rtl_writephy(tp, 0x1f, 0x0000);
3848 /* CHN EST parameters adjust - giga slave */
3849 rtl_writephy(tp, 0x1f, 0x0a43);
3850 rtl_writephy(tp, 0x13, 0x80ad);
3851 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3852 rtl_writephy(tp, 0x13, 0x80b4);
3853 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3854 rtl_writephy(tp, 0x13, 0x80ac);
3855 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3856 rtl_writephy(tp, 0x1f, 0x0000);
3858 /* CHN EST parameters adjust - fnet */
3859 rtl_writephy(tp, 0x1f, 0x0a43);
3860 rtl_writephy(tp, 0x13, 0x808e);
3861 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3862 rtl_writephy(tp, 0x13, 0x8090);
3863 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3864 rtl_writephy(tp, 0x13, 0x8092);
3865 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3866 rtl_writephy(tp, 0x1f, 0x0000);
3868 /* enable R-tune & PGA-retune function */
3870 rtl_writephy(tp, 0x1f, 0x0a46);
3871 data = rtl_readphy(tp, 0x13);
3874 dout_tapbin |= data;
3875 data = rtl_readphy(tp, 0x12);
3878 dout_tapbin |= data;
3879 dout_tapbin = ~(dout_tapbin^0x08);
3881 dout_tapbin &= 0xf000;
3882 rtl_writephy(tp, 0x1f, 0x0a43);
3883 rtl_writephy(tp, 0x13, 0x827a);
3884 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3885 rtl_writephy(tp, 0x13, 0x827b);
3886 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3887 rtl_writephy(tp, 0x13, 0x827c);
3888 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3889 rtl_writephy(tp, 0x13, 0x827d);
3890 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3892 rtl_writephy(tp, 0x1f, 0x0a43);
3893 rtl_writephy(tp, 0x13, 0x0811);
3894 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3895 rtl_writephy(tp, 0x1f, 0x0a42);
3896 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3897 rtl_writephy(tp, 0x1f, 0x0000);
3899 /* enable GPHY 10M */
3900 rtl_writephy(tp, 0x1f, 0x0a44);
3901 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3902 rtl_writephy(tp, 0x1f, 0x0000);
3904 /* SAR ADC performance */
3905 rtl_writephy(tp, 0x1f, 0x0bca);
3906 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3907 rtl_writephy(tp, 0x1f, 0x0000);
3909 rtl_writephy(tp, 0x1f, 0x0a43);
3910 rtl_writephy(tp, 0x13, 0x803f);
3911 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3912 rtl_writephy(tp, 0x13, 0x8047);
3913 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3914 rtl_writephy(tp, 0x13, 0x804f);
3915 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3916 rtl_writephy(tp, 0x13, 0x8057);
3917 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3918 rtl_writephy(tp, 0x13, 0x805f);
3919 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3920 rtl_writephy(tp, 0x13, 0x8067);
3921 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3922 rtl_writephy(tp, 0x13, 0x806f);
3923 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3924 rtl_writephy(tp, 0x1f, 0x0000);
3926 /* disable phy pfm mode */
3927 rtl_writephy(tp, 0x1f, 0x0a44);
3928 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3929 rtl_writephy(tp, 0x1f, 0x0000);
3931 /* Check ALDPS bit, disable it if enabled */
3932 rtl_writephy(tp, 0x1f, 0x0a43);
3933 if (rtl_readphy(tp, 0x10) & 0x0004)
3934 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3936 rtl_writephy(tp, 0x1f, 0x0000);
3939 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3941 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3945 rtl_apply_firmware(tp);
3947 /* CHIN EST parameter update */
3948 rtl_writephy(tp, 0x1f, 0x0a43);
3949 rtl_writephy(tp, 0x13, 0x808a);
3950 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3951 rtl_writephy(tp, 0x1f, 0x0000);
3953 /* enable R-tune & PGA-retune function */
3954 rtl_writephy(tp, 0x1f, 0x0a43);
3955 rtl_writephy(tp, 0x13, 0x0811);
3956 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3957 rtl_writephy(tp, 0x1f, 0x0a42);
3958 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3959 rtl_writephy(tp, 0x1f, 0x0000);
3961 /* enable GPHY 10M */
3962 rtl_writephy(tp, 0x1f, 0x0a44);
3963 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3964 rtl_writephy(tp, 0x1f, 0x0000);
3966 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3967 data = r8168_mac_ocp_read(tp, 0xdd02);
3968 ioffset_p3 = ((data & 0x80)>>7);
3971 data = r8168_mac_ocp_read(tp, 0xdd00);
3972 ioffset_p3 |= ((data & (0xe000))>>13);
3973 ioffset_p2 = ((data & (0x1e00))>>9);
3974 ioffset_p1 = ((data & (0x01e0))>>5);
3975 ioffset_p0 = ((data & 0x0010)>>4);
3977 ioffset_p0 |= (data & (0x07));
3978 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3980 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3981 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3982 rtl_writephy(tp, 0x1f, 0x0bcf);
3983 rtl_writephy(tp, 0x16, data);
3984 rtl_writephy(tp, 0x1f, 0x0000);
3987 /* Modify rlen (TX LPF corner frequency) level */
3988 rtl_writephy(tp, 0x1f, 0x0bcd);
3989 data = rtl_readphy(tp, 0x16);
3994 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3995 rtl_writephy(tp, 0x17, data);
3996 rtl_writephy(tp, 0x1f, 0x0bcd);
3997 rtl_writephy(tp, 0x1f, 0x0000);
3999 /* disable phy pfm mode */
4000 rtl_writephy(tp, 0x1f, 0x0a44);
4001 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4002 rtl_writephy(tp, 0x1f, 0x0000);
4004 /* Check ALDPS bit, disable it if enabled */
4005 rtl_writephy(tp, 0x1f, 0x0a43);
4006 if (rtl_readphy(tp, 0x10) & 0x0004)
4007 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4012 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4014 /* Enable PHY auto speed down */
4015 rtl_writephy(tp, 0x1f, 0x0a44);
4016 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4017 rtl_writephy(tp, 0x1f, 0x0000);
4019 /* patch 10M & ALDPS */
4020 rtl_writephy(tp, 0x1f, 0x0bcc);
4021 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4022 rtl_writephy(tp, 0x1f, 0x0a44);
4023 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4024 rtl_writephy(tp, 0x1f, 0x0a43);
4025 rtl_writephy(tp, 0x13, 0x8084);
4026 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4027 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4028 rtl_writephy(tp, 0x1f, 0x0000);
4030 /* Enable EEE auto-fallback function */
4031 rtl_writephy(tp, 0x1f, 0x0a4b);
4032 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4033 rtl_writephy(tp, 0x1f, 0x0000);
4035 /* Enable UC LPF tune function */
4036 rtl_writephy(tp, 0x1f, 0x0a43);
4037 rtl_writephy(tp, 0x13, 0x8012);
4038 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4039 rtl_writephy(tp, 0x1f, 0x0000);
4041 /* set rg_sel_sdm_rate */
4042 rtl_writephy(tp, 0x1f, 0x0c42);
4043 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4044 rtl_writephy(tp, 0x1f, 0x0000);
4046 /* Check ALDPS bit, disable it if enabled */
4047 rtl_writephy(tp, 0x1f, 0x0a43);
4048 if (rtl_readphy(tp, 0x10) & 0x0004)
4049 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4051 rtl_writephy(tp, 0x1f, 0x0000);
4054 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4056 /* patch 10M & ALDPS */
4057 rtl_writephy(tp, 0x1f, 0x0bcc);
4058 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4059 rtl_writephy(tp, 0x1f, 0x0a44);
4060 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4061 rtl_writephy(tp, 0x1f, 0x0a43);
4062 rtl_writephy(tp, 0x13, 0x8084);
4063 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4064 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4065 rtl_writephy(tp, 0x1f, 0x0000);
4067 /* Enable UC LPF tune function */
4068 rtl_writephy(tp, 0x1f, 0x0a43);
4069 rtl_writephy(tp, 0x13, 0x8012);
4070 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4071 rtl_writephy(tp, 0x1f, 0x0000);
4073 /* Set rg_sel_sdm_rate */
4074 rtl_writephy(tp, 0x1f, 0x0c42);
4075 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4076 rtl_writephy(tp, 0x1f, 0x0000);
4078 /* Channel estimation parameters */
4079 rtl_writephy(tp, 0x1f, 0x0a43);
4080 rtl_writephy(tp, 0x13, 0x80f3);
4081 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4082 rtl_writephy(tp, 0x13, 0x80f0);
4083 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4084 rtl_writephy(tp, 0x13, 0x80ef);
4085 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4086 rtl_writephy(tp, 0x13, 0x80f6);
4087 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4088 rtl_writephy(tp, 0x13, 0x80ec);
4089 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4090 rtl_writephy(tp, 0x13, 0x80ed);
4091 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4092 rtl_writephy(tp, 0x13, 0x80f2);
4093 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4094 rtl_writephy(tp, 0x13, 0x80f4);
4095 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4096 rtl_writephy(tp, 0x1f, 0x0a43);
4097 rtl_writephy(tp, 0x13, 0x8110);
4098 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4099 rtl_writephy(tp, 0x13, 0x810f);
4100 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4101 rtl_writephy(tp, 0x13, 0x8111);
4102 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4103 rtl_writephy(tp, 0x13, 0x8113);
4104 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4105 rtl_writephy(tp, 0x13, 0x8115);
4106 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4107 rtl_writephy(tp, 0x13, 0x810e);
4108 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4109 rtl_writephy(tp, 0x13, 0x810c);
4110 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4111 rtl_writephy(tp, 0x13, 0x810b);
4112 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4113 rtl_writephy(tp, 0x1f, 0x0a43);
4114 rtl_writephy(tp, 0x13, 0x80d1);
4115 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4116 rtl_writephy(tp, 0x13, 0x80cd);
4117 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4118 rtl_writephy(tp, 0x13, 0x80d3);
4119 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4120 rtl_writephy(tp, 0x13, 0x80d5);
4121 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4122 rtl_writephy(tp, 0x13, 0x80d7);
4123 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4125 /* Force PWM-mode */
4126 rtl_writephy(tp, 0x1f, 0x0bcd);
4127 rtl_writephy(tp, 0x14, 0x5065);
4128 rtl_writephy(tp, 0x14, 0xd065);
4129 rtl_writephy(tp, 0x1f, 0x0bc8);
4130 rtl_writephy(tp, 0x12, 0x00ed);
4131 rtl_writephy(tp, 0x1f, 0x0bcd);
4132 rtl_writephy(tp, 0x14, 0x1065);
4133 rtl_writephy(tp, 0x14, 0x9065);
4134 rtl_writephy(tp, 0x14, 0x1065);
4135 rtl_writephy(tp, 0x1f, 0x0000);
4137 /* Check ALDPS bit, disable it if enabled */
4138 rtl_writephy(tp, 0x1f, 0x0a43);
4139 if (rtl_readphy(tp, 0x10) & 0x0004)
4140 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4142 rtl_writephy(tp, 0x1f, 0x0000);
4145 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4147 static const struct phy_reg phy_reg_init[] = {
4154 rtl_writephy(tp, 0x1f, 0x0000);
4155 rtl_patchphy(tp, 0x11, 1 << 12);
4156 rtl_patchphy(tp, 0x19, 1 << 13);
4157 rtl_patchphy(tp, 0x10, 1 << 15);
4159 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4162 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4164 static const struct phy_reg phy_reg_init[] = {
4178 /* Disable ALDPS before ram code */
4179 rtl_writephy(tp, 0x1f, 0x0000);
4180 rtl_writephy(tp, 0x18, 0x0310);
4183 rtl_apply_firmware(tp);
4185 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4188 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4190 /* Disable ALDPS before setting firmware */
4191 rtl_writephy(tp, 0x1f, 0x0000);
4192 rtl_writephy(tp, 0x18, 0x0310);
4195 rtl_apply_firmware(tp);
4198 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4199 rtl_writephy(tp, 0x1f, 0x0004);
4200 rtl_writephy(tp, 0x10, 0x401f);
4201 rtl_writephy(tp, 0x19, 0x7030);
4202 rtl_writephy(tp, 0x1f, 0x0000);
4205 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4207 static const struct phy_reg phy_reg_init[] = {
4214 /* Disable ALDPS before ram code */
4215 rtl_writephy(tp, 0x1f, 0x0000);
4216 rtl_writephy(tp, 0x18, 0x0310);
4219 rtl_apply_firmware(tp);
4221 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4222 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4224 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4227 static void rtl_hw_phy_config(struct net_device *dev)
4229 struct rtl8169_private *tp = netdev_priv(dev);
4231 rtl8169_print_mac_version(tp);
4233 switch (tp->mac_version) {
4234 case RTL_GIGA_MAC_VER_01:
4236 case RTL_GIGA_MAC_VER_02:
4237 case RTL_GIGA_MAC_VER_03:
4238 rtl8169s_hw_phy_config(tp);
4240 case RTL_GIGA_MAC_VER_04:
4241 rtl8169sb_hw_phy_config(tp);
4243 case RTL_GIGA_MAC_VER_05:
4244 rtl8169scd_hw_phy_config(tp);
4246 case RTL_GIGA_MAC_VER_06:
4247 rtl8169sce_hw_phy_config(tp);
4249 case RTL_GIGA_MAC_VER_07:
4250 case RTL_GIGA_MAC_VER_08:
4251 case RTL_GIGA_MAC_VER_09:
4252 rtl8102e_hw_phy_config(tp);
4254 case RTL_GIGA_MAC_VER_11:
4255 rtl8168bb_hw_phy_config(tp);
4257 case RTL_GIGA_MAC_VER_12:
4258 rtl8168bef_hw_phy_config(tp);
4260 case RTL_GIGA_MAC_VER_17:
4261 rtl8168bef_hw_phy_config(tp);
4263 case RTL_GIGA_MAC_VER_18:
4264 rtl8168cp_1_hw_phy_config(tp);
4266 case RTL_GIGA_MAC_VER_19:
4267 rtl8168c_1_hw_phy_config(tp);
4269 case RTL_GIGA_MAC_VER_20:
4270 rtl8168c_2_hw_phy_config(tp);
4272 case RTL_GIGA_MAC_VER_21:
4273 rtl8168c_3_hw_phy_config(tp);
4275 case RTL_GIGA_MAC_VER_22:
4276 rtl8168c_4_hw_phy_config(tp);
4278 case RTL_GIGA_MAC_VER_23:
4279 case RTL_GIGA_MAC_VER_24:
4280 rtl8168cp_2_hw_phy_config(tp);
4282 case RTL_GIGA_MAC_VER_25:
4283 rtl8168d_1_hw_phy_config(tp);
4285 case RTL_GIGA_MAC_VER_26:
4286 rtl8168d_2_hw_phy_config(tp);
4288 case RTL_GIGA_MAC_VER_27:
4289 rtl8168d_3_hw_phy_config(tp);
4291 case RTL_GIGA_MAC_VER_28:
4292 rtl8168d_4_hw_phy_config(tp);
4294 case RTL_GIGA_MAC_VER_29:
4295 case RTL_GIGA_MAC_VER_30:
4296 rtl8105e_hw_phy_config(tp);
4298 case RTL_GIGA_MAC_VER_31:
4301 case RTL_GIGA_MAC_VER_32:
4302 case RTL_GIGA_MAC_VER_33:
4303 rtl8168e_1_hw_phy_config(tp);
4305 case RTL_GIGA_MAC_VER_34:
4306 rtl8168e_2_hw_phy_config(tp);
4308 case RTL_GIGA_MAC_VER_35:
4309 rtl8168f_1_hw_phy_config(tp);
4311 case RTL_GIGA_MAC_VER_36:
4312 rtl8168f_2_hw_phy_config(tp);
4315 case RTL_GIGA_MAC_VER_37:
4316 rtl8402_hw_phy_config(tp);
4319 case RTL_GIGA_MAC_VER_38:
4320 rtl8411_hw_phy_config(tp);
4323 case RTL_GIGA_MAC_VER_39:
4324 rtl8106e_hw_phy_config(tp);
4327 case RTL_GIGA_MAC_VER_40:
4328 rtl8168g_1_hw_phy_config(tp);
4330 case RTL_GIGA_MAC_VER_42:
4331 case RTL_GIGA_MAC_VER_43:
4332 case RTL_GIGA_MAC_VER_44:
4333 rtl8168g_2_hw_phy_config(tp);
4335 case RTL_GIGA_MAC_VER_45:
4336 case RTL_GIGA_MAC_VER_47:
4337 rtl8168h_1_hw_phy_config(tp);
4339 case RTL_GIGA_MAC_VER_46:
4340 case RTL_GIGA_MAC_VER_48:
4341 rtl8168h_2_hw_phy_config(tp);
4344 case RTL_GIGA_MAC_VER_49:
4345 rtl8168ep_1_hw_phy_config(tp);
4347 case RTL_GIGA_MAC_VER_50:
4348 case RTL_GIGA_MAC_VER_51:
4349 rtl8168ep_2_hw_phy_config(tp);
4352 case RTL_GIGA_MAC_VER_41:
4358 static void rtl_phy_work(struct rtl8169_private *tp)
4360 struct timer_list *timer = &tp->timer;
4361 void __iomem *ioaddr = tp->mmio_addr;
4362 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4364 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4366 if (tp->phy_reset_pending(tp)) {
4368 * A busy loop could burn quite a few cycles on nowadays CPU.
4369 * Let's delay the execution of the timer for a few ticks.
4375 if (tp->link_ok(ioaddr))
4378 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4380 tp->phy_reset_enable(tp);
4383 mod_timer(timer, jiffies + timeout);
4386 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4388 if (!test_and_set_bit(flag, tp->wk.flags))
4389 schedule_work(&tp->wk.work);
4392 static void rtl8169_phy_timer(unsigned long __opaque)
4394 struct net_device *dev = (struct net_device *)__opaque;
4395 struct rtl8169_private *tp = netdev_priv(dev);
4397 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4400 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4401 void __iomem *ioaddr)
4404 pci_release_regions(pdev);
4405 pci_clear_mwi(pdev);
4406 pci_disable_device(pdev);
4410 DECLARE_RTL_COND(rtl_phy_reset_cond)
4412 return tp->phy_reset_pending(tp);
4415 static void rtl8169_phy_reset(struct net_device *dev,
4416 struct rtl8169_private *tp)
4418 tp->phy_reset_enable(tp);
4419 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4422 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4424 void __iomem *ioaddr = tp->mmio_addr;
4426 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4427 (RTL_R8(PHYstatus) & TBI_Enable);
4430 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4432 void __iomem *ioaddr = tp->mmio_addr;
4434 rtl_hw_phy_config(dev);
4436 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4437 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4441 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4443 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4444 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4446 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4447 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4449 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4450 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4453 rtl8169_phy_reset(dev, tp);
4455 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4456 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4457 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4458 (tp->mii.supports_gmii ?
4459 ADVERTISED_1000baseT_Half |
4460 ADVERTISED_1000baseT_Full : 0));
4462 if (rtl_tbi_enabled(tp))
4463 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4466 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4468 void __iomem *ioaddr = tp->mmio_addr;
4472 RTL_W8(Cfg9346, Cfg9346_Unlock);
4474 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4477 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4480 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4481 rtl_rar_exgmac_set(tp, addr);
4483 RTL_W8(Cfg9346, Cfg9346_Lock);
4485 rtl_unlock_work(tp);
4488 static int rtl_set_mac_address(struct net_device *dev, void *p)
4490 struct rtl8169_private *tp = netdev_priv(dev);
4491 struct device *d = &tp->pci_dev->dev;
4492 struct sockaddr *addr = p;
4494 if (!is_valid_ether_addr(addr->sa_data))
4495 return -EADDRNOTAVAIL;
4497 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4499 pm_runtime_get_noresume(d);
4501 if (pm_runtime_active(d))
4502 rtl_rar_set(tp, dev->dev_addr);
4504 pm_runtime_put_noidle(d);
4509 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4511 struct rtl8169_private *tp = netdev_priv(dev);
4512 struct mii_ioctl_data *data = if_mii(ifr);
4514 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4517 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4518 struct mii_ioctl_data *data, int cmd)
4522 data->phy_id = 32; /* Internal PHY */
4526 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4530 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4536 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4541 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4543 if (tp->features & RTL_FEATURE_MSI) {
4544 pci_disable_msi(pdev);
4545 tp->features &= ~RTL_FEATURE_MSI;
4549 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4551 struct mdio_ops *ops = &tp->mdio_ops;
4553 switch (tp->mac_version) {
4554 case RTL_GIGA_MAC_VER_27:
4555 ops->write = r8168dp_1_mdio_write;
4556 ops->read = r8168dp_1_mdio_read;
4558 case RTL_GIGA_MAC_VER_28:
4559 case RTL_GIGA_MAC_VER_31:
4560 ops->write = r8168dp_2_mdio_write;
4561 ops->read = r8168dp_2_mdio_read;
4563 case RTL_GIGA_MAC_VER_40:
4564 case RTL_GIGA_MAC_VER_41:
4565 case RTL_GIGA_MAC_VER_42:
4566 case RTL_GIGA_MAC_VER_43:
4567 case RTL_GIGA_MAC_VER_44:
4568 case RTL_GIGA_MAC_VER_45:
4569 case RTL_GIGA_MAC_VER_46:
4570 case RTL_GIGA_MAC_VER_47:
4571 case RTL_GIGA_MAC_VER_48:
4572 case RTL_GIGA_MAC_VER_49:
4573 case RTL_GIGA_MAC_VER_50:
4574 case RTL_GIGA_MAC_VER_51:
4575 ops->write = r8168g_mdio_write;
4576 ops->read = r8168g_mdio_read;
4579 ops->write = r8169_mdio_write;
4580 ops->read = r8169_mdio_read;
4585 static void rtl_speed_down(struct rtl8169_private *tp)
4590 rtl_writephy(tp, 0x1f, 0x0000);
4591 lpa = rtl_readphy(tp, MII_LPA);
4593 if (lpa & (LPA_10HALF | LPA_10FULL))
4594 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4595 else if (lpa & (LPA_100HALF | LPA_100FULL))
4596 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4597 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4599 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4600 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4601 (tp->mii.supports_gmii ?
4602 ADVERTISED_1000baseT_Half |
4603 ADVERTISED_1000baseT_Full : 0);
4605 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4609 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4611 void __iomem *ioaddr = tp->mmio_addr;
4613 switch (tp->mac_version) {
4614 case RTL_GIGA_MAC_VER_25:
4615 case RTL_GIGA_MAC_VER_26:
4616 case RTL_GIGA_MAC_VER_29:
4617 case RTL_GIGA_MAC_VER_30:
4618 case RTL_GIGA_MAC_VER_32:
4619 case RTL_GIGA_MAC_VER_33:
4620 case RTL_GIGA_MAC_VER_34:
4621 case RTL_GIGA_MAC_VER_37:
4622 case RTL_GIGA_MAC_VER_38:
4623 case RTL_GIGA_MAC_VER_39:
4624 case RTL_GIGA_MAC_VER_40:
4625 case RTL_GIGA_MAC_VER_41:
4626 case RTL_GIGA_MAC_VER_42:
4627 case RTL_GIGA_MAC_VER_43:
4628 case RTL_GIGA_MAC_VER_44:
4629 case RTL_GIGA_MAC_VER_45:
4630 case RTL_GIGA_MAC_VER_46:
4631 case RTL_GIGA_MAC_VER_47:
4632 case RTL_GIGA_MAC_VER_48:
4633 case RTL_GIGA_MAC_VER_49:
4634 case RTL_GIGA_MAC_VER_50:
4635 case RTL_GIGA_MAC_VER_51:
4636 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4637 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4644 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4646 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4650 rtl_wol_suspend_quirk(tp);
4655 static void r810x_phy_power_down(struct rtl8169_private *tp)
4657 rtl_writephy(tp, 0x1f, 0x0000);
4658 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4661 static void r810x_phy_power_up(struct rtl8169_private *tp)
4663 rtl_writephy(tp, 0x1f, 0x0000);
4664 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4667 static void r810x_pll_power_down(struct rtl8169_private *tp)
4669 void __iomem *ioaddr = tp->mmio_addr;
4671 if (rtl_wol_pll_power_down(tp))
4674 r810x_phy_power_down(tp);
4676 switch (tp->mac_version) {
4677 case RTL_GIGA_MAC_VER_07:
4678 case RTL_GIGA_MAC_VER_08:
4679 case RTL_GIGA_MAC_VER_09:
4680 case RTL_GIGA_MAC_VER_10:
4681 case RTL_GIGA_MAC_VER_13:
4682 case RTL_GIGA_MAC_VER_16:
4685 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4690 static void r810x_pll_power_up(struct rtl8169_private *tp)
4692 void __iomem *ioaddr = tp->mmio_addr;
4694 r810x_phy_power_up(tp);
4696 switch (tp->mac_version) {
4697 case RTL_GIGA_MAC_VER_07:
4698 case RTL_GIGA_MAC_VER_08:
4699 case RTL_GIGA_MAC_VER_09:
4700 case RTL_GIGA_MAC_VER_10:
4701 case RTL_GIGA_MAC_VER_13:
4702 case RTL_GIGA_MAC_VER_16:
4704 case RTL_GIGA_MAC_VER_47:
4705 case RTL_GIGA_MAC_VER_48:
4706 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4709 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4714 static void r8168_phy_power_up(struct rtl8169_private *tp)
4716 rtl_writephy(tp, 0x1f, 0x0000);
4717 switch (tp->mac_version) {
4718 case RTL_GIGA_MAC_VER_11:
4719 case RTL_GIGA_MAC_VER_12:
4720 case RTL_GIGA_MAC_VER_17:
4721 case RTL_GIGA_MAC_VER_18:
4722 case RTL_GIGA_MAC_VER_19:
4723 case RTL_GIGA_MAC_VER_20:
4724 case RTL_GIGA_MAC_VER_21:
4725 case RTL_GIGA_MAC_VER_22:
4726 case RTL_GIGA_MAC_VER_23:
4727 case RTL_GIGA_MAC_VER_24:
4728 case RTL_GIGA_MAC_VER_25:
4729 case RTL_GIGA_MAC_VER_26:
4730 case RTL_GIGA_MAC_VER_27:
4731 case RTL_GIGA_MAC_VER_28:
4732 case RTL_GIGA_MAC_VER_31:
4733 rtl_writephy(tp, 0x0e, 0x0000);
4738 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4741 static void r8168_phy_power_down(struct rtl8169_private *tp)
4743 rtl_writephy(tp, 0x1f, 0x0000);
4744 switch (tp->mac_version) {
4745 case RTL_GIGA_MAC_VER_32:
4746 case RTL_GIGA_MAC_VER_33:
4747 case RTL_GIGA_MAC_VER_40:
4748 case RTL_GIGA_MAC_VER_41:
4749 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4752 case RTL_GIGA_MAC_VER_11:
4753 case RTL_GIGA_MAC_VER_12:
4754 case RTL_GIGA_MAC_VER_17:
4755 case RTL_GIGA_MAC_VER_18:
4756 case RTL_GIGA_MAC_VER_19:
4757 case RTL_GIGA_MAC_VER_20:
4758 case RTL_GIGA_MAC_VER_21:
4759 case RTL_GIGA_MAC_VER_22:
4760 case RTL_GIGA_MAC_VER_23:
4761 case RTL_GIGA_MAC_VER_24:
4762 case RTL_GIGA_MAC_VER_25:
4763 case RTL_GIGA_MAC_VER_26:
4764 case RTL_GIGA_MAC_VER_27:
4765 case RTL_GIGA_MAC_VER_28:
4766 case RTL_GIGA_MAC_VER_31:
4767 rtl_writephy(tp, 0x0e, 0x0200);
4769 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4774 static void r8168_pll_power_down(struct rtl8169_private *tp)
4776 void __iomem *ioaddr = tp->mmio_addr;
4778 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4779 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4780 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4781 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4782 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4783 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4784 r8168_check_dash(tp)) {
4788 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4789 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4790 (RTL_R16(CPlusCmd) & ASF)) {
4794 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4795 tp->mac_version == RTL_GIGA_MAC_VER_33)
4796 rtl_ephy_write(tp, 0x19, 0xff64);
4798 if (rtl_wol_pll_power_down(tp))
4801 r8168_phy_power_down(tp);
4803 switch (tp->mac_version) {
4804 case RTL_GIGA_MAC_VER_25:
4805 case RTL_GIGA_MAC_VER_26:
4806 case RTL_GIGA_MAC_VER_27:
4807 case RTL_GIGA_MAC_VER_28:
4808 case RTL_GIGA_MAC_VER_31:
4809 case RTL_GIGA_MAC_VER_32:
4810 case RTL_GIGA_MAC_VER_33:
4811 case RTL_GIGA_MAC_VER_44:
4812 case RTL_GIGA_MAC_VER_45:
4813 case RTL_GIGA_MAC_VER_46:
4814 case RTL_GIGA_MAC_VER_50:
4815 case RTL_GIGA_MAC_VER_51:
4816 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4818 case RTL_GIGA_MAC_VER_40:
4819 case RTL_GIGA_MAC_VER_41:
4820 case RTL_GIGA_MAC_VER_49:
4821 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4822 0xfc000000, ERIAR_EXGMAC);
4823 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4828 static void r8168_pll_power_up(struct rtl8169_private *tp)
4830 void __iomem *ioaddr = tp->mmio_addr;
4832 switch (tp->mac_version) {
4833 case RTL_GIGA_MAC_VER_25:
4834 case RTL_GIGA_MAC_VER_26:
4835 case RTL_GIGA_MAC_VER_27:
4836 case RTL_GIGA_MAC_VER_28:
4837 case RTL_GIGA_MAC_VER_31:
4838 case RTL_GIGA_MAC_VER_32:
4839 case RTL_GIGA_MAC_VER_33:
4840 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4842 case RTL_GIGA_MAC_VER_44:
4843 case RTL_GIGA_MAC_VER_45:
4844 case RTL_GIGA_MAC_VER_46:
4845 case RTL_GIGA_MAC_VER_50:
4846 case RTL_GIGA_MAC_VER_51:
4847 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4849 case RTL_GIGA_MAC_VER_40:
4850 case RTL_GIGA_MAC_VER_41:
4851 case RTL_GIGA_MAC_VER_49:
4852 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4853 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4854 0x00000000, ERIAR_EXGMAC);
4858 r8168_phy_power_up(tp);
4861 static void rtl_generic_op(struct rtl8169_private *tp,
4862 void (*op)(struct rtl8169_private *))
4868 static void rtl_pll_power_down(struct rtl8169_private *tp)
4870 rtl_generic_op(tp, tp->pll_power_ops.down);
4873 static void rtl_pll_power_up(struct rtl8169_private *tp)
4875 rtl_generic_op(tp, tp->pll_power_ops.up);
4878 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4880 struct pll_power_ops *ops = &tp->pll_power_ops;
4882 switch (tp->mac_version) {
4883 case RTL_GIGA_MAC_VER_07:
4884 case RTL_GIGA_MAC_VER_08:
4885 case RTL_GIGA_MAC_VER_09:
4886 case RTL_GIGA_MAC_VER_10:
4887 case RTL_GIGA_MAC_VER_16:
4888 case RTL_GIGA_MAC_VER_29:
4889 case RTL_GIGA_MAC_VER_30:
4890 case RTL_GIGA_MAC_VER_37:
4891 case RTL_GIGA_MAC_VER_39:
4892 case RTL_GIGA_MAC_VER_43:
4893 case RTL_GIGA_MAC_VER_47:
4894 case RTL_GIGA_MAC_VER_48:
4895 ops->down = r810x_pll_power_down;
4896 ops->up = r810x_pll_power_up;
4899 case RTL_GIGA_MAC_VER_11:
4900 case RTL_GIGA_MAC_VER_12:
4901 case RTL_GIGA_MAC_VER_17:
4902 case RTL_GIGA_MAC_VER_18:
4903 case RTL_GIGA_MAC_VER_19:
4904 case RTL_GIGA_MAC_VER_20:
4905 case RTL_GIGA_MAC_VER_21:
4906 case RTL_GIGA_MAC_VER_22:
4907 case RTL_GIGA_MAC_VER_23:
4908 case RTL_GIGA_MAC_VER_24:
4909 case RTL_GIGA_MAC_VER_25:
4910 case RTL_GIGA_MAC_VER_26:
4911 case RTL_GIGA_MAC_VER_27:
4912 case RTL_GIGA_MAC_VER_28:
4913 case RTL_GIGA_MAC_VER_31:
4914 case RTL_GIGA_MAC_VER_32:
4915 case RTL_GIGA_MAC_VER_33:
4916 case RTL_GIGA_MAC_VER_34:
4917 case RTL_GIGA_MAC_VER_35:
4918 case RTL_GIGA_MAC_VER_36:
4919 case RTL_GIGA_MAC_VER_38:
4920 case RTL_GIGA_MAC_VER_40:
4921 case RTL_GIGA_MAC_VER_41:
4922 case RTL_GIGA_MAC_VER_42:
4923 case RTL_GIGA_MAC_VER_44:
4924 case RTL_GIGA_MAC_VER_45:
4925 case RTL_GIGA_MAC_VER_46:
4926 case RTL_GIGA_MAC_VER_49:
4927 case RTL_GIGA_MAC_VER_50:
4928 case RTL_GIGA_MAC_VER_51:
4929 ops->down = r8168_pll_power_down;
4930 ops->up = r8168_pll_power_up;
4940 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4942 void __iomem *ioaddr = tp->mmio_addr;
4944 switch (tp->mac_version) {
4945 case RTL_GIGA_MAC_VER_01:
4946 case RTL_GIGA_MAC_VER_02:
4947 case RTL_GIGA_MAC_VER_03:
4948 case RTL_GIGA_MAC_VER_04:
4949 case RTL_GIGA_MAC_VER_05:
4950 case RTL_GIGA_MAC_VER_06:
4951 case RTL_GIGA_MAC_VER_10:
4952 case RTL_GIGA_MAC_VER_11:
4953 case RTL_GIGA_MAC_VER_12:
4954 case RTL_GIGA_MAC_VER_13:
4955 case RTL_GIGA_MAC_VER_14:
4956 case RTL_GIGA_MAC_VER_15:
4957 case RTL_GIGA_MAC_VER_16:
4958 case RTL_GIGA_MAC_VER_17:
4959 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4961 case RTL_GIGA_MAC_VER_18:
4962 case RTL_GIGA_MAC_VER_19:
4963 case RTL_GIGA_MAC_VER_20:
4964 case RTL_GIGA_MAC_VER_21:
4965 case RTL_GIGA_MAC_VER_22:
4966 case RTL_GIGA_MAC_VER_23:
4967 case RTL_GIGA_MAC_VER_24:
4968 case RTL_GIGA_MAC_VER_34:
4969 case RTL_GIGA_MAC_VER_35:
4970 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4972 case RTL_GIGA_MAC_VER_40:
4973 case RTL_GIGA_MAC_VER_41:
4974 case RTL_GIGA_MAC_VER_42:
4975 case RTL_GIGA_MAC_VER_43:
4976 case RTL_GIGA_MAC_VER_44:
4977 case RTL_GIGA_MAC_VER_45:
4978 case RTL_GIGA_MAC_VER_46:
4979 case RTL_GIGA_MAC_VER_47:
4980 case RTL_GIGA_MAC_VER_48:
4981 case RTL_GIGA_MAC_VER_49:
4982 case RTL_GIGA_MAC_VER_50:
4983 case RTL_GIGA_MAC_VER_51:
4984 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4987 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4992 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4994 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4997 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4999 void __iomem *ioaddr = tp->mmio_addr;
5001 RTL_W8(Cfg9346, Cfg9346_Unlock);
5002 rtl_generic_op(tp, tp->jumbo_ops.enable);
5003 RTL_W8(Cfg9346, Cfg9346_Lock);
5006 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5008 void __iomem *ioaddr = tp->mmio_addr;
5010 RTL_W8(Cfg9346, Cfg9346_Unlock);
5011 rtl_generic_op(tp, tp->jumbo_ops.disable);
5012 RTL_W8(Cfg9346, Cfg9346_Lock);
5015 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5017 void __iomem *ioaddr = tp->mmio_addr;
5019 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5020 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5021 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5024 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5026 void __iomem *ioaddr = tp->mmio_addr;
5028 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5029 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5030 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5033 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5035 void __iomem *ioaddr = tp->mmio_addr;
5037 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5040 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5042 void __iomem *ioaddr = tp->mmio_addr;
5044 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5047 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5049 void __iomem *ioaddr = tp->mmio_addr;
5051 RTL_W8(MaxTxPacketSize, 0x3f);
5052 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5053 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5054 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5057 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5059 void __iomem *ioaddr = tp->mmio_addr;
5061 RTL_W8(MaxTxPacketSize, 0x0c);
5062 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5063 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5064 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5067 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5069 rtl_tx_performance_tweak(tp->pci_dev,
5070 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5073 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5075 rtl_tx_performance_tweak(tp->pci_dev,
5076 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5079 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5081 void __iomem *ioaddr = tp->mmio_addr;
5083 r8168b_0_hw_jumbo_enable(tp);
5085 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5088 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5090 void __iomem *ioaddr = tp->mmio_addr;
5092 r8168b_0_hw_jumbo_disable(tp);
5094 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5097 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5099 struct jumbo_ops *ops = &tp->jumbo_ops;
5101 switch (tp->mac_version) {
5102 case RTL_GIGA_MAC_VER_11:
5103 ops->disable = r8168b_0_hw_jumbo_disable;
5104 ops->enable = r8168b_0_hw_jumbo_enable;
5106 case RTL_GIGA_MAC_VER_12:
5107 case RTL_GIGA_MAC_VER_17:
5108 ops->disable = r8168b_1_hw_jumbo_disable;
5109 ops->enable = r8168b_1_hw_jumbo_enable;
5111 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5112 case RTL_GIGA_MAC_VER_19:
5113 case RTL_GIGA_MAC_VER_20:
5114 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5115 case RTL_GIGA_MAC_VER_22:
5116 case RTL_GIGA_MAC_VER_23:
5117 case RTL_GIGA_MAC_VER_24:
5118 case RTL_GIGA_MAC_VER_25:
5119 case RTL_GIGA_MAC_VER_26:
5120 ops->disable = r8168c_hw_jumbo_disable;
5121 ops->enable = r8168c_hw_jumbo_enable;
5123 case RTL_GIGA_MAC_VER_27:
5124 case RTL_GIGA_MAC_VER_28:
5125 ops->disable = r8168dp_hw_jumbo_disable;
5126 ops->enable = r8168dp_hw_jumbo_enable;
5128 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5129 case RTL_GIGA_MAC_VER_32:
5130 case RTL_GIGA_MAC_VER_33:
5131 case RTL_GIGA_MAC_VER_34:
5132 ops->disable = r8168e_hw_jumbo_disable;
5133 ops->enable = r8168e_hw_jumbo_enable;
5137 * No action needed for jumbo frames with 8169.
5138 * No jumbo for 810x at all.
5140 case RTL_GIGA_MAC_VER_40:
5141 case RTL_GIGA_MAC_VER_41:
5142 case RTL_GIGA_MAC_VER_42:
5143 case RTL_GIGA_MAC_VER_43:
5144 case RTL_GIGA_MAC_VER_44:
5145 case RTL_GIGA_MAC_VER_45:
5146 case RTL_GIGA_MAC_VER_46:
5147 case RTL_GIGA_MAC_VER_47:
5148 case RTL_GIGA_MAC_VER_48:
5149 case RTL_GIGA_MAC_VER_49:
5150 case RTL_GIGA_MAC_VER_50:
5151 case RTL_GIGA_MAC_VER_51:
5153 ops->disable = NULL;
5159 DECLARE_RTL_COND(rtl_chipcmd_cond)
5161 void __iomem *ioaddr = tp->mmio_addr;
5163 return RTL_R8(ChipCmd) & CmdReset;
5166 static void rtl_hw_reset(struct rtl8169_private *tp)
5168 void __iomem *ioaddr = tp->mmio_addr;
5170 RTL_W8(ChipCmd, CmdReset);
5172 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5175 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5177 struct rtl_fw *rtl_fw;
5181 name = rtl_lookup_firmware_name(tp);
5183 goto out_no_firmware;
5185 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5189 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5193 rc = rtl_check_firmware(tp, rtl_fw);
5195 goto err_release_firmware;
5197 tp->rtl_fw = rtl_fw;
5201 err_release_firmware:
5202 release_firmware(rtl_fw->fw);
5206 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5213 static void rtl_request_firmware(struct rtl8169_private *tp)
5215 if (IS_ERR(tp->rtl_fw))
5216 rtl_request_uncached_firmware(tp);
5219 static void rtl_rx_close(struct rtl8169_private *tp)
5221 void __iomem *ioaddr = tp->mmio_addr;
5223 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5226 DECLARE_RTL_COND(rtl_npq_cond)
5228 void __iomem *ioaddr = tp->mmio_addr;
5230 return RTL_R8(TxPoll) & NPQ;
5233 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5235 void __iomem *ioaddr = tp->mmio_addr;
5237 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5240 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5242 void __iomem *ioaddr = tp->mmio_addr;
5244 /* Disable interrupts */
5245 rtl8169_irq_mask_and_ack(tp);
5249 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5250 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5251 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5252 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5253 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5254 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5255 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5256 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5257 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5258 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5259 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5260 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5261 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5262 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5263 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5264 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5265 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5266 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5267 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5268 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5269 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5270 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5271 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5273 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5280 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5282 void __iomem *ioaddr = tp->mmio_addr;
5284 /* Set DMA burst size and Interframe Gap Time */
5285 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5286 (InterFrameGap << TxInterFrameGapShift));
5289 static void rtl_hw_start(struct net_device *dev)
5291 struct rtl8169_private *tp = netdev_priv(dev);
5295 rtl_irq_enable_all(tp);
5298 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5299 void __iomem *ioaddr)
5302 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5303 * register to be written before TxDescAddrLow to work.
5304 * Switching from MMIO to I/O access fixes the issue as well.
5306 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5307 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5308 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5309 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5312 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5316 cmd = RTL_R16(CPlusCmd);
5317 RTL_W16(CPlusCmd, cmd);
5321 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5323 /* Low hurts. Let's disable the filtering. */
5324 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5327 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5329 static const struct rtl_cfg2_info {
5334 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5335 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5336 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5337 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5339 const struct rtl_cfg2_info *p = cfg2_info;
5343 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5344 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5345 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5346 RTL_W32(0x7c, p->val);
5352 static void rtl_set_rx_mode(struct net_device *dev)
5354 struct rtl8169_private *tp = netdev_priv(dev);
5355 void __iomem *ioaddr = tp->mmio_addr;
5356 u32 mc_filter[2]; /* Multicast hash filter */
5360 if (dev->flags & IFF_PROMISC) {
5361 /* Unconditionally log net taps. */
5362 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5364 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5366 mc_filter[1] = mc_filter[0] = 0xffffffff;
5367 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5368 (dev->flags & IFF_ALLMULTI)) {
5369 /* Too many to filter perfectly -- accept all multicasts. */
5370 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5371 mc_filter[1] = mc_filter[0] = 0xffffffff;
5373 struct netdev_hw_addr *ha;
5375 rx_mode = AcceptBroadcast | AcceptMyPhys;
5376 mc_filter[1] = mc_filter[0] = 0;
5377 netdev_for_each_mc_addr(ha, dev) {
5378 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5379 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5380 rx_mode |= AcceptMulticast;
5384 if (dev->features & NETIF_F_RXALL)
5385 rx_mode |= (AcceptErr | AcceptRunt);
5387 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5389 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5390 u32 data = mc_filter[0];
5392 mc_filter[0] = swab32(mc_filter[1]);
5393 mc_filter[1] = swab32(data);
5396 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5397 mc_filter[1] = mc_filter[0] = 0xffffffff;
5399 RTL_W32(MAR0 + 4, mc_filter[1]);
5400 RTL_W32(MAR0 + 0, mc_filter[0]);
5402 RTL_W32(RxConfig, tmp);
5405 static void rtl_hw_start_8169(struct net_device *dev)
5407 struct rtl8169_private *tp = netdev_priv(dev);
5408 void __iomem *ioaddr = tp->mmio_addr;
5409 struct pci_dev *pdev = tp->pci_dev;
5411 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5412 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5413 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5416 RTL_W8(Cfg9346, Cfg9346_Unlock);
5417 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5418 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5419 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5420 tp->mac_version == RTL_GIGA_MAC_VER_04)
5421 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5425 RTL_W8(EarlyTxThres, NoEarlyTx);
5427 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5429 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5430 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5431 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5432 tp->mac_version == RTL_GIGA_MAC_VER_04)
5433 rtl_set_rx_tx_config_registers(tp);
5435 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5437 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5438 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5439 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5440 "Bit-3 and bit-14 MUST be 1\n");
5441 tp->cp_cmd |= (1 << 14);
5444 RTL_W16(CPlusCmd, tp->cp_cmd);
5446 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5449 * Undocumented corner. Supposedly:
5450 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5452 RTL_W16(IntrMitigate, 0x0000);
5454 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5456 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5457 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5458 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5459 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5460 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5461 rtl_set_rx_tx_config_registers(tp);
5464 RTL_W8(Cfg9346, Cfg9346_Lock);
5466 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5469 RTL_W32(RxMissed, 0);
5471 rtl_set_rx_mode(dev);
5473 /* no early-rx interrupts */
5474 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5477 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5479 if (tp->csi_ops.write)
5480 tp->csi_ops.write(tp, addr, value);
5483 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5485 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5488 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5492 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5493 rtl_csi_write(tp, 0x070c, csi | bits);
5496 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5498 rtl_csi_access_enable(tp, 0x17000000);
5501 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5503 rtl_csi_access_enable(tp, 0x27000000);
5506 DECLARE_RTL_COND(rtl_csiar_cond)
5508 void __iomem *ioaddr = tp->mmio_addr;
5510 return RTL_R32(CSIAR) & CSIAR_FLAG;
5513 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5515 void __iomem *ioaddr = tp->mmio_addr;
5517 RTL_W32(CSIDR, value);
5518 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5519 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5521 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5524 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5526 void __iomem *ioaddr = tp->mmio_addr;
5528 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5529 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5531 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5532 RTL_R32(CSIDR) : ~0;
5535 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5537 void __iomem *ioaddr = tp->mmio_addr;
5539 RTL_W32(CSIDR, value);
5540 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5541 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5544 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5547 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5549 void __iomem *ioaddr = tp->mmio_addr;
5551 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5552 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5554 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5555 RTL_R32(CSIDR) : ~0;
5558 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5560 void __iomem *ioaddr = tp->mmio_addr;
5562 RTL_W32(CSIDR, value);
5563 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5564 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5567 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5570 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5572 void __iomem *ioaddr = tp->mmio_addr;
5574 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5575 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5577 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5578 RTL_R32(CSIDR) : ~0;
5581 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5583 struct csi_ops *ops = &tp->csi_ops;
5585 switch (tp->mac_version) {
5586 case RTL_GIGA_MAC_VER_01:
5587 case RTL_GIGA_MAC_VER_02:
5588 case RTL_GIGA_MAC_VER_03:
5589 case RTL_GIGA_MAC_VER_04:
5590 case RTL_GIGA_MAC_VER_05:
5591 case RTL_GIGA_MAC_VER_06:
5592 case RTL_GIGA_MAC_VER_10:
5593 case RTL_GIGA_MAC_VER_11:
5594 case RTL_GIGA_MAC_VER_12:
5595 case RTL_GIGA_MAC_VER_13:
5596 case RTL_GIGA_MAC_VER_14:
5597 case RTL_GIGA_MAC_VER_15:
5598 case RTL_GIGA_MAC_VER_16:
5599 case RTL_GIGA_MAC_VER_17:
5604 case RTL_GIGA_MAC_VER_37:
5605 case RTL_GIGA_MAC_VER_38:
5606 ops->write = r8402_csi_write;
5607 ops->read = r8402_csi_read;
5610 case RTL_GIGA_MAC_VER_44:
5611 ops->write = r8411_csi_write;
5612 ops->read = r8411_csi_read;
5616 ops->write = r8169_csi_write;
5617 ops->read = r8169_csi_read;
5623 unsigned int offset;
5628 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5634 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5635 rtl_ephy_write(tp, e->offset, w);
5640 static void rtl_disable_clock_request(struct pci_dev *pdev)
5642 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5643 PCI_EXP_LNKCTL_CLKREQ_EN);
5646 static void rtl_enable_clock_request(struct pci_dev *pdev)
5648 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5649 PCI_EXP_LNKCTL_CLKREQ_EN);
5652 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5654 void __iomem *ioaddr = tp->mmio_addr;
5657 data = RTL_R8(Config3);
5662 data &= ~Rdy_to_L23;
5664 RTL_W8(Config3, data);
5667 #define R8168_CPCMD_QUIRK_MASK (\
5678 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5680 void __iomem *ioaddr = tp->mmio_addr;
5681 struct pci_dev *pdev = tp->pci_dev;
5683 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5685 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5687 if (tp->dev->mtu <= ETH_DATA_LEN) {
5688 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5689 PCI_EXP_DEVCTL_NOSNOOP_EN);
5693 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5695 void __iomem *ioaddr = tp->mmio_addr;
5697 rtl_hw_start_8168bb(tp);
5699 RTL_W8(MaxTxPacketSize, TxPacketMax);
5701 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5704 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5706 void __iomem *ioaddr = tp->mmio_addr;
5707 struct pci_dev *pdev = tp->pci_dev;
5709 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5711 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5713 if (tp->dev->mtu <= ETH_DATA_LEN)
5714 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5716 rtl_disable_clock_request(pdev);
5718 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5721 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5723 static const struct ephy_info e_info_8168cp[] = {
5724 { 0x01, 0, 0x0001 },
5725 { 0x02, 0x0800, 0x1000 },
5726 { 0x03, 0, 0x0042 },
5727 { 0x06, 0x0080, 0x0000 },
5731 rtl_csi_access_enable_2(tp);
5733 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5735 __rtl_hw_start_8168cp(tp);
5738 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5740 void __iomem *ioaddr = tp->mmio_addr;
5741 struct pci_dev *pdev = tp->pci_dev;
5743 rtl_csi_access_enable_2(tp);
5745 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5747 if (tp->dev->mtu <= ETH_DATA_LEN)
5748 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5750 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5753 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5755 void __iomem *ioaddr = tp->mmio_addr;
5756 struct pci_dev *pdev = tp->pci_dev;
5758 rtl_csi_access_enable_2(tp);
5760 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5763 RTL_W8(DBG_REG, 0x20);
5765 RTL_W8(MaxTxPacketSize, TxPacketMax);
5767 if (tp->dev->mtu <= ETH_DATA_LEN)
5768 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5770 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5773 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5775 void __iomem *ioaddr = tp->mmio_addr;
5776 static const struct ephy_info e_info_8168c_1[] = {
5777 { 0x02, 0x0800, 0x1000 },
5778 { 0x03, 0, 0x0002 },
5779 { 0x06, 0x0080, 0x0000 }
5782 rtl_csi_access_enable_2(tp);
5784 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5786 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5788 __rtl_hw_start_8168cp(tp);
5791 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5793 static const struct ephy_info e_info_8168c_2[] = {
5794 { 0x01, 0, 0x0001 },
5795 { 0x03, 0x0400, 0x0220 }
5798 rtl_csi_access_enable_2(tp);
5800 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5802 __rtl_hw_start_8168cp(tp);
5805 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5807 rtl_hw_start_8168c_2(tp);
5810 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5812 rtl_csi_access_enable_2(tp);
5814 __rtl_hw_start_8168cp(tp);
5817 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5819 void __iomem *ioaddr = tp->mmio_addr;
5820 struct pci_dev *pdev = tp->pci_dev;
5822 rtl_csi_access_enable_2(tp);
5824 rtl_disable_clock_request(pdev);
5826 RTL_W8(MaxTxPacketSize, TxPacketMax);
5828 if (tp->dev->mtu <= ETH_DATA_LEN)
5829 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5831 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5834 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5836 void __iomem *ioaddr = tp->mmio_addr;
5837 struct pci_dev *pdev = tp->pci_dev;
5839 rtl_csi_access_enable_1(tp);
5841 if (tp->dev->mtu <= ETH_DATA_LEN)
5842 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5844 RTL_W8(MaxTxPacketSize, TxPacketMax);
5846 rtl_disable_clock_request(pdev);
5849 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5851 void __iomem *ioaddr = tp->mmio_addr;
5852 struct pci_dev *pdev = tp->pci_dev;
5853 static const struct ephy_info e_info_8168d_4[] = {
5854 { 0x0b, 0x0000, 0x0048 },
5855 { 0x19, 0x0020, 0x0050 },
5856 { 0x0c, 0x0100, 0x0020 }
5859 rtl_csi_access_enable_1(tp);
5861 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5863 RTL_W8(MaxTxPacketSize, TxPacketMax);
5865 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5867 rtl_enable_clock_request(pdev);
5870 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5872 void __iomem *ioaddr = tp->mmio_addr;
5873 struct pci_dev *pdev = tp->pci_dev;
5874 static const struct ephy_info e_info_8168e_1[] = {
5875 { 0x00, 0x0200, 0x0100 },
5876 { 0x00, 0x0000, 0x0004 },
5877 { 0x06, 0x0002, 0x0001 },
5878 { 0x06, 0x0000, 0x0030 },
5879 { 0x07, 0x0000, 0x2000 },
5880 { 0x00, 0x0000, 0x0020 },
5881 { 0x03, 0x5800, 0x2000 },
5882 { 0x03, 0x0000, 0x0001 },
5883 { 0x01, 0x0800, 0x1000 },
5884 { 0x07, 0x0000, 0x4000 },
5885 { 0x1e, 0x0000, 0x2000 },
5886 { 0x19, 0xffff, 0xfe6c },
5887 { 0x0a, 0x0000, 0x0040 }
5890 rtl_csi_access_enable_2(tp);
5892 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5894 if (tp->dev->mtu <= ETH_DATA_LEN)
5895 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5897 RTL_W8(MaxTxPacketSize, TxPacketMax);
5899 rtl_disable_clock_request(pdev);
5901 /* Reset tx FIFO pointer */
5902 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5903 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5905 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5908 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5910 void __iomem *ioaddr = tp->mmio_addr;
5911 struct pci_dev *pdev = tp->pci_dev;
5912 static const struct ephy_info e_info_8168e_2[] = {
5913 { 0x09, 0x0000, 0x0080 },
5914 { 0x19, 0x0000, 0x0224 }
5917 rtl_csi_access_enable_1(tp);
5919 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5921 if (tp->dev->mtu <= ETH_DATA_LEN)
5922 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5927 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5928 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5929 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5930 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5931 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5933 RTL_W8(MaxTxPacketSize, EarlySize);
5935 rtl_disable_clock_request(pdev);
5937 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5938 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5940 /* Adjust EEE LED frequency */
5941 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5943 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5944 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5945 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5948 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5950 void __iomem *ioaddr = tp->mmio_addr;
5951 struct pci_dev *pdev = tp->pci_dev;
5953 rtl_csi_access_enable_2(tp);
5955 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5957 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5958 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5959 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5960 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5961 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5962 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5963 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5964 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5965 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5966 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5968 RTL_W8(MaxTxPacketSize, EarlySize);
5970 rtl_disable_clock_request(pdev);
5972 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5973 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5974 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5975 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5976 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5979 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5981 void __iomem *ioaddr = tp->mmio_addr;
5982 static const struct ephy_info e_info_8168f_1[] = {
5983 { 0x06, 0x00c0, 0x0020 },
5984 { 0x08, 0x0001, 0x0002 },
5985 { 0x09, 0x0000, 0x0080 },
5986 { 0x19, 0x0000, 0x0224 }
5989 rtl_hw_start_8168f(tp);
5991 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5993 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5995 /* Adjust EEE LED frequency */
5996 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5999 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6001 static const struct ephy_info e_info_8168f_1[] = {
6002 { 0x06, 0x00c0, 0x0020 },
6003 { 0x0f, 0xffff, 0x5200 },
6004 { 0x1e, 0x0000, 0x4000 },
6005 { 0x19, 0x0000, 0x0224 }
6008 rtl_hw_start_8168f(tp);
6009 rtl_pcie_state_l2l3_enable(tp, false);
6011 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6013 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6016 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6018 void __iomem *ioaddr = tp->mmio_addr;
6019 struct pci_dev *pdev = tp->pci_dev;
6021 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6023 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6024 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6025 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6026 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6028 rtl_csi_access_enable_1(tp);
6030 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6032 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6033 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6034 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6036 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6037 RTL_W8(MaxTxPacketSize, EarlySize);
6039 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6040 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6042 /* Adjust EEE LED frequency */
6043 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6045 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6046 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6048 rtl_pcie_state_l2l3_enable(tp, false);
6051 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6053 void __iomem *ioaddr = tp->mmio_addr;
6054 static const struct ephy_info e_info_8168g_1[] = {
6055 { 0x00, 0x0000, 0x0008 },
6056 { 0x0c, 0x37d0, 0x0820 },
6057 { 0x1e, 0x0000, 0x0001 },
6058 { 0x19, 0x8000, 0x0000 }
6061 rtl_hw_start_8168g(tp);
6063 /* disable aspm and clock request before access ephy */
6064 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6065 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6066 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6069 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6071 void __iomem *ioaddr = tp->mmio_addr;
6072 static const struct ephy_info e_info_8168g_2[] = {
6073 { 0x00, 0x0000, 0x0008 },
6074 { 0x0c, 0x3df0, 0x0200 },
6075 { 0x19, 0xffff, 0xfc00 },
6076 { 0x1e, 0xffff, 0x20eb }
6079 rtl_hw_start_8168g(tp);
6081 /* disable aspm and clock request before access ephy */
6082 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6083 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6084 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6087 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6089 void __iomem *ioaddr = tp->mmio_addr;
6090 static const struct ephy_info e_info_8411_2[] = {
6091 { 0x00, 0x0000, 0x0008 },
6092 { 0x0c, 0x3df0, 0x0200 },
6093 { 0x0f, 0xffff, 0x5200 },
6094 { 0x19, 0x0020, 0x0000 },
6095 { 0x1e, 0x0000, 0x2000 }
6098 rtl_hw_start_8168g(tp);
6100 /* disable aspm and clock request before access ephy */
6101 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6102 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6103 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6106 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6108 void __iomem *ioaddr = tp->mmio_addr;
6109 struct pci_dev *pdev = tp->pci_dev;
6112 static const struct ephy_info e_info_8168h_1[] = {
6113 { 0x1e, 0x0800, 0x0001 },
6114 { 0x1d, 0x0000, 0x0800 },
6115 { 0x05, 0xffff, 0x2089 },
6116 { 0x06, 0xffff, 0x5881 },
6117 { 0x04, 0xffff, 0x154a },
6118 { 0x01, 0xffff, 0x068b }
6121 /* disable aspm and clock request before access ephy */
6122 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6123 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6124 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6126 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6128 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6129 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6130 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6131 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6133 rtl_csi_access_enable_1(tp);
6135 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6137 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6138 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6140 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6142 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6144 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6146 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6147 RTL_W8(MaxTxPacketSize, EarlySize);
6149 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6150 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6152 /* Adjust EEE LED frequency */
6153 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6155 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6156 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6158 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6160 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6162 rtl_pcie_state_l2l3_enable(tp, false);
6164 rtl_writephy(tp, 0x1f, 0x0c42);
6165 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6166 rtl_writephy(tp, 0x1f, 0x0000);
6167 if (rg_saw_cnt > 0) {
6170 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6171 sw_cnt_1ms_ini &= 0x0fff;
6172 data = r8168_mac_ocp_read(tp, 0xd412);
6174 data |= sw_cnt_1ms_ini;
6175 r8168_mac_ocp_write(tp, 0xd412, data);
6178 data = r8168_mac_ocp_read(tp, 0xe056);
6181 r8168_mac_ocp_write(tp, 0xe056, data);
6183 data = r8168_mac_ocp_read(tp, 0xe052);
6186 r8168_mac_ocp_write(tp, 0xe052, data);
6188 data = r8168_mac_ocp_read(tp, 0xe0d6);
6191 r8168_mac_ocp_write(tp, 0xe0d6, data);
6193 data = r8168_mac_ocp_read(tp, 0xd420);
6196 r8168_mac_ocp_write(tp, 0xd420, data);
6198 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6199 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6200 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6201 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6204 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6206 void __iomem *ioaddr = tp->mmio_addr;
6207 struct pci_dev *pdev = tp->pci_dev;
6209 rtl8168ep_stop_cmac(tp);
6211 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6213 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6214 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6215 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6216 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6218 rtl_csi_access_enable_1(tp);
6220 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6222 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6223 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6225 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6227 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6229 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6230 RTL_W8(MaxTxPacketSize, EarlySize);
6232 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6233 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6235 /* Adjust EEE LED frequency */
6236 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6238 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6240 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6242 rtl_pcie_state_l2l3_enable(tp, false);
6245 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6247 void __iomem *ioaddr = tp->mmio_addr;
6248 static const struct ephy_info e_info_8168ep_1[] = {
6249 { 0x00, 0xffff, 0x10ab },
6250 { 0x06, 0xffff, 0xf030 },
6251 { 0x08, 0xffff, 0x2006 },
6252 { 0x0d, 0xffff, 0x1666 },
6253 { 0x0c, 0x3ff0, 0x0000 }
6256 /* disable aspm and clock request before access ephy */
6257 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6258 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6259 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6261 rtl_hw_start_8168ep(tp);
6264 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6266 void __iomem *ioaddr = tp->mmio_addr;
6267 static const struct ephy_info e_info_8168ep_2[] = {
6268 { 0x00, 0xffff, 0x10a3 },
6269 { 0x19, 0xffff, 0xfc00 },
6270 { 0x1e, 0xffff, 0x20ea }
6273 /* disable aspm and clock request before access ephy */
6274 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6275 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6276 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6278 rtl_hw_start_8168ep(tp);
6280 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6281 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6284 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6286 void __iomem *ioaddr = tp->mmio_addr;
6288 static const struct ephy_info e_info_8168ep_3[] = {
6289 { 0x00, 0xffff, 0x10a3 },
6290 { 0x19, 0xffff, 0x7c00 },
6291 { 0x1e, 0xffff, 0x20eb },
6292 { 0x0d, 0xffff, 0x1666 }
6295 /* disable aspm and clock request before access ephy */
6296 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6297 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6298 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6300 rtl_hw_start_8168ep(tp);
6302 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6303 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6305 data = r8168_mac_ocp_read(tp, 0xd3e2);
6308 r8168_mac_ocp_write(tp, 0xd3e2, data);
6310 data = r8168_mac_ocp_read(tp, 0xd3e4);
6312 r8168_mac_ocp_write(tp, 0xd3e4, data);
6314 data = r8168_mac_ocp_read(tp, 0xe860);
6316 r8168_mac_ocp_write(tp, 0xe860, data);
6319 static void rtl_hw_start_8168(struct net_device *dev)
6321 struct rtl8169_private *tp = netdev_priv(dev);
6322 void __iomem *ioaddr = tp->mmio_addr;
6324 RTL_W8(Cfg9346, Cfg9346_Unlock);
6326 RTL_W8(MaxTxPacketSize, TxPacketMax);
6328 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6330 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6332 RTL_W16(CPlusCmd, tp->cp_cmd);
6334 RTL_W16(IntrMitigate, 0x5151);
6336 /* Work around for RxFIFO overflow. */
6337 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6338 tp->event_slow |= RxFIFOOver | PCSTimeout;
6339 tp->event_slow &= ~RxOverflow;
6342 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6344 rtl_set_rx_tx_config_registers(tp);
6348 switch (tp->mac_version) {
6349 case RTL_GIGA_MAC_VER_11:
6350 rtl_hw_start_8168bb(tp);
6353 case RTL_GIGA_MAC_VER_12:
6354 case RTL_GIGA_MAC_VER_17:
6355 rtl_hw_start_8168bef(tp);
6358 case RTL_GIGA_MAC_VER_18:
6359 rtl_hw_start_8168cp_1(tp);
6362 case RTL_GIGA_MAC_VER_19:
6363 rtl_hw_start_8168c_1(tp);
6366 case RTL_GIGA_MAC_VER_20:
6367 rtl_hw_start_8168c_2(tp);
6370 case RTL_GIGA_MAC_VER_21:
6371 rtl_hw_start_8168c_3(tp);
6374 case RTL_GIGA_MAC_VER_22:
6375 rtl_hw_start_8168c_4(tp);
6378 case RTL_GIGA_MAC_VER_23:
6379 rtl_hw_start_8168cp_2(tp);
6382 case RTL_GIGA_MAC_VER_24:
6383 rtl_hw_start_8168cp_3(tp);
6386 case RTL_GIGA_MAC_VER_25:
6387 case RTL_GIGA_MAC_VER_26:
6388 case RTL_GIGA_MAC_VER_27:
6389 rtl_hw_start_8168d(tp);
6392 case RTL_GIGA_MAC_VER_28:
6393 rtl_hw_start_8168d_4(tp);
6396 case RTL_GIGA_MAC_VER_31:
6397 rtl_hw_start_8168dp(tp);
6400 case RTL_GIGA_MAC_VER_32:
6401 case RTL_GIGA_MAC_VER_33:
6402 rtl_hw_start_8168e_1(tp);
6404 case RTL_GIGA_MAC_VER_34:
6405 rtl_hw_start_8168e_2(tp);
6408 case RTL_GIGA_MAC_VER_35:
6409 case RTL_GIGA_MAC_VER_36:
6410 rtl_hw_start_8168f_1(tp);
6413 case RTL_GIGA_MAC_VER_38:
6414 rtl_hw_start_8411(tp);
6417 case RTL_GIGA_MAC_VER_40:
6418 case RTL_GIGA_MAC_VER_41:
6419 rtl_hw_start_8168g_1(tp);
6421 case RTL_GIGA_MAC_VER_42:
6422 rtl_hw_start_8168g_2(tp);
6425 case RTL_GIGA_MAC_VER_44:
6426 rtl_hw_start_8411_2(tp);
6429 case RTL_GIGA_MAC_VER_45:
6430 case RTL_GIGA_MAC_VER_46:
6431 rtl_hw_start_8168h_1(tp);
6434 case RTL_GIGA_MAC_VER_49:
6435 rtl_hw_start_8168ep_1(tp);
6438 case RTL_GIGA_MAC_VER_50:
6439 rtl_hw_start_8168ep_2(tp);
6442 case RTL_GIGA_MAC_VER_51:
6443 rtl_hw_start_8168ep_3(tp);
6447 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6448 dev->name, tp->mac_version);
6452 RTL_W8(Cfg9346, Cfg9346_Lock);
6454 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6456 rtl_set_rx_mode(dev);
6458 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6461 #define R810X_CPCMD_QUIRK_MASK (\
6472 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6474 void __iomem *ioaddr = tp->mmio_addr;
6475 struct pci_dev *pdev = tp->pci_dev;
6476 static const struct ephy_info e_info_8102e_1[] = {
6477 { 0x01, 0, 0x6e65 },
6478 { 0x02, 0, 0x091f },
6479 { 0x03, 0, 0xc2f9 },
6480 { 0x06, 0, 0xafb5 },
6481 { 0x07, 0, 0x0e00 },
6482 { 0x19, 0, 0xec80 },
6483 { 0x01, 0, 0x2e65 },
6488 rtl_csi_access_enable_2(tp);
6490 RTL_W8(DBG_REG, FIX_NAK_1);
6492 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6495 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6496 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6498 cfg1 = RTL_R8(Config1);
6499 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6500 RTL_W8(Config1, cfg1 & ~LEDS0);
6502 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6505 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6507 void __iomem *ioaddr = tp->mmio_addr;
6508 struct pci_dev *pdev = tp->pci_dev;
6510 rtl_csi_access_enable_2(tp);
6512 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6514 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6515 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6518 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6520 rtl_hw_start_8102e_2(tp);
6522 rtl_ephy_write(tp, 0x03, 0xc2f9);
6525 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6527 void __iomem *ioaddr = tp->mmio_addr;
6528 static const struct ephy_info e_info_8105e_1[] = {
6529 { 0x07, 0, 0x4000 },
6530 { 0x19, 0, 0x0200 },
6531 { 0x19, 0, 0x0020 },
6532 { 0x1e, 0, 0x2000 },
6533 { 0x03, 0, 0x0001 },
6534 { 0x19, 0, 0x0100 },
6535 { 0x19, 0, 0x0004 },
6539 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6540 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6542 /* Disable Early Tally Counter */
6543 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6545 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6546 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6548 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6550 rtl_pcie_state_l2l3_enable(tp, false);
6553 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6555 rtl_hw_start_8105e_1(tp);
6556 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6559 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6561 void __iomem *ioaddr = tp->mmio_addr;
6562 static const struct ephy_info e_info_8402[] = {
6563 { 0x19, 0xffff, 0xff64 },
6567 rtl_csi_access_enable_2(tp);
6569 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6570 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6572 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6573 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6575 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6577 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6579 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6580 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6581 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6582 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6583 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6584 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6585 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6587 rtl_pcie_state_l2l3_enable(tp, false);
6590 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6592 void __iomem *ioaddr = tp->mmio_addr;
6594 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6595 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6597 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6598 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6599 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6601 rtl_pcie_state_l2l3_enable(tp, false);
6604 static void rtl_hw_start_8101(struct net_device *dev)
6606 struct rtl8169_private *tp = netdev_priv(dev);
6607 void __iomem *ioaddr = tp->mmio_addr;
6608 struct pci_dev *pdev = tp->pci_dev;
6610 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6611 tp->event_slow &= ~RxFIFOOver;
6613 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6614 tp->mac_version == RTL_GIGA_MAC_VER_16)
6615 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6616 PCI_EXP_DEVCTL_NOSNOOP_EN);
6618 RTL_W8(Cfg9346, Cfg9346_Unlock);
6620 RTL_W8(MaxTxPacketSize, TxPacketMax);
6622 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6624 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6625 RTL_W16(CPlusCmd, tp->cp_cmd);
6627 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6629 rtl_set_rx_tx_config_registers(tp);
6631 switch (tp->mac_version) {
6632 case RTL_GIGA_MAC_VER_07:
6633 rtl_hw_start_8102e_1(tp);
6636 case RTL_GIGA_MAC_VER_08:
6637 rtl_hw_start_8102e_3(tp);
6640 case RTL_GIGA_MAC_VER_09:
6641 rtl_hw_start_8102e_2(tp);
6644 case RTL_GIGA_MAC_VER_29:
6645 rtl_hw_start_8105e_1(tp);
6647 case RTL_GIGA_MAC_VER_30:
6648 rtl_hw_start_8105e_2(tp);
6651 case RTL_GIGA_MAC_VER_37:
6652 rtl_hw_start_8402(tp);
6655 case RTL_GIGA_MAC_VER_39:
6656 rtl_hw_start_8106(tp);
6658 case RTL_GIGA_MAC_VER_43:
6659 rtl_hw_start_8168g_2(tp);
6661 case RTL_GIGA_MAC_VER_47:
6662 case RTL_GIGA_MAC_VER_48:
6663 rtl_hw_start_8168h_1(tp);
6667 RTL_W8(Cfg9346, Cfg9346_Lock);
6669 RTL_W16(IntrMitigate, 0x0000);
6671 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6673 rtl_set_rx_mode(dev);
6677 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6680 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6682 struct rtl8169_private *tp = netdev_priv(dev);
6684 if (new_mtu > ETH_DATA_LEN)
6685 rtl_hw_jumbo_enable(tp);
6687 rtl_hw_jumbo_disable(tp);
6690 netdev_update_features(dev);
6695 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6697 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6698 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6701 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6702 void **data_buff, struct RxDesc *desc)
6704 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6709 rtl8169_make_unusable_by_asic(desc);
6712 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6714 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6716 /* Force memory writes to complete before releasing descriptor */
6719 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6722 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6725 desc->addr = cpu_to_le64(mapping);
6726 rtl8169_mark_to_asic(desc, rx_buf_sz);
6729 static inline void *rtl8169_align(void *data)
6731 return (void *)ALIGN((long)data, 16);
6734 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6735 struct RxDesc *desc)
6739 struct device *d = &tp->pci_dev->dev;
6740 struct net_device *dev = tp->dev;
6741 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6743 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6747 if (rtl8169_align(data) != data) {
6749 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6754 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6756 if (unlikely(dma_mapping_error(d, mapping))) {
6757 if (net_ratelimit())
6758 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6762 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6770 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6774 for (i = 0; i < NUM_RX_DESC; i++) {
6775 if (tp->Rx_databuff[i]) {
6776 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6777 tp->RxDescArray + i);
6782 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6784 desc->opts1 |= cpu_to_le32(RingEnd);
6787 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6791 for (i = 0; i < NUM_RX_DESC; i++) {
6794 if (tp->Rx_databuff[i])
6797 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6799 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6802 tp->Rx_databuff[i] = data;
6805 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6809 rtl8169_rx_clear(tp);
6813 static int rtl8169_init_ring(struct net_device *dev)
6815 struct rtl8169_private *tp = netdev_priv(dev);
6817 rtl8169_init_ring_indexes(tp);
6819 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6820 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6822 return rtl8169_rx_fill(tp);
6825 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6826 struct TxDesc *desc)
6828 unsigned int len = tx_skb->len;
6830 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6838 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6843 for (i = 0; i < n; i++) {
6844 unsigned int entry = (start + i) % NUM_TX_DESC;
6845 struct ring_info *tx_skb = tp->tx_skb + entry;
6846 unsigned int len = tx_skb->len;
6849 struct sk_buff *skb = tx_skb->skb;
6851 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6852 tp->TxDescArray + entry);
6854 tp->dev->stats.tx_dropped++;
6855 dev_kfree_skb_any(skb);
6862 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6864 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6865 tp->cur_tx = tp->dirty_tx = 0;
6868 static void rtl_reset_work(struct rtl8169_private *tp)
6870 struct net_device *dev = tp->dev;
6873 napi_disable(&tp->napi);
6874 netif_stop_queue(dev);
6875 synchronize_sched();
6877 rtl8169_hw_reset(tp);
6879 for (i = 0; i < NUM_RX_DESC; i++)
6880 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6882 rtl8169_tx_clear(tp);
6883 rtl8169_init_ring_indexes(tp);
6885 napi_enable(&tp->napi);
6887 netif_wake_queue(dev);
6888 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6891 static void rtl8169_tx_timeout(struct net_device *dev)
6893 struct rtl8169_private *tp = netdev_priv(dev);
6895 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6898 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6901 struct skb_shared_info *info = skb_shinfo(skb);
6902 unsigned int cur_frag, entry;
6903 struct TxDesc *uninitialized_var(txd);
6904 struct device *d = &tp->pci_dev->dev;
6907 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6908 const skb_frag_t *frag = info->frags + cur_frag;
6913 entry = (entry + 1) % NUM_TX_DESC;
6915 txd = tp->TxDescArray + entry;
6916 len = skb_frag_size(frag);
6917 addr = skb_frag_address(frag);
6918 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6919 if (unlikely(dma_mapping_error(d, mapping))) {
6920 if (net_ratelimit())
6921 netif_err(tp, drv, tp->dev,
6922 "Failed to map TX fragments DMA!\n");
6926 /* Anti gcc 2.95.3 bugware (sic) */
6927 status = opts[0] | len |
6928 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6930 txd->opts1 = cpu_to_le32(status);
6931 txd->opts2 = cpu_to_le32(opts[1]);
6932 txd->addr = cpu_to_le64(mapping);
6934 tp->tx_skb[entry].len = len;
6938 tp->tx_skb[entry].skb = skb;
6939 txd->opts1 |= cpu_to_le32(LastFrag);
6945 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6949 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6951 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6954 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6955 struct net_device *dev);
6956 /* r8169_csum_workaround()
6957 * The hw limites the value the transport offset. When the offset is out of the
6958 * range, calculate the checksum by sw.
6960 static void r8169_csum_workaround(struct rtl8169_private *tp,
6961 struct sk_buff *skb)
6963 if (skb_shinfo(skb)->gso_size) {
6964 netdev_features_t features = tp->dev->features;
6965 struct sk_buff *segs, *nskb;
6967 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6968 segs = skb_gso_segment(skb, features);
6969 if (IS_ERR(segs) || !segs)
6976 rtl8169_start_xmit(nskb, tp->dev);
6979 dev_consume_skb_any(skb);
6980 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6981 if (skb_checksum_help(skb) < 0)
6984 rtl8169_start_xmit(skb, tp->dev);
6986 struct net_device_stats *stats;
6989 stats = &tp->dev->stats;
6990 stats->tx_dropped++;
6991 dev_kfree_skb_any(skb);
6995 /* msdn_giant_send_check()
6996 * According to the document of microsoft, the TCP Pseudo Header excludes the
6997 * packet length for IPv6 TCP large packets.
6999 static int msdn_giant_send_check(struct sk_buff *skb)
7001 const struct ipv6hdr *ipv6h;
7005 ret = skb_cow_head(skb, 0);
7009 ipv6h = ipv6_hdr(skb);
7013 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7018 static inline __be16 get_protocol(struct sk_buff *skb)
7022 if (skb->protocol == htons(ETH_P_8021Q))
7023 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7025 protocol = skb->protocol;
7030 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7031 struct sk_buff *skb, u32 *opts)
7033 u32 mss = skb_shinfo(skb)->gso_size;
7037 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7038 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7039 const struct iphdr *ip = ip_hdr(skb);
7041 if (ip->protocol == IPPROTO_TCP)
7042 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7043 else if (ip->protocol == IPPROTO_UDP)
7044 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7052 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7053 struct sk_buff *skb, u32 *opts)
7055 u32 transport_offset = (u32)skb_transport_offset(skb);
7056 u32 mss = skb_shinfo(skb)->gso_size;
7059 if (transport_offset > GTTCPHO_MAX) {
7060 netif_warn(tp, tx_err, tp->dev,
7061 "Invalid transport offset 0x%x for TSO\n",
7066 switch (get_protocol(skb)) {
7067 case htons(ETH_P_IP):
7068 opts[0] |= TD1_GTSENV4;
7071 case htons(ETH_P_IPV6):
7072 if (msdn_giant_send_check(skb))
7075 opts[0] |= TD1_GTSENV6;
7083 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7084 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7085 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7088 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7089 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7091 if (transport_offset > TCPHO_MAX) {
7092 netif_warn(tp, tx_err, tp->dev,
7093 "Invalid transport offset 0x%x\n",
7098 switch (get_protocol(skb)) {
7099 case htons(ETH_P_IP):
7100 opts[1] |= TD1_IPv4_CS;
7101 ip_protocol = ip_hdr(skb)->protocol;
7104 case htons(ETH_P_IPV6):
7105 opts[1] |= TD1_IPv6_CS;
7106 ip_protocol = ipv6_hdr(skb)->nexthdr;
7110 ip_protocol = IPPROTO_RAW;
7114 if (ip_protocol == IPPROTO_TCP)
7115 opts[1] |= TD1_TCP_CS;
7116 else if (ip_protocol == IPPROTO_UDP)
7117 opts[1] |= TD1_UDP_CS;
7121 opts[1] |= transport_offset << TCPHO_SHIFT;
7123 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7124 return !eth_skb_pad(skb);
7130 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7131 struct net_device *dev)
7133 struct rtl8169_private *tp = netdev_priv(dev);
7134 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7135 struct TxDesc *txd = tp->TxDescArray + entry;
7136 void __iomem *ioaddr = tp->mmio_addr;
7137 struct device *d = &tp->pci_dev->dev;
7143 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7144 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7148 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7151 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7154 if (!tp->tso_csum(tp, skb, opts)) {
7155 r8169_csum_workaround(tp, skb);
7156 return NETDEV_TX_OK;
7159 len = skb_headlen(skb);
7160 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7161 if (unlikely(dma_mapping_error(d, mapping))) {
7162 if (net_ratelimit())
7163 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7167 tp->tx_skb[entry].len = len;
7168 txd->addr = cpu_to_le64(mapping);
7170 frags = rtl8169_xmit_frags(tp, skb, opts);
7174 opts[0] |= FirstFrag;
7176 opts[0] |= FirstFrag | LastFrag;
7177 tp->tx_skb[entry].skb = skb;
7180 txd->opts2 = cpu_to_le32(opts[1]);
7182 skb_tx_timestamp(skb);
7184 /* Force memory writes to complete before releasing descriptor */
7187 /* Anti gcc 2.95.3 bugware (sic) */
7188 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7189 txd->opts1 = cpu_to_le32(status);
7191 /* Force all memory writes to complete before notifying device */
7194 tp->cur_tx += frags + 1;
7196 RTL_W8(TxPoll, NPQ);
7200 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7201 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7202 * not miss a ring update when it notices a stopped queue.
7205 netif_stop_queue(dev);
7206 /* Sync with rtl_tx:
7207 * - publish queue status and cur_tx ring index (write barrier)
7208 * - refresh dirty_tx ring index (read barrier).
7209 * May the current thread have a pessimistic view of the ring
7210 * status and forget to wake up queue, a racing rtl_tx thread
7214 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7215 netif_wake_queue(dev);
7218 return NETDEV_TX_OK;
7221 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7223 dev_kfree_skb_any(skb);
7224 dev->stats.tx_dropped++;
7225 return NETDEV_TX_OK;
7228 netif_stop_queue(dev);
7229 dev->stats.tx_dropped++;
7230 return NETDEV_TX_BUSY;
7233 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7235 struct rtl8169_private *tp = netdev_priv(dev);
7236 struct pci_dev *pdev = tp->pci_dev;
7237 u16 pci_status, pci_cmd;
7239 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7240 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7242 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7243 pci_cmd, pci_status);
7246 * The recovery sequence below admits a very elaborated explanation:
7247 * - it seems to work;
7248 * - I did not see what else could be done;
7249 * - it makes iop3xx happy.
7251 * Feel free to adjust to your needs.
7253 if (pdev->broken_parity_status)
7254 pci_cmd &= ~PCI_COMMAND_PARITY;
7256 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7258 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7260 pci_write_config_word(pdev, PCI_STATUS,
7261 pci_status & (PCI_STATUS_DETECTED_PARITY |
7262 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7263 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7265 /* The infamous DAC f*ckup only happens at boot time */
7266 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7267 void __iomem *ioaddr = tp->mmio_addr;
7269 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7270 tp->cp_cmd &= ~PCIDAC;
7271 RTL_W16(CPlusCmd, tp->cp_cmd);
7272 dev->features &= ~NETIF_F_HIGHDMA;
7275 rtl8169_hw_reset(tp);
7277 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7280 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7282 unsigned int dirty_tx, tx_left;
7284 dirty_tx = tp->dirty_tx;
7286 tx_left = tp->cur_tx - dirty_tx;
7288 while (tx_left > 0) {
7289 unsigned int entry = dirty_tx % NUM_TX_DESC;
7290 struct ring_info *tx_skb = tp->tx_skb + entry;
7293 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7294 if (status & DescOwn)
7297 /* This barrier is needed to keep us from reading
7298 * any other fields out of the Tx descriptor until
7299 * we know the status of DescOwn
7303 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7304 tp->TxDescArray + entry);
7305 if (status & LastFrag) {
7306 u64_stats_update_begin(&tp->tx_stats.syncp);
7307 tp->tx_stats.packets++;
7308 tp->tx_stats.bytes += tx_skb->skb->len;
7309 u64_stats_update_end(&tp->tx_stats.syncp);
7310 dev_kfree_skb_any(tx_skb->skb);
7317 if (tp->dirty_tx != dirty_tx) {
7318 tp->dirty_tx = dirty_tx;
7319 /* Sync with rtl8169_start_xmit:
7320 * - publish dirty_tx ring index (write barrier)
7321 * - refresh cur_tx ring index and queue status (read barrier)
7322 * May the current thread miss the stopped queue condition,
7323 * a racing xmit thread can only have a right view of the
7327 if (netif_queue_stopped(dev) &&
7328 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7329 netif_wake_queue(dev);
7332 * 8168 hack: TxPoll requests are lost when the Tx packets are
7333 * too close. Let's kick an extra TxPoll request when a burst
7334 * of start_xmit activity is detected (if it is not detected,
7335 * it is slow enough). -- FR
7337 if (tp->cur_tx != dirty_tx) {
7338 void __iomem *ioaddr = tp->mmio_addr;
7340 RTL_W8(TxPoll, NPQ);
7345 static inline int rtl8169_fragmented_frame(u32 status)
7347 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7350 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7352 u32 status = opts1 & RxProtoMask;
7354 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7355 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7356 skb->ip_summed = CHECKSUM_UNNECESSARY;
7358 skb_checksum_none_assert(skb);
7361 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7362 struct rtl8169_private *tp,
7366 struct sk_buff *skb;
7367 struct device *d = &tp->pci_dev->dev;
7369 data = rtl8169_align(data);
7370 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7372 skb = napi_alloc_skb(&tp->napi, pkt_size);
7374 memcpy(skb->data, data, pkt_size);
7375 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7380 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7382 unsigned int cur_rx, rx_left;
7385 cur_rx = tp->cur_rx;
7387 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7388 unsigned int entry = cur_rx % NUM_RX_DESC;
7389 struct RxDesc *desc = tp->RxDescArray + entry;
7392 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7393 if (status & DescOwn)
7396 /* This barrier is needed to keep us from reading
7397 * any other fields out of the Rx descriptor until
7398 * we know the status of DescOwn
7402 if (unlikely(status & RxRES)) {
7403 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7405 dev->stats.rx_errors++;
7406 if (status & (RxRWT | RxRUNT))
7407 dev->stats.rx_length_errors++;
7409 dev->stats.rx_crc_errors++;
7410 if (status & RxFOVF) {
7411 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7412 dev->stats.rx_fifo_errors++;
7414 if ((status & (RxRUNT | RxCRC)) &&
7415 !(status & (RxRWT | RxFOVF)) &&
7416 (dev->features & NETIF_F_RXALL))
7419 struct sk_buff *skb;
7424 addr = le64_to_cpu(desc->addr);
7425 if (likely(!(dev->features & NETIF_F_RXFCS)))
7426 pkt_size = (status & 0x00003fff) - 4;
7428 pkt_size = status & 0x00003fff;
7431 * The driver does not support incoming fragmented
7432 * frames. They are seen as a symptom of over-mtu
7435 if (unlikely(rtl8169_fragmented_frame(status))) {
7436 dev->stats.rx_dropped++;
7437 dev->stats.rx_length_errors++;
7438 goto release_descriptor;
7441 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7442 tp, pkt_size, addr);
7444 dev->stats.rx_dropped++;
7445 goto release_descriptor;
7448 rtl8169_rx_csum(skb, status);
7449 skb_put(skb, pkt_size);
7450 skb->protocol = eth_type_trans(skb, dev);
7452 rtl8169_rx_vlan_tag(desc, skb);
7454 if (skb->pkt_type == PACKET_MULTICAST)
7455 dev->stats.multicast++;
7457 napi_gro_receive(&tp->napi, skb);
7459 u64_stats_update_begin(&tp->rx_stats.syncp);
7460 tp->rx_stats.packets++;
7461 tp->rx_stats.bytes += pkt_size;
7462 u64_stats_update_end(&tp->rx_stats.syncp);
7466 rtl8169_mark_to_asic(desc, rx_buf_sz);
7469 count = cur_rx - tp->cur_rx;
7470 tp->cur_rx = cur_rx;
7475 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7477 struct net_device *dev = dev_instance;
7478 struct rtl8169_private *tp = netdev_priv(dev);
7482 status = rtl_get_events(tp);
7483 if (status && status != 0xffff) {
7484 status &= RTL_EVENT_NAPI | tp->event_slow;
7488 rtl_irq_disable(tp);
7489 napi_schedule(&tp->napi);
7492 return IRQ_RETVAL(handled);
7496 * Workqueue context.
7498 static void rtl_slow_event_work(struct rtl8169_private *tp)
7500 struct net_device *dev = tp->dev;
7503 status = rtl_get_events(tp) & tp->event_slow;
7504 rtl_ack_events(tp, status);
7506 if (unlikely(status & RxFIFOOver)) {
7507 switch (tp->mac_version) {
7508 /* Work around for rx fifo overflow */
7509 case RTL_GIGA_MAC_VER_11:
7510 netif_stop_queue(dev);
7511 /* XXX - Hack alert. See rtl_task(). */
7512 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7518 if (unlikely(status & SYSErr))
7519 rtl8169_pcierr_interrupt(dev);
7521 if (status & LinkChg)
7522 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7524 rtl_irq_enable_all(tp);
7527 static void rtl_task(struct work_struct *work)
7529 static const struct {
7531 void (*action)(struct rtl8169_private *);
7533 /* XXX - keep rtl_slow_event_work() as first element. */
7534 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7535 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7536 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7538 struct rtl8169_private *tp =
7539 container_of(work, struct rtl8169_private, wk.work);
7540 struct net_device *dev = tp->dev;
7545 if (!netif_running(dev) ||
7546 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7549 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7552 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7554 rtl_work[i].action(tp);
7558 rtl_unlock_work(tp);
7561 static int rtl8169_poll(struct napi_struct *napi, int budget)
7563 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7564 struct net_device *dev = tp->dev;
7565 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7569 status = rtl_get_events(tp);
7570 rtl_ack_events(tp, status & ~tp->event_slow);
7572 if (status & RTL_EVENT_NAPI_RX)
7573 work_done = rtl_rx(dev, tp, (u32) budget);
7575 if (status & RTL_EVENT_NAPI_TX)
7578 if (status & tp->event_slow) {
7579 enable_mask &= ~tp->event_slow;
7581 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7584 if (work_done < budget) {
7585 napi_complete(napi);
7587 rtl_irq_enable(tp, enable_mask);
7594 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7596 struct rtl8169_private *tp = netdev_priv(dev);
7598 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7601 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7602 RTL_W32(RxMissed, 0);
7605 static void rtl8169_down(struct net_device *dev)
7607 struct rtl8169_private *tp = netdev_priv(dev);
7608 void __iomem *ioaddr = tp->mmio_addr;
7610 del_timer_sync(&tp->timer);
7612 napi_disable(&tp->napi);
7613 netif_stop_queue(dev);
7615 rtl8169_hw_reset(tp);
7617 * At this point device interrupts can not be enabled in any function,
7618 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7619 * and napi is disabled (rtl8169_poll).
7621 rtl8169_rx_missed(dev, ioaddr);
7623 /* Give a racing hard_start_xmit a few cycles to complete. */
7624 synchronize_sched();
7626 rtl8169_tx_clear(tp);
7628 rtl8169_rx_clear(tp);
7630 rtl_pll_power_down(tp);
7633 static int rtl8169_close(struct net_device *dev)
7635 struct rtl8169_private *tp = netdev_priv(dev);
7636 struct pci_dev *pdev = tp->pci_dev;
7638 pm_runtime_get_sync(&pdev->dev);
7640 /* Update counters before going down */
7641 rtl8169_update_counters(dev);
7644 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7647 rtl_unlock_work(tp);
7649 cancel_work_sync(&tp->wk.work);
7651 free_irq(pdev->irq, dev);
7653 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7655 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7657 tp->TxDescArray = NULL;
7658 tp->RxDescArray = NULL;
7660 pm_runtime_put_sync(&pdev->dev);
7665 #ifdef CONFIG_NET_POLL_CONTROLLER
7666 static void rtl8169_netpoll(struct net_device *dev)
7668 struct rtl8169_private *tp = netdev_priv(dev);
7670 rtl8169_interrupt(tp->pci_dev->irq, dev);
7674 static int rtl_open(struct net_device *dev)
7676 struct rtl8169_private *tp = netdev_priv(dev);
7677 void __iomem *ioaddr = tp->mmio_addr;
7678 struct pci_dev *pdev = tp->pci_dev;
7679 int retval = -ENOMEM;
7681 pm_runtime_get_sync(&pdev->dev);
7684 * Rx and Tx descriptors needs 256 bytes alignment.
7685 * dma_alloc_coherent provides more.
7687 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7688 &tp->TxPhyAddr, GFP_KERNEL);
7689 if (!tp->TxDescArray)
7690 goto err_pm_runtime_put;
7692 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7693 &tp->RxPhyAddr, GFP_KERNEL);
7694 if (!tp->RxDescArray)
7697 retval = rtl8169_init_ring(dev);
7701 INIT_WORK(&tp->wk.work, rtl_task);
7705 rtl_request_firmware(tp);
7707 retval = request_irq(pdev->irq, rtl8169_interrupt,
7708 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7711 goto err_release_fw_2;
7715 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7717 napi_enable(&tp->napi);
7719 rtl8169_init_phy(dev, tp);
7721 __rtl8169_set_features(dev, dev->features);
7723 rtl_pll_power_up(tp);
7727 if (!rtl8169_init_counter_offsets(dev))
7728 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7730 netif_start_queue(dev);
7732 rtl_unlock_work(tp);
7734 tp->saved_wolopts = 0;
7735 pm_runtime_put_noidle(&pdev->dev);
7737 rtl8169_check_link_status(dev, tp, ioaddr);
7742 rtl_release_firmware(tp);
7743 rtl8169_rx_clear(tp);
7745 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7747 tp->RxDescArray = NULL;
7749 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7751 tp->TxDescArray = NULL;
7753 pm_runtime_put_noidle(&pdev->dev);
7757 static struct rtnl_link_stats64 *
7758 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7760 struct rtl8169_private *tp = netdev_priv(dev);
7761 void __iomem *ioaddr = tp->mmio_addr;
7762 struct pci_dev *pdev = tp->pci_dev;
7763 struct rtl8169_counters *counters = tp->counters;
7766 pm_runtime_get_noresume(&pdev->dev);
7768 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7769 rtl8169_rx_missed(dev, ioaddr);
7772 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7773 stats->rx_packets = tp->rx_stats.packets;
7774 stats->rx_bytes = tp->rx_stats.bytes;
7775 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7778 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7779 stats->tx_packets = tp->tx_stats.packets;
7780 stats->tx_bytes = tp->tx_stats.bytes;
7781 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7783 stats->rx_dropped = dev->stats.rx_dropped;
7784 stats->tx_dropped = dev->stats.tx_dropped;
7785 stats->rx_length_errors = dev->stats.rx_length_errors;
7786 stats->rx_errors = dev->stats.rx_errors;
7787 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7788 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7789 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7790 stats->multicast = dev->stats.multicast;
7793 * Fetch additonal counter values missing in stats collected by driver
7794 * from tally counters.
7796 if (pm_runtime_active(&pdev->dev))
7797 rtl8169_update_counters(dev);
7800 * Subtract values fetched during initalization.
7801 * See rtl8169_init_counter_offsets for a description why we do that.
7803 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7804 le64_to_cpu(tp->tc_offset.tx_errors);
7805 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7806 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7807 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7808 le16_to_cpu(tp->tc_offset.tx_aborted);
7810 pm_runtime_put_noidle(&pdev->dev);
7815 static void rtl8169_net_suspend(struct net_device *dev)
7817 struct rtl8169_private *tp = netdev_priv(dev);
7819 if (!netif_running(dev))
7822 netif_device_detach(dev);
7823 netif_stop_queue(dev);
7826 napi_disable(&tp->napi);
7827 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7828 rtl_unlock_work(tp);
7830 rtl_pll_power_down(tp);
7835 static int rtl8169_suspend(struct device *device)
7837 struct pci_dev *pdev = to_pci_dev(device);
7838 struct net_device *dev = pci_get_drvdata(pdev);
7840 rtl8169_net_suspend(dev);
7845 static void __rtl8169_resume(struct net_device *dev)
7847 struct rtl8169_private *tp = netdev_priv(dev);
7849 netif_device_attach(dev);
7851 rtl_pll_power_up(tp);
7854 napi_enable(&tp->napi);
7855 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7856 rtl_unlock_work(tp);
7858 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7861 static int rtl8169_resume(struct device *device)
7863 struct pci_dev *pdev = to_pci_dev(device);
7864 struct net_device *dev = pci_get_drvdata(pdev);
7865 struct rtl8169_private *tp = netdev_priv(dev);
7867 rtl8169_init_phy(dev, tp);
7869 if (netif_running(dev))
7870 __rtl8169_resume(dev);
7875 static int rtl8169_runtime_suspend(struct device *device)
7877 struct pci_dev *pdev = to_pci_dev(device);
7878 struct net_device *dev = pci_get_drvdata(pdev);
7879 struct rtl8169_private *tp = netdev_priv(dev);
7881 if (!tp->TxDescArray)
7885 tp->saved_wolopts = __rtl8169_get_wol(tp);
7886 __rtl8169_set_wol(tp, WAKE_ANY);
7887 rtl_unlock_work(tp);
7889 rtl8169_net_suspend(dev);
7891 /* Update counters before going runtime suspend */
7892 rtl8169_rx_missed(dev, tp->mmio_addr);
7893 rtl8169_update_counters(dev);
7898 static int rtl8169_runtime_resume(struct device *device)
7900 struct pci_dev *pdev = to_pci_dev(device);
7901 struct net_device *dev = pci_get_drvdata(pdev);
7902 struct rtl8169_private *tp = netdev_priv(dev);
7903 rtl_rar_set(tp, dev->dev_addr);
7905 if (!tp->TxDescArray)
7909 __rtl8169_set_wol(tp, tp->saved_wolopts);
7910 tp->saved_wolopts = 0;
7911 rtl_unlock_work(tp);
7913 rtl8169_init_phy(dev, tp);
7915 __rtl8169_resume(dev);
7920 static int rtl8169_runtime_idle(struct device *device)
7922 struct pci_dev *pdev = to_pci_dev(device);
7923 struct net_device *dev = pci_get_drvdata(pdev);
7924 struct rtl8169_private *tp = netdev_priv(dev);
7926 return tp->TxDescArray ? -EBUSY : 0;
7929 static const struct dev_pm_ops rtl8169_pm_ops = {
7930 .suspend = rtl8169_suspend,
7931 .resume = rtl8169_resume,
7932 .freeze = rtl8169_suspend,
7933 .thaw = rtl8169_resume,
7934 .poweroff = rtl8169_suspend,
7935 .restore = rtl8169_resume,
7936 .runtime_suspend = rtl8169_runtime_suspend,
7937 .runtime_resume = rtl8169_runtime_resume,
7938 .runtime_idle = rtl8169_runtime_idle,
7941 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7943 #else /* !CONFIG_PM */
7945 #define RTL8169_PM_OPS NULL
7947 #endif /* !CONFIG_PM */
7949 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7951 void __iomem *ioaddr = tp->mmio_addr;
7953 /* WoL fails with 8168b when the receiver is disabled. */
7954 switch (tp->mac_version) {
7955 case RTL_GIGA_MAC_VER_11:
7956 case RTL_GIGA_MAC_VER_12:
7957 case RTL_GIGA_MAC_VER_17:
7958 pci_clear_master(tp->pci_dev);
7960 RTL_W8(ChipCmd, CmdRxEnb);
7969 static void rtl_shutdown(struct pci_dev *pdev)
7971 struct net_device *dev = pci_get_drvdata(pdev);
7972 struct rtl8169_private *tp = netdev_priv(dev);
7973 struct device *d = &pdev->dev;
7975 pm_runtime_get_sync(d);
7977 rtl8169_net_suspend(dev);
7979 /* Restore original MAC address */
7980 rtl_rar_set(tp, dev->perm_addr);
7982 rtl8169_hw_reset(tp);
7984 if (system_state == SYSTEM_POWER_OFF) {
7985 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7986 rtl_wol_suspend_quirk(tp);
7987 rtl_wol_shutdown_quirk(tp);
7990 pci_wake_from_d3(pdev, true);
7991 pci_set_power_state(pdev, PCI_D3hot);
7994 pm_runtime_put_noidle(d);
7997 static void rtl_remove_one(struct pci_dev *pdev)
7999 struct net_device *dev = pci_get_drvdata(pdev);
8000 struct rtl8169_private *tp = netdev_priv(dev);
8002 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8003 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8004 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8005 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8006 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8007 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8008 r8168_check_dash(tp)) {
8009 rtl8168_driver_stop(tp);
8012 netif_napi_del(&tp->napi);
8014 unregister_netdev(dev);
8016 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8017 tp->counters, tp->counters_phys_addr);
8019 rtl_release_firmware(tp);
8021 if (pci_dev_run_wake(pdev))
8022 pm_runtime_get_noresume(&pdev->dev);
8024 /* restore original MAC address */
8025 rtl_rar_set(tp, dev->perm_addr);
8027 rtl_disable_msi(pdev, tp);
8028 rtl8169_release_board(pdev, dev, tp->mmio_addr);
8031 static const struct net_device_ops rtl_netdev_ops = {
8032 .ndo_open = rtl_open,
8033 .ndo_stop = rtl8169_close,
8034 .ndo_get_stats64 = rtl8169_get_stats64,
8035 .ndo_start_xmit = rtl8169_start_xmit,
8036 .ndo_tx_timeout = rtl8169_tx_timeout,
8037 .ndo_validate_addr = eth_validate_addr,
8038 .ndo_change_mtu = rtl8169_change_mtu,
8039 .ndo_fix_features = rtl8169_fix_features,
8040 .ndo_set_features = rtl8169_set_features,
8041 .ndo_set_mac_address = rtl_set_mac_address,
8042 .ndo_do_ioctl = rtl8169_ioctl,
8043 .ndo_set_rx_mode = rtl_set_rx_mode,
8044 #ifdef CONFIG_NET_POLL_CONTROLLER
8045 .ndo_poll_controller = rtl8169_netpoll,
8050 static const struct rtl_cfg_info {
8051 void (*hw_start)(struct net_device *);
8052 unsigned int region;
8057 } rtl_cfg_infos [] = {
8059 .hw_start = rtl_hw_start_8169,
8062 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8063 .features = RTL_FEATURE_GMII,
8064 .default_ver = RTL_GIGA_MAC_VER_01,
8067 .hw_start = rtl_hw_start_8168,
8070 .event_slow = SYSErr | LinkChg | RxOverflow,
8071 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8072 .default_ver = RTL_GIGA_MAC_VER_11,
8075 .hw_start = rtl_hw_start_8101,
8078 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8080 .features = RTL_FEATURE_MSI,
8081 .default_ver = RTL_GIGA_MAC_VER_13,
8085 /* Cfg9346_Unlock assumed. */
8086 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8087 const struct rtl_cfg_info *cfg)
8089 void __iomem *ioaddr = tp->mmio_addr;
8093 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8094 if (cfg->features & RTL_FEATURE_MSI) {
8095 if (pci_enable_msi(tp->pci_dev)) {
8096 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8099 msi = RTL_FEATURE_MSI;
8102 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8103 RTL_W8(Config2, cfg2);
8107 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8109 void __iomem *ioaddr = tp->mmio_addr;
8111 return RTL_R8(MCU) & LINK_LIST_RDY;
8114 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8116 void __iomem *ioaddr = tp->mmio_addr;
8118 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8121 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8123 void __iomem *ioaddr = tp->mmio_addr;
8126 tp->ocp_base = OCP_STD_PHY_BASE;
8128 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8130 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8133 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8136 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8138 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8140 data = r8168_mac_ocp_read(tp, 0xe8de);
8142 r8168_mac_ocp_write(tp, 0xe8de, data);
8144 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8147 data = r8168_mac_ocp_read(tp, 0xe8de);
8149 r8168_mac_ocp_write(tp, 0xe8de, data);
8151 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8155 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8157 rtl8168ep_stop_cmac(tp);
8158 rtl_hw_init_8168g(tp);
8161 static void rtl_hw_initialize(struct rtl8169_private *tp)
8163 switch (tp->mac_version) {
8164 case RTL_GIGA_MAC_VER_40:
8165 case RTL_GIGA_MAC_VER_41:
8166 case RTL_GIGA_MAC_VER_42:
8167 case RTL_GIGA_MAC_VER_43:
8168 case RTL_GIGA_MAC_VER_44:
8169 case RTL_GIGA_MAC_VER_45:
8170 case RTL_GIGA_MAC_VER_46:
8171 case RTL_GIGA_MAC_VER_47:
8172 case RTL_GIGA_MAC_VER_48:
8173 rtl_hw_init_8168g(tp);
8175 case RTL_GIGA_MAC_VER_49:
8176 case RTL_GIGA_MAC_VER_50:
8177 case RTL_GIGA_MAC_VER_51:
8178 rtl_hw_init_8168ep(tp);
8185 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8187 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8188 const unsigned int region = cfg->region;
8189 struct rtl8169_private *tp;
8190 struct mii_if_info *mii;
8191 struct net_device *dev;
8192 void __iomem *ioaddr;
8196 if (netif_msg_drv(&debug)) {
8197 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8198 MODULENAME, RTL8169_VERSION);
8201 dev = alloc_etherdev(sizeof (*tp));
8207 SET_NETDEV_DEV(dev, &pdev->dev);
8208 dev->netdev_ops = &rtl_netdev_ops;
8209 tp = netdev_priv(dev);
8212 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8216 mii->mdio_read = rtl_mdio_read;
8217 mii->mdio_write = rtl_mdio_write;
8218 mii->phy_id_mask = 0x1f;
8219 mii->reg_num_mask = 0x1f;
8220 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8222 /* disable ASPM completely as that cause random device stop working
8223 * problems as well as full system hangs for some PCIe devices users */
8224 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8225 PCIE_LINK_STATE_CLKPM);
8227 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8228 rc = pci_enable_device(pdev);
8230 netif_err(tp, probe, dev, "enable failure\n");
8231 goto err_out_free_dev_1;
8234 if (pci_set_mwi(pdev) < 0)
8235 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8237 /* make sure PCI base addr 1 is MMIO */
8238 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8239 netif_err(tp, probe, dev,
8240 "region #%d not an MMIO resource, aborting\n",
8246 /* check for weird/broken PCI region reporting */
8247 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8248 netif_err(tp, probe, dev,
8249 "Invalid PCI region size(s), aborting\n");
8254 rc = pci_request_regions(pdev, MODULENAME);
8256 netif_err(tp, probe, dev, "could not request regions\n");
8260 /* ioremap MMIO region */
8261 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8263 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8265 goto err_out_free_res_3;
8267 tp->mmio_addr = ioaddr;
8269 if (!pci_is_pcie(pdev))
8270 netif_info(tp, probe, dev, "not PCI Express\n");
8272 /* Identify chip attached to board */
8273 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8277 if ((sizeof(dma_addr_t) > 4) &&
8278 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8279 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8280 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8281 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8283 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8284 if (!pci_is_pcie(pdev))
8285 tp->cp_cmd |= PCIDAC;
8286 dev->features |= NETIF_F_HIGHDMA;
8288 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8290 netif_err(tp, probe, dev, "DMA configuration failed\n");
8291 goto err_out_unmap_4;
8297 rtl_irq_disable(tp);
8299 rtl_hw_initialize(tp);
8303 rtl_ack_events(tp, 0xffff);
8305 pci_set_master(pdev);
8307 rtl_init_mdio_ops(tp);
8308 rtl_init_pll_power_ops(tp);
8309 rtl_init_jumbo_ops(tp);
8310 rtl_init_csi_ops(tp);
8312 rtl8169_print_mac_version(tp);
8314 chipset = tp->mac_version;
8315 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8317 RTL_W8(Cfg9346, Cfg9346_Unlock);
8318 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8319 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8320 switch (tp->mac_version) {
8321 case RTL_GIGA_MAC_VER_34:
8322 case RTL_GIGA_MAC_VER_35:
8323 case RTL_GIGA_MAC_VER_36:
8324 case RTL_GIGA_MAC_VER_37:
8325 case RTL_GIGA_MAC_VER_38:
8326 case RTL_GIGA_MAC_VER_40:
8327 case RTL_GIGA_MAC_VER_41:
8328 case RTL_GIGA_MAC_VER_42:
8329 case RTL_GIGA_MAC_VER_43:
8330 case RTL_GIGA_MAC_VER_44:
8331 case RTL_GIGA_MAC_VER_45:
8332 case RTL_GIGA_MAC_VER_46:
8333 case RTL_GIGA_MAC_VER_47:
8334 case RTL_GIGA_MAC_VER_48:
8335 case RTL_GIGA_MAC_VER_49:
8336 case RTL_GIGA_MAC_VER_50:
8337 case RTL_GIGA_MAC_VER_51:
8338 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8339 tp->features |= RTL_FEATURE_WOL;
8340 if ((RTL_R8(Config3) & LinkUp) != 0)
8341 tp->features |= RTL_FEATURE_WOL;
8344 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8345 tp->features |= RTL_FEATURE_WOL;
8348 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8349 tp->features |= RTL_FEATURE_WOL;
8350 tp->features |= rtl_try_msi(tp, cfg);
8351 RTL_W8(Cfg9346, Cfg9346_Lock);
8353 if (rtl_tbi_enabled(tp)) {
8354 tp->set_speed = rtl8169_set_speed_tbi;
8355 tp->get_settings = rtl8169_gset_tbi;
8356 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8357 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8358 tp->link_ok = rtl8169_tbi_link_ok;
8359 tp->do_ioctl = rtl_tbi_ioctl;
8361 tp->set_speed = rtl8169_set_speed_xmii;
8362 tp->get_settings = rtl8169_gset_xmii;
8363 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8364 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8365 tp->link_ok = rtl8169_xmii_link_ok;
8366 tp->do_ioctl = rtl_xmii_ioctl;
8369 mutex_init(&tp->wk.mutex);
8370 u64_stats_init(&tp->rx_stats.syncp);
8371 u64_stats_init(&tp->tx_stats.syncp);
8373 /* Get MAC address */
8374 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8375 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8376 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8377 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8378 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8379 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8380 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8381 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8382 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8383 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8384 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8385 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8386 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8387 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8388 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8389 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8392 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8393 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8395 if (is_valid_ether_addr((u8 *)mac_addr))
8396 rtl_rar_set(tp, (u8 *)mac_addr);
8398 for (i = 0; i < ETH_ALEN; i++)
8399 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8401 dev->ethtool_ops = &rtl8169_ethtool_ops;
8402 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8404 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8406 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8407 * properly for all devices */
8408 dev->features |= NETIF_F_RXCSUM |
8409 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8411 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8412 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8413 NETIF_F_HW_VLAN_CTAG_RX;
8414 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8417 tp->cp_cmd |= RxChkSum | RxVlan;
8420 * Pretend we are using VLANs; This bypasses a nasty bug where
8421 * Interrupts stop flowing on high load on 8110SCd controllers.
8423 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8424 /* Disallow toggling */
8425 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8427 if (tp->txd_version == RTL_TD_0)
8428 tp->tso_csum = rtl8169_tso_csum_v1;
8429 else if (tp->txd_version == RTL_TD_1) {
8430 tp->tso_csum = rtl8169_tso_csum_v2;
8431 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8435 dev->hw_features |= NETIF_F_RXALL;
8436 dev->hw_features |= NETIF_F_RXFCS;
8438 /* MTU range: 60 - hw-specific max */
8439 dev->min_mtu = ETH_ZLEN;
8440 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8442 tp->hw_start = cfg->hw_start;
8443 tp->event_slow = cfg->event_slow;
8445 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8446 ~(RxBOVF | RxFOVF) : ~0;
8448 init_timer(&tp->timer);
8449 tp->timer.data = (unsigned long) dev;
8450 tp->timer.function = rtl8169_phy_timer;
8452 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8454 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8455 &tp->counters_phys_addr, GFP_KERNEL);
8456 if (!tp->counters) {
8461 rc = register_netdev(dev);
8465 pci_set_drvdata(pdev, dev);
8467 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8468 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8469 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8470 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8471 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8472 "tx checksumming: %s]\n",
8473 rtl_chip_infos[chipset].jumbo_max,
8474 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8477 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8478 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8479 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8480 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8481 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8482 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8483 r8168_check_dash(tp)) {
8484 rtl8168_driver_start(tp);
8487 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8489 if (pci_dev_run_wake(pdev))
8490 pm_runtime_put_noidle(&pdev->dev);
8492 netif_carrier_off(dev);
8498 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8499 tp->counters_phys_addr);
8501 netif_napi_del(&tp->napi);
8502 rtl_disable_msi(pdev, tp);
8506 pci_release_regions(pdev);
8508 pci_clear_mwi(pdev);
8509 pci_disable_device(pdev);
8515 static struct pci_driver rtl8169_pci_driver = {
8517 .id_table = rtl8169_pci_tbl,
8518 .probe = rtl_init_one,
8519 .remove = rtl_remove_one,
8520 .shutdown = rtl_shutdown,
8521 .driver.pm = RTL8169_PM_OPS,
8524 module_pci_driver(rtl8169_pci_driver);