2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
49 #define assert(expr) \
51 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
52 #expr,__FILE__,__func__,__LINE__); \
54 #define dprintk(fmt, args...) \
55 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #define assert(expr) do {} while (0)
58 #define dprintk(fmt, args...) do {} while (0)
59 #endif /* RTL8169_DEBUG */
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64 #define TX_SLOTS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
69 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
72 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
73 static const int multicast_filter_limit = 32;
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01 = 0,
140 RTL_GIGA_MAC_NONE = 0xff,
143 enum rtl_tx_desc_version {
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
154 #define _R(NAME,TD,FW,SZ,B) { \
162 static const struct {
164 enum rtl_tx_desc_version txd_version;
168 } rtl_chip_infos[] = {
170 [RTL_GIGA_MAC_VER_01] =
171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_02] =
173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_03] =
175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_04] =
177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_05] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_06] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_07] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_08] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_09] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_10] =
190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
191 [RTL_GIGA_MAC_VER_11] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_12] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
195 [RTL_GIGA_MAC_VER_13] =
196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_14] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_15] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_16] =
202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_17] =
204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
205 [RTL_GIGA_MAC_VER_18] =
206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_19] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_20] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_21] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_22] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_23] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_24] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_25] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
222 [RTL_GIGA_MAC_VER_26] =
223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
232 [RTL_GIGA_MAC_VER_30] =
233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
235 [RTL_GIGA_MAC_VER_31] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_32] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
240 [RTL_GIGA_MAC_VER_33] =
241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
243 [RTL_GIGA_MAC_VER_34] =
244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
246 [RTL_GIGA_MAC_VER_35] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
249 [RTL_GIGA_MAC_VER_36] =
250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
267 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
271 { PCI_VENDOR_ID_LINKSYS, 0x1032,
272 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
274 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280 static int rx_buf_sz = 16383;
287 MAC0 = 0, /* Ethernet hardware address. */
289 MAR0 = 8, /* Multicast filter. */
290 CounterAddrLow = 0x10,
291 CounterAddrHigh = 0x14,
292 TxDescStartAddrLow = 0x20,
293 TxDescStartAddrHigh = 0x24,
294 TxHDescStartAddrLow = 0x28,
295 TxHDescStartAddrHigh = 0x2c,
304 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
305 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
308 #define RX128_INT_EN (1 << 15) /* 8111c and later */
309 #define RX_MULTI_EN (1 << 14) /* 8111c only */
310 #define RXCFG_FIFO_SHIFT 13
311 /* No threshold before first PCI xfer */
312 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
313 #define RXCFG_DMA_SHIFT 8
314 /* Unlimited maximum PCI burst. */
315 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
331 RxDescAddrLow = 0xe4,
332 RxDescAddrHigh = 0xe8,
333 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
337 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339 #define TxPacketMax (8064 >> 7)
340 #define EarlySize 0x27
343 FuncEventMask = 0xf4,
344 FuncPresetState = 0xf8,
345 FuncForceEvent = 0xfc,
348 enum rtl8110_registers {
354 enum rtl8168_8101_registers {
357 #define CSIAR_FLAG 0x80000000
358 #define CSIAR_WRITE_CMD 0x80000000
359 #define CSIAR_BYTE_ENABLE 0x0f
360 #define CSIAR_BYTE_ENABLE_SHIFT 12
361 #define CSIAR_ADDR_MASK 0x0fff
364 #define EPHYAR_FLAG 0x80000000
365 #define EPHYAR_WRITE_CMD 0x80000000
366 #define EPHYAR_REG_MASK 0x1f
367 #define EPHYAR_REG_SHIFT 16
368 #define EPHYAR_DATA_MASK 0xffff
370 #define PFM_EN (1 << 6)
372 #define FIX_NAK_1 (1 << 4)
373 #define FIX_NAK_2 (1 << 3)
376 #define NOW_IS_OOB (1 << 7)
377 #define EN_NDP (1 << 3)
378 #define EN_OOB_RESET (1 << 2)
380 #define EFUSEAR_FLAG 0x80000000
381 #define EFUSEAR_WRITE_CMD 0x80000000
382 #define EFUSEAR_READ_CMD 0x00000000
383 #define EFUSEAR_REG_MASK 0x03ff
384 #define EFUSEAR_REG_SHIFT 8
385 #define EFUSEAR_DATA_MASK 0xff
388 enum rtl8168_registers {
393 #define ERIAR_FLAG 0x80000000
394 #define ERIAR_WRITE_CMD 0x80000000
395 #define ERIAR_READ_CMD 0x00000000
396 #define ERIAR_ADDR_BYTE_ALIGN 4
397 #define ERIAR_TYPE_SHIFT 16
398 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
399 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_MASK_SHIFT 12
402 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
403 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
405 EPHY_RXER_NUM = 0x7c,
406 OCPDR = 0xb0, /* OCP GPHY access */
407 #define OCPDR_WRITE_CMD 0x80000000
408 #define OCPDR_READ_CMD 0x00000000
409 #define OCPDR_REG_MASK 0x7f
410 #define OCPDR_GPHY_REG_SHIFT 16
411 #define OCPDR_DATA_MASK 0xffff
413 #define OCPAR_FLAG 0x80000000
414 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
415 #define OCPAR_GPHY_READ_CMD 0x0000f060
416 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
417 MISC = 0xf0, /* 8168e only. */
418 #define TXPLA_RST (1 << 29)
419 #define PWM_EN (1 << 22)
422 enum rtl_register_content {
423 /* InterruptStatusBits */
427 TxDescUnavail = 0x0080,
451 /* TXPoll register p.5 */
452 HPQ = 0x80, /* Poll cmd on the high prio queue */
453 NPQ = 0x40, /* Poll cmd on the low prio queue */
454 FSWInt = 0x01, /* Forced software interrupt */
458 Cfg9346_Unlock = 0xc0,
463 AcceptBroadcast = 0x08,
464 AcceptMulticast = 0x04,
466 AcceptAllPhys = 0x01,
467 #define RX_CONFIG_ACCEPT_MASK 0x3f
470 TxInterFrameGapShift = 24,
471 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473 /* Config1 register p.24 */
476 Speed_down = (1 << 4),
480 PMEnable = (1 << 0), /* Power Management Enable */
482 /* Config2 register p. 25 */
483 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
484 PCI_Clock_66MHz = 0x01,
485 PCI_Clock_33MHz = 0x00,
487 /* Config3 register p.25 */
488 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
489 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
490 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
491 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
493 /* Config4 register */
494 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496 /* Config5 register p.27 */
497 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
498 MWF = (1 << 5), /* Accept Multicast wakeup frame */
499 UWF = (1 << 4), /* Accept Unicast wakeup frame */
501 LanWake = (1 << 1), /* LanWake enable/disable */
502 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
505 TBIReset = 0x80000000,
506 TBILoopback = 0x40000000,
507 TBINwEnable = 0x20000000,
508 TBINwRestart = 0x10000000,
509 TBILinkOk = 0x02000000,
510 TBINwComplete = 0x01000000,
513 EnableBist = (1 << 15), // 8168 8101
514 Mac_dbgo_oe = (1 << 14), // 8168 8101
515 Normal_mode = (1 << 13), // unused
516 Force_half_dup = (1 << 12), // 8168 8101
517 Force_rxflow_en = (1 << 11), // 8168 8101
518 Force_txflow_en = (1 << 10), // 8168 8101
519 Cxpl_dbg_sel = (1 << 9), // 8168 8101
520 ASF = (1 << 8), // 8168 8101
521 PktCntrDisable = (1 << 7), // 8168 8101
522 Mac_dbgo_sel = 0x001c, // 8168
527 INTT_0 = 0x0000, // 8168
528 INTT_1 = 0x0001, // 8168
529 INTT_2 = 0x0002, // 8168
530 INTT_3 = 0x0003, // 8168
532 /* rtl8169_PHYstatus */
543 TBILinkOK = 0x02000000,
545 /* DumpCounterCommand */
550 /* First doubleword. */
551 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
552 RingEnd = (1 << 30), /* End of descriptor ring */
553 FirstFrag = (1 << 29), /* First segment of a packet */
554 LastFrag = (1 << 28), /* Final segment of a packet */
558 enum rtl_tx_desc_bit {
559 /* First doubleword. */
560 TD_LSO = (1 << 27), /* Large Send Offload */
561 #define TD_MSS_MAX 0x07ffu /* MSS value */
563 /* Second doubleword. */
564 TxVlanTag = (1 << 17), /* Add VLAN tag */
567 /* 8169, 8168b and 810x except 8102e. */
568 enum rtl_tx_desc_bit_0 {
569 /* First doubleword. */
570 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
571 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
572 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
573 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
576 /* 8102e, 8168c and beyond. */
577 enum rtl_tx_desc_bit_1 {
578 /* Second doubleword. */
579 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
580 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
581 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
582 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
585 static const struct rtl_tx_desc_info {
592 } tx_desc_info [] = {
595 .udp = TD0_IP_CS | TD0_UDP_CS,
596 .tcp = TD0_IP_CS | TD0_TCP_CS
598 .mss_shift = TD0_MSS_SHIFT,
603 .udp = TD1_IP_CS | TD1_UDP_CS,
604 .tcp = TD1_IP_CS | TD1_TCP_CS
606 .mss_shift = TD1_MSS_SHIFT,
611 enum rtl_rx_desc_bit {
613 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
614 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616 #define RxProtoUDP (PID1)
617 #define RxProtoTCP (PID0)
618 #define RxProtoIP (PID1 | PID0)
619 #define RxProtoMask RxProtoIP
621 IPFail = (1 << 16), /* IP checksum failed */
622 UDPFail = (1 << 15), /* UDP/IP checksum failed */
623 TCPFail = (1 << 14), /* TCP/IP checksum failed */
624 RxVlanTag = (1 << 16), /* VLAN tag available */
627 #define RsvdMask 0x3fffc000
644 u8 __pad[sizeof(void *) - sizeof(u32)];
648 RTL_FEATURE_WOL = (1 << 0),
649 RTL_FEATURE_MSI = (1 << 1),
650 RTL_FEATURE_GMII = (1 << 2),
653 struct rtl8169_counters {
660 __le32 tx_one_collision;
661 __le32 tx_multi_collision;
670 RTL_FLAG_TASK_ENABLED,
671 RTL_FLAG_TASK_SLOW_PENDING,
672 RTL_FLAG_TASK_RESET_PENDING,
673 RTL_FLAG_TASK_PHY_PENDING,
677 struct rtl8169_stats {
680 struct u64_stats_sync syncp;
683 struct rtl8169_private {
684 void __iomem *mmio_addr; /* memory map physical address */
685 struct pci_dev *pci_dev;
686 struct net_device *dev;
687 struct napi_struct napi;
691 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
692 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
695 struct rtl8169_stats rx_stats;
696 struct rtl8169_stats tx_stats;
697 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
698 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
699 dma_addr_t TxPhyAddr;
700 dma_addr_t RxPhyAddr;
701 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
702 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
703 struct timer_list timer;
709 void (*write)(void __iomem *, int, int);
710 int (*read)(void __iomem *, int);
713 struct pll_power_ops {
714 void (*down)(struct rtl8169_private *);
715 void (*up)(struct rtl8169_private *);
719 void (*enable)(struct rtl8169_private *);
720 void (*disable)(struct rtl8169_private *);
723 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
724 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
725 void (*phy_reset_enable)(struct rtl8169_private *tp);
726 void (*hw_start)(struct net_device *);
727 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
728 unsigned int (*link_ok)(void __iomem *);
729 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
732 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
734 struct work_struct work;
739 struct mii_if_info mii;
740 struct rtl8169_counters counters;
745 const struct firmware *fw;
747 #define RTL_VER_SIZE 32
749 char version[RTL_VER_SIZE];
751 struct rtl_fw_phy_action {
756 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
759 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
760 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
761 module_param(use_dac, int, 0);
762 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
763 module_param_named(debug, debug.msg_enable, int, 0);
764 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
765 MODULE_LICENSE("GPL");
766 MODULE_VERSION(RTL8169_VERSION);
767 MODULE_FIRMWARE(FIRMWARE_8168D_1);
768 MODULE_FIRMWARE(FIRMWARE_8168D_2);
769 MODULE_FIRMWARE(FIRMWARE_8168E_1);
770 MODULE_FIRMWARE(FIRMWARE_8168E_2);
771 MODULE_FIRMWARE(FIRMWARE_8168E_3);
772 MODULE_FIRMWARE(FIRMWARE_8105E_1);
773 MODULE_FIRMWARE(FIRMWARE_8168F_1);
774 MODULE_FIRMWARE(FIRMWARE_8168F_2);
776 static void rtl_lock_work(struct rtl8169_private *tp)
778 mutex_lock(&tp->wk.mutex);
781 static void rtl_unlock_work(struct rtl8169_private *tp)
783 mutex_unlock(&tp->wk.mutex);
786 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
788 int cap = pci_pcie_cap(pdev);
793 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
794 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
795 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
799 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
801 void __iomem *ioaddr = tp->mmio_addr;
804 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
805 for (i = 0; i < 20; i++) {
807 if (RTL_R32(OCPAR) & OCPAR_FLAG)
810 return RTL_R32(OCPDR);
813 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
815 void __iomem *ioaddr = tp->mmio_addr;
818 RTL_W32(OCPDR, data);
819 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
820 for (i = 0; i < 20; i++) {
822 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
827 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
829 void __iomem *ioaddr = tp->mmio_addr;
833 RTL_W32(ERIAR, 0x800010e8);
835 for (i = 0; i < 5; i++) {
837 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
841 ocp_write(tp, 0x1, 0x30, 0x00000001);
844 #define OOB_CMD_RESET 0x00
845 #define OOB_CMD_DRIVER_START 0x05
846 #define OOB_CMD_DRIVER_STOP 0x06
848 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
850 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
853 static void rtl8168_driver_start(struct rtl8169_private *tp)
858 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
860 reg = rtl8168_get_ocp_reg(tp);
862 for (i = 0; i < 10; i++) {
864 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
869 static void rtl8168_driver_stop(struct rtl8169_private *tp)
874 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
876 reg = rtl8168_get_ocp_reg(tp);
878 for (i = 0; i < 10; i++) {
880 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
885 static int r8168dp_check_dash(struct rtl8169_private *tp)
887 u16 reg = rtl8168_get_ocp_reg(tp);
889 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
892 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
896 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
898 for (i = 20; i > 0; i--) {
900 * Check if the RTL8169 has completed writing to the specified
903 if (!(RTL_R32(PHYAR) & 0x80000000))
908 * According to hardware specs a 20us delay is required after write
909 * complete indication, but before sending next command.
914 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
918 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
920 for (i = 20; i > 0; i--) {
922 * Check if the RTL8169 has completed retrieving data from
923 * the specified MII register.
925 if (RTL_R32(PHYAR) & 0x80000000) {
926 value = RTL_R32(PHYAR) & 0xffff;
932 * According to hardware specs a 20us delay is required after read
933 * complete indication, but before sending next command.
940 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
944 RTL_W32(OCPDR, data |
945 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
946 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
947 RTL_W32(EPHY_RXER_NUM, 0);
949 for (i = 0; i < 100; i++) {
951 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
956 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
958 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
959 (value & OCPDR_DATA_MASK));
962 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
966 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
969 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
970 RTL_W32(EPHY_RXER_NUM, 0);
972 for (i = 0; i < 100; i++) {
974 if (RTL_R32(OCPAR) & OCPAR_FLAG)
978 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
981 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
983 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
985 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
988 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
990 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
993 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
995 r8168dp_2_mdio_start(ioaddr);
997 r8169_mdio_write(ioaddr, reg_addr, value);
999 r8168dp_2_mdio_stop(ioaddr);
1002 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1006 r8168dp_2_mdio_start(ioaddr);
1008 value = r8169_mdio_read(ioaddr, reg_addr);
1010 r8168dp_2_mdio_stop(ioaddr);
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1017 tp->mdio_ops.write(tp->mmio_addr, location, val);
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1022 return tp->mdio_ops.read(tp->mmio_addr, location);
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1027 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 val = rtl_readphy(tp, reg_addr);
1035 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1038 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1041 struct rtl8169_private *tp = netdev_priv(dev);
1043 rtl_writephy(tp, location, val);
1046 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1048 struct rtl8169_private *tp = netdev_priv(dev);
1050 return rtl_readphy(tp, location);
1053 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1057 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1058 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1060 for (i = 0; i < 100; i++) {
1061 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1067 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1072 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1074 for (i = 0; i < 100; i++) {
1075 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1076 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1085 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1089 RTL_W32(CSIDR, value);
1090 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1091 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1093 for (i = 0; i < 100; i++) {
1094 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1100 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1105 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1106 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1108 for (i = 0; i < 100; i++) {
1109 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1110 value = RTL_R32(CSIDR);
1120 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1124 BUG_ON((addr & 3) || (mask == 0));
1125 RTL_W32(ERIDR, val);
1126 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1128 for (i = 0; i < 100; i++) {
1129 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1135 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1140 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1142 for (i = 0; i < 100; i++) {
1143 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1144 value = RTL_R32(ERIDR);
1154 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1158 val = rtl_eri_read(ioaddr, addr, type);
1159 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1168 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1169 const struct exgmac_reg *r, int len)
1172 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1177 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1182 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1184 for (i = 0; i < 300; i++) {
1185 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1186 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1195 static u16 rtl_get_events(struct rtl8169_private *tp)
1197 void __iomem *ioaddr = tp->mmio_addr;
1199 return RTL_R16(IntrStatus);
1202 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1204 void __iomem *ioaddr = tp->mmio_addr;
1206 RTL_W16(IntrStatus, bits);
1210 static void rtl_irq_disable(struct rtl8169_private *tp)
1212 void __iomem *ioaddr = tp->mmio_addr;
1214 RTL_W16(IntrMask, 0);
1218 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1220 void __iomem *ioaddr = tp->mmio_addr;
1222 RTL_W16(IntrMask, bits);
1225 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1226 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1227 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1229 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1231 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1234 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1236 void __iomem *ioaddr = tp->mmio_addr;
1238 rtl_irq_disable(tp);
1239 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1243 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1245 void __iomem *ioaddr = tp->mmio_addr;
1247 return RTL_R32(TBICSR) & TBIReset;
1250 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1252 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1255 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1257 return RTL_R32(TBICSR) & TBILinkOk;
1260 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1262 return RTL_R8(PHYstatus) & LinkStatus;
1265 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1267 void __iomem *ioaddr = tp->mmio_addr;
1269 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1272 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1276 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1277 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1280 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1282 void __iomem *ioaddr = tp->mmio_addr;
1283 struct net_device *dev = tp->dev;
1285 if (!netif_running(dev))
1288 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1289 if (RTL_R8(PHYstatus) & _1000bpsF) {
1290 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1291 0x00000011, ERIAR_EXGMAC);
1292 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1293 0x00000005, ERIAR_EXGMAC);
1294 } else if (RTL_R8(PHYstatus) & _100bps) {
1295 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1296 0x0000001f, ERIAR_EXGMAC);
1297 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1298 0x00000005, ERIAR_EXGMAC);
1300 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1301 0x0000001f, ERIAR_EXGMAC);
1302 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1303 0x0000003f, ERIAR_EXGMAC);
1305 /* Reset packet filter */
1306 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1308 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1310 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1311 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1312 if (RTL_R8(PHYstatus) & _1000bpsF) {
1313 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1314 0x00000011, ERIAR_EXGMAC);
1315 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1316 0x00000005, ERIAR_EXGMAC);
1318 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1319 0x0000001f, ERIAR_EXGMAC);
1320 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1321 0x0000003f, ERIAR_EXGMAC);
1326 static void __rtl8169_check_link_status(struct net_device *dev,
1327 struct rtl8169_private *tp,
1328 void __iomem *ioaddr, bool pm)
1330 if (tp->link_ok(ioaddr)) {
1331 rtl_link_chg_patch(tp);
1332 /* This is to cancel a scheduled suspend if there's one. */
1334 pm_request_resume(&tp->pci_dev->dev);
1335 netif_carrier_on(dev);
1336 if (net_ratelimit())
1337 netif_info(tp, ifup, dev, "link up\n");
1339 netif_carrier_off(dev);
1340 netif_info(tp, ifdown, dev, "link down\n");
1342 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1346 static void rtl8169_check_link_status(struct net_device *dev,
1347 struct rtl8169_private *tp,
1348 void __iomem *ioaddr)
1350 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1353 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1355 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1357 void __iomem *ioaddr = tp->mmio_addr;
1361 options = RTL_R8(Config1);
1362 if (!(options & PMEnable))
1365 options = RTL_R8(Config3);
1366 if (options & LinkUp)
1367 wolopts |= WAKE_PHY;
1368 if (options & MagicPacket)
1369 wolopts |= WAKE_MAGIC;
1371 options = RTL_R8(Config5);
1373 wolopts |= WAKE_UCAST;
1375 wolopts |= WAKE_BCAST;
1377 wolopts |= WAKE_MCAST;
1382 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1384 struct rtl8169_private *tp = netdev_priv(dev);
1388 wol->supported = WAKE_ANY;
1389 wol->wolopts = __rtl8169_get_wol(tp);
1391 rtl_unlock_work(tp);
1394 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1396 void __iomem *ioaddr = tp->mmio_addr;
1398 static const struct {
1403 { WAKE_ANY, Config1, PMEnable },
1404 { WAKE_PHY, Config3, LinkUp },
1405 { WAKE_MAGIC, Config3, MagicPacket },
1406 { WAKE_UCAST, Config5, UWF },
1407 { WAKE_BCAST, Config5, BWF },
1408 { WAKE_MCAST, Config5, MWF },
1409 { WAKE_ANY, Config5, LanWake }
1412 RTL_W8(Cfg9346, Cfg9346_Unlock);
1414 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1415 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1416 if (wolopts & cfg[i].opt)
1417 options |= cfg[i].mask;
1418 RTL_W8(cfg[i].reg, options);
1421 RTL_W8(Cfg9346, Cfg9346_Lock);
1424 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1426 struct rtl8169_private *tp = netdev_priv(dev);
1431 tp->features |= RTL_FEATURE_WOL;
1433 tp->features &= ~RTL_FEATURE_WOL;
1434 __rtl8169_set_wol(tp, wol->wolopts);
1436 rtl_unlock_work(tp);
1438 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1443 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1445 return rtl_chip_infos[tp->mac_version].fw_name;
1448 static void rtl8169_get_drvinfo(struct net_device *dev,
1449 struct ethtool_drvinfo *info)
1451 struct rtl8169_private *tp = netdev_priv(dev);
1452 struct rtl_fw *rtl_fw = tp->rtl_fw;
1454 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1455 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1456 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1457 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1458 if (!IS_ERR_OR_NULL(rtl_fw))
1459 strlcpy(info->fw_version, rtl_fw->version,
1460 sizeof(info->fw_version));
1463 static int rtl8169_get_regs_len(struct net_device *dev)
1465 return R8169_REGS_SIZE;
1468 static int rtl8169_set_speed_tbi(struct net_device *dev,
1469 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1471 struct rtl8169_private *tp = netdev_priv(dev);
1472 void __iomem *ioaddr = tp->mmio_addr;
1476 reg = RTL_R32(TBICSR);
1477 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1478 (duplex == DUPLEX_FULL)) {
1479 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1480 } else if (autoneg == AUTONEG_ENABLE)
1481 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1483 netif_warn(tp, link, dev,
1484 "incorrect speed setting refused in TBI mode\n");
1491 static int rtl8169_set_speed_xmii(struct net_device *dev,
1492 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1494 struct rtl8169_private *tp = netdev_priv(dev);
1495 int giga_ctrl, bmcr;
1498 rtl_writephy(tp, 0x1f, 0x0000);
1500 if (autoneg == AUTONEG_ENABLE) {
1503 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1504 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1505 ADVERTISE_100HALF | ADVERTISE_100FULL);
1507 if (adv & ADVERTISED_10baseT_Half)
1508 auto_nego |= ADVERTISE_10HALF;
1509 if (adv & ADVERTISED_10baseT_Full)
1510 auto_nego |= ADVERTISE_10FULL;
1511 if (adv & ADVERTISED_100baseT_Half)
1512 auto_nego |= ADVERTISE_100HALF;
1513 if (adv & ADVERTISED_100baseT_Full)
1514 auto_nego |= ADVERTISE_100FULL;
1516 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1518 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1519 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1521 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1522 if (tp->mii.supports_gmii) {
1523 if (adv & ADVERTISED_1000baseT_Half)
1524 giga_ctrl |= ADVERTISE_1000HALF;
1525 if (adv & ADVERTISED_1000baseT_Full)
1526 giga_ctrl |= ADVERTISE_1000FULL;
1527 } else if (adv & (ADVERTISED_1000baseT_Half |
1528 ADVERTISED_1000baseT_Full)) {
1529 netif_info(tp, link, dev,
1530 "PHY does not support 1000Mbps\n");
1534 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1536 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1537 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1541 if (speed == SPEED_10)
1543 else if (speed == SPEED_100)
1544 bmcr = BMCR_SPEED100;
1548 if (duplex == DUPLEX_FULL)
1549 bmcr |= BMCR_FULLDPLX;
1552 rtl_writephy(tp, MII_BMCR, bmcr);
1554 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1555 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1556 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1557 rtl_writephy(tp, 0x17, 0x2138);
1558 rtl_writephy(tp, 0x0e, 0x0260);
1560 rtl_writephy(tp, 0x17, 0x2108);
1561 rtl_writephy(tp, 0x0e, 0x0000);
1570 static int rtl8169_set_speed(struct net_device *dev,
1571 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1573 struct rtl8169_private *tp = netdev_priv(dev);
1576 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1580 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1581 (advertising & ADVERTISED_1000baseT_Full)) {
1582 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1588 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1590 struct rtl8169_private *tp = netdev_priv(dev);
1593 del_timer_sync(&tp->timer);
1596 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1597 cmd->duplex, cmd->advertising);
1598 rtl_unlock_work(tp);
1603 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1604 netdev_features_t features)
1606 struct rtl8169_private *tp = netdev_priv(dev);
1608 if (dev->mtu > TD_MSS_MAX)
1609 features &= ~NETIF_F_ALL_TSO;
1611 if (dev->mtu > JUMBO_1K &&
1612 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1613 features &= ~NETIF_F_IP_CSUM;
1618 static void __rtl8169_set_features(struct net_device *dev,
1619 netdev_features_t features)
1621 struct rtl8169_private *tp = netdev_priv(dev);
1622 netdev_features_t changed = features ^ dev->features;
1623 void __iomem *ioaddr = tp->mmio_addr;
1625 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1628 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1629 if (features & NETIF_F_RXCSUM)
1630 tp->cp_cmd |= RxChkSum;
1632 tp->cp_cmd &= ~RxChkSum;
1634 if (dev->features & NETIF_F_HW_VLAN_RX)
1635 tp->cp_cmd |= RxVlan;
1637 tp->cp_cmd &= ~RxVlan;
1639 RTL_W16(CPlusCmd, tp->cp_cmd);
1642 if (changed & NETIF_F_RXALL) {
1643 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1644 if (features & NETIF_F_RXALL)
1645 tmp |= (AcceptErr | AcceptRunt);
1646 RTL_W32(RxConfig, tmp);
1650 static int rtl8169_set_features(struct net_device *dev,
1651 netdev_features_t features)
1653 struct rtl8169_private *tp = netdev_priv(dev);
1656 __rtl8169_set_features(dev, features);
1657 rtl_unlock_work(tp);
1663 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1664 struct sk_buff *skb)
1666 return (vlan_tx_tag_present(skb)) ?
1667 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1670 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1672 u32 opts2 = le32_to_cpu(desc->opts2);
1674 if (opts2 & RxVlanTag)
1675 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1680 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1682 struct rtl8169_private *tp = netdev_priv(dev);
1683 void __iomem *ioaddr = tp->mmio_addr;
1687 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1688 cmd->port = PORT_FIBRE;
1689 cmd->transceiver = XCVR_INTERNAL;
1691 status = RTL_R32(TBICSR);
1692 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1693 cmd->autoneg = !!(status & TBINwEnable);
1695 ethtool_cmd_speed_set(cmd, SPEED_1000);
1696 cmd->duplex = DUPLEX_FULL; /* Always set */
1701 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1703 struct rtl8169_private *tp = netdev_priv(dev);
1705 return mii_ethtool_gset(&tp->mii, cmd);
1708 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1710 struct rtl8169_private *tp = netdev_priv(dev);
1714 rc = tp->get_settings(dev, cmd);
1715 rtl_unlock_work(tp);
1720 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1723 struct rtl8169_private *tp = netdev_priv(dev);
1725 if (regs->len > R8169_REGS_SIZE)
1726 regs->len = R8169_REGS_SIZE;
1729 memcpy_fromio(p, tp->mmio_addr, regs->len);
1730 rtl_unlock_work(tp);
1733 static u32 rtl8169_get_msglevel(struct net_device *dev)
1735 struct rtl8169_private *tp = netdev_priv(dev);
1737 return tp->msg_enable;
1740 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1742 struct rtl8169_private *tp = netdev_priv(dev);
1744 tp->msg_enable = value;
1747 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1754 "tx_single_collisions",
1755 "tx_multi_collisions",
1763 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1767 return ARRAY_SIZE(rtl8169_gstrings);
1773 static void rtl8169_update_counters(struct net_device *dev)
1775 struct rtl8169_private *tp = netdev_priv(dev);
1776 void __iomem *ioaddr = tp->mmio_addr;
1777 struct device *d = &tp->pci_dev->dev;
1778 struct rtl8169_counters *counters;
1784 * Some chips are unable to dump tally counters when the receiver
1787 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1790 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1794 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1795 cmd = (u64)paddr & DMA_BIT_MASK(32);
1796 RTL_W32(CounterAddrLow, cmd);
1797 RTL_W32(CounterAddrLow, cmd | CounterDump);
1800 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1801 memcpy(&tp->counters, counters, sizeof(*counters));
1807 RTL_W32(CounterAddrLow, 0);
1808 RTL_W32(CounterAddrHigh, 0);
1810 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1813 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1814 struct ethtool_stats *stats, u64 *data)
1816 struct rtl8169_private *tp = netdev_priv(dev);
1820 rtl8169_update_counters(dev);
1822 data[0] = le64_to_cpu(tp->counters.tx_packets);
1823 data[1] = le64_to_cpu(tp->counters.rx_packets);
1824 data[2] = le64_to_cpu(tp->counters.tx_errors);
1825 data[3] = le32_to_cpu(tp->counters.rx_errors);
1826 data[4] = le16_to_cpu(tp->counters.rx_missed);
1827 data[5] = le16_to_cpu(tp->counters.align_errors);
1828 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1829 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1830 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1831 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1832 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1833 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1834 data[12] = le16_to_cpu(tp->counters.tx_underun);
1837 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1841 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1846 static const struct ethtool_ops rtl8169_ethtool_ops = {
1847 .get_drvinfo = rtl8169_get_drvinfo,
1848 .get_regs_len = rtl8169_get_regs_len,
1849 .get_link = ethtool_op_get_link,
1850 .get_settings = rtl8169_get_settings,
1851 .set_settings = rtl8169_set_settings,
1852 .get_msglevel = rtl8169_get_msglevel,
1853 .set_msglevel = rtl8169_set_msglevel,
1854 .get_regs = rtl8169_get_regs,
1855 .get_wol = rtl8169_get_wol,
1856 .set_wol = rtl8169_set_wol,
1857 .get_strings = rtl8169_get_strings,
1858 .get_sset_count = rtl8169_get_sset_count,
1859 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1862 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1863 struct net_device *dev, u8 default_version)
1865 void __iomem *ioaddr = tp->mmio_addr;
1867 * The driver currently handles the 8168Bf and the 8168Be identically
1868 * but they can be identified more specifically through the test below
1871 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1873 * Same thing for the 8101Eb and the 8101Ec:
1875 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1877 static const struct rtl_mac_info {
1883 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1884 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1887 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1888 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1889 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1890 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1893 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1894 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1895 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1897 /* 8168DP family. */
1898 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1899 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1900 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1903 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1904 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1905 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1906 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1907 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1908 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1909 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1910 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1911 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1914 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1915 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1916 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1917 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1920 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1921 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1922 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1923 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1924 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1925 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1926 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1927 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1928 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1929 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1930 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1931 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1932 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1933 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1934 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1935 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1936 /* FIXME: where did these entries come from ? -- FR */
1937 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1938 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1941 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1942 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1943 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1944 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1945 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1946 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1949 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1951 const struct rtl_mac_info *p = mac_info;
1954 reg = RTL_R32(TxConfig);
1955 while ((reg & p->mask) != p->val)
1957 tp->mac_version = p->mac_version;
1959 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1960 netif_notice(tp, probe, dev,
1961 "unknown MAC, using family default\n");
1962 tp->mac_version = default_version;
1966 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1968 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1976 static void rtl_writephy_batch(struct rtl8169_private *tp,
1977 const struct phy_reg *regs, int len)
1980 rtl_writephy(tp, regs->reg, regs->val);
1985 #define PHY_READ 0x00000000
1986 #define PHY_DATA_OR 0x10000000
1987 #define PHY_DATA_AND 0x20000000
1988 #define PHY_BJMPN 0x30000000
1989 #define PHY_READ_EFUSE 0x40000000
1990 #define PHY_READ_MAC_BYTE 0x50000000
1991 #define PHY_WRITE_MAC_BYTE 0x60000000
1992 #define PHY_CLEAR_READCOUNT 0x70000000
1993 #define PHY_WRITE 0x80000000
1994 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1995 #define PHY_COMP_EQ_SKIPN 0xa0000000
1996 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1997 #define PHY_WRITE_PREVIOUS 0xc0000000
1998 #define PHY_SKIPN 0xd0000000
1999 #define PHY_DELAY_MS 0xe0000000
2000 #define PHY_WRITE_ERI_WORD 0xf0000000
2004 char version[RTL_VER_SIZE];
2010 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2012 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2014 const struct firmware *fw = rtl_fw->fw;
2015 struct fw_info *fw_info = (struct fw_info *)fw->data;
2016 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2017 char *version = rtl_fw->version;
2020 if (fw->size < FW_OPCODE_SIZE)
2023 if (!fw_info->magic) {
2024 size_t i, size, start;
2027 if (fw->size < sizeof(*fw_info))
2030 for (i = 0; i < fw->size; i++)
2031 checksum += fw->data[i];
2035 start = le32_to_cpu(fw_info->fw_start);
2036 if (start > fw->size)
2039 size = le32_to_cpu(fw_info->fw_len);
2040 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2043 memcpy(version, fw_info->version, RTL_VER_SIZE);
2045 pa->code = (__le32 *)(fw->data + start);
2048 if (fw->size % FW_OPCODE_SIZE)
2051 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2053 pa->code = (__le32 *)fw->data;
2054 pa->size = fw->size / FW_OPCODE_SIZE;
2056 version[RTL_VER_SIZE - 1] = 0;
2063 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2064 struct rtl_fw_phy_action *pa)
2069 for (index = 0; index < pa->size; index++) {
2070 u32 action = le32_to_cpu(pa->code[index]);
2071 u32 regno = (action & 0x0fff0000) >> 16;
2073 switch(action & 0xf0000000) {
2077 case PHY_READ_EFUSE:
2078 case PHY_CLEAR_READCOUNT:
2080 case PHY_WRITE_PREVIOUS:
2085 if (regno > index) {
2086 netif_err(tp, ifup, tp->dev,
2087 "Out of range of firmware\n");
2091 case PHY_READCOUNT_EQ_SKIP:
2092 if (index + 2 >= pa->size) {
2093 netif_err(tp, ifup, tp->dev,
2094 "Out of range of firmware\n");
2098 case PHY_COMP_EQ_SKIPN:
2099 case PHY_COMP_NEQ_SKIPN:
2101 if (index + 1 + regno >= pa->size) {
2102 netif_err(tp, ifup, tp->dev,
2103 "Out of range of firmware\n");
2108 case PHY_READ_MAC_BYTE:
2109 case PHY_WRITE_MAC_BYTE:
2110 case PHY_WRITE_ERI_WORD:
2112 netif_err(tp, ifup, tp->dev,
2113 "Invalid action 0x%08x\n", action);
2122 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2124 struct net_device *dev = tp->dev;
2127 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2128 netif_err(tp, ifup, dev, "invalid firwmare\n");
2132 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2138 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2140 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2144 predata = count = 0;
2146 for (index = 0; index < pa->size; ) {
2147 u32 action = le32_to_cpu(pa->code[index]);
2148 u32 data = action & 0x0000ffff;
2149 u32 regno = (action & 0x0fff0000) >> 16;
2154 switch(action & 0xf0000000) {
2156 predata = rtl_readphy(tp, regno);
2171 case PHY_READ_EFUSE:
2172 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2175 case PHY_CLEAR_READCOUNT:
2180 rtl_writephy(tp, regno, data);
2183 case PHY_READCOUNT_EQ_SKIP:
2184 index += (count == data) ? 2 : 1;
2186 case PHY_COMP_EQ_SKIPN:
2187 if (predata == data)
2191 case PHY_COMP_NEQ_SKIPN:
2192 if (predata != data)
2196 case PHY_WRITE_PREVIOUS:
2197 rtl_writephy(tp, regno, predata);
2208 case PHY_READ_MAC_BYTE:
2209 case PHY_WRITE_MAC_BYTE:
2210 case PHY_WRITE_ERI_WORD:
2217 static void rtl_release_firmware(struct rtl8169_private *tp)
2219 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2220 release_firmware(tp->rtl_fw->fw);
2223 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2226 static void rtl_apply_firmware(struct rtl8169_private *tp)
2228 struct rtl_fw *rtl_fw = tp->rtl_fw;
2230 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2231 if (!IS_ERR_OR_NULL(rtl_fw))
2232 rtl_phy_write_fw(tp, rtl_fw);
2235 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2237 if (rtl_readphy(tp, reg) != val)
2238 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2240 rtl_apply_firmware(tp);
2243 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2245 static const struct phy_reg phy_reg_init[] = {
2307 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2310 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2312 static const struct phy_reg phy_reg_init[] = {
2318 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2321 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2323 struct pci_dev *pdev = tp->pci_dev;
2325 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2326 (pdev->subsystem_device != 0xe000))
2329 rtl_writephy(tp, 0x1f, 0x0001);
2330 rtl_writephy(tp, 0x10, 0xf01b);
2331 rtl_writephy(tp, 0x1f, 0x0000);
2334 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2336 static const struct phy_reg phy_reg_init[] = {
2376 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2378 rtl8169scd_hw_phy_config_quirk(tp);
2381 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2383 static const struct phy_reg phy_reg_init[] = {
2431 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2434 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2436 static const struct phy_reg phy_reg_init[] = {
2441 rtl_writephy(tp, 0x1f, 0x0001);
2442 rtl_patchphy(tp, 0x16, 1 << 0);
2444 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2447 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2449 static const struct phy_reg phy_reg_init[] = {
2455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2458 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2460 static const struct phy_reg phy_reg_init[] = {
2468 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2471 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2473 static const struct phy_reg phy_reg_init[] = {
2479 rtl_writephy(tp, 0x1f, 0x0000);
2480 rtl_patchphy(tp, 0x14, 1 << 5);
2481 rtl_patchphy(tp, 0x0d, 1 << 5);
2483 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2486 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2488 static const struct phy_reg phy_reg_init[] = {
2508 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2510 rtl_patchphy(tp, 0x14, 1 << 5);
2511 rtl_patchphy(tp, 0x0d, 1 << 5);
2512 rtl_writephy(tp, 0x1f, 0x0000);
2515 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2517 static const struct phy_reg phy_reg_init[] = {
2535 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537 rtl_patchphy(tp, 0x16, 1 << 0);
2538 rtl_patchphy(tp, 0x14, 1 << 5);
2539 rtl_patchphy(tp, 0x0d, 1 << 5);
2540 rtl_writephy(tp, 0x1f, 0x0000);
2543 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2545 static const struct phy_reg phy_reg_init[] = {
2557 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559 rtl_patchphy(tp, 0x16, 1 << 0);
2560 rtl_patchphy(tp, 0x14, 1 << 5);
2561 rtl_patchphy(tp, 0x0d, 1 << 5);
2562 rtl_writephy(tp, 0x1f, 0x0000);
2565 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2567 rtl8168c_3_hw_phy_config(tp);
2570 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2572 static const struct phy_reg phy_reg_init_0[] = {
2573 /* Channel Estimation */
2594 * Enhance line driver power
2603 * Can not link to 1Gbps with bad cable
2604 * Decrease SNR threshold form 21.07dB to 19.04dB
2612 void __iomem *ioaddr = tp->mmio_addr;
2614 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2618 * Fine Tune Switching regulator parameter
2620 rtl_writephy(tp, 0x1f, 0x0002);
2621 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2622 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2624 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2625 static const struct phy_reg phy_reg_init[] = {
2635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637 val = rtl_readphy(tp, 0x0d);
2639 if ((val & 0x00ff) != 0x006c) {
2640 static const u32 set[] = {
2641 0x0065, 0x0066, 0x0067, 0x0068,
2642 0x0069, 0x006a, 0x006b, 0x006c
2646 rtl_writephy(tp, 0x1f, 0x0002);
2649 for (i = 0; i < ARRAY_SIZE(set); i++)
2650 rtl_writephy(tp, 0x0d, val | set[i]);
2653 static const struct phy_reg phy_reg_init[] = {
2661 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2664 /* RSET couple improve */
2665 rtl_writephy(tp, 0x1f, 0x0002);
2666 rtl_patchphy(tp, 0x0d, 0x0300);
2667 rtl_patchphy(tp, 0x0f, 0x0010);
2669 /* Fine tune PLL performance */
2670 rtl_writephy(tp, 0x1f, 0x0002);
2671 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2672 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2674 rtl_writephy(tp, 0x1f, 0x0005);
2675 rtl_writephy(tp, 0x05, 0x001b);
2677 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2679 rtl_writephy(tp, 0x1f, 0x0000);
2682 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2684 static const struct phy_reg phy_reg_init_0[] = {
2685 /* Channel Estimation */
2706 * Enhance line driver power
2715 * Can not link to 1Gbps with bad cable
2716 * Decrease SNR threshold form 21.07dB to 19.04dB
2724 void __iomem *ioaddr = tp->mmio_addr;
2726 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2728 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2729 static const struct phy_reg phy_reg_init[] = {
2740 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2742 val = rtl_readphy(tp, 0x0d);
2743 if ((val & 0x00ff) != 0x006c) {
2744 static const u32 set[] = {
2745 0x0065, 0x0066, 0x0067, 0x0068,
2746 0x0069, 0x006a, 0x006b, 0x006c
2750 rtl_writephy(tp, 0x1f, 0x0002);
2753 for (i = 0; i < ARRAY_SIZE(set); i++)
2754 rtl_writephy(tp, 0x0d, val | set[i]);
2757 static const struct phy_reg phy_reg_init[] = {
2765 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2768 /* Fine tune PLL performance */
2769 rtl_writephy(tp, 0x1f, 0x0002);
2770 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2771 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2773 /* Switching regulator Slew rate */
2774 rtl_writephy(tp, 0x1f, 0x0002);
2775 rtl_patchphy(tp, 0x0f, 0x0017);
2777 rtl_writephy(tp, 0x1f, 0x0005);
2778 rtl_writephy(tp, 0x05, 0x001b);
2780 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2782 rtl_writephy(tp, 0x1f, 0x0000);
2785 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2787 static const struct phy_reg phy_reg_init[] = {
2843 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2846 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2848 static const struct phy_reg phy_reg_init[] = {
2858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2859 rtl_patchphy(tp, 0x0d, 1 << 5);
2862 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2864 static const struct phy_reg phy_reg_init[] = {
2865 /* Enable Delay cap */
2871 /* Channel estimation fine tune */
2880 /* Update PFM & 10M TX idle timer */
2892 rtl_apply_firmware(tp);
2894 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2896 /* DCO enable for 10M IDLE Power */
2897 rtl_writephy(tp, 0x1f, 0x0007);
2898 rtl_writephy(tp, 0x1e, 0x0023);
2899 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2900 rtl_writephy(tp, 0x1f, 0x0000);
2902 /* For impedance matching */
2903 rtl_writephy(tp, 0x1f, 0x0002);
2904 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2905 rtl_writephy(tp, 0x1f, 0x0000);
2907 /* PHY auto speed down */
2908 rtl_writephy(tp, 0x1f, 0x0007);
2909 rtl_writephy(tp, 0x1e, 0x002d);
2910 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2911 rtl_writephy(tp, 0x1f, 0x0000);
2912 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2914 rtl_writephy(tp, 0x1f, 0x0005);
2915 rtl_writephy(tp, 0x05, 0x8b86);
2916 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2917 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_writephy(tp, 0x1f, 0x0005);
2920 rtl_writephy(tp, 0x05, 0x8b85);
2921 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2922 rtl_writephy(tp, 0x1f, 0x0007);
2923 rtl_writephy(tp, 0x1e, 0x0020);
2924 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2925 rtl_writephy(tp, 0x1f, 0x0006);
2926 rtl_writephy(tp, 0x00, 0x5a00);
2927 rtl_writephy(tp, 0x1f, 0x0000);
2928 rtl_writephy(tp, 0x0d, 0x0007);
2929 rtl_writephy(tp, 0x0e, 0x003c);
2930 rtl_writephy(tp, 0x0d, 0x4007);
2931 rtl_writephy(tp, 0x0e, 0x0000);
2932 rtl_writephy(tp, 0x0d, 0x0000);
2935 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2937 static const struct phy_reg phy_reg_init[] = {
2938 /* Enable Delay cap */
2947 /* Channel estimation fine tune */
2964 rtl_apply_firmware(tp);
2966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2968 /* For 4-corner performance improve */
2969 rtl_writephy(tp, 0x1f, 0x0005);
2970 rtl_writephy(tp, 0x05, 0x8b80);
2971 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2972 rtl_writephy(tp, 0x1f, 0x0000);
2974 /* PHY auto speed down */
2975 rtl_writephy(tp, 0x1f, 0x0004);
2976 rtl_writephy(tp, 0x1f, 0x0007);
2977 rtl_writephy(tp, 0x1e, 0x002d);
2978 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2979 rtl_writephy(tp, 0x1f, 0x0002);
2980 rtl_writephy(tp, 0x1f, 0x0000);
2981 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2983 /* improve 10M EEE waveform */
2984 rtl_writephy(tp, 0x1f, 0x0005);
2985 rtl_writephy(tp, 0x05, 0x8b86);
2986 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2987 rtl_writephy(tp, 0x1f, 0x0000);
2989 /* Improve 2-pair detection performance */
2990 rtl_writephy(tp, 0x1f, 0x0005);
2991 rtl_writephy(tp, 0x05, 0x8b85);
2992 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2993 rtl_writephy(tp, 0x1f, 0x0000);
2996 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2998 rtl_writephy(tp, 0x1f, 0x0005);
2999 rtl_writephy(tp, 0x05, 0x8b85);
3000 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3001 rtl_writephy(tp, 0x1f, 0x0004);
3002 rtl_writephy(tp, 0x1f, 0x0007);
3003 rtl_writephy(tp, 0x1e, 0x0020);
3004 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3005 rtl_writephy(tp, 0x1f, 0x0002);
3006 rtl_writephy(tp, 0x1f, 0x0000);
3007 rtl_writephy(tp, 0x0d, 0x0007);
3008 rtl_writephy(tp, 0x0e, 0x003c);
3009 rtl_writephy(tp, 0x0d, 0x4007);
3010 rtl_writephy(tp, 0x0e, 0x0000);
3011 rtl_writephy(tp, 0x0d, 0x0000);
3014 rtl_writephy(tp, 0x1f, 0x0003);
3015 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3016 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3017 rtl_writephy(tp, 0x1f, 0x0000);
3020 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3022 static const struct phy_reg phy_reg_init[] = {
3023 /* Channel estimation fine tune */
3028 /* Modify green table for giga & fnet */
3045 /* Modify green table for 10M */
3051 /* Disable hiimpedance detection (RTCT) */
3057 rtl_apply_firmware(tp);
3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3061 /* For 4-corner performance improve */
3062 rtl_writephy(tp, 0x1f, 0x0005);
3063 rtl_writephy(tp, 0x05, 0x8b80);
3064 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3065 rtl_writephy(tp, 0x1f, 0x0000);
3067 /* PHY auto speed down */
3068 rtl_writephy(tp, 0x1f, 0x0007);
3069 rtl_writephy(tp, 0x1e, 0x002d);
3070 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3071 rtl_writephy(tp, 0x1f, 0x0000);
3072 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3074 /* Improve 10M EEE waveform */
3075 rtl_writephy(tp, 0x1f, 0x0005);
3076 rtl_writephy(tp, 0x05, 0x8b86);
3077 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3080 /* Improve 2-pair detection performance */
3081 rtl_writephy(tp, 0x1f, 0x0005);
3082 rtl_writephy(tp, 0x05, 0x8b85);
3083 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3084 rtl_writephy(tp, 0x1f, 0x0000);
3087 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3089 rtl_apply_firmware(tp);
3091 /* For 4-corner performance improve */
3092 rtl_writephy(tp, 0x1f, 0x0005);
3093 rtl_writephy(tp, 0x05, 0x8b80);
3094 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3095 rtl_writephy(tp, 0x1f, 0x0000);
3097 /* PHY auto speed down */
3098 rtl_writephy(tp, 0x1f, 0x0007);
3099 rtl_writephy(tp, 0x1e, 0x002d);
3100 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3101 rtl_writephy(tp, 0x1f, 0x0000);
3102 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3104 /* Improve 10M EEE waveform */
3105 rtl_writephy(tp, 0x1f, 0x0005);
3106 rtl_writephy(tp, 0x05, 0x8b86);
3107 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3111 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3113 static const struct phy_reg phy_reg_init[] = {
3120 rtl_writephy(tp, 0x1f, 0x0000);
3121 rtl_patchphy(tp, 0x11, 1 << 12);
3122 rtl_patchphy(tp, 0x19, 1 << 13);
3123 rtl_patchphy(tp, 0x10, 1 << 15);
3125 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3128 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3130 static const struct phy_reg phy_reg_init[] = {
3144 /* Disable ALDPS before ram code */
3145 rtl_writephy(tp, 0x1f, 0x0000);
3146 rtl_writephy(tp, 0x18, 0x0310);
3149 rtl_apply_firmware(tp);
3151 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3154 static void rtl_hw_phy_config(struct net_device *dev)
3156 struct rtl8169_private *tp = netdev_priv(dev);
3158 rtl8169_print_mac_version(tp);
3160 switch (tp->mac_version) {
3161 case RTL_GIGA_MAC_VER_01:
3163 case RTL_GIGA_MAC_VER_02:
3164 case RTL_GIGA_MAC_VER_03:
3165 rtl8169s_hw_phy_config(tp);
3167 case RTL_GIGA_MAC_VER_04:
3168 rtl8169sb_hw_phy_config(tp);
3170 case RTL_GIGA_MAC_VER_05:
3171 rtl8169scd_hw_phy_config(tp);
3173 case RTL_GIGA_MAC_VER_06:
3174 rtl8169sce_hw_phy_config(tp);
3176 case RTL_GIGA_MAC_VER_07:
3177 case RTL_GIGA_MAC_VER_08:
3178 case RTL_GIGA_MAC_VER_09:
3179 rtl8102e_hw_phy_config(tp);
3181 case RTL_GIGA_MAC_VER_11:
3182 rtl8168bb_hw_phy_config(tp);
3184 case RTL_GIGA_MAC_VER_12:
3185 rtl8168bef_hw_phy_config(tp);
3187 case RTL_GIGA_MAC_VER_17:
3188 rtl8168bef_hw_phy_config(tp);
3190 case RTL_GIGA_MAC_VER_18:
3191 rtl8168cp_1_hw_phy_config(tp);
3193 case RTL_GIGA_MAC_VER_19:
3194 rtl8168c_1_hw_phy_config(tp);
3196 case RTL_GIGA_MAC_VER_20:
3197 rtl8168c_2_hw_phy_config(tp);
3199 case RTL_GIGA_MAC_VER_21:
3200 rtl8168c_3_hw_phy_config(tp);
3202 case RTL_GIGA_MAC_VER_22:
3203 rtl8168c_4_hw_phy_config(tp);
3205 case RTL_GIGA_MAC_VER_23:
3206 case RTL_GIGA_MAC_VER_24:
3207 rtl8168cp_2_hw_phy_config(tp);
3209 case RTL_GIGA_MAC_VER_25:
3210 rtl8168d_1_hw_phy_config(tp);
3212 case RTL_GIGA_MAC_VER_26:
3213 rtl8168d_2_hw_phy_config(tp);
3215 case RTL_GIGA_MAC_VER_27:
3216 rtl8168d_3_hw_phy_config(tp);
3218 case RTL_GIGA_MAC_VER_28:
3219 rtl8168d_4_hw_phy_config(tp);
3221 case RTL_GIGA_MAC_VER_29:
3222 case RTL_GIGA_MAC_VER_30:
3223 rtl8105e_hw_phy_config(tp);
3225 case RTL_GIGA_MAC_VER_31:
3228 case RTL_GIGA_MAC_VER_32:
3229 case RTL_GIGA_MAC_VER_33:
3230 rtl8168e_1_hw_phy_config(tp);
3232 case RTL_GIGA_MAC_VER_34:
3233 rtl8168e_2_hw_phy_config(tp);
3235 case RTL_GIGA_MAC_VER_35:
3236 rtl8168f_1_hw_phy_config(tp);
3238 case RTL_GIGA_MAC_VER_36:
3239 rtl8168f_2_hw_phy_config(tp);
3247 static void rtl_phy_work(struct rtl8169_private *tp)
3249 struct timer_list *timer = &tp->timer;
3250 void __iomem *ioaddr = tp->mmio_addr;
3251 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3253 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3255 if (tp->phy_reset_pending(tp)) {
3257 * A busy loop could burn quite a few cycles on nowadays CPU.
3258 * Let's delay the execution of the timer for a few ticks.
3264 if (tp->link_ok(ioaddr))
3267 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3269 tp->phy_reset_enable(tp);
3272 mod_timer(timer, jiffies + timeout);
3275 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3277 if (!test_and_set_bit(flag, tp->wk.flags))
3278 schedule_work(&tp->wk.work);
3281 static void rtl8169_phy_timer(unsigned long __opaque)
3283 struct net_device *dev = (struct net_device *)__opaque;
3284 struct rtl8169_private *tp = netdev_priv(dev);
3286 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3289 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3290 void __iomem *ioaddr)
3293 pci_release_regions(pdev);
3294 pci_clear_mwi(pdev);
3295 pci_disable_device(pdev);
3299 static void rtl8169_phy_reset(struct net_device *dev,
3300 struct rtl8169_private *tp)
3304 tp->phy_reset_enable(tp);
3305 for (i = 0; i < 100; i++) {
3306 if (!tp->phy_reset_pending(tp))
3310 netif_err(tp, link, dev, "PHY reset failed\n");
3313 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3315 void __iomem *ioaddr = tp->mmio_addr;
3317 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3318 (RTL_R8(PHYstatus) & TBI_Enable);
3321 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3323 void __iomem *ioaddr = tp->mmio_addr;
3325 rtl_hw_phy_config(dev);
3327 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3328 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3332 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3334 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3335 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3337 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3338 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3340 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3341 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3344 rtl8169_phy_reset(dev, tp);
3346 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3347 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3348 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3349 (tp->mii.supports_gmii ?
3350 ADVERTISED_1000baseT_Half |
3351 ADVERTISED_1000baseT_Full : 0));
3353 if (rtl_tbi_enabled(tp))
3354 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3357 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3359 void __iomem *ioaddr = tp->mmio_addr;
3363 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3364 high = addr[4] | (addr[5] << 8);
3368 RTL_W8(Cfg9346, Cfg9346_Unlock);
3370 RTL_W32(MAC4, high);
3376 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3377 const struct exgmac_reg e[] = {
3378 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3379 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3380 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3381 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3385 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3388 RTL_W8(Cfg9346, Cfg9346_Lock);
3390 rtl_unlock_work(tp);
3393 static int rtl_set_mac_address(struct net_device *dev, void *p)
3395 struct rtl8169_private *tp = netdev_priv(dev);
3396 struct sockaddr *addr = p;
3398 if (!is_valid_ether_addr(addr->sa_data))
3399 return -EADDRNOTAVAIL;
3401 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3403 rtl_rar_set(tp, dev->dev_addr);
3408 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3410 struct rtl8169_private *tp = netdev_priv(dev);
3411 struct mii_ioctl_data *data = if_mii(ifr);
3413 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3416 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3417 struct mii_ioctl_data *data, int cmd)
3421 data->phy_id = 32; /* Internal PHY */
3425 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3429 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3435 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3440 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3442 if (tp->features & RTL_FEATURE_MSI) {
3443 pci_disable_msi(pdev);
3444 tp->features &= ~RTL_FEATURE_MSI;
3448 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3450 struct mdio_ops *ops = &tp->mdio_ops;
3452 switch (tp->mac_version) {
3453 case RTL_GIGA_MAC_VER_27:
3454 ops->write = r8168dp_1_mdio_write;
3455 ops->read = r8168dp_1_mdio_read;
3457 case RTL_GIGA_MAC_VER_28:
3458 case RTL_GIGA_MAC_VER_31:
3459 ops->write = r8168dp_2_mdio_write;
3460 ops->read = r8168dp_2_mdio_read;
3463 ops->write = r8169_mdio_write;
3464 ops->read = r8169_mdio_read;
3469 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3471 void __iomem *ioaddr = tp->mmio_addr;
3473 switch (tp->mac_version) {
3474 case RTL_GIGA_MAC_VER_29:
3475 case RTL_GIGA_MAC_VER_30:
3476 case RTL_GIGA_MAC_VER_32:
3477 case RTL_GIGA_MAC_VER_33:
3478 case RTL_GIGA_MAC_VER_34:
3479 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3480 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3487 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3489 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3492 rtl_writephy(tp, 0x1f, 0x0000);
3493 rtl_writephy(tp, MII_BMCR, 0x0000);
3495 rtl_wol_suspend_quirk(tp);
3500 static void r810x_phy_power_down(struct rtl8169_private *tp)
3502 rtl_writephy(tp, 0x1f, 0x0000);
3503 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3506 static void r810x_phy_power_up(struct rtl8169_private *tp)
3508 rtl_writephy(tp, 0x1f, 0x0000);
3509 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3512 static void r810x_pll_power_down(struct rtl8169_private *tp)
3514 if (rtl_wol_pll_power_down(tp))
3517 r810x_phy_power_down(tp);
3520 static void r810x_pll_power_up(struct rtl8169_private *tp)
3522 r810x_phy_power_up(tp);
3525 static void r8168_phy_power_up(struct rtl8169_private *tp)
3527 rtl_writephy(tp, 0x1f, 0x0000);
3528 switch (tp->mac_version) {
3529 case RTL_GIGA_MAC_VER_11:
3530 case RTL_GIGA_MAC_VER_12:
3531 case RTL_GIGA_MAC_VER_17:
3532 case RTL_GIGA_MAC_VER_18:
3533 case RTL_GIGA_MAC_VER_19:
3534 case RTL_GIGA_MAC_VER_20:
3535 case RTL_GIGA_MAC_VER_21:
3536 case RTL_GIGA_MAC_VER_22:
3537 case RTL_GIGA_MAC_VER_23:
3538 case RTL_GIGA_MAC_VER_24:
3539 case RTL_GIGA_MAC_VER_25:
3540 case RTL_GIGA_MAC_VER_26:
3541 case RTL_GIGA_MAC_VER_27:
3542 case RTL_GIGA_MAC_VER_28:
3543 case RTL_GIGA_MAC_VER_31:
3544 rtl_writephy(tp, 0x0e, 0x0000);
3549 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3552 static void r8168_phy_power_down(struct rtl8169_private *tp)
3554 rtl_writephy(tp, 0x1f, 0x0000);
3555 switch (tp->mac_version) {
3556 case RTL_GIGA_MAC_VER_32:
3557 case RTL_GIGA_MAC_VER_33:
3558 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3561 case RTL_GIGA_MAC_VER_11:
3562 case RTL_GIGA_MAC_VER_12:
3563 case RTL_GIGA_MAC_VER_17:
3564 case RTL_GIGA_MAC_VER_18:
3565 case RTL_GIGA_MAC_VER_19:
3566 case RTL_GIGA_MAC_VER_20:
3567 case RTL_GIGA_MAC_VER_21:
3568 case RTL_GIGA_MAC_VER_22:
3569 case RTL_GIGA_MAC_VER_23:
3570 case RTL_GIGA_MAC_VER_24:
3571 case RTL_GIGA_MAC_VER_25:
3572 case RTL_GIGA_MAC_VER_26:
3573 case RTL_GIGA_MAC_VER_27:
3574 case RTL_GIGA_MAC_VER_28:
3575 case RTL_GIGA_MAC_VER_31:
3576 rtl_writephy(tp, 0x0e, 0x0200);
3578 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3583 static void r8168_pll_power_down(struct rtl8169_private *tp)
3585 void __iomem *ioaddr = tp->mmio_addr;
3587 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3588 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3589 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3590 r8168dp_check_dash(tp)) {
3594 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3595 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3596 (RTL_R16(CPlusCmd) & ASF)) {
3600 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3601 tp->mac_version == RTL_GIGA_MAC_VER_33)
3602 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3604 if (rtl_wol_pll_power_down(tp))
3607 r8168_phy_power_down(tp);
3609 switch (tp->mac_version) {
3610 case RTL_GIGA_MAC_VER_25:
3611 case RTL_GIGA_MAC_VER_26:
3612 case RTL_GIGA_MAC_VER_27:
3613 case RTL_GIGA_MAC_VER_28:
3614 case RTL_GIGA_MAC_VER_31:
3615 case RTL_GIGA_MAC_VER_32:
3616 case RTL_GIGA_MAC_VER_33:
3617 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3622 static void r8168_pll_power_up(struct rtl8169_private *tp)
3624 void __iomem *ioaddr = tp->mmio_addr;
3626 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3627 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3628 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3629 r8168dp_check_dash(tp)) {
3633 switch (tp->mac_version) {
3634 case RTL_GIGA_MAC_VER_25:
3635 case RTL_GIGA_MAC_VER_26:
3636 case RTL_GIGA_MAC_VER_27:
3637 case RTL_GIGA_MAC_VER_28:
3638 case RTL_GIGA_MAC_VER_31:
3639 case RTL_GIGA_MAC_VER_32:
3640 case RTL_GIGA_MAC_VER_33:
3641 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3645 r8168_phy_power_up(tp);
3648 static void rtl_generic_op(struct rtl8169_private *tp,
3649 void (*op)(struct rtl8169_private *))
3655 static void rtl_pll_power_down(struct rtl8169_private *tp)
3657 rtl_generic_op(tp, tp->pll_power_ops.down);
3660 static void rtl_pll_power_up(struct rtl8169_private *tp)
3662 rtl_generic_op(tp, tp->pll_power_ops.up);
3665 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3667 struct pll_power_ops *ops = &tp->pll_power_ops;
3669 switch (tp->mac_version) {
3670 case RTL_GIGA_MAC_VER_07:
3671 case RTL_GIGA_MAC_VER_08:
3672 case RTL_GIGA_MAC_VER_09:
3673 case RTL_GIGA_MAC_VER_10:
3674 case RTL_GIGA_MAC_VER_16:
3675 case RTL_GIGA_MAC_VER_29:
3676 case RTL_GIGA_MAC_VER_30:
3677 ops->down = r810x_pll_power_down;
3678 ops->up = r810x_pll_power_up;
3681 case RTL_GIGA_MAC_VER_11:
3682 case RTL_GIGA_MAC_VER_12:
3683 case RTL_GIGA_MAC_VER_17:
3684 case RTL_GIGA_MAC_VER_18:
3685 case RTL_GIGA_MAC_VER_19:
3686 case RTL_GIGA_MAC_VER_20:
3687 case RTL_GIGA_MAC_VER_21:
3688 case RTL_GIGA_MAC_VER_22:
3689 case RTL_GIGA_MAC_VER_23:
3690 case RTL_GIGA_MAC_VER_24:
3691 case RTL_GIGA_MAC_VER_25:
3692 case RTL_GIGA_MAC_VER_26:
3693 case RTL_GIGA_MAC_VER_27:
3694 case RTL_GIGA_MAC_VER_28:
3695 case RTL_GIGA_MAC_VER_31:
3696 case RTL_GIGA_MAC_VER_32:
3697 case RTL_GIGA_MAC_VER_33:
3698 case RTL_GIGA_MAC_VER_34:
3699 case RTL_GIGA_MAC_VER_35:
3700 case RTL_GIGA_MAC_VER_36:
3701 ops->down = r8168_pll_power_down;
3702 ops->up = r8168_pll_power_up;
3712 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3714 void __iomem *ioaddr = tp->mmio_addr;
3716 switch (tp->mac_version) {
3717 case RTL_GIGA_MAC_VER_01:
3718 case RTL_GIGA_MAC_VER_02:
3719 case RTL_GIGA_MAC_VER_03:
3720 case RTL_GIGA_MAC_VER_04:
3721 case RTL_GIGA_MAC_VER_05:
3722 case RTL_GIGA_MAC_VER_06:
3723 case RTL_GIGA_MAC_VER_10:
3724 case RTL_GIGA_MAC_VER_11:
3725 case RTL_GIGA_MAC_VER_12:
3726 case RTL_GIGA_MAC_VER_13:
3727 case RTL_GIGA_MAC_VER_14:
3728 case RTL_GIGA_MAC_VER_15:
3729 case RTL_GIGA_MAC_VER_16:
3730 case RTL_GIGA_MAC_VER_17:
3731 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3733 case RTL_GIGA_MAC_VER_18:
3734 case RTL_GIGA_MAC_VER_19:
3735 case RTL_GIGA_MAC_VER_20:
3736 case RTL_GIGA_MAC_VER_21:
3737 case RTL_GIGA_MAC_VER_22:
3738 case RTL_GIGA_MAC_VER_23:
3739 case RTL_GIGA_MAC_VER_24:
3740 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3743 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3748 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3750 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3753 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3755 void __iomem *ioaddr = tp->mmio_addr;
3757 RTL_W8(Cfg9346, Cfg9346_Unlock);
3758 rtl_generic_op(tp, tp->jumbo_ops.enable);
3759 RTL_W8(Cfg9346, Cfg9346_Lock);
3762 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3764 void __iomem *ioaddr = tp->mmio_addr;
3766 RTL_W8(Cfg9346, Cfg9346_Unlock);
3767 rtl_generic_op(tp, tp->jumbo_ops.disable);
3768 RTL_W8(Cfg9346, Cfg9346_Lock);
3771 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3773 void __iomem *ioaddr = tp->mmio_addr;
3775 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3776 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3777 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3780 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3782 void __iomem *ioaddr = tp->mmio_addr;
3784 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3785 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3786 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3789 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3791 void __iomem *ioaddr = tp->mmio_addr;
3793 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3796 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3798 void __iomem *ioaddr = tp->mmio_addr;
3800 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3803 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3805 void __iomem *ioaddr = tp->mmio_addr;
3807 RTL_W8(MaxTxPacketSize, 0x3f);
3808 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3809 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3810 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3813 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3815 void __iomem *ioaddr = tp->mmio_addr;
3817 RTL_W8(MaxTxPacketSize, 0x0c);
3818 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3819 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3820 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3823 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3825 rtl_tx_performance_tweak(tp->pci_dev,
3826 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3829 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3831 rtl_tx_performance_tweak(tp->pci_dev,
3832 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3835 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3837 void __iomem *ioaddr = tp->mmio_addr;
3839 r8168b_0_hw_jumbo_enable(tp);
3841 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3844 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3846 void __iomem *ioaddr = tp->mmio_addr;
3848 r8168b_0_hw_jumbo_disable(tp);
3850 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3853 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3855 struct jumbo_ops *ops = &tp->jumbo_ops;
3857 switch (tp->mac_version) {
3858 case RTL_GIGA_MAC_VER_11:
3859 ops->disable = r8168b_0_hw_jumbo_disable;
3860 ops->enable = r8168b_0_hw_jumbo_enable;
3862 case RTL_GIGA_MAC_VER_12:
3863 case RTL_GIGA_MAC_VER_17:
3864 ops->disable = r8168b_1_hw_jumbo_disable;
3865 ops->enable = r8168b_1_hw_jumbo_enable;
3867 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3868 case RTL_GIGA_MAC_VER_19:
3869 case RTL_GIGA_MAC_VER_20:
3870 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3871 case RTL_GIGA_MAC_VER_22:
3872 case RTL_GIGA_MAC_VER_23:
3873 case RTL_GIGA_MAC_VER_24:
3874 case RTL_GIGA_MAC_VER_25:
3875 case RTL_GIGA_MAC_VER_26:
3876 ops->disable = r8168c_hw_jumbo_disable;
3877 ops->enable = r8168c_hw_jumbo_enable;
3879 case RTL_GIGA_MAC_VER_27:
3880 case RTL_GIGA_MAC_VER_28:
3881 ops->disable = r8168dp_hw_jumbo_disable;
3882 ops->enable = r8168dp_hw_jumbo_enable;
3884 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3885 case RTL_GIGA_MAC_VER_32:
3886 case RTL_GIGA_MAC_VER_33:
3887 case RTL_GIGA_MAC_VER_34:
3888 ops->disable = r8168e_hw_jumbo_disable;
3889 ops->enable = r8168e_hw_jumbo_enable;
3893 * No action needed for jumbo frames with 8169.
3894 * No jumbo for 810x at all.
3897 ops->disable = NULL;
3903 static void rtl_hw_reset(struct rtl8169_private *tp)
3905 void __iomem *ioaddr = tp->mmio_addr;
3908 /* Soft reset the chip. */
3909 RTL_W8(ChipCmd, CmdReset);
3911 /* Check that the chip has finished the reset. */
3912 for (i = 0; i < 100; i++) {
3913 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3919 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3921 struct rtl_fw *rtl_fw;
3925 name = rtl_lookup_firmware_name(tp);
3927 goto out_no_firmware;
3929 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3933 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3937 rc = rtl_check_firmware(tp, rtl_fw);
3939 goto err_release_firmware;
3941 tp->rtl_fw = rtl_fw;
3945 err_release_firmware:
3946 release_firmware(rtl_fw->fw);
3950 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3957 static void rtl_request_firmware(struct rtl8169_private *tp)
3959 if (IS_ERR(tp->rtl_fw))
3960 rtl_request_uncached_firmware(tp);
3963 static void rtl_rx_close(struct rtl8169_private *tp)
3965 void __iomem *ioaddr = tp->mmio_addr;
3967 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3970 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3972 void __iomem *ioaddr = tp->mmio_addr;
3974 /* Disable interrupts */
3975 rtl8169_irq_mask_and_ack(tp);
3979 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3980 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3981 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3982 while (RTL_R8(TxPoll) & NPQ)
3984 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3985 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3986 tp->mac_version == RTL_GIGA_MAC_VER_36) {
3987 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3988 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3991 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3998 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4000 void __iomem *ioaddr = tp->mmio_addr;
4002 /* Set DMA burst size and Interframe Gap Time */
4003 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4004 (InterFrameGap << TxInterFrameGapShift));
4007 static void rtl_hw_start(struct net_device *dev)
4009 struct rtl8169_private *tp = netdev_priv(dev);
4013 rtl_irq_enable_all(tp);
4016 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4017 void __iomem *ioaddr)
4020 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4021 * register to be written before TxDescAddrLow to work.
4022 * Switching from MMIO to I/O access fixes the issue as well.
4024 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4025 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4026 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4027 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4030 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4034 cmd = RTL_R16(CPlusCmd);
4035 RTL_W16(CPlusCmd, cmd);
4039 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4041 /* Low hurts. Let's disable the filtering. */
4042 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4045 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4047 static const struct rtl_cfg2_info {
4052 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4053 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4054 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4055 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4057 const struct rtl_cfg2_info *p = cfg2_info;
4061 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4062 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4063 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4064 RTL_W32(0x7c, p->val);
4070 static void rtl_set_rx_mode(struct net_device *dev)
4072 struct rtl8169_private *tp = netdev_priv(dev);
4073 void __iomem *ioaddr = tp->mmio_addr;
4074 u32 mc_filter[2]; /* Multicast hash filter */
4078 if (dev->flags & IFF_PROMISC) {
4079 /* Unconditionally log net taps. */
4080 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4082 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4084 mc_filter[1] = mc_filter[0] = 0xffffffff;
4085 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4086 (dev->flags & IFF_ALLMULTI)) {
4087 /* Too many to filter perfectly -- accept all multicasts. */
4088 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4089 mc_filter[1] = mc_filter[0] = 0xffffffff;
4091 struct netdev_hw_addr *ha;
4093 rx_mode = AcceptBroadcast | AcceptMyPhys;
4094 mc_filter[1] = mc_filter[0] = 0;
4095 netdev_for_each_mc_addr(ha, dev) {
4096 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4097 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4098 rx_mode |= AcceptMulticast;
4102 if (dev->features & NETIF_F_RXALL)
4103 rx_mode |= (AcceptErr | AcceptRunt);
4105 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4107 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4108 u32 data = mc_filter[0];
4110 mc_filter[0] = swab32(mc_filter[1]);
4111 mc_filter[1] = swab32(data);
4114 RTL_W32(MAR0 + 4, mc_filter[1]);
4115 RTL_W32(MAR0 + 0, mc_filter[0]);
4117 RTL_W32(RxConfig, tmp);
4120 static void rtl_hw_start_8169(struct net_device *dev)
4122 struct rtl8169_private *tp = netdev_priv(dev);
4123 void __iomem *ioaddr = tp->mmio_addr;
4124 struct pci_dev *pdev = tp->pci_dev;
4126 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4127 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4128 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4131 RTL_W8(Cfg9346, Cfg9346_Unlock);
4132 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4133 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4134 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4135 tp->mac_version == RTL_GIGA_MAC_VER_04)
4136 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4140 RTL_W8(EarlyTxThres, NoEarlyTx);
4142 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4144 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4145 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4146 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4147 tp->mac_version == RTL_GIGA_MAC_VER_04)
4148 rtl_set_rx_tx_config_registers(tp);
4150 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4152 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4153 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4154 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4155 "Bit-3 and bit-14 MUST be 1\n");
4156 tp->cp_cmd |= (1 << 14);
4159 RTL_W16(CPlusCmd, tp->cp_cmd);
4161 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4164 * Undocumented corner. Supposedly:
4165 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4167 RTL_W16(IntrMitigate, 0x0000);
4169 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4171 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4172 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4173 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4174 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4175 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4176 rtl_set_rx_tx_config_registers(tp);
4179 RTL_W8(Cfg9346, Cfg9346_Lock);
4181 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4184 RTL_W32(RxMissed, 0);
4186 rtl_set_rx_mode(dev);
4188 /* no early-rx interrupts */
4189 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4192 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4196 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4197 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4200 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4202 rtl_csi_access_enable(ioaddr, 0x17000000);
4205 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4207 rtl_csi_access_enable(ioaddr, 0x27000000);
4211 unsigned int offset;
4216 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4221 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4222 rtl_ephy_write(ioaddr, e->offset, w);
4227 static void rtl_disable_clock_request(struct pci_dev *pdev)
4229 int cap = pci_pcie_cap(pdev);
4234 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4235 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4236 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4240 static void rtl_enable_clock_request(struct pci_dev *pdev)
4242 int cap = pci_pcie_cap(pdev);
4247 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4248 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4249 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4253 #define R8168_CPCMD_QUIRK_MASK (\
4264 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4266 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4268 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4270 rtl_tx_performance_tweak(pdev,
4271 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4274 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4276 rtl_hw_start_8168bb(ioaddr, pdev);
4278 RTL_W8(MaxTxPacketSize, TxPacketMax);
4280 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4283 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4285 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4287 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4289 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4291 rtl_disable_clock_request(pdev);
4293 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4296 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4298 static const struct ephy_info e_info_8168cp[] = {
4299 { 0x01, 0, 0x0001 },
4300 { 0x02, 0x0800, 0x1000 },
4301 { 0x03, 0, 0x0042 },
4302 { 0x06, 0x0080, 0x0000 },
4306 rtl_csi_access_enable_2(ioaddr);
4308 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4310 __rtl_hw_start_8168cp(ioaddr, pdev);
4313 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4315 rtl_csi_access_enable_2(ioaddr);
4317 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4319 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4321 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4324 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4326 rtl_csi_access_enable_2(ioaddr);
4328 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4331 RTL_W8(DBG_REG, 0x20);
4333 RTL_W8(MaxTxPacketSize, TxPacketMax);
4335 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4337 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4340 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4342 static const struct ephy_info e_info_8168c_1[] = {
4343 { 0x02, 0x0800, 0x1000 },
4344 { 0x03, 0, 0x0002 },
4345 { 0x06, 0x0080, 0x0000 }
4348 rtl_csi_access_enable_2(ioaddr);
4350 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4352 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4354 __rtl_hw_start_8168cp(ioaddr, pdev);
4357 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4359 static const struct ephy_info e_info_8168c_2[] = {
4360 { 0x01, 0, 0x0001 },
4361 { 0x03, 0x0400, 0x0220 }
4364 rtl_csi_access_enable_2(ioaddr);
4366 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4368 __rtl_hw_start_8168cp(ioaddr, pdev);
4371 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4373 rtl_hw_start_8168c_2(ioaddr, pdev);
4376 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4378 rtl_csi_access_enable_2(ioaddr);
4380 __rtl_hw_start_8168cp(ioaddr, pdev);
4383 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4385 rtl_csi_access_enable_2(ioaddr);
4387 rtl_disable_clock_request(pdev);
4389 RTL_W8(MaxTxPacketSize, TxPacketMax);
4391 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4393 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4396 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4398 rtl_csi_access_enable_1(ioaddr);
4400 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4402 RTL_W8(MaxTxPacketSize, TxPacketMax);
4404 rtl_disable_clock_request(pdev);
4407 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4409 static const struct ephy_info e_info_8168d_4[] = {
4411 { 0x19, 0x20, 0x50 },
4416 rtl_csi_access_enable_1(ioaddr);
4418 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4420 RTL_W8(MaxTxPacketSize, TxPacketMax);
4422 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4423 const struct ephy_info *e = e_info_8168d_4 + i;
4426 w = rtl_ephy_read(ioaddr, e->offset);
4427 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4430 rtl_enable_clock_request(pdev);
4433 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4435 static const struct ephy_info e_info_8168e_1[] = {
4436 { 0x00, 0x0200, 0x0100 },
4437 { 0x00, 0x0000, 0x0004 },
4438 { 0x06, 0x0002, 0x0001 },
4439 { 0x06, 0x0000, 0x0030 },
4440 { 0x07, 0x0000, 0x2000 },
4441 { 0x00, 0x0000, 0x0020 },
4442 { 0x03, 0x5800, 0x2000 },
4443 { 0x03, 0x0000, 0x0001 },
4444 { 0x01, 0x0800, 0x1000 },
4445 { 0x07, 0x0000, 0x4000 },
4446 { 0x1e, 0x0000, 0x2000 },
4447 { 0x19, 0xffff, 0xfe6c },
4448 { 0x0a, 0x0000, 0x0040 }
4451 rtl_csi_access_enable_2(ioaddr);
4453 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4455 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4457 RTL_W8(MaxTxPacketSize, TxPacketMax);
4459 rtl_disable_clock_request(pdev);
4461 /* Reset tx FIFO pointer */
4462 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4463 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4465 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4468 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4470 static const struct ephy_info e_info_8168e_2[] = {
4471 { 0x09, 0x0000, 0x0080 },
4472 { 0x19, 0x0000, 0x0224 }
4475 rtl_csi_access_enable_1(ioaddr);
4477 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4479 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4481 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4482 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4483 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4484 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4485 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4486 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4487 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4488 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4491 RTL_W8(MaxTxPacketSize, EarlySize);
4493 rtl_disable_clock_request(pdev);
4495 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4496 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4498 /* Adjust EEE LED frequency */
4499 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4501 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4502 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4503 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4506 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4508 static const struct ephy_info e_info_8168f_1[] = {
4509 { 0x06, 0x00c0, 0x0020 },
4510 { 0x08, 0x0001, 0x0002 },
4511 { 0x09, 0x0000, 0x0080 },
4512 { 0x19, 0x0000, 0x0224 }
4515 rtl_csi_access_enable_1(ioaddr);
4517 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4519 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4521 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4522 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4523 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4524 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4525 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4526 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4527 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4528 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4529 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4530 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4531 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4534 RTL_W8(MaxTxPacketSize, EarlySize);
4536 rtl_disable_clock_request(pdev);
4538 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4539 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4541 /* Adjust EEE LED frequency */
4542 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4544 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4545 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4546 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4549 static void rtl_hw_start_8168(struct net_device *dev)
4551 struct rtl8169_private *tp = netdev_priv(dev);
4552 void __iomem *ioaddr = tp->mmio_addr;
4553 struct pci_dev *pdev = tp->pci_dev;
4555 RTL_W8(Cfg9346, Cfg9346_Unlock);
4557 RTL_W8(MaxTxPacketSize, TxPacketMax);
4559 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4561 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4563 RTL_W16(CPlusCmd, tp->cp_cmd);
4565 RTL_W16(IntrMitigate, 0x5151);
4567 /* Work around for RxFIFO overflow. */
4568 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4569 tp->event_slow |= RxFIFOOver | PCSTimeout;
4570 tp->event_slow &= ~RxOverflow;
4573 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4575 rtl_set_rx_mode(dev);
4577 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4578 (InterFrameGap << TxInterFrameGapShift));
4582 switch (tp->mac_version) {
4583 case RTL_GIGA_MAC_VER_11:
4584 rtl_hw_start_8168bb(ioaddr, pdev);
4587 case RTL_GIGA_MAC_VER_12:
4588 case RTL_GIGA_MAC_VER_17:
4589 rtl_hw_start_8168bef(ioaddr, pdev);
4592 case RTL_GIGA_MAC_VER_18:
4593 rtl_hw_start_8168cp_1(ioaddr, pdev);
4596 case RTL_GIGA_MAC_VER_19:
4597 rtl_hw_start_8168c_1(ioaddr, pdev);
4600 case RTL_GIGA_MAC_VER_20:
4601 rtl_hw_start_8168c_2(ioaddr, pdev);
4604 case RTL_GIGA_MAC_VER_21:
4605 rtl_hw_start_8168c_3(ioaddr, pdev);
4608 case RTL_GIGA_MAC_VER_22:
4609 rtl_hw_start_8168c_4(ioaddr, pdev);
4612 case RTL_GIGA_MAC_VER_23:
4613 rtl_hw_start_8168cp_2(ioaddr, pdev);
4616 case RTL_GIGA_MAC_VER_24:
4617 rtl_hw_start_8168cp_3(ioaddr, pdev);
4620 case RTL_GIGA_MAC_VER_25:
4621 case RTL_GIGA_MAC_VER_26:
4622 case RTL_GIGA_MAC_VER_27:
4623 rtl_hw_start_8168d(ioaddr, pdev);
4626 case RTL_GIGA_MAC_VER_28:
4627 rtl_hw_start_8168d_4(ioaddr, pdev);
4630 case RTL_GIGA_MAC_VER_31:
4631 rtl_hw_start_8168dp(ioaddr, pdev);
4634 case RTL_GIGA_MAC_VER_32:
4635 case RTL_GIGA_MAC_VER_33:
4636 rtl_hw_start_8168e_1(ioaddr, pdev);
4638 case RTL_GIGA_MAC_VER_34:
4639 rtl_hw_start_8168e_2(ioaddr, pdev);
4642 case RTL_GIGA_MAC_VER_35:
4643 case RTL_GIGA_MAC_VER_36:
4644 rtl_hw_start_8168f_1(ioaddr, pdev);
4648 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4649 dev->name, tp->mac_version);
4653 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4655 RTL_W8(Cfg9346, Cfg9346_Lock);
4657 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4660 #define R810X_CPCMD_QUIRK_MASK (\
4671 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4673 static const struct ephy_info e_info_8102e_1[] = {
4674 { 0x01, 0, 0x6e65 },
4675 { 0x02, 0, 0x091f },
4676 { 0x03, 0, 0xc2f9 },
4677 { 0x06, 0, 0xafb5 },
4678 { 0x07, 0, 0x0e00 },
4679 { 0x19, 0, 0xec80 },
4680 { 0x01, 0, 0x2e65 },
4685 rtl_csi_access_enable_2(ioaddr);
4687 RTL_W8(DBG_REG, FIX_NAK_1);
4689 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4692 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4693 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4695 cfg1 = RTL_R8(Config1);
4696 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4697 RTL_W8(Config1, cfg1 & ~LEDS0);
4699 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4702 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4704 rtl_csi_access_enable_2(ioaddr);
4706 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4708 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4709 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4712 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4714 rtl_hw_start_8102e_2(ioaddr, pdev);
4716 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4719 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4721 static const struct ephy_info e_info_8105e_1[] = {
4722 { 0x07, 0, 0x4000 },
4723 { 0x19, 0, 0x0200 },
4724 { 0x19, 0, 0x0020 },
4725 { 0x1e, 0, 0x2000 },
4726 { 0x03, 0, 0x0001 },
4727 { 0x19, 0, 0x0100 },
4728 { 0x19, 0, 0x0004 },
4732 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4733 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4735 /* Disable Early Tally Counter */
4736 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4738 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4739 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4741 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4744 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4746 rtl_hw_start_8105e_1(ioaddr, pdev);
4747 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4750 static void rtl_hw_start_8101(struct net_device *dev)
4752 struct rtl8169_private *tp = netdev_priv(dev);
4753 void __iomem *ioaddr = tp->mmio_addr;
4754 struct pci_dev *pdev = tp->pci_dev;
4756 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4757 tp->event_slow &= ~RxFIFOOver;
4759 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4760 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4761 int cap = pci_pcie_cap(pdev);
4764 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4765 PCI_EXP_DEVCTL_NOSNOOP_EN);
4769 RTL_W8(Cfg9346, Cfg9346_Unlock);
4771 switch (tp->mac_version) {
4772 case RTL_GIGA_MAC_VER_07:
4773 rtl_hw_start_8102e_1(ioaddr, pdev);
4776 case RTL_GIGA_MAC_VER_08:
4777 rtl_hw_start_8102e_3(ioaddr, pdev);
4780 case RTL_GIGA_MAC_VER_09:
4781 rtl_hw_start_8102e_2(ioaddr, pdev);
4784 case RTL_GIGA_MAC_VER_29:
4785 rtl_hw_start_8105e_1(ioaddr, pdev);
4787 case RTL_GIGA_MAC_VER_30:
4788 rtl_hw_start_8105e_2(ioaddr, pdev);
4792 RTL_W8(Cfg9346, Cfg9346_Lock);
4794 RTL_W8(MaxTxPacketSize, TxPacketMax);
4796 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4798 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4799 RTL_W16(CPlusCmd, tp->cp_cmd);
4801 RTL_W16(IntrMitigate, 0x0000);
4803 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4805 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4806 rtl_set_rx_tx_config_registers(tp);
4810 rtl_set_rx_mode(dev);
4812 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4815 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4817 struct rtl8169_private *tp = netdev_priv(dev);
4819 if (new_mtu < ETH_ZLEN ||
4820 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4823 if (new_mtu > ETH_DATA_LEN)
4824 rtl_hw_jumbo_enable(tp);
4826 rtl_hw_jumbo_disable(tp);
4829 netdev_update_features(dev);
4834 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4836 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4837 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4840 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4841 void **data_buff, struct RxDesc *desc)
4843 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4848 rtl8169_make_unusable_by_asic(desc);
4851 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4853 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4855 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4858 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4861 desc->addr = cpu_to_le64(mapping);
4863 rtl8169_mark_to_asic(desc, rx_buf_sz);
4866 static inline void *rtl8169_align(void *data)
4868 return (void *)ALIGN((long)data, 16);
4871 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4872 struct RxDesc *desc)
4876 struct device *d = &tp->pci_dev->dev;
4877 struct net_device *dev = tp->dev;
4878 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4880 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4884 if (rtl8169_align(data) != data) {
4886 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4891 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4893 if (unlikely(dma_mapping_error(d, mapping))) {
4894 if (net_ratelimit())
4895 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4899 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4907 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4911 for (i = 0; i < NUM_RX_DESC; i++) {
4912 if (tp->Rx_databuff[i]) {
4913 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4914 tp->RxDescArray + i);
4919 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4921 desc->opts1 |= cpu_to_le32(RingEnd);
4924 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4928 for (i = 0; i < NUM_RX_DESC; i++) {
4931 if (tp->Rx_databuff[i])
4934 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4936 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4939 tp->Rx_databuff[i] = data;
4942 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4946 rtl8169_rx_clear(tp);
4950 static int rtl8169_init_ring(struct net_device *dev)
4952 struct rtl8169_private *tp = netdev_priv(dev);
4954 rtl8169_init_ring_indexes(tp);
4956 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4957 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4959 return rtl8169_rx_fill(tp);
4962 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4963 struct TxDesc *desc)
4965 unsigned int len = tx_skb->len;
4967 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4975 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4980 for (i = 0; i < n; i++) {
4981 unsigned int entry = (start + i) % NUM_TX_DESC;
4982 struct ring_info *tx_skb = tp->tx_skb + entry;
4983 unsigned int len = tx_skb->len;
4986 struct sk_buff *skb = tx_skb->skb;
4988 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4989 tp->TxDescArray + entry);
4991 tp->dev->stats.tx_dropped++;
4999 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5001 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5002 tp->cur_tx = tp->dirty_tx = 0;
5003 netdev_reset_queue(tp->dev);
5006 static void rtl_reset_work(struct rtl8169_private *tp)
5008 struct net_device *dev = tp->dev;
5011 napi_disable(&tp->napi);
5012 netif_stop_queue(dev);
5013 synchronize_sched();
5015 rtl8169_hw_reset(tp);
5017 for (i = 0; i < NUM_RX_DESC; i++)
5018 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5020 rtl8169_tx_clear(tp);
5021 rtl8169_init_ring_indexes(tp);
5023 napi_enable(&tp->napi);
5025 netif_wake_queue(dev);
5026 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5029 static void rtl8169_tx_timeout(struct net_device *dev)
5031 struct rtl8169_private *tp = netdev_priv(dev);
5033 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5036 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5039 struct skb_shared_info *info = skb_shinfo(skb);
5040 unsigned int cur_frag, entry;
5041 struct TxDesc * uninitialized_var(txd);
5042 struct device *d = &tp->pci_dev->dev;
5045 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5046 const skb_frag_t *frag = info->frags + cur_frag;
5051 entry = (entry + 1) % NUM_TX_DESC;
5053 txd = tp->TxDescArray + entry;
5054 len = skb_frag_size(frag);
5055 addr = skb_frag_address(frag);
5056 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5057 if (unlikely(dma_mapping_error(d, mapping))) {
5058 if (net_ratelimit())
5059 netif_err(tp, drv, tp->dev,
5060 "Failed to map TX fragments DMA!\n");
5064 /* Anti gcc 2.95.3 bugware (sic) */
5065 status = opts[0] | len |
5066 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5068 txd->opts1 = cpu_to_le32(status);
5069 txd->opts2 = cpu_to_le32(opts[1]);
5070 txd->addr = cpu_to_le64(mapping);
5072 tp->tx_skb[entry].len = len;
5076 tp->tx_skb[entry].skb = skb;
5077 txd->opts1 |= cpu_to_le32(LastFrag);
5083 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5087 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5088 struct sk_buff *skb, u32 *opts)
5090 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5091 u32 mss = skb_shinfo(skb)->gso_size;
5092 int offset = info->opts_offset;
5096 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5097 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5098 const struct iphdr *ip = ip_hdr(skb);
5100 if (ip->protocol == IPPROTO_TCP)
5101 opts[offset] |= info->checksum.tcp;
5102 else if (ip->protocol == IPPROTO_UDP)
5103 opts[offset] |= info->checksum.udp;
5109 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5110 struct net_device *dev)
5112 struct rtl8169_private *tp = netdev_priv(dev);
5113 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5114 struct TxDesc *txd = tp->TxDescArray + entry;
5115 void __iomem *ioaddr = tp->mmio_addr;
5116 struct device *d = &tp->pci_dev->dev;
5122 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5123 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5127 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5130 len = skb_headlen(skb);
5131 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5132 if (unlikely(dma_mapping_error(d, mapping))) {
5133 if (net_ratelimit())
5134 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5138 tp->tx_skb[entry].len = len;
5139 txd->addr = cpu_to_le64(mapping);
5141 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5144 rtl8169_tso_csum(tp, skb, opts);
5146 frags = rtl8169_xmit_frags(tp, skb, opts);
5150 opts[0] |= FirstFrag;
5152 opts[0] |= FirstFrag | LastFrag;
5153 tp->tx_skb[entry].skb = skb;
5156 txd->opts2 = cpu_to_le32(opts[1]);
5158 netdev_sent_queue(dev, skb->len);
5160 skb_tx_timestamp(skb);
5164 /* Anti gcc 2.95.3 bugware (sic) */
5165 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5166 txd->opts1 = cpu_to_le32(status);
5168 tp->cur_tx += frags + 1;
5172 RTL_W8(TxPoll, NPQ);
5176 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5177 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5178 * not miss a ring update when it notices a stopped queue.
5181 netif_stop_queue(dev);
5182 /* Sync with rtl_tx:
5183 * - publish queue status and cur_tx ring index (write barrier)
5184 * - refresh dirty_tx ring index (read barrier).
5185 * May the current thread have a pessimistic view of the ring
5186 * status and forget to wake up queue, a racing rtl_tx thread
5190 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5191 netif_wake_queue(dev);
5194 return NETDEV_TX_OK;
5197 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5200 dev->stats.tx_dropped++;
5201 return NETDEV_TX_OK;
5204 netif_stop_queue(dev);
5205 dev->stats.tx_dropped++;
5206 return NETDEV_TX_BUSY;
5209 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5211 struct rtl8169_private *tp = netdev_priv(dev);
5212 struct pci_dev *pdev = tp->pci_dev;
5213 u16 pci_status, pci_cmd;
5215 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5216 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5218 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5219 pci_cmd, pci_status);
5222 * The recovery sequence below admits a very elaborated explanation:
5223 * - it seems to work;
5224 * - I did not see what else could be done;
5225 * - it makes iop3xx happy.
5227 * Feel free to adjust to your needs.
5229 if (pdev->broken_parity_status)
5230 pci_cmd &= ~PCI_COMMAND_PARITY;
5232 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5234 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5236 pci_write_config_word(pdev, PCI_STATUS,
5237 pci_status & (PCI_STATUS_DETECTED_PARITY |
5238 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5239 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5241 /* The infamous DAC f*ckup only happens at boot time */
5242 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5243 void __iomem *ioaddr = tp->mmio_addr;
5245 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5246 tp->cp_cmd &= ~PCIDAC;
5247 RTL_W16(CPlusCmd, tp->cp_cmd);
5248 dev->features &= ~NETIF_F_HIGHDMA;
5251 rtl8169_hw_reset(tp);
5253 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5261 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5263 struct rtl8169_stats *tx_stats = &tp->tx_stats;
5264 unsigned int dirty_tx, tx_left;
5265 struct rtl_txc txc = { 0, 0 };
5267 dirty_tx = tp->dirty_tx;
5269 tx_left = tp->cur_tx - dirty_tx;
5271 while (tx_left > 0) {
5272 unsigned int entry = dirty_tx % NUM_TX_DESC;
5273 struct ring_info *tx_skb = tp->tx_skb + entry;
5277 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5278 if (status & DescOwn)
5281 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5282 tp->TxDescArray + entry);
5283 if (status & LastFrag) {
5284 struct sk_buff *skb = tx_skb->skb;
5287 txc.bytes += skb->len;
5295 u64_stats_update_begin(&tx_stats->syncp);
5296 tx_stats->packets += txc.packets;
5297 tx_stats->bytes += txc.bytes;
5298 u64_stats_update_end(&tx_stats->syncp);
5300 netdev_completed_queue(dev, txc.packets, txc.bytes);
5302 if (tp->dirty_tx != dirty_tx) {
5303 tp->dirty_tx = dirty_tx;
5304 /* Sync with rtl8169_start_xmit:
5305 * - publish dirty_tx ring index (write barrier)
5306 * - refresh cur_tx ring index and queue status (read barrier)
5307 * May the current thread miss the stopped queue condition,
5308 * a racing xmit thread can only have a right view of the
5312 if (netif_queue_stopped(dev) &&
5313 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5314 netif_wake_queue(dev);
5317 * 8168 hack: TxPoll requests are lost when the Tx packets are
5318 * too close. Let's kick an extra TxPoll request when a burst
5319 * of start_xmit activity is detected (if it is not detected,
5320 * it is slow enough). -- FR
5322 if (tp->cur_tx != dirty_tx) {
5323 void __iomem *ioaddr = tp->mmio_addr;
5325 RTL_W8(TxPoll, NPQ);
5330 static inline int rtl8169_fragmented_frame(u32 status)
5332 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5335 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5337 u32 status = opts1 & RxProtoMask;
5339 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5340 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5341 skb->ip_summed = CHECKSUM_UNNECESSARY;
5343 skb_checksum_none_assert(skb);
5346 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5347 struct rtl8169_private *tp,
5351 struct sk_buff *skb;
5352 struct device *d = &tp->pci_dev->dev;
5354 data = rtl8169_align(data);
5355 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5357 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5359 memcpy(skb->data, data, pkt_size);
5360 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5365 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5367 unsigned int cur_rx, rx_left;
5370 cur_rx = tp->cur_rx;
5371 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5372 rx_left = min(rx_left, budget);
5374 for (; rx_left > 0; rx_left--, cur_rx++) {
5375 unsigned int entry = cur_rx % NUM_RX_DESC;
5376 struct RxDesc *desc = tp->RxDescArray + entry;
5380 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5382 if (status & DescOwn)
5384 if (unlikely(status & RxRES)) {
5385 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5387 dev->stats.rx_errors++;
5388 if (status & (RxRWT | RxRUNT))
5389 dev->stats.rx_length_errors++;
5391 dev->stats.rx_crc_errors++;
5392 if (status & RxFOVF) {
5393 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5394 dev->stats.rx_fifo_errors++;
5396 if ((status & (RxRUNT | RxCRC)) &&
5397 !(status & (RxRWT | RxFOVF)) &&
5398 (dev->features & NETIF_F_RXALL))
5401 rtl8169_mark_to_asic(desc, rx_buf_sz);
5403 struct sk_buff *skb;
5408 addr = le64_to_cpu(desc->addr);
5409 if (likely(!(dev->features & NETIF_F_RXFCS)))
5410 pkt_size = (status & 0x00003fff) - 4;
5412 pkt_size = status & 0x00003fff;
5415 * The driver does not support incoming fragmented
5416 * frames. They are seen as a symptom of over-mtu
5419 if (unlikely(rtl8169_fragmented_frame(status))) {
5420 dev->stats.rx_dropped++;
5421 dev->stats.rx_length_errors++;
5422 rtl8169_mark_to_asic(desc, rx_buf_sz);
5426 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5427 tp, pkt_size, addr);
5428 rtl8169_mark_to_asic(desc, rx_buf_sz);
5430 dev->stats.rx_dropped++;
5434 rtl8169_rx_csum(skb, status);
5435 skb_put(skb, pkt_size);
5436 skb->protocol = eth_type_trans(skb, dev);
5438 rtl8169_rx_vlan_tag(desc, skb);
5440 napi_gro_receive(&tp->napi, skb);
5442 u64_stats_update_begin(&tp->rx_stats.syncp);
5443 tp->rx_stats.packets++;
5444 tp->rx_stats.bytes += pkt_size;
5445 u64_stats_update_end(&tp->rx_stats.syncp);
5448 /* Work around for AMD plateform. */
5449 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5450 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5456 count = cur_rx - tp->cur_rx;
5457 tp->cur_rx = cur_rx;
5459 tp->dirty_rx += count;
5464 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5466 struct net_device *dev = dev_instance;
5467 struct rtl8169_private *tp = netdev_priv(dev);
5471 status = rtl_get_events(tp);
5472 if (status && status != 0xffff) {
5473 status &= RTL_EVENT_NAPI | tp->event_slow;
5477 rtl_irq_disable(tp);
5478 napi_schedule(&tp->napi);
5481 return IRQ_RETVAL(handled);
5485 * Workqueue context.
5487 static void rtl_slow_event_work(struct rtl8169_private *tp)
5489 struct net_device *dev = tp->dev;
5492 status = rtl_get_events(tp) & tp->event_slow;
5493 rtl_ack_events(tp, status);
5495 if (unlikely(status & RxFIFOOver)) {
5496 switch (tp->mac_version) {
5497 /* Work around for rx fifo overflow */
5498 case RTL_GIGA_MAC_VER_11:
5499 netif_stop_queue(dev);
5500 /* XXX - Hack alert. See rtl_task(). */
5501 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5507 if (unlikely(status & SYSErr))
5508 rtl8169_pcierr_interrupt(dev);
5510 if (status & LinkChg)
5511 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5513 napi_disable(&tp->napi);
5514 rtl_irq_disable(tp);
5516 napi_enable(&tp->napi);
5517 napi_schedule(&tp->napi);
5520 static void rtl_task(struct work_struct *work)
5522 static const struct {
5524 void (*action)(struct rtl8169_private *);
5526 /* XXX - keep rtl_slow_event_work() as first element. */
5527 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5528 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5529 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5531 struct rtl8169_private *tp =
5532 container_of(work, struct rtl8169_private, wk.work);
5533 struct net_device *dev = tp->dev;
5538 if (!netif_running(dev) ||
5539 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5542 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5545 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5547 rtl_work[i].action(tp);
5551 rtl_unlock_work(tp);
5554 static int rtl8169_poll(struct napi_struct *napi, int budget)
5556 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5557 struct net_device *dev = tp->dev;
5558 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5562 status = rtl_get_events(tp);
5563 rtl_ack_events(tp, status & ~tp->event_slow);
5565 if (status & RTL_EVENT_NAPI_RX)
5566 work_done = rtl_rx(dev, tp, (u32) budget);
5568 if (status & RTL_EVENT_NAPI_TX)
5571 if (status & tp->event_slow) {
5572 enable_mask &= ~tp->event_slow;
5574 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5577 if (work_done < budget) {
5578 napi_complete(napi);
5580 rtl_irq_enable(tp, enable_mask);
5587 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5589 struct rtl8169_private *tp = netdev_priv(dev);
5591 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5594 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5595 RTL_W32(RxMissed, 0);
5598 static void rtl8169_down(struct net_device *dev)
5600 struct rtl8169_private *tp = netdev_priv(dev);
5601 void __iomem *ioaddr = tp->mmio_addr;
5603 del_timer_sync(&tp->timer);
5605 napi_disable(&tp->napi);
5606 netif_stop_queue(dev);
5608 rtl8169_hw_reset(tp);
5610 * At this point device interrupts can not be enabled in any function,
5611 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5612 * and napi is disabled (rtl8169_poll).
5614 rtl8169_rx_missed(dev, ioaddr);
5616 /* Give a racing hard_start_xmit a few cycles to complete. */
5617 synchronize_sched();
5619 rtl8169_tx_clear(tp);
5621 rtl8169_rx_clear(tp);
5623 rtl_pll_power_down(tp);
5626 static int rtl8169_close(struct net_device *dev)
5628 struct rtl8169_private *tp = netdev_priv(dev);
5629 struct pci_dev *pdev = tp->pci_dev;
5631 pm_runtime_get_sync(&pdev->dev);
5633 /* Update counters before going down */
5634 rtl8169_update_counters(dev);
5637 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5640 rtl_unlock_work(tp);
5642 free_irq(pdev->irq, dev);
5644 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5646 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5648 tp->TxDescArray = NULL;
5649 tp->RxDescArray = NULL;
5651 pm_runtime_put_sync(&pdev->dev);
5656 #ifdef CONFIG_NET_POLL_CONTROLLER
5657 static void rtl8169_netpoll(struct net_device *dev)
5659 struct rtl8169_private *tp = netdev_priv(dev);
5661 rtl8169_interrupt(tp->pci_dev->irq, dev);
5665 static int rtl_open(struct net_device *dev)
5667 struct rtl8169_private *tp = netdev_priv(dev);
5668 void __iomem *ioaddr = tp->mmio_addr;
5669 struct pci_dev *pdev = tp->pci_dev;
5670 int retval = -ENOMEM;
5672 pm_runtime_get_sync(&pdev->dev);
5675 * Rx and Tx desscriptors needs 256 bytes alignment.
5676 * dma_alloc_coherent provides more.
5678 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5679 &tp->TxPhyAddr, GFP_KERNEL);
5680 if (!tp->TxDescArray)
5681 goto err_pm_runtime_put;
5683 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5684 &tp->RxPhyAddr, GFP_KERNEL);
5685 if (!tp->RxDescArray)
5688 retval = rtl8169_init_ring(dev);
5692 INIT_WORK(&tp->wk.work, rtl_task);
5696 rtl_request_firmware(tp);
5698 retval = request_irq(pdev->irq, rtl8169_interrupt,
5699 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5702 goto err_release_fw_2;
5706 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5708 napi_enable(&tp->napi);
5710 rtl8169_init_phy(dev, tp);
5712 __rtl8169_set_features(dev, dev->features);
5714 rtl_pll_power_up(tp);
5718 netif_start_queue(dev);
5720 rtl_unlock_work(tp);
5722 tp->saved_wolopts = 0;
5723 pm_runtime_put_noidle(&pdev->dev);
5725 rtl8169_check_link_status(dev, tp, ioaddr);
5730 rtl_release_firmware(tp);
5731 rtl8169_rx_clear(tp);
5733 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5735 tp->RxDescArray = NULL;
5737 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5739 tp->TxDescArray = NULL;
5741 pm_runtime_put_noidle(&pdev->dev);
5745 static struct rtnl_link_stats64 *
5746 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5748 struct rtl8169_private *tp = netdev_priv(dev);
5749 void __iomem *ioaddr = tp->mmio_addr;
5752 if (netif_running(dev))
5753 rtl8169_rx_missed(dev, ioaddr);
5756 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5757 stats->rx_packets = tp->rx_stats.packets;
5758 stats->rx_bytes = tp->rx_stats.bytes;
5759 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5763 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5764 stats->tx_packets = tp->tx_stats.packets;
5765 stats->tx_bytes = tp->tx_stats.bytes;
5766 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5768 stats->rx_dropped = dev->stats.rx_dropped;
5769 stats->tx_dropped = dev->stats.tx_dropped;
5770 stats->rx_length_errors = dev->stats.rx_length_errors;
5771 stats->rx_errors = dev->stats.rx_errors;
5772 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5773 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5774 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5779 static void rtl8169_net_suspend(struct net_device *dev)
5781 struct rtl8169_private *tp = netdev_priv(dev);
5783 if (!netif_running(dev))
5786 netif_device_detach(dev);
5787 netif_stop_queue(dev);
5790 napi_disable(&tp->napi);
5791 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5792 rtl_unlock_work(tp);
5794 rtl_pll_power_down(tp);
5799 static int rtl8169_suspend(struct device *device)
5801 struct pci_dev *pdev = to_pci_dev(device);
5802 struct net_device *dev = pci_get_drvdata(pdev);
5804 rtl8169_net_suspend(dev);
5809 static void __rtl8169_resume(struct net_device *dev)
5811 struct rtl8169_private *tp = netdev_priv(dev);
5813 netif_device_attach(dev);
5815 rtl_pll_power_up(tp);
5818 napi_enable(&tp->napi);
5819 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5820 rtl_unlock_work(tp);
5822 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5825 static int rtl8169_resume(struct device *device)
5827 struct pci_dev *pdev = to_pci_dev(device);
5828 struct net_device *dev = pci_get_drvdata(pdev);
5829 struct rtl8169_private *tp = netdev_priv(dev);
5831 rtl8169_init_phy(dev, tp);
5833 if (netif_running(dev))
5834 __rtl8169_resume(dev);
5839 static int rtl8169_runtime_suspend(struct device *device)
5841 struct pci_dev *pdev = to_pci_dev(device);
5842 struct net_device *dev = pci_get_drvdata(pdev);
5843 struct rtl8169_private *tp = netdev_priv(dev);
5845 if (!tp->TxDescArray)
5849 tp->saved_wolopts = __rtl8169_get_wol(tp);
5850 __rtl8169_set_wol(tp, WAKE_ANY);
5851 rtl_unlock_work(tp);
5853 rtl8169_net_suspend(dev);
5858 static int rtl8169_runtime_resume(struct device *device)
5860 struct pci_dev *pdev = to_pci_dev(device);
5861 struct net_device *dev = pci_get_drvdata(pdev);
5862 struct rtl8169_private *tp = netdev_priv(dev);
5864 if (!tp->TxDescArray)
5868 __rtl8169_set_wol(tp, tp->saved_wolopts);
5869 tp->saved_wolopts = 0;
5870 rtl_unlock_work(tp);
5872 rtl8169_init_phy(dev, tp);
5874 __rtl8169_resume(dev);
5879 static int rtl8169_runtime_idle(struct device *device)
5881 struct pci_dev *pdev = to_pci_dev(device);
5882 struct net_device *dev = pci_get_drvdata(pdev);
5883 struct rtl8169_private *tp = netdev_priv(dev);
5885 return tp->TxDescArray ? -EBUSY : 0;
5888 static const struct dev_pm_ops rtl8169_pm_ops = {
5889 .suspend = rtl8169_suspend,
5890 .resume = rtl8169_resume,
5891 .freeze = rtl8169_suspend,
5892 .thaw = rtl8169_resume,
5893 .poweroff = rtl8169_suspend,
5894 .restore = rtl8169_resume,
5895 .runtime_suspend = rtl8169_runtime_suspend,
5896 .runtime_resume = rtl8169_runtime_resume,
5897 .runtime_idle = rtl8169_runtime_idle,
5900 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5902 #else /* !CONFIG_PM */
5904 #define RTL8169_PM_OPS NULL
5906 #endif /* !CONFIG_PM */
5908 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5910 void __iomem *ioaddr = tp->mmio_addr;
5912 /* WoL fails with 8168b when the receiver is disabled. */
5913 switch (tp->mac_version) {
5914 case RTL_GIGA_MAC_VER_11:
5915 case RTL_GIGA_MAC_VER_12:
5916 case RTL_GIGA_MAC_VER_17:
5917 pci_clear_master(tp->pci_dev);
5919 RTL_W8(ChipCmd, CmdRxEnb);
5928 static void rtl_shutdown(struct pci_dev *pdev)
5930 struct net_device *dev = pci_get_drvdata(pdev);
5931 struct rtl8169_private *tp = netdev_priv(dev);
5932 struct device *d = &pdev->dev;
5934 pm_runtime_get_sync(d);
5936 rtl8169_net_suspend(dev);
5938 /* Restore original MAC address */
5939 rtl_rar_set(tp, dev->perm_addr);
5941 rtl8169_hw_reset(tp);
5943 if (system_state == SYSTEM_POWER_OFF) {
5944 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5945 rtl_wol_suspend_quirk(tp);
5946 rtl_wol_shutdown_quirk(tp);
5949 pci_wake_from_d3(pdev, true);
5950 pci_set_power_state(pdev, PCI_D3hot);
5953 pm_runtime_put_noidle(d);
5956 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5958 struct net_device *dev = pci_get_drvdata(pdev);
5959 struct rtl8169_private *tp = netdev_priv(dev);
5961 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5962 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5963 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5964 rtl8168_driver_stop(tp);
5967 cancel_work_sync(&tp->wk.work);
5969 unregister_netdev(dev);
5971 rtl_release_firmware(tp);
5973 if (pci_dev_run_wake(pdev))
5974 pm_runtime_get_noresume(&pdev->dev);
5976 /* restore original MAC address */
5977 rtl_rar_set(tp, dev->perm_addr);
5979 rtl_disable_msi(pdev, tp);
5980 rtl8169_release_board(pdev, dev, tp->mmio_addr);
5981 pci_set_drvdata(pdev, NULL);
5984 static const struct net_device_ops rtl_netdev_ops = {
5985 .ndo_open = rtl_open,
5986 .ndo_stop = rtl8169_close,
5987 .ndo_get_stats64 = rtl8169_get_stats64,
5988 .ndo_start_xmit = rtl8169_start_xmit,
5989 .ndo_tx_timeout = rtl8169_tx_timeout,
5990 .ndo_validate_addr = eth_validate_addr,
5991 .ndo_change_mtu = rtl8169_change_mtu,
5992 .ndo_fix_features = rtl8169_fix_features,
5993 .ndo_set_features = rtl8169_set_features,
5994 .ndo_set_mac_address = rtl_set_mac_address,
5995 .ndo_do_ioctl = rtl8169_ioctl,
5996 .ndo_set_rx_mode = rtl_set_rx_mode,
5997 #ifdef CONFIG_NET_POLL_CONTROLLER
5998 .ndo_poll_controller = rtl8169_netpoll,
6003 static const struct rtl_cfg_info {
6004 void (*hw_start)(struct net_device *);
6005 unsigned int region;
6010 } rtl_cfg_infos [] = {
6012 .hw_start = rtl_hw_start_8169,
6015 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6016 .features = RTL_FEATURE_GMII,
6017 .default_ver = RTL_GIGA_MAC_VER_01,
6020 .hw_start = rtl_hw_start_8168,
6023 .event_slow = SYSErr | LinkChg | RxOverflow,
6024 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6025 .default_ver = RTL_GIGA_MAC_VER_11,
6028 .hw_start = rtl_hw_start_8101,
6031 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6033 .features = RTL_FEATURE_MSI,
6034 .default_ver = RTL_GIGA_MAC_VER_13,
6038 /* Cfg9346_Unlock assumed. */
6039 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6040 const struct rtl_cfg_info *cfg)
6042 void __iomem *ioaddr = tp->mmio_addr;
6046 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6047 if (cfg->features & RTL_FEATURE_MSI) {
6048 if (pci_enable_msi(tp->pci_dev)) {
6049 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6052 msi = RTL_FEATURE_MSI;
6055 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6056 RTL_W8(Config2, cfg2);
6060 static int __devinit
6061 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6063 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6064 const unsigned int region = cfg->region;
6065 struct rtl8169_private *tp;
6066 struct mii_if_info *mii;
6067 struct net_device *dev;
6068 void __iomem *ioaddr;
6072 if (netif_msg_drv(&debug)) {
6073 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6074 MODULENAME, RTL8169_VERSION);
6077 dev = alloc_etherdev(sizeof (*tp));
6083 SET_NETDEV_DEV(dev, &pdev->dev);
6084 dev->netdev_ops = &rtl_netdev_ops;
6085 tp = netdev_priv(dev);
6088 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6092 mii->mdio_read = rtl_mdio_read;
6093 mii->mdio_write = rtl_mdio_write;
6094 mii->phy_id_mask = 0x1f;
6095 mii->reg_num_mask = 0x1f;
6096 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6098 /* disable ASPM completely as that cause random device stop working
6099 * problems as well as full system hangs for some PCIe devices users */
6100 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6101 PCIE_LINK_STATE_CLKPM);
6103 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6104 rc = pci_enable_device(pdev);
6106 netif_err(tp, probe, dev, "enable failure\n");
6107 goto err_out_free_dev_1;
6110 if (pci_set_mwi(pdev) < 0)
6111 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6113 /* make sure PCI base addr 1 is MMIO */
6114 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6115 netif_err(tp, probe, dev,
6116 "region #%d not an MMIO resource, aborting\n",
6122 /* check for weird/broken PCI region reporting */
6123 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6124 netif_err(tp, probe, dev,
6125 "Invalid PCI region size(s), aborting\n");
6130 rc = pci_request_regions(pdev, MODULENAME);
6132 netif_err(tp, probe, dev, "could not request regions\n");
6136 tp->cp_cmd = RxChkSum;
6138 if ((sizeof(dma_addr_t) > 4) &&
6139 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6140 tp->cp_cmd |= PCIDAC;
6141 dev->features |= NETIF_F_HIGHDMA;
6143 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6145 netif_err(tp, probe, dev, "DMA configuration failed\n");
6146 goto err_out_free_res_3;
6150 /* ioremap MMIO region */
6151 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6153 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6155 goto err_out_free_res_3;
6157 tp->mmio_addr = ioaddr;
6159 if (!pci_is_pcie(pdev))
6160 netif_info(tp, probe, dev, "not PCI Express\n");
6162 /* Identify chip attached to board */
6163 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6167 rtl_irq_disable(tp);
6171 rtl_ack_events(tp, 0xffff);
6173 pci_set_master(pdev);
6176 * Pretend we are using VLANs; This bypasses a nasty bug where
6177 * Interrupts stop flowing on high load on 8110SCd controllers.
6179 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6180 tp->cp_cmd |= RxVlan;
6182 rtl_init_mdio_ops(tp);
6183 rtl_init_pll_power_ops(tp);
6184 rtl_init_jumbo_ops(tp);
6186 rtl8169_print_mac_version(tp);
6188 chipset = tp->mac_version;
6189 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6191 RTL_W8(Cfg9346, Cfg9346_Unlock);
6192 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6193 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6194 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6195 tp->features |= RTL_FEATURE_WOL;
6196 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6197 tp->features |= RTL_FEATURE_WOL;
6198 tp->features |= rtl_try_msi(tp, cfg);
6199 RTL_W8(Cfg9346, Cfg9346_Lock);
6201 if (rtl_tbi_enabled(tp)) {
6202 tp->set_speed = rtl8169_set_speed_tbi;
6203 tp->get_settings = rtl8169_gset_tbi;
6204 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6205 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6206 tp->link_ok = rtl8169_tbi_link_ok;
6207 tp->do_ioctl = rtl_tbi_ioctl;
6209 tp->set_speed = rtl8169_set_speed_xmii;
6210 tp->get_settings = rtl8169_gset_xmii;
6211 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6212 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6213 tp->link_ok = rtl8169_xmii_link_ok;
6214 tp->do_ioctl = rtl_xmii_ioctl;
6217 mutex_init(&tp->wk.mutex);
6219 /* Get MAC address */
6220 for (i = 0; i < ETH_ALEN; i++)
6221 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6222 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6224 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6225 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6227 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6229 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6230 * properly for all devices */
6231 dev->features |= NETIF_F_RXCSUM |
6232 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6234 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6235 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6236 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6239 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6240 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6241 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6243 dev->hw_features |= NETIF_F_RXALL;
6244 dev->hw_features |= NETIF_F_RXFCS;
6246 tp->hw_start = cfg->hw_start;
6247 tp->event_slow = cfg->event_slow;
6249 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6250 ~(RxBOVF | RxFOVF) : ~0;
6252 init_timer(&tp->timer);
6253 tp->timer.data = (unsigned long) dev;
6254 tp->timer.function = rtl8169_phy_timer;
6256 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6258 rc = register_netdev(dev);
6262 pci_set_drvdata(pdev, dev);
6264 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6265 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6266 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6267 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6268 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6269 "tx checksumming: %s]\n",
6270 rtl_chip_infos[chipset].jumbo_max,
6271 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6274 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6275 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6276 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6277 rtl8168_driver_start(tp);
6280 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6282 if (pci_dev_run_wake(pdev))
6283 pm_runtime_put_noidle(&pdev->dev);
6285 netif_carrier_off(dev);
6291 rtl_disable_msi(pdev, tp);
6294 pci_release_regions(pdev);
6296 pci_clear_mwi(pdev);
6297 pci_disable_device(pdev);
6303 static struct pci_driver rtl8169_pci_driver = {
6305 .id_table = rtl8169_pci_tbl,
6306 .probe = rtl_init_one,
6307 .remove = __devexit_p(rtl_remove_one),
6308 .shutdown = rtl_shutdown,
6309 .driver.pm = RTL8169_PM_OPS,
6312 static int __init rtl8169_init_module(void)
6314 return pci_register_driver(&rtl8169_pci_driver);
6317 static void __exit rtl8169_cleanup_module(void)
6319 pci_unregister_driver(&rtl8169_pci_driver);
6322 module_init(rtl8169_init_module);
6323 module_exit(rtl8169_cleanup_module);