1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
35 #include <asm/div64.h>
39 #define RAVB_DEF_MSG_ENABLE \
45 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
48 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
51 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
55 for (i = 0; i < 10000; i++) {
56 if ((ravb_read(ndev, reg) & mask) == value)
63 static int ravb_config(struct net_device *ndev)
68 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
69 /* Check if the operating mode is changed to the config mode */
70 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
72 netdev_err(ndev, "failed to switch device to config mode\n");
77 static void ravb_set_duplex(struct net_device *ndev)
79 struct ravb_private *priv = netdev_priv(ndev);
81 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
84 static void ravb_set_rate(struct net_device *ndev)
86 struct ravb_private *priv = netdev_priv(ndev);
88 switch (priv->speed) {
89 case 100: /* 100BASE */
90 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 case 1000: /* 1000BASE */
93 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
100 static void ravb_set_buffer_align(struct sk_buff *skb)
102 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
105 skb_reserve(skb, RAVB_ALIGN - reserve);
108 /* Get MAC address from the MAC address registers
110 * Ethernet AVB device doesn't have ROM for MAC address.
111 * This function gets the MAC address that was used by a bootloader.
113 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
116 ether_addr_copy(ndev->dev_addr, mac);
118 u32 mahr = ravb_read(ndev, MAHR);
119 u32 malr = ravb_read(ndev, MALR);
121 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
122 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
123 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
124 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
125 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
126 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
130 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
132 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
135 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
138 /* MDC pin control */
139 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
141 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
144 /* Data I/O pin control */
145 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
147 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
151 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
153 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
157 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
159 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
162 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
165 /* MDIO bus control struct */
166 static struct mdiobb_ops bb_ops = {
167 .owner = THIS_MODULE,
168 .set_mdc = ravb_set_mdc,
169 .set_mdio_dir = ravb_set_mdio_dir,
170 .set_mdio_data = ravb_set_mdio_data,
171 .get_mdio_data = ravb_get_mdio_data,
174 /* Free skb's and DMA buffers for Ethernet AVB */
175 static void ravb_ring_free(struct net_device *ndev, int q)
177 struct ravb_private *priv = netdev_priv(ndev);
181 /* Free RX skb ringbuffer */
182 if (priv->rx_skb[q]) {
183 for (i = 0; i < priv->num_rx_ring[q]; i++)
184 dev_kfree_skb(priv->rx_skb[q][i]);
186 kfree(priv->rx_skb[q]);
187 priv->rx_skb[q] = NULL;
189 /* Free TX skb ringbuffer */
190 if (priv->tx_skb[q]) {
191 for (i = 0; i < priv->num_tx_ring[q]; i++)
192 dev_kfree_skb(priv->tx_skb[q][i]);
194 kfree(priv->tx_skb[q]);
195 priv->tx_skb[q] = NULL;
197 /* Free aligned TX buffers */
198 kfree(priv->tx_align[q]);
199 priv->tx_align[q] = NULL;
201 if (priv->rx_ring[q]) {
202 ring_size = sizeof(struct ravb_ex_rx_desc) *
203 (priv->num_rx_ring[q] + 1);
204 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
205 priv->rx_desc_dma[q]);
206 priv->rx_ring[q] = NULL;
209 if (priv->tx_ring[q]) {
210 ring_size = sizeof(struct ravb_tx_desc) *
211 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
212 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
213 priv->tx_desc_dma[q]);
214 priv->tx_ring[q] = NULL;
218 /* Format skb and descriptor buffer for Ethernet AVB */
219 static void ravb_ring_format(struct net_device *ndev, int q)
221 struct ravb_private *priv = netdev_priv(ndev);
222 struct ravb_ex_rx_desc *rx_desc;
223 struct ravb_tx_desc *tx_desc;
224 struct ravb_desc *desc;
225 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
226 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
233 priv->dirty_rx[q] = 0;
234 priv->dirty_tx[q] = 0;
236 memset(priv->rx_ring[q], 0, rx_ring_size);
237 /* Build RX ring buffer */
238 for (i = 0; i < priv->num_rx_ring[q]; i++) {
240 rx_desc = &priv->rx_ring[q][i];
241 /* The size of the buffer should be on 16-byte boundary. */
242 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
243 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
244 ALIGN(PKT_BUF_SZ, 16),
246 /* We just set the data size to 0 for a failed mapping which
247 * should prevent DMA from happening...
249 if (dma_mapping_error(ndev->dev.parent, dma_addr))
250 rx_desc->ds_cc = cpu_to_le16(0);
251 rx_desc->dptr = cpu_to_le32(dma_addr);
252 rx_desc->die_dt = DT_FEMPTY;
254 rx_desc = &priv->rx_ring[q][i];
255 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
256 rx_desc->die_dt = DT_LINKFIX; /* type */
258 memset(priv->tx_ring[q], 0, tx_ring_size);
259 /* Build TX ring buffer */
260 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
262 tx_desc->die_dt = DT_EEMPTY;
264 tx_desc->die_dt = DT_EEMPTY;
266 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
267 tx_desc->die_dt = DT_LINKFIX; /* type */
269 /* RX descriptor base address for best effort */
270 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
271 desc->die_dt = DT_LINKFIX; /* type */
272 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
274 /* TX descriptor base address for best effort */
275 desc = &priv->desc_bat[q];
276 desc->die_dt = DT_LINKFIX; /* type */
277 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
280 /* Init skb and descriptor buffer for Ethernet AVB */
281 static int ravb_ring_init(struct net_device *ndev, int q)
283 struct ravb_private *priv = netdev_priv(ndev);
288 /* Allocate RX and TX skb rings */
289 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
290 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
291 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
292 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
293 if (!priv->rx_skb[q] || !priv->tx_skb[q])
296 for (i = 0; i < priv->num_rx_ring[q]; i++) {
297 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
300 ravb_set_buffer_align(skb);
301 priv->rx_skb[q][i] = skb;
304 /* Allocate rings for the aligned buffers */
305 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
306 DPTR_ALIGN - 1, GFP_KERNEL);
307 if (!priv->tx_align[q])
310 /* Allocate all RX descriptors. */
311 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
312 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
313 &priv->rx_desc_dma[q],
315 if (!priv->rx_ring[q])
318 priv->dirty_rx[q] = 0;
320 /* Allocate all TX descriptors. */
321 ring_size = sizeof(struct ravb_tx_desc) *
322 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
323 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
324 &priv->tx_desc_dma[q],
326 if (!priv->tx_ring[q])
332 ravb_ring_free(ndev, q);
337 /* E-MAC init function */
338 static void ravb_emac_init(struct net_device *ndev)
340 struct ravb_private *priv = netdev_priv(ndev);
342 /* Receive frame limit set register */
343 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
345 /* PAUSE prohibition */
346 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
347 ECMR_TE | ECMR_RE, ECMR);
351 /* Set MAC address */
353 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
354 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
356 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
358 ravb_write(ndev, 1, MPR);
360 /* E-MAC status register clear */
361 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
363 /* E-MAC interrupt enable register */
364 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
367 /* Device init function for Ethernet AVB */
368 static int ravb_dmac_init(struct net_device *ndev)
372 /* Set CONFIG mode */
373 error = ravb_config(ndev);
377 error = ravb_ring_init(ndev, RAVB_BE);
380 error = ravb_ring_init(ndev, RAVB_NC);
382 ravb_ring_free(ndev, RAVB_BE);
386 /* Descriptor format */
387 ravb_ring_format(ndev, RAVB_BE);
388 ravb_ring_format(ndev, RAVB_NC);
390 #if defined(__LITTLE_ENDIAN)
391 ravb_modify(ndev, CCC, CCC_BOC, 0);
393 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
397 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
400 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
402 /* Timestamp enable */
403 ravb_write(ndev, TCCR_TFEN, TCCR);
405 /* Interrupt init: */
407 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
408 /* Disable FIFO full warning */
409 ravb_write(ndev, 0, RIC1);
410 /* Receive FIFO full error, descriptor empty */
411 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
412 /* Frame transmitted, timestamp FIFO updated */
413 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
415 /* Setting the control will start the AVB-DMAC process. */
416 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
421 /* Free TX skb function for AVB-IP */
422 static int ravb_tx_free(struct net_device *ndev, int q)
424 struct ravb_private *priv = netdev_priv(ndev);
425 struct net_device_stats *stats = &priv->stats[q];
426 struct ravb_tx_desc *desc;
431 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
432 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
434 desc = &priv->tx_ring[q][entry];
435 if (desc->die_dt != DT_FEMPTY)
437 /* Descriptor type must be checked before all other reads */
439 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
440 /* Free the original skb. */
441 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
442 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
443 size, DMA_TO_DEVICE);
444 /* Last packet descriptor? */
445 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
446 entry /= NUM_TX_DESC;
447 dev_kfree_skb_any(priv->tx_skb[q][entry]);
448 priv->tx_skb[q][entry] = NULL;
453 stats->tx_bytes += size;
454 desc->die_dt = DT_EEMPTY;
459 static void ravb_get_tx_tstamp(struct net_device *ndev)
461 struct ravb_private *priv = netdev_priv(ndev);
462 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
463 struct skb_shared_hwtstamps shhwtstamps;
465 struct timespec64 ts;
470 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
472 tfa2 = ravb_read(ndev, TFA2);
473 tfa_tag = (tfa2 & TFA2_TST) >> 16;
474 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
475 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
476 ravb_read(ndev, TFA1);
477 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
478 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
479 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
483 list_del(&ts_skb->list);
485 if (tag == tfa_tag) {
486 skb_tstamp_tx(skb, &shhwtstamps);
490 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
494 /* Packet receive function for Ethernet AVB */
495 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
497 struct ravb_private *priv = netdev_priv(ndev);
498 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
499 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
501 struct net_device_stats *stats = &priv->stats[q];
502 struct ravb_ex_rx_desc *desc;
505 struct timespec64 ts;
510 boguscnt = min(boguscnt, *quota);
512 desc = &priv->rx_ring[q][entry];
513 while (desc->die_dt != DT_FEMPTY) {
514 /* Descriptor type must be checked before all other reads */
516 desc_status = desc->msc;
517 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
522 /* We use 0-byte descriptors to mark the DMA mapping errors */
526 if (desc_status & MSC_MC)
529 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
532 if (desc_status & MSC_CRC)
533 stats->rx_crc_errors++;
534 if (desc_status & MSC_RFE)
535 stats->rx_frame_errors++;
536 if (desc_status & (MSC_RTLF | MSC_RTSF))
537 stats->rx_length_errors++;
538 if (desc_status & MSC_CEEF)
539 stats->rx_missed_errors++;
541 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
543 skb = priv->rx_skb[q][entry];
544 priv->rx_skb[q][entry] = NULL;
545 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
546 ALIGN(PKT_BUF_SZ, 16),
548 get_ts &= (q == RAVB_NC) ?
549 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
550 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
552 struct skb_shared_hwtstamps *shhwtstamps;
554 shhwtstamps = skb_hwtstamps(skb);
555 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
556 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
557 32) | le32_to_cpu(desc->ts_sl);
558 ts.tv_nsec = le32_to_cpu(desc->ts_n);
559 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
561 skb_put(skb, pkt_len);
562 skb->protocol = eth_type_trans(skb, ndev);
563 napi_gro_receive(&priv->napi[q], skb);
565 stats->rx_bytes += pkt_len;
568 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
569 desc = &priv->rx_ring[q][entry];
572 /* Refill the RX ring buffers. */
573 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
574 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
575 desc = &priv->rx_ring[q][entry];
576 /* The size of the buffer should be on 16-byte boundary. */
577 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
579 if (!priv->rx_skb[q][entry]) {
580 skb = netdev_alloc_skb(ndev,
581 PKT_BUF_SZ + RAVB_ALIGN - 1);
583 break; /* Better luck next round. */
584 ravb_set_buffer_align(skb);
585 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
586 le16_to_cpu(desc->ds_cc),
588 skb_checksum_none_assert(skb);
589 /* We just set the data size to 0 for a failed mapping
590 * which should prevent DMA from happening...
592 if (dma_mapping_error(ndev->dev.parent, dma_addr))
593 desc->ds_cc = cpu_to_le16(0);
594 desc->dptr = cpu_to_le32(dma_addr);
595 priv->rx_skb[q][entry] = skb;
597 /* Descriptor type must be set after all the above writes */
599 desc->die_dt = DT_FEMPTY;
602 *quota -= limit - (++boguscnt);
604 return boguscnt <= 0;
607 static void ravb_rcv_snd_disable(struct net_device *ndev)
609 /* Disable TX and RX */
610 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
613 static void ravb_rcv_snd_enable(struct net_device *ndev)
615 /* Enable TX and RX */
616 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
619 /* function for waiting dma process finished */
620 static int ravb_stop_dma(struct net_device *ndev)
624 /* Wait for stopping the hardware TX process */
625 error = ravb_wait(ndev, TCCR,
626 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
630 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
635 /* Stop the E-MAC's RX/TX processes. */
636 ravb_rcv_snd_disable(ndev);
638 /* Wait for stopping the RX DMA process */
639 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
643 /* Stop AVB-DMAC process */
644 return ravb_config(ndev);
647 /* E-MAC interrupt handler */
648 static void ravb_emac_interrupt(struct net_device *ndev)
650 struct ravb_private *priv = netdev_priv(ndev);
653 ecsr = ravb_read(ndev, ECSR);
654 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
656 ndev->stats.tx_carrier_errors++;
657 if (ecsr & ECSR_LCHNG) {
659 if (priv->no_avb_link)
661 psr = ravb_read(ndev, PSR);
662 if (priv->avb_link_active_low)
664 if (!(psr & PSR_LMON)) {
665 /* DIsable RX and TX */
666 ravb_rcv_snd_disable(ndev);
668 /* Enable RX and TX */
669 ravb_rcv_snd_enable(ndev);
674 /* Error interrupt handler */
675 static void ravb_error_interrupt(struct net_device *ndev)
677 struct ravb_private *priv = netdev_priv(ndev);
680 eis = ravb_read(ndev, EIS);
681 ravb_write(ndev, ~EIS_QFS, EIS);
683 ris2 = ravb_read(ndev, RIS2);
684 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
686 /* Receive Descriptor Empty int */
687 if (ris2 & RIS2_QFF0)
688 priv->stats[RAVB_BE].rx_over_errors++;
690 /* Receive Descriptor Empty int */
691 if (ris2 & RIS2_QFF1)
692 priv->stats[RAVB_NC].rx_over_errors++;
694 /* Receive FIFO Overflow int */
695 if (ris2 & RIS2_RFFF)
696 priv->rx_fifo_errors++;
700 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
702 struct net_device *ndev = dev_id;
703 struct ravb_private *priv = netdev_priv(ndev);
704 irqreturn_t result = IRQ_NONE;
707 spin_lock(&priv->lock);
708 /* Get interrupt status */
709 iss = ravb_read(ndev, ISS);
711 /* Received and transmitted interrupts */
712 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
713 u32 ris0 = ravb_read(ndev, RIS0);
714 u32 ric0 = ravb_read(ndev, RIC0);
715 u32 tis = ravb_read(ndev, TIS);
716 u32 tic = ravb_read(ndev, TIC);
719 /* Timestamp updated */
720 if (tis & TIS_TFUF) {
721 ravb_write(ndev, ~TIS_TFUF, TIS);
722 ravb_get_tx_tstamp(ndev);
723 result = IRQ_HANDLED;
726 /* Network control and best effort queue RX/TX */
727 for (q = RAVB_NC; q >= RAVB_BE; q--) {
728 if (((ris0 & ric0) & BIT(q)) ||
729 ((tis & tic) & BIT(q))) {
730 if (napi_schedule_prep(&priv->napi[q])) {
731 /* Mask RX and TX interrupts */
734 ravb_write(ndev, ric0, RIC0);
735 ravb_write(ndev, tic, TIC);
736 __napi_schedule(&priv->napi[q]);
739 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
742 " tx status 0x%08x, tx mask 0x%08x.\n",
745 result = IRQ_HANDLED;
750 /* E-MAC status summary */
752 ravb_emac_interrupt(ndev);
753 result = IRQ_HANDLED;
756 /* Error status summary */
758 ravb_error_interrupt(ndev);
759 result = IRQ_HANDLED;
763 result = ravb_ptp_interrupt(ndev);
766 spin_unlock(&priv->lock);
770 static int ravb_poll(struct napi_struct *napi, int budget)
772 struct net_device *ndev = napi->dev;
773 struct ravb_private *priv = netdev_priv(ndev);
775 int q = napi - priv->napi;
781 tis = ravb_read(ndev, TIS);
782 ris0 = ravb_read(ndev, RIS0);
783 if (!((ris0 & mask) || (tis & mask)))
786 /* Processing RX Descriptor Ring */
788 /* Clear RX interrupt */
789 ravb_write(ndev, ~mask, RIS0);
790 if (ravb_rx(ndev, "a, q))
793 /* Processing TX Descriptor Ring */
795 spin_lock_irqsave(&priv->lock, flags);
796 /* Clear TX interrupt */
797 ravb_write(ndev, ~mask, TIS);
798 ravb_tx_free(ndev, q);
799 netif_wake_subqueue(ndev, q);
801 spin_unlock_irqrestore(&priv->lock, flags);
807 /* Re-enable RX/TX interrupts */
808 spin_lock_irqsave(&priv->lock, flags);
809 ravb_modify(ndev, RIC0, mask, mask);
810 ravb_modify(ndev, TIC, mask, mask);
812 spin_unlock_irqrestore(&priv->lock, flags);
814 /* Receive error message handling */
815 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
816 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
817 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
818 ndev->stats.rx_over_errors = priv->rx_over_errors;
819 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
821 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
822 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
823 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
826 return budget - quota;
829 /* PHY state control function */
830 static void ravb_adjust_link(struct net_device *ndev)
832 struct ravb_private *priv = netdev_priv(ndev);
833 struct phy_device *phydev = priv->phydev;
834 bool new_state = false;
837 if (phydev->duplex != priv->duplex) {
839 priv->duplex = phydev->duplex;
840 ravb_set_duplex(ndev);
843 if (phydev->speed != priv->speed) {
845 priv->speed = phydev->speed;
849 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
851 priv->link = phydev->link;
852 if (priv->no_avb_link)
853 ravb_rcv_snd_enable(ndev);
855 } else if (priv->link) {
860 if (priv->no_avb_link)
861 ravb_rcv_snd_disable(ndev);
864 if (new_state && netif_msg_link(priv))
865 phy_print_status(phydev);
868 /* PHY init function */
869 static int ravb_phy_init(struct net_device *ndev)
871 struct device_node *np = ndev->dev.parent->of_node;
872 struct ravb_private *priv = netdev_priv(ndev);
873 struct phy_device *phydev;
874 struct device_node *pn;
881 /* Try connecting to PHY */
882 pn = of_parse_phandle(np, "phy-handle", 0);
884 /* In the case of a fixed PHY, the DT node associated
885 * to the PHY is the Ethernet MAC DT node.
887 if (of_phy_is_fixed_link(np)) {
888 err = of_phy_register_fixed_link(np);
892 pn = of_node_get(np);
894 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
895 priv->phy_interface);
897 netdev_err(ndev, "failed to connect PHY\n");
901 /* This driver only support 10/100Mbit speeds on Gen3
904 if (priv->chip_id == RCAR_GEN3) {
907 err = phy_set_max_speed(phydev, SPEED_100);
909 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
910 phy_disconnect(phydev);
914 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
917 /* 10BASE is not supported */
918 phydev->supported &= ~PHY_10BT_FEATURES;
920 phy_attached_info(phydev);
922 priv->phydev = phydev;
927 /* PHY control start function */
928 static int ravb_phy_start(struct net_device *ndev)
930 struct ravb_private *priv = netdev_priv(ndev);
933 error = ravb_phy_init(ndev);
937 phy_start(priv->phydev);
942 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
944 struct ravb_private *priv = netdev_priv(ndev);
949 spin_lock_irqsave(&priv->lock, flags);
950 error = phy_ethtool_gset(priv->phydev, ecmd);
951 spin_unlock_irqrestore(&priv->lock, flags);
957 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
959 struct ravb_private *priv = netdev_priv(ndev);
966 spin_lock_irqsave(&priv->lock, flags);
968 /* Disable TX and RX */
969 ravb_rcv_snd_disable(ndev);
971 error = phy_ethtool_sset(priv->phydev, ecmd);
975 if (ecmd->duplex == DUPLEX_FULL)
980 ravb_set_duplex(ndev);
985 /* Enable TX and RX */
986 ravb_rcv_snd_enable(ndev);
989 spin_unlock_irqrestore(&priv->lock, flags);
994 static int ravb_nway_reset(struct net_device *ndev)
996 struct ravb_private *priv = netdev_priv(ndev);
1001 spin_lock_irqsave(&priv->lock, flags);
1002 error = phy_start_aneg(priv->phydev);
1003 spin_unlock_irqrestore(&priv->lock, flags);
1009 static u32 ravb_get_msglevel(struct net_device *ndev)
1011 struct ravb_private *priv = netdev_priv(ndev);
1013 return priv->msg_enable;
1016 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1018 struct ravb_private *priv = netdev_priv(ndev);
1020 priv->msg_enable = value;
1023 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1024 "rx_queue_0_current",
1025 "tx_queue_0_current",
1028 "rx_queue_0_packets",
1029 "tx_queue_0_packets",
1032 "rx_queue_0_mcast_packets",
1033 "rx_queue_0_errors",
1034 "rx_queue_0_crc_errors",
1035 "rx_queue_0_frame_errors",
1036 "rx_queue_0_length_errors",
1037 "rx_queue_0_missed_errors",
1038 "rx_queue_0_over_errors",
1040 "rx_queue_1_current",
1041 "tx_queue_1_current",
1044 "rx_queue_1_packets",
1045 "tx_queue_1_packets",
1048 "rx_queue_1_mcast_packets",
1049 "rx_queue_1_errors",
1050 "rx_queue_1_crc_errors",
1051 "rx_queue_1_frame_errors",
1052 "rx_queue_1_length_errors",
1053 "rx_queue_1_missed_errors",
1054 "rx_queue_1_over_errors",
1057 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1059 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1063 return RAVB_STATS_LEN;
1069 static void ravb_get_ethtool_stats(struct net_device *ndev,
1070 struct ethtool_stats *stats, u64 *data)
1072 struct ravb_private *priv = netdev_priv(ndev);
1076 /* Device-specific stats */
1077 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1078 struct net_device_stats *stats = &priv->stats[q];
1080 data[i++] = priv->cur_rx[q];
1081 data[i++] = priv->cur_tx[q];
1082 data[i++] = priv->dirty_rx[q];
1083 data[i++] = priv->dirty_tx[q];
1084 data[i++] = stats->rx_packets;
1085 data[i++] = stats->tx_packets;
1086 data[i++] = stats->rx_bytes;
1087 data[i++] = stats->tx_bytes;
1088 data[i++] = stats->multicast;
1089 data[i++] = stats->rx_errors;
1090 data[i++] = stats->rx_crc_errors;
1091 data[i++] = stats->rx_frame_errors;
1092 data[i++] = stats->rx_length_errors;
1093 data[i++] = stats->rx_missed_errors;
1094 data[i++] = stats->rx_over_errors;
1098 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1100 switch (stringset) {
1102 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1107 static void ravb_get_ringparam(struct net_device *ndev,
1108 struct ethtool_ringparam *ring)
1110 struct ravb_private *priv = netdev_priv(ndev);
1112 ring->rx_max_pending = BE_RX_RING_MAX;
1113 ring->tx_max_pending = BE_TX_RING_MAX;
1114 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1115 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1118 static int ravb_set_ringparam(struct net_device *ndev,
1119 struct ethtool_ringparam *ring)
1121 struct ravb_private *priv = netdev_priv(ndev);
1124 if (ring->tx_pending > BE_TX_RING_MAX ||
1125 ring->rx_pending > BE_RX_RING_MAX ||
1126 ring->tx_pending < BE_TX_RING_MIN ||
1127 ring->rx_pending < BE_RX_RING_MIN)
1129 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1132 if (netif_running(ndev)) {
1133 netif_device_detach(ndev);
1134 /* Stop PTP Clock driver */
1135 ravb_ptp_stop(ndev);
1136 /* Wait for DMA stopping */
1137 error = ravb_stop_dma(ndev);
1140 "cannot set ringparam! Any AVB processes are still running?\n");
1143 synchronize_irq(ndev->irq);
1145 /* Free all the skb's in the RX queue and the DMA buffers. */
1146 ravb_ring_free(ndev, RAVB_BE);
1147 ravb_ring_free(ndev, RAVB_NC);
1150 /* Set new parameters */
1151 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1152 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1154 if (netif_running(ndev)) {
1155 error = ravb_dmac_init(ndev);
1158 "%s: ravb_dmac_init() failed, error %d\n",
1163 ravb_emac_init(ndev);
1165 /* Initialise PTP Clock driver */
1166 ravb_ptp_init(ndev, priv->pdev);
1168 netif_device_attach(ndev);
1174 static int ravb_get_ts_info(struct net_device *ndev,
1175 struct ethtool_ts_info *info)
1177 struct ravb_private *priv = netdev_priv(ndev);
1179 info->so_timestamping =
1180 SOF_TIMESTAMPING_TX_SOFTWARE |
1181 SOF_TIMESTAMPING_RX_SOFTWARE |
1182 SOF_TIMESTAMPING_SOFTWARE |
1183 SOF_TIMESTAMPING_TX_HARDWARE |
1184 SOF_TIMESTAMPING_RX_HARDWARE |
1185 SOF_TIMESTAMPING_RAW_HARDWARE;
1186 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1188 (1 << HWTSTAMP_FILTER_NONE) |
1189 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1190 (1 << HWTSTAMP_FILTER_ALL);
1191 info->phc_index = ptp_clock_index(priv->ptp.clock);
1196 static const struct ethtool_ops ravb_ethtool_ops = {
1197 .get_settings = ravb_get_settings,
1198 .set_settings = ravb_set_settings,
1199 .nway_reset = ravb_nway_reset,
1200 .get_msglevel = ravb_get_msglevel,
1201 .set_msglevel = ravb_set_msglevel,
1202 .get_link = ethtool_op_get_link,
1203 .get_strings = ravb_get_strings,
1204 .get_ethtool_stats = ravb_get_ethtool_stats,
1205 .get_sset_count = ravb_get_sset_count,
1206 .get_ringparam = ravb_get_ringparam,
1207 .set_ringparam = ravb_set_ringparam,
1208 .get_ts_info = ravb_get_ts_info,
1211 /* Network device open function for Ethernet AVB */
1212 static int ravb_open(struct net_device *ndev)
1214 struct ravb_private *priv = netdev_priv(ndev);
1217 napi_enable(&priv->napi[RAVB_BE]);
1218 napi_enable(&priv->napi[RAVB_NC]);
1220 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1223 netdev_err(ndev, "cannot request IRQ\n");
1227 if (priv->chip_id == RCAR_GEN3) {
1228 error = request_irq(priv->emac_irq, ravb_interrupt,
1229 IRQF_SHARED, ndev->name, ndev);
1231 netdev_err(ndev, "cannot request IRQ\n");
1237 error = ravb_dmac_init(ndev);
1240 ravb_emac_init(ndev);
1242 /* Initialise PTP Clock driver */
1243 if (priv->chip_id == RCAR_GEN2)
1244 ravb_ptp_init(ndev, priv->pdev);
1246 netif_tx_start_all_queues(ndev);
1248 /* PHY control start */
1249 error = ravb_phy_start(ndev);
1256 /* Stop PTP Clock driver */
1257 if (priv->chip_id == RCAR_GEN2)
1258 ravb_ptp_stop(ndev);
1260 if (priv->chip_id == RCAR_GEN3)
1261 free_irq(priv->emac_irq, ndev);
1263 free_irq(ndev->irq, ndev);
1265 napi_disable(&priv->napi[RAVB_NC]);
1266 napi_disable(&priv->napi[RAVB_BE]);
1270 /* Timeout function for Ethernet AVB */
1271 static void ravb_tx_timeout(struct net_device *ndev)
1273 struct ravb_private *priv = netdev_priv(ndev);
1275 netif_err(priv, tx_err, ndev,
1276 "transmit timed out, status %08x, resetting...\n",
1277 ravb_read(ndev, ISS));
1279 /* tx_errors count up */
1280 ndev->stats.tx_errors++;
1282 schedule_work(&priv->work);
1285 static void ravb_tx_timeout_work(struct work_struct *work)
1287 struct ravb_private *priv = container_of(work, struct ravb_private,
1289 struct net_device *ndev = priv->ndev;
1291 netif_tx_stop_all_queues(ndev);
1293 /* Stop PTP Clock driver */
1294 ravb_ptp_stop(ndev);
1296 /* Wait for DMA stopping */
1297 ravb_stop_dma(ndev);
1299 ravb_ring_free(ndev, RAVB_BE);
1300 ravb_ring_free(ndev, RAVB_NC);
1303 ravb_dmac_init(ndev);
1304 ravb_emac_init(ndev);
1306 /* Initialise PTP Clock driver */
1307 ravb_ptp_init(ndev, priv->pdev);
1309 netif_tx_start_all_queues(ndev);
1312 /* Packet transmit function for Ethernet AVB */
1313 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1315 struct ravb_private *priv = netdev_priv(ndev);
1316 u16 q = skb_get_queue_mapping(skb);
1317 struct ravb_tstamp_skb *ts_skb;
1318 struct ravb_tx_desc *desc;
1319 unsigned long flags;
1325 spin_lock_irqsave(&priv->lock, flags);
1326 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1328 netif_err(priv, tx_queued, ndev,
1329 "still transmitting with the full ring!\n");
1330 netif_stop_subqueue(ndev, q);
1331 spin_unlock_irqrestore(&priv->lock, flags);
1332 return NETDEV_TX_BUSY;
1334 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1335 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1337 if (skb_put_padto(skb, ETH_ZLEN))
1340 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1341 entry / NUM_TX_DESC * DPTR_ALIGN;
1342 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1343 memcpy(buffer, skb->data, len);
1344 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1345 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1348 desc = &priv->tx_ring[q][entry];
1349 desc->ds_tagl = cpu_to_le16(len);
1350 desc->dptr = cpu_to_le32(dma_addr);
1352 buffer = skb->data + len;
1353 len = skb->len - len;
1354 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1355 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1359 desc->ds_tagl = cpu_to_le16(len);
1360 desc->dptr = cpu_to_le32(dma_addr);
1362 /* TX timestamp required */
1364 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1367 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1372 ts_skb->tag = priv->ts_skb_tag++;
1373 priv->ts_skb_tag &= 0x3ff;
1374 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1376 /* TAG and timestamp required flag */
1377 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1378 skb_tx_timestamp(skb);
1379 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1380 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1383 /* Descriptor type must be set after all the above writes */
1385 desc->die_dt = DT_FEND;
1387 desc->die_dt = DT_FSTART;
1389 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1391 priv->cur_tx[q] += NUM_TX_DESC;
1392 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1393 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
1394 netif_stop_subqueue(ndev, q);
1398 spin_unlock_irqrestore(&priv->lock, flags);
1399 return NETDEV_TX_OK;
1402 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1403 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1405 dev_kfree_skb_any(skb);
1406 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1410 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1411 void *accel_priv, select_queue_fallback_t fallback)
1413 /* If skb needs TX timestamp, it is handled in network control queue */
1414 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1419 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1421 struct ravb_private *priv = netdev_priv(ndev);
1422 struct net_device_stats *nstats, *stats0, *stats1;
1424 nstats = &ndev->stats;
1425 stats0 = &priv->stats[RAVB_BE];
1426 stats1 = &priv->stats[RAVB_NC];
1428 nstats->tx_dropped += ravb_read(ndev, TROCR);
1429 ravb_write(ndev, 0, TROCR); /* (write clear) */
1430 nstats->collisions += ravb_read(ndev, CDCR);
1431 ravb_write(ndev, 0, CDCR); /* (write clear) */
1432 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1433 ravb_write(ndev, 0, LCCR); /* (write clear) */
1435 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1436 ravb_write(ndev, 0, CERCR); /* (write clear) */
1437 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1438 ravb_write(ndev, 0, CEECR); /* (write clear) */
1440 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1441 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1442 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1443 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1444 nstats->multicast = stats0->multicast + stats1->multicast;
1445 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1446 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1447 nstats->rx_frame_errors =
1448 stats0->rx_frame_errors + stats1->rx_frame_errors;
1449 nstats->rx_length_errors =
1450 stats0->rx_length_errors + stats1->rx_length_errors;
1451 nstats->rx_missed_errors =
1452 stats0->rx_missed_errors + stats1->rx_missed_errors;
1453 nstats->rx_over_errors =
1454 stats0->rx_over_errors + stats1->rx_over_errors;
1459 /* Update promiscuous bit */
1460 static void ravb_set_rx_mode(struct net_device *ndev)
1462 struct ravb_private *priv = netdev_priv(ndev);
1463 unsigned long flags;
1465 spin_lock_irqsave(&priv->lock, flags);
1466 ravb_modify(ndev, ECMR, ECMR_PRM,
1467 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1469 spin_unlock_irqrestore(&priv->lock, flags);
1472 /* Device close function for Ethernet AVB */
1473 static int ravb_close(struct net_device *ndev)
1475 struct ravb_private *priv = netdev_priv(ndev);
1476 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1478 netif_tx_stop_all_queues(ndev);
1480 /* Disable interrupts by clearing the interrupt masks. */
1481 ravb_write(ndev, 0, RIC0);
1482 ravb_write(ndev, 0, RIC2);
1483 ravb_write(ndev, 0, TIC);
1485 /* Stop PTP Clock driver */
1486 if (priv->chip_id == RCAR_GEN2)
1487 ravb_ptp_stop(ndev);
1489 /* Set the config mode to stop the AVB-DMAC's processes */
1490 if (ravb_stop_dma(ndev) < 0)
1492 "device will be stopped after h/w processes are done.\n");
1494 /* Clear the timestamp list */
1495 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1496 list_del(&ts_skb->list);
1500 /* PHY disconnect */
1502 phy_stop(priv->phydev);
1503 phy_disconnect(priv->phydev);
1504 priv->phydev = NULL;
1507 free_irq(ndev->irq, ndev);
1509 napi_disable(&priv->napi[RAVB_NC]);
1510 napi_disable(&priv->napi[RAVB_BE]);
1512 /* Free all the skb's in the RX queue and the DMA buffers. */
1513 ravb_ring_free(ndev, RAVB_BE);
1514 ravb_ring_free(ndev, RAVB_NC);
1519 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1521 struct ravb_private *priv = netdev_priv(ndev);
1522 struct hwtstamp_config config;
1525 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1527 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1528 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1529 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1530 config.rx_filter = HWTSTAMP_FILTER_ALL;
1532 config.rx_filter = HWTSTAMP_FILTER_NONE;
1534 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1538 /* Control hardware time stamping */
1539 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1541 struct ravb_private *priv = netdev_priv(ndev);
1542 struct hwtstamp_config config;
1543 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1546 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1549 /* Reserved for future extensions */
1553 switch (config.tx_type) {
1554 case HWTSTAMP_TX_OFF:
1557 case HWTSTAMP_TX_ON:
1558 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1564 switch (config.rx_filter) {
1565 case HWTSTAMP_FILTER_NONE:
1568 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1569 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1572 config.rx_filter = HWTSTAMP_FILTER_ALL;
1573 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1576 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1577 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1579 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1583 /* ioctl to device function */
1584 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1586 struct ravb_private *priv = netdev_priv(ndev);
1587 struct phy_device *phydev = priv->phydev;
1589 if (!netif_running(ndev))
1597 return ravb_hwtstamp_get(ndev, req);
1599 return ravb_hwtstamp_set(ndev, req);
1602 return phy_mii_ioctl(phydev, req, cmd);
1605 static const struct net_device_ops ravb_netdev_ops = {
1606 .ndo_open = ravb_open,
1607 .ndo_stop = ravb_close,
1608 .ndo_start_xmit = ravb_start_xmit,
1609 .ndo_select_queue = ravb_select_queue,
1610 .ndo_get_stats = ravb_get_stats,
1611 .ndo_set_rx_mode = ravb_set_rx_mode,
1612 .ndo_tx_timeout = ravb_tx_timeout,
1613 .ndo_do_ioctl = ravb_do_ioctl,
1614 .ndo_validate_addr = eth_validate_addr,
1615 .ndo_set_mac_address = eth_mac_addr,
1616 .ndo_change_mtu = eth_change_mtu,
1619 /* MDIO bus init function */
1620 static int ravb_mdio_init(struct ravb_private *priv)
1622 struct platform_device *pdev = priv->pdev;
1623 struct device *dev = &pdev->dev;
1627 priv->mdiobb.ops = &bb_ops;
1629 /* MII controller setting */
1630 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1634 /* Hook up MII support for ethtool */
1635 priv->mii_bus->name = "ravb_mii";
1636 priv->mii_bus->parent = dev;
1637 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1638 pdev->name, pdev->id);
1640 /* Register MDIO bus */
1641 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1648 free_mdio_bitbang(priv->mii_bus);
1652 /* MDIO bus release function */
1653 static int ravb_mdio_release(struct ravb_private *priv)
1655 /* Unregister mdio bus */
1656 mdiobus_unregister(priv->mii_bus);
1658 /* Free bitbang info */
1659 free_mdio_bitbang(priv->mii_bus);
1664 static const struct of_device_id ravb_match_table[] = {
1665 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1666 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1667 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1668 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1669 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1672 MODULE_DEVICE_TABLE(of, ravb_match_table);
1674 static int ravb_set_gti(struct net_device *ndev)
1677 struct device *dev = ndev->dev.parent;
1678 struct device_node *np = dev->of_node;
1683 clk = of_clk_get(np, 0);
1685 dev_err(dev, "could not get clock\n");
1686 return PTR_ERR(clk);
1689 rate = clk_get_rate(clk);
1692 inc = 1000000000ULL << 20;
1695 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1696 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1697 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1701 ravb_write(ndev, inc, GTI);
1706 static int ravb_probe(struct platform_device *pdev)
1708 struct device_node *np = pdev->dev.of_node;
1709 const struct of_device_id *match;
1710 struct ravb_private *priv;
1711 enum ravb_chip_id chip_id;
1712 struct net_device *ndev;
1714 struct resource *res;
1718 "this driver is required to be instantiated from device tree\n");
1722 /* Get base address */
1723 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1725 dev_err(&pdev->dev, "invalid resource\n");
1729 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1730 NUM_TX_QUEUE, NUM_RX_QUEUE);
1734 pm_runtime_enable(&pdev->dev);
1735 pm_runtime_get_sync(&pdev->dev);
1737 /* The Ether-specific entries in the device structure. */
1738 ndev->base_addr = res->start;
1741 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev);
1742 chip_id = (enum ravb_chip_id)match->data;
1744 if (chip_id == RCAR_GEN3)
1745 irq = platform_get_irq_byname(pdev, "ch22");
1747 irq = platform_get_irq(pdev, 0);
1754 SET_NETDEV_DEV(ndev, &pdev->dev);
1756 priv = netdev_priv(ndev);
1759 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1760 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1761 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1762 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1763 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1764 if (IS_ERR(priv->addr)) {
1765 error = PTR_ERR(priv->addr);
1769 spin_lock_init(&priv->lock);
1770 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1772 priv->phy_interface = of_get_phy_mode(np);
1774 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1775 priv->avb_link_active_low =
1776 of_property_read_bool(np, "renesas,ether-link-active-low");
1778 if (chip_id == RCAR_GEN3) {
1779 irq = platform_get_irq_byname(pdev, "ch24");
1784 priv->emac_irq = irq;
1787 priv->chip_id = chip_id;
1790 ndev->netdev_ops = &ravb_netdev_ops;
1791 ndev->ethtool_ops = &ravb_ethtool_ops;
1793 /* Set AVB config mode */
1794 if (chip_id == RCAR_GEN2) {
1795 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1796 /* Set CSEL value */
1797 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1799 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1800 CCC_GAC | CCC_CSEL_HPB);
1803 /* Set CSEL value */
1804 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1808 error = ravb_set_gti(ndev);
1812 /* Request GTI loading */
1813 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
1815 /* Allocate descriptor base address table */
1816 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
1817 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
1818 &priv->desc_bat_dma, GFP_KERNEL);
1819 if (!priv->desc_bat) {
1821 "Cannot allocate desc base address table (size %d bytes)\n",
1822 priv->desc_bat_size);
1826 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1827 priv->desc_bat[q].die_dt = DT_EOS;
1828 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1830 /* Initialise HW timestamp list */
1831 INIT_LIST_HEAD(&priv->ts_skb_list);
1833 /* Initialise PTP Clock driver */
1834 if (chip_id != RCAR_GEN2)
1835 ravb_ptp_init(ndev, pdev);
1837 /* Debug message level */
1838 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1840 /* Read and set MAC address */
1841 ravb_read_mac_address(ndev, of_get_mac_address(np));
1842 if (!is_valid_ether_addr(ndev->dev_addr)) {
1843 dev_warn(&pdev->dev,
1844 "no valid MAC address supplied, using a random one\n");
1845 eth_hw_addr_random(ndev);
1849 error = ravb_mdio_init(priv);
1851 dev_err(&pdev->dev, "failed to initialize MDIO\n");
1855 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1856 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1858 /* Network device register */
1859 error = register_netdev(ndev);
1863 /* Print device information */
1864 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1865 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1867 platform_set_drvdata(pdev, ndev);
1872 netif_napi_del(&priv->napi[RAVB_NC]);
1873 netif_napi_del(&priv->napi[RAVB_BE]);
1874 ravb_mdio_release(priv);
1876 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1877 priv->desc_bat_dma);
1879 /* Stop PTP Clock driver */
1880 if (chip_id != RCAR_GEN2)
1881 ravb_ptp_stop(ndev);
1886 pm_runtime_put(&pdev->dev);
1887 pm_runtime_disable(&pdev->dev);
1891 static int ravb_remove(struct platform_device *pdev)
1893 struct net_device *ndev = platform_get_drvdata(pdev);
1894 struct ravb_private *priv = netdev_priv(ndev);
1896 /* Stop PTP Clock driver */
1897 if (priv->chip_id != RCAR_GEN2)
1898 ravb_ptp_stop(ndev);
1900 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1901 priv->desc_bat_dma);
1902 /* Set reset mode */
1903 ravb_write(ndev, CCC_OPC_RESET, CCC);
1904 pm_runtime_put_sync(&pdev->dev);
1905 unregister_netdev(ndev);
1906 netif_napi_del(&priv->napi[RAVB_NC]);
1907 netif_napi_del(&priv->napi[RAVB_BE]);
1908 ravb_mdio_release(priv);
1909 pm_runtime_disable(&pdev->dev);
1911 platform_set_drvdata(pdev, NULL);
1917 static int ravb_runtime_nop(struct device *dev)
1919 /* Runtime PM callback shared between ->runtime_suspend()
1920 * and ->runtime_resume(). Simply returns success.
1922 * This driver re-initializes all registers after
1923 * pm_runtime_get_sync() anyway so there is no need
1924 * to save and restore registers here.
1929 static const struct dev_pm_ops ravb_dev_pm_ops = {
1930 .runtime_suspend = ravb_runtime_nop,
1931 .runtime_resume = ravb_runtime_nop,
1934 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
1936 #define RAVB_PM_OPS NULL
1939 static struct platform_driver ravb_driver = {
1940 .probe = ravb_probe,
1941 .remove = ravb_remove,
1945 .of_match_table = ravb_match_table,
1949 module_platform_driver(ravb_driver);
1951 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1952 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1953 MODULE_LICENSE("GPL v2");