1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/sys_soc.h>
36 #include <asm/div64.h>
40 #define RAVB_DEF_MSG_ENABLE \
46 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
51 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
56 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
59 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
62 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
66 for (i = 0; i < 10000; i++) {
67 if ((ravb_read(ndev, reg) & mask) == value)
74 static int ravb_config(struct net_device *ndev)
79 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
80 /* Check if the operating mode is changed to the config mode */
81 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
83 netdev_err(ndev, "failed to switch device to config mode\n");
88 static void ravb_set_duplex(struct net_device *ndev)
90 struct ravb_private *priv = netdev_priv(ndev);
92 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
95 static void ravb_set_rate(struct net_device *ndev)
97 struct ravb_private *priv = netdev_priv(ndev);
99 switch (priv->speed) {
100 case 100: /* 100BASE */
101 ravb_write(ndev, GECMR_SPEED_100, GECMR);
103 case 1000: /* 1000BASE */
104 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
109 static void ravb_set_buffer_align(struct sk_buff *skb)
111 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
114 skb_reserve(skb, RAVB_ALIGN - reserve);
117 /* Get MAC address from the MAC address registers
119 * Ethernet AVB device doesn't have ROM for MAC address.
120 * This function gets the MAC address that was used by a bootloader.
122 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
125 ether_addr_copy(ndev->dev_addr, mac);
127 u32 mahr = ravb_read(ndev, MAHR);
128 u32 malr = ravb_read(ndev, MALR);
130 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
131 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
132 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
133 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
134 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
135 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
139 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
141 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
144 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
147 /* MDC pin control */
148 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
150 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
153 /* Data I/O pin control */
154 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
156 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
160 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
162 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
166 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
168 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
171 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
174 /* MDIO bus control struct */
175 static struct mdiobb_ops bb_ops = {
176 .owner = THIS_MODULE,
177 .set_mdc = ravb_set_mdc,
178 .set_mdio_dir = ravb_set_mdio_dir,
179 .set_mdio_data = ravb_set_mdio_data,
180 .get_mdio_data = ravb_get_mdio_data,
183 /* Free TX skb function for AVB-IP */
184 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
186 struct ravb_private *priv = netdev_priv(ndev);
187 struct net_device_stats *stats = &priv->stats[q];
188 struct ravb_tx_desc *desc;
193 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
196 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
198 desc = &priv->tx_ring[q][entry];
199 txed = desc->die_dt == DT_FEMPTY;
200 if (free_txed_only && !txed)
202 /* Descriptor type must be checked before all other reads */
204 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
205 /* Free the original skb. */
206 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
207 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
208 size, DMA_TO_DEVICE);
209 /* Last packet descriptor? */
210 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
211 entry /= NUM_TX_DESC;
212 dev_kfree_skb_any(priv->tx_skb[q][entry]);
213 priv->tx_skb[q][entry] = NULL;
220 stats->tx_bytes += size;
221 desc->die_dt = DT_EEMPTY;
226 /* Free skb's and DMA buffers for Ethernet AVB */
227 static void ravb_ring_free(struct net_device *ndev, int q)
229 struct ravb_private *priv = netdev_priv(ndev);
233 /* Free RX skb ringbuffer */
234 if (priv->rx_skb[q]) {
235 for (i = 0; i < priv->num_rx_ring[q]; i++)
236 dev_kfree_skb(priv->rx_skb[q][i]);
238 kfree(priv->rx_skb[q]);
239 priv->rx_skb[q] = NULL;
241 /* Free aligned TX buffers */
242 kfree(priv->tx_align[q]);
243 priv->tx_align[q] = NULL;
245 if (priv->rx_ring[q]) {
246 for (i = 0; i < priv->num_rx_ring[q]; i++) {
247 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
249 if (!dma_mapping_error(ndev->dev.parent,
250 le32_to_cpu(desc->dptr)))
251 dma_unmap_single(ndev->dev.parent,
252 le32_to_cpu(desc->dptr),
256 ring_size = sizeof(struct ravb_ex_rx_desc) *
257 (priv->num_rx_ring[q] + 1);
258 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
259 priv->rx_desc_dma[q]);
260 priv->rx_ring[q] = NULL;
263 if (priv->tx_ring[q]) {
264 ravb_tx_free(ndev, q, false);
266 ring_size = sizeof(struct ravb_tx_desc) *
267 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
268 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
269 priv->tx_desc_dma[q]);
270 priv->tx_ring[q] = NULL;
273 /* Free TX skb ringbuffer.
274 * SKBs are freed by ravb_tx_free() call above.
276 kfree(priv->tx_skb[q]);
277 priv->tx_skb[q] = NULL;
280 /* Format skb and descriptor buffer for Ethernet AVB */
281 static void ravb_ring_format(struct net_device *ndev, int q)
283 struct ravb_private *priv = netdev_priv(ndev);
284 struct ravb_ex_rx_desc *rx_desc;
285 struct ravb_tx_desc *tx_desc;
286 struct ravb_desc *desc;
287 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
288 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
295 priv->dirty_rx[q] = 0;
296 priv->dirty_tx[q] = 0;
298 memset(priv->rx_ring[q], 0, rx_ring_size);
299 /* Build RX ring buffer */
300 for (i = 0; i < priv->num_rx_ring[q]; i++) {
302 rx_desc = &priv->rx_ring[q][i];
303 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
304 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
307 /* We just set the data size to 0 for a failed mapping which
308 * should prevent DMA from happening...
310 if (dma_mapping_error(ndev->dev.parent, dma_addr))
311 rx_desc->ds_cc = cpu_to_le16(0);
312 rx_desc->dptr = cpu_to_le32(dma_addr);
313 rx_desc->die_dt = DT_FEMPTY;
315 rx_desc = &priv->rx_ring[q][i];
316 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
317 rx_desc->die_dt = DT_LINKFIX; /* type */
319 memset(priv->tx_ring[q], 0, tx_ring_size);
320 /* Build TX ring buffer */
321 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
323 tx_desc->die_dt = DT_EEMPTY;
325 tx_desc->die_dt = DT_EEMPTY;
327 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
328 tx_desc->die_dt = DT_LINKFIX; /* type */
330 /* RX descriptor base address for best effort */
331 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
332 desc->die_dt = DT_LINKFIX; /* type */
333 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
335 /* TX descriptor base address for best effort */
336 desc = &priv->desc_bat[q];
337 desc->die_dt = DT_LINKFIX; /* type */
338 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
341 /* Init skb and descriptor buffer for Ethernet AVB */
342 static int ravb_ring_init(struct net_device *ndev, int q)
344 struct ravb_private *priv = netdev_priv(ndev);
349 /* Allocate RX and TX skb rings */
350 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
351 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
352 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
353 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
354 if (!priv->rx_skb[q] || !priv->tx_skb[q])
357 for (i = 0; i < priv->num_rx_ring[q]; i++) {
358 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
361 ravb_set_buffer_align(skb);
362 priv->rx_skb[q][i] = skb;
365 /* Allocate rings for the aligned buffers */
366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
367 DPTR_ALIGN - 1, GFP_KERNEL);
368 if (!priv->tx_align[q])
371 /* Allocate all RX descriptors. */
372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
374 &priv->rx_desc_dma[q],
376 if (!priv->rx_ring[q])
379 priv->dirty_rx[q] = 0;
381 /* Allocate all TX descriptors. */
382 ring_size = sizeof(struct ravb_tx_desc) *
383 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
385 &priv->tx_desc_dma[q],
387 if (!priv->tx_ring[q])
393 ravb_ring_free(ndev, q);
398 /* E-MAC init function */
399 static void ravb_emac_init(struct net_device *ndev)
401 struct ravb_private *priv = netdev_priv(ndev);
403 /* Receive frame limit set register */
404 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
406 /* PAUSE prohibition */
407 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
408 ECMR_TE | ECMR_RE, ECMR);
412 /* Set MAC address */
414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
419 /* E-MAC status register clear */
420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
422 /* E-MAC interrupt enable register */
423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
426 /* Device init function for Ethernet AVB */
427 static int ravb_dmac_init(struct net_device *ndev)
429 struct ravb_private *priv = netdev_priv(ndev);
432 /* Set CONFIG mode */
433 error = ravb_config(ndev);
437 error = ravb_ring_init(ndev, RAVB_BE);
440 error = ravb_ring_init(ndev, RAVB_NC);
442 ravb_ring_free(ndev, RAVB_BE);
446 /* Descriptor format */
447 ravb_ring_format(ndev, RAVB_BE);
448 ravb_ring_format(ndev, RAVB_NC);
450 #if defined(__LITTLE_ENDIAN)
451 ravb_modify(ndev, CCC, CCC_BOC, 0);
453 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
458 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
461 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
463 /* Timestamp enable */
464 ravb_write(ndev, TCCR_TFEN, TCCR);
466 /* Interrupt init: */
467 if (priv->chip_id == RCAR_GEN3) {
469 ravb_write(ndev, 0, DIL);
470 /* Set queue specific interrupt */
471 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
474 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
475 /* Disable FIFO full warning */
476 ravb_write(ndev, 0, RIC1);
477 /* Receive FIFO full error, descriptor empty */
478 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
479 /* Frame transmitted, timestamp FIFO updated */
480 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
482 /* Setting the control will start the AVB-DMAC process. */
483 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
488 static void ravb_get_tx_tstamp(struct net_device *ndev)
490 struct ravb_private *priv = netdev_priv(ndev);
491 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
492 struct skb_shared_hwtstamps shhwtstamps;
494 struct timespec64 ts;
499 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
501 tfa2 = ravb_read(ndev, TFA2);
502 tfa_tag = (tfa2 & TFA2_TST) >> 16;
503 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
504 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
505 ravb_read(ndev, TFA1);
506 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
507 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
508 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
512 list_del(&ts_skb->list);
514 if (tag == tfa_tag) {
515 skb_tstamp_tx(skb, &shhwtstamps);
519 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
523 /* Packet receive function for Ethernet AVB */
524 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
526 struct ravb_private *priv = netdev_priv(ndev);
527 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
528 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
530 struct net_device_stats *stats = &priv->stats[q];
531 struct ravb_ex_rx_desc *desc;
534 struct timespec64 ts;
539 boguscnt = min(boguscnt, *quota);
541 desc = &priv->rx_ring[q][entry];
542 while (desc->die_dt != DT_FEMPTY) {
543 /* Descriptor type must be checked before all other reads */
545 desc_status = desc->msc;
546 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
551 /* We use 0-byte descriptors to mark the DMA mapping errors */
555 if (desc_status & MSC_MC)
558 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
561 if (desc_status & MSC_CRC)
562 stats->rx_crc_errors++;
563 if (desc_status & MSC_RFE)
564 stats->rx_frame_errors++;
565 if (desc_status & (MSC_RTLF | MSC_RTSF))
566 stats->rx_length_errors++;
567 if (desc_status & MSC_CEEF)
568 stats->rx_missed_errors++;
570 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
572 skb = priv->rx_skb[q][entry];
573 priv->rx_skb[q][entry] = NULL;
574 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
577 get_ts &= (q == RAVB_NC) ?
578 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
579 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
581 struct skb_shared_hwtstamps *shhwtstamps;
583 shhwtstamps = skb_hwtstamps(skb);
584 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
585 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
586 32) | le32_to_cpu(desc->ts_sl);
587 ts.tv_nsec = le32_to_cpu(desc->ts_n);
588 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
590 skb_put(skb, pkt_len);
591 skb->protocol = eth_type_trans(skb, ndev);
592 napi_gro_receive(&priv->napi[q], skb);
594 stats->rx_bytes += pkt_len;
597 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
598 desc = &priv->rx_ring[q][entry];
601 /* Refill the RX ring buffers. */
602 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
603 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
604 desc = &priv->rx_ring[q][entry];
605 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
607 if (!priv->rx_skb[q][entry]) {
608 skb = netdev_alloc_skb(ndev,
609 PKT_BUF_SZ + RAVB_ALIGN - 1);
611 break; /* Better luck next round. */
612 ravb_set_buffer_align(skb);
613 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
614 le16_to_cpu(desc->ds_cc),
616 skb_checksum_none_assert(skb);
617 /* We just set the data size to 0 for a failed mapping
618 * which should prevent DMA from happening...
620 if (dma_mapping_error(ndev->dev.parent, dma_addr))
621 desc->ds_cc = cpu_to_le16(0);
622 desc->dptr = cpu_to_le32(dma_addr);
623 priv->rx_skb[q][entry] = skb;
625 /* Descriptor type must be set after all the above writes */
627 desc->die_dt = DT_FEMPTY;
630 *quota -= limit - (++boguscnt);
632 return boguscnt <= 0;
635 static void ravb_rcv_snd_disable(struct net_device *ndev)
637 /* Disable TX and RX */
638 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
641 static void ravb_rcv_snd_enable(struct net_device *ndev)
643 /* Enable TX and RX */
644 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
647 /* function for waiting dma process finished */
648 static int ravb_stop_dma(struct net_device *ndev)
652 /* Wait for stopping the hardware TX process */
653 error = ravb_wait(ndev, TCCR,
654 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
658 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
663 /* Stop the E-MAC's RX/TX processes. */
664 ravb_rcv_snd_disable(ndev);
666 /* Wait for stopping the RX DMA process */
667 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
671 /* Stop AVB-DMAC process */
672 return ravb_config(ndev);
675 /* E-MAC interrupt handler */
676 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
678 struct ravb_private *priv = netdev_priv(ndev);
681 ecsr = ravb_read(ndev, ECSR);
682 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
684 ndev->stats.tx_carrier_errors++;
685 if (ecsr & ECSR_LCHNG) {
687 if (priv->no_avb_link)
689 psr = ravb_read(ndev, PSR);
690 if (priv->avb_link_active_low)
692 if (!(psr & PSR_LMON)) {
693 /* DIsable RX and TX */
694 ravb_rcv_snd_disable(ndev);
696 /* Enable RX and TX */
697 ravb_rcv_snd_enable(ndev);
702 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
704 struct net_device *ndev = dev_id;
705 struct ravb_private *priv = netdev_priv(ndev);
707 spin_lock(&priv->lock);
708 ravb_emac_interrupt_unlocked(ndev);
710 spin_unlock(&priv->lock);
714 /* Error interrupt handler */
715 static void ravb_error_interrupt(struct net_device *ndev)
717 struct ravb_private *priv = netdev_priv(ndev);
720 eis = ravb_read(ndev, EIS);
721 ravb_write(ndev, ~EIS_QFS, EIS);
723 ris2 = ravb_read(ndev, RIS2);
724 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
726 /* Receive Descriptor Empty int */
727 if (ris2 & RIS2_QFF0)
728 priv->stats[RAVB_BE].rx_over_errors++;
730 /* Receive Descriptor Empty int */
731 if (ris2 & RIS2_QFF1)
732 priv->stats[RAVB_NC].rx_over_errors++;
734 /* Receive FIFO Overflow int */
735 if (ris2 & RIS2_RFFF)
736 priv->rx_fifo_errors++;
740 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
742 struct ravb_private *priv = netdev_priv(ndev);
743 u32 ris0 = ravb_read(ndev, RIS0);
744 u32 ric0 = ravb_read(ndev, RIC0);
745 u32 tis = ravb_read(ndev, TIS);
746 u32 tic = ravb_read(ndev, TIC);
748 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
749 if (napi_schedule_prep(&priv->napi[q])) {
750 /* Mask RX and TX interrupts */
751 if (priv->chip_id == RCAR_GEN2) {
752 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
753 ravb_write(ndev, tic & ~BIT(q), TIC);
755 ravb_write(ndev, BIT(q), RID0);
756 ravb_write(ndev, BIT(q), TID);
758 __napi_schedule(&priv->napi[q]);
761 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
764 " tx status 0x%08x, tx mask 0x%08x.\n",
772 static bool ravb_timestamp_interrupt(struct net_device *ndev)
774 u32 tis = ravb_read(ndev, TIS);
776 if (tis & TIS_TFUF) {
777 ravb_write(ndev, ~TIS_TFUF, TIS);
778 ravb_get_tx_tstamp(ndev);
784 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
786 struct net_device *ndev = dev_id;
787 struct ravb_private *priv = netdev_priv(ndev);
788 irqreturn_t result = IRQ_NONE;
791 spin_lock(&priv->lock);
792 /* Get interrupt status */
793 iss = ravb_read(ndev, ISS);
795 /* Received and transmitted interrupts */
796 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
799 /* Timestamp updated */
800 if (ravb_timestamp_interrupt(ndev))
801 result = IRQ_HANDLED;
803 /* Network control and best effort queue RX/TX */
804 for (q = RAVB_NC; q >= RAVB_BE; q--) {
805 if (ravb_queue_interrupt(ndev, q))
806 result = IRQ_HANDLED;
810 /* E-MAC status summary */
812 ravb_emac_interrupt_unlocked(ndev);
813 result = IRQ_HANDLED;
816 /* Error status summary */
818 ravb_error_interrupt(ndev);
819 result = IRQ_HANDLED;
822 /* gPTP interrupt status summary */
823 if (iss & ISS_CGIS) {
824 ravb_ptp_interrupt(ndev);
825 result = IRQ_HANDLED;
829 spin_unlock(&priv->lock);
833 /* Timestamp/Error/gPTP interrupt handler */
834 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
836 struct net_device *ndev = dev_id;
837 struct ravb_private *priv = netdev_priv(ndev);
838 irqreturn_t result = IRQ_NONE;
841 spin_lock(&priv->lock);
842 /* Get interrupt status */
843 iss = ravb_read(ndev, ISS);
845 /* Timestamp updated */
846 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
847 result = IRQ_HANDLED;
849 /* Error status summary */
851 ravb_error_interrupt(ndev);
852 result = IRQ_HANDLED;
855 /* gPTP interrupt status summary */
856 if (iss & ISS_CGIS) {
857 ravb_ptp_interrupt(ndev);
858 result = IRQ_HANDLED;
862 spin_unlock(&priv->lock);
866 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
868 struct net_device *ndev = dev_id;
869 struct ravb_private *priv = netdev_priv(ndev);
870 irqreturn_t result = IRQ_NONE;
872 spin_lock(&priv->lock);
874 /* Network control/Best effort queue RX/TX */
875 if (ravb_queue_interrupt(ndev, q))
876 result = IRQ_HANDLED;
879 spin_unlock(&priv->lock);
883 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
885 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
888 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
890 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
893 static int ravb_poll(struct napi_struct *napi, int budget)
895 struct net_device *ndev = napi->dev;
896 struct ravb_private *priv = netdev_priv(ndev);
898 int q = napi - priv->napi;
904 tis = ravb_read(ndev, TIS);
905 ris0 = ravb_read(ndev, RIS0);
906 if (!((ris0 & mask) || (tis & mask)))
909 /* Processing RX Descriptor Ring */
911 /* Clear RX interrupt */
912 ravb_write(ndev, ~mask, RIS0);
913 if (ravb_rx(ndev, "a, q))
916 /* Processing TX Descriptor Ring */
918 spin_lock_irqsave(&priv->lock, flags);
919 /* Clear TX interrupt */
920 ravb_write(ndev, ~mask, TIS);
921 ravb_tx_free(ndev, q, true);
922 netif_wake_subqueue(ndev, q);
924 spin_unlock_irqrestore(&priv->lock, flags);
930 /* Re-enable RX/TX interrupts */
931 spin_lock_irqsave(&priv->lock, flags);
932 if (priv->chip_id == RCAR_GEN2) {
933 ravb_modify(ndev, RIC0, mask, mask);
934 ravb_modify(ndev, TIC, mask, mask);
936 ravb_write(ndev, mask, RIE0);
937 ravb_write(ndev, mask, TIE);
940 spin_unlock_irqrestore(&priv->lock, flags);
942 /* Receive error message handling */
943 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
944 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
945 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
946 ndev->stats.rx_over_errors = priv->rx_over_errors;
947 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
948 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
950 return budget - quota;
953 /* PHY state control function */
954 static void ravb_adjust_link(struct net_device *ndev)
956 struct ravb_private *priv = netdev_priv(ndev);
957 struct phy_device *phydev = ndev->phydev;
958 bool new_state = false;
961 if (phydev->duplex != priv->duplex) {
963 priv->duplex = phydev->duplex;
964 ravb_set_duplex(ndev);
967 if (phydev->speed != priv->speed) {
969 priv->speed = phydev->speed;
973 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
975 priv->link = phydev->link;
976 if (priv->no_avb_link)
977 ravb_rcv_snd_enable(ndev);
979 } else if (priv->link) {
984 if (priv->no_avb_link)
985 ravb_rcv_snd_disable(ndev);
988 if (new_state && netif_msg_link(priv))
989 phy_print_status(phydev);
992 static const struct soc_device_attribute r8a7795es10[] = {
993 { .soc_id = "r8a7795", .revision = "ES1.0", },
997 /* PHY init function */
998 static int ravb_phy_init(struct net_device *ndev)
1000 struct device_node *np = ndev->dev.parent->of_node;
1001 struct ravb_private *priv = netdev_priv(ndev);
1002 struct phy_device *phydev;
1003 struct device_node *pn;
1010 /* Try connecting to PHY */
1011 pn = of_parse_phandle(np, "phy-handle", 0);
1013 /* In the case of a fixed PHY, the DT node associated
1014 * to the PHY is the Ethernet MAC DT node.
1016 if (of_phy_is_fixed_link(np)) {
1017 err = of_phy_register_fixed_link(np);
1021 pn = of_node_get(np);
1023 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1024 priv->phy_interface);
1027 netdev_err(ndev, "failed to connect PHY\n");
1029 goto err_deregister_fixed_link;
1032 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1035 if (soc_device_match(r8a7795es10)) {
1036 err = phy_set_max_speed(phydev, SPEED_100);
1038 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1039 goto err_phy_disconnect;
1042 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1045 /* 10BASE is not supported */
1046 phydev->supported &= ~PHY_10BT_FEATURES;
1048 phy_attached_info(phydev);
1053 phy_disconnect(phydev);
1054 err_deregister_fixed_link:
1055 if (of_phy_is_fixed_link(np))
1056 of_phy_deregister_fixed_link(np);
1061 /* PHY control start function */
1062 static int ravb_phy_start(struct net_device *ndev)
1066 error = ravb_phy_init(ndev);
1070 phy_start(ndev->phydev);
1075 static int ravb_get_link_ksettings(struct net_device *ndev,
1076 struct ethtool_link_ksettings *cmd)
1078 struct ravb_private *priv = netdev_priv(ndev);
1079 int error = -ENODEV;
1080 unsigned long flags;
1083 spin_lock_irqsave(&priv->lock, flags);
1084 error = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1085 spin_unlock_irqrestore(&priv->lock, flags);
1091 static int ravb_set_link_ksettings(struct net_device *ndev,
1092 const struct ethtool_link_ksettings *cmd)
1094 struct ravb_private *priv = netdev_priv(ndev);
1095 unsigned long flags;
1101 spin_lock_irqsave(&priv->lock, flags);
1103 /* Disable TX and RX */
1104 ravb_rcv_snd_disable(ndev);
1106 error = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1110 if (cmd->base.duplex == DUPLEX_FULL)
1115 ravb_set_duplex(ndev);
1120 /* Enable TX and RX */
1121 ravb_rcv_snd_enable(ndev);
1124 spin_unlock_irqrestore(&priv->lock, flags);
1129 static int ravb_nway_reset(struct net_device *ndev)
1131 struct ravb_private *priv = netdev_priv(ndev);
1132 int error = -ENODEV;
1133 unsigned long flags;
1136 spin_lock_irqsave(&priv->lock, flags);
1137 error = phy_start_aneg(ndev->phydev);
1138 spin_unlock_irqrestore(&priv->lock, flags);
1144 static u32 ravb_get_msglevel(struct net_device *ndev)
1146 struct ravb_private *priv = netdev_priv(ndev);
1148 return priv->msg_enable;
1151 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1153 struct ravb_private *priv = netdev_priv(ndev);
1155 priv->msg_enable = value;
1158 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1159 "rx_queue_0_current",
1160 "tx_queue_0_current",
1163 "rx_queue_0_packets",
1164 "tx_queue_0_packets",
1167 "rx_queue_0_mcast_packets",
1168 "rx_queue_0_errors",
1169 "rx_queue_0_crc_errors",
1170 "rx_queue_0_frame_errors",
1171 "rx_queue_0_length_errors",
1172 "rx_queue_0_missed_errors",
1173 "rx_queue_0_over_errors",
1175 "rx_queue_1_current",
1176 "tx_queue_1_current",
1179 "rx_queue_1_packets",
1180 "tx_queue_1_packets",
1183 "rx_queue_1_mcast_packets",
1184 "rx_queue_1_errors",
1185 "rx_queue_1_crc_errors",
1186 "rx_queue_1_frame_errors",
1187 "rx_queue_1_length_errors",
1188 "rx_queue_1_missed_errors",
1189 "rx_queue_1_over_errors",
1192 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1194 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1198 return RAVB_STATS_LEN;
1204 static void ravb_get_ethtool_stats(struct net_device *ndev,
1205 struct ethtool_stats *stats, u64 *data)
1207 struct ravb_private *priv = netdev_priv(ndev);
1211 /* Device-specific stats */
1212 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1213 struct net_device_stats *stats = &priv->stats[q];
1215 data[i++] = priv->cur_rx[q];
1216 data[i++] = priv->cur_tx[q];
1217 data[i++] = priv->dirty_rx[q];
1218 data[i++] = priv->dirty_tx[q];
1219 data[i++] = stats->rx_packets;
1220 data[i++] = stats->tx_packets;
1221 data[i++] = stats->rx_bytes;
1222 data[i++] = stats->tx_bytes;
1223 data[i++] = stats->multicast;
1224 data[i++] = stats->rx_errors;
1225 data[i++] = stats->rx_crc_errors;
1226 data[i++] = stats->rx_frame_errors;
1227 data[i++] = stats->rx_length_errors;
1228 data[i++] = stats->rx_missed_errors;
1229 data[i++] = stats->rx_over_errors;
1233 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1235 switch (stringset) {
1237 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1242 static void ravb_get_ringparam(struct net_device *ndev,
1243 struct ethtool_ringparam *ring)
1245 struct ravb_private *priv = netdev_priv(ndev);
1247 ring->rx_max_pending = BE_RX_RING_MAX;
1248 ring->tx_max_pending = BE_TX_RING_MAX;
1249 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1250 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1253 static int ravb_set_ringparam(struct net_device *ndev,
1254 struct ethtool_ringparam *ring)
1256 struct ravb_private *priv = netdev_priv(ndev);
1259 if (ring->tx_pending > BE_TX_RING_MAX ||
1260 ring->rx_pending > BE_RX_RING_MAX ||
1261 ring->tx_pending < BE_TX_RING_MIN ||
1262 ring->rx_pending < BE_RX_RING_MIN)
1264 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1267 if (netif_running(ndev)) {
1268 netif_device_detach(ndev);
1269 /* Stop PTP Clock driver */
1270 if (priv->chip_id == RCAR_GEN2)
1271 ravb_ptp_stop(ndev);
1272 /* Wait for DMA stopping */
1273 error = ravb_stop_dma(ndev);
1276 "cannot set ringparam! Any AVB processes are still running?\n");
1279 synchronize_irq(ndev->irq);
1281 /* Free all the skb's in the RX queue and the DMA buffers. */
1282 ravb_ring_free(ndev, RAVB_BE);
1283 ravb_ring_free(ndev, RAVB_NC);
1286 /* Set new parameters */
1287 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1288 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1290 if (netif_running(ndev)) {
1291 error = ravb_dmac_init(ndev);
1294 "%s: ravb_dmac_init() failed, error %d\n",
1299 ravb_emac_init(ndev);
1301 /* Initialise PTP Clock driver */
1302 if (priv->chip_id == RCAR_GEN2)
1303 ravb_ptp_init(ndev, priv->pdev);
1305 netif_device_attach(ndev);
1311 static int ravb_get_ts_info(struct net_device *ndev,
1312 struct ethtool_ts_info *info)
1314 struct ravb_private *priv = netdev_priv(ndev);
1316 info->so_timestamping =
1317 SOF_TIMESTAMPING_TX_SOFTWARE |
1318 SOF_TIMESTAMPING_RX_SOFTWARE |
1319 SOF_TIMESTAMPING_SOFTWARE |
1320 SOF_TIMESTAMPING_TX_HARDWARE |
1321 SOF_TIMESTAMPING_RX_HARDWARE |
1322 SOF_TIMESTAMPING_RAW_HARDWARE;
1323 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1325 (1 << HWTSTAMP_FILTER_NONE) |
1326 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1327 (1 << HWTSTAMP_FILTER_ALL);
1328 info->phc_index = ptp_clock_index(priv->ptp.clock);
1333 static const struct ethtool_ops ravb_ethtool_ops = {
1334 .nway_reset = ravb_nway_reset,
1335 .get_msglevel = ravb_get_msglevel,
1336 .set_msglevel = ravb_set_msglevel,
1337 .get_link = ethtool_op_get_link,
1338 .get_strings = ravb_get_strings,
1339 .get_ethtool_stats = ravb_get_ethtool_stats,
1340 .get_sset_count = ravb_get_sset_count,
1341 .get_ringparam = ravb_get_ringparam,
1342 .set_ringparam = ravb_set_ringparam,
1343 .get_ts_info = ravb_get_ts_info,
1344 .get_link_ksettings = ravb_get_link_ksettings,
1345 .set_link_ksettings = ravb_set_link_ksettings,
1348 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1349 struct net_device *ndev, struct device *dev,
1355 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1358 error = request_irq(irq, handler, 0, name, ndev);
1360 netdev_err(ndev, "cannot request IRQ %s\n", name);
1365 /* Network device open function for Ethernet AVB */
1366 static int ravb_open(struct net_device *ndev)
1368 struct ravb_private *priv = netdev_priv(ndev);
1369 struct platform_device *pdev = priv->pdev;
1370 struct device *dev = &pdev->dev;
1373 napi_enable(&priv->napi[RAVB_BE]);
1374 napi_enable(&priv->napi[RAVB_NC]);
1376 if (priv->chip_id == RCAR_GEN2) {
1377 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1380 netdev_err(ndev, "cannot request IRQ\n");
1384 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1388 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1392 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1393 ndev, dev, "ch0:rx_be");
1395 goto out_free_irq_emac;
1396 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1397 ndev, dev, "ch18:tx_be");
1399 goto out_free_irq_be_rx;
1400 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1401 ndev, dev, "ch1:rx_nc");
1403 goto out_free_irq_be_tx;
1404 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1405 ndev, dev, "ch19:tx_nc");
1407 goto out_free_irq_nc_rx;
1411 error = ravb_dmac_init(ndev);
1413 goto out_free_irq_nc_tx;
1414 ravb_emac_init(ndev);
1416 /* Initialise PTP Clock driver */
1417 if (priv->chip_id == RCAR_GEN2)
1418 ravb_ptp_init(ndev, priv->pdev);
1420 netif_tx_start_all_queues(ndev);
1422 /* PHY control start */
1423 error = ravb_phy_start(ndev);
1430 /* Stop PTP Clock driver */
1431 if (priv->chip_id == RCAR_GEN2)
1432 ravb_ptp_stop(ndev);
1434 if (priv->chip_id == RCAR_GEN2)
1436 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1438 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1440 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1442 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1444 free_irq(priv->emac_irq, ndev);
1446 free_irq(ndev->irq, ndev);
1448 napi_disable(&priv->napi[RAVB_NC]);
1449 napi_disable(&priv->napi[RAVB_BE]);
1453 /* Timeout function for Ethernet AVB */
1454 static void ravb_tx_timeout(struct net_device *ndev)
1456 struct ravb_private *priv = netdev_priv(ndev);
1458 netif_err(priv, tx_err, ndev,
1459 "transmit timed out, status %08x, resetting...\n",
1460 ravb_read(ndev, ISS));
1462 /* tx_errors count up */
1463 ndev->stats.tx_errors++;
1465 schedule_work(&priv->work);
1468 static void ravb_tx_timeout_work(struct work_struct *work)
1470 struct ravb_private *priv = container_of(work, struct ravb_private,
1472 struct net_device *ndev = priv->ndev;
1474 netif_tx_stop_all_queues(ndev);
1476 /* Stop PTP Clock driver */
1477 if (priv->chip_id == RCAR_GEN2)
1478 ravb_ptp_stop(ndev);
1480 /* Wait for DMA stopping */
1481 ravb_stop_dma(ndev);
1483 ravb_ring_free(ndev, RAVB_BE);
1484 ravb_ring_free(ndev, RAVB_NC);
1487 ravb_dmac_init(ndev);
1488 ravb_emac_init(ndev);
1490 /* Initialise PTP Clock driver */
1491 if (priv->chip_id == RCAR_GEN2)
1492 ravb_ptp_init(ndev, priv->pdev);
1494 netif_tx_start_all_queues(ndev);
1497 /* Packet transmit function for Ethernet AVB */
1498 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1500 struct ravb_private *priv = netdev_priv(ndev);
1501 u16 q = skb_get_queue_mapping(skb);
1502 struct ravb_tstamp_skb *ts_skb;
1503 struct ravb_tx_desc *desc;
1504 unsigned long flags;
1510 spin_lock_irqsave(&priv->lock, flags);
1511 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1513 netif_err(priv, tx_queued, ndev,
1514 "still transmitting with the full ring!\n");
1515 netif_stop_subqueue(ndev, q);
1516 spin_unlock_irqrestore(&priv->lock, flags);
1517 return NETDEV_TX_BUSY;
1519 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1520 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1522 if (skb_put_padto(skb, ETH_ZLEN))
1525 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1526 entry / NUM_TX_DESC * DPTR_ALIGN;
1527 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1528 /* Zero length DMA descriptors are problematic as they seem to
1529 * terminate DMA transfers. Avoid them by simply using a length of
1530 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1532 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1533 * data by the call to skb_put_padto() above this is safe with
1534 * respect to both the length of the first DMA descriptor (len)
1535 * overflowing the available data and the length of the second DMA
1536 * descriptor (skb->len - len) being negative.
1541 memcpy(buffer, skb->data, len);
1542 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1543 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1546 desc = &priv->tx_ring[q][entry];
1547 desc->ds_tagl = cpu_to_le16(len);
1548 desc->dptr = cpu_to_le32(dma_addr);
1550 buffer = skb->data + len;
1551 len = skb->len - len;
1552 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1553 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1557 desc->ds_tagl = cpu_to_le16(len);
1558 desc->dptr = cpu_to_le32(dma_addr);
1560 /* TX timestamp required */
1562 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1565 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1570 ts_skb->tag = priv->ts_skb_tag++;
1571 priv->ts_skb_tag &= 0x3ff;
1572 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1574 /* TAG and timestamp required flag */
1575 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1576 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1577 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1580 skb_tx_timestamp(skb);
1581 /* Descriptor type must be set after all the above writes */
1583 desc->die_dt = DT_FEND;
1585 desc->die_dt = DT_FSTART;
1587 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1589 priv->cur_tx[q] += NUM_TX_DESC;
1590 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1591 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1592 !ravb_tx_free(ndev, q, true))
1593 netif_stop_subqueue(ndev, q);
1597 spin_unlock_irqrestore(&priv->lock, flags);
1598 return NETDEV_TX_OK;
1601 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1602 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1604 dev_kfree_skb_any(skb);
1605 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1609 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1610 void *accel_priv, select_queue_fallback_t fallback)
1612 /* If skb needs TX timestamp, it is handled in network control queue */
1613 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1618 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1620 struct ravb_private *priv = netdev_priv(ndev);
1621 struct net_device_stats *nstats, *stats0, *stats1;
1623 nstats = &ndev->stats;
1624 stats0 = &priv->stats[RAVB_BE];
1625 stats1 = &priv->stats[RAVB_NC];
1627 nstats->tx_dropped += ravb_read(ndev, TROCR);
1628 ravb_write(ndev, 0, TROCR); /* (write clear) */
1629 nstats->collisions += ravb_read(ndev, CDCR);
1630 ravb_write(ndev, 0, CDCR); /* (write clear) */
1631 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1632 ravb_write(ndev, 0, LCCR); /* (write clear) */
1634 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1635 ravb_write(ndev, 0, CERCR); /* (write clear) */
1636 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1637 ravb_write(ndev, 0, CEECR); /* (write clear) */
1639 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1640 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1641 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1642 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1643 nstats->multicast = stats0->multicast + stats1->multicast;
1644 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1645 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1646 nstats->rx_frame_errors =
1647 stats0->rx_frame_errors + stats1->rx_frame_errors;
1648 nstats->rx_length_errors =
1649 stats0->rx_length_errors + stats1->rx_length_errors;
1650 nstats->rx_missed_errors =
1651 stats0->rx_missed_errors + stats1->rx_missed_errors;
1652 nstats->rx_over_errors =
1653 stats0->rx_over_errors + stats1->rx_over_errors;
1658 /* Update promiscuous bit */
1659 static void ravb_set_rx_mode(struct net_device *ndev)
1661 struct ravb_private *priv = netdev_priv(ndev);
1662 unsigned long flags;
1664 spin_lock_irqsave(&priv->lock, flags);
1665 ravb_modify(ndev, ECMR, ECMR_PRM,
1666 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1668 spin_unlock_irqrestore(&priv->lock, flags);
1671 /* Device close function for Ethernet AVB */
1672 static int ravb_close(struct net_device *ndev)
1674 struct device_node *np = ndev->dev.parent->of_node;
1675 struct ravb_private *priv = netdev_priv(ndev);
1676 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1678 netif_tx_stop_all_queues(ndev);
1680 /* Disable interrupts by clearing the interrupt masks. */
1681 ravb_write(ndev, 0, RIC0);
1682 ravb_write(ndev, 0, RIC2);
1683 ravb_write(ndev, 0, TIC);
1685 /* Stop PTP Clock driver */
1686 if (priv->chip_id == RCAR_GEN2)
1687 ravb_ptp_stop(ndev);
1689 /* Set the config mode to stop the AVB-DMAC's processes */
1690 if (ravb_stop_dma(ndev) < 0)
1692 "device will be stopped after h/w processes are done.\n");
1694 /* Clear the timestamp list */
1695 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1696 list_del(&ts_skb->list);
1700 /* PHY disconnect */
1702 phy_stop(ndev->phydev);
1703 phy_disconnect(ndev->phydev);
1704 if (of_phy_is_fixed_link(np))
1705 of_phy_deregister_fixed_link(np);
1708 if (priv->chip_id != RCAR_GEN2) {
1709 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1710 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1711 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1712 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1713 free_irq(priv->emac_irq, ndev);
1715 free_irq(ndev->irq, ndev);
1717 napi_disable(&priv->napi[RAVB_NC]);
1718 napi_disable(&priv->napi[RAVB_BE]);
1720 /* Free all the skb's in the RX queue and the DMA buffers. */
1721 ravb_ring_free(ndev, RAVB_BE);
1722 ravb_ring_free(ndev, RAVB_NC);
1727 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1729 struct ravb_private *priv = netdev_priv(ndev);
1730 struct hwtstamp_config config;
1733 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1735 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1736 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1737 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1738 config.rx_filter = HWTSTAMP_FILTER_ALL;
1740 config.rx_filter = HWTSTAMP_FILTER_NONE;
1742 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1746 /* Control hardware time stamping */
1747 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1749 struct ravb_private *priv = netdev_priv(ndev);
1750 struct hwtstamp_config config;
1751 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1754 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1757 /* Reserved for future extensions */
1761 switch (config.tx_type) {
1762 case HWTSTAMP_TX_OFF:
1765 case HWTSTAMP_TX_ON:
1766 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1772 switch (config.rx_filter) {
1773 case HWTSTAMP_FILTER_NONE:
1776 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1777 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1780 config.rx_filter = HWTSTAMP_FILTER_ALL;
1781 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1784 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1785 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1787 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1791 /* ioctl to device function */
1792 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1794 struct phy_device *phydev = ndev->phydev;
1796 if (!netif_running(ndev))
1804 return ravb_hwtstamp_get(ndev, req);
1806 return ravb_hwtstamp_set(ndev, req);
1809 return phy_mii_ioctl(phydev, req, cmd);
1812 static const struct net_device_ops ravb_netdev_ops = {
1813 .ndo_open = ravb_open,
1814 .ndo_stop = ravb_close,
1815 .ndo_start_xmit = ravb_start_xmit,
1816 .ndo_select_queue = ravb_select_queue,
1817 .ndo_get_stats = ravb_get_stats,
1818 .ndo_set_rx_mode = ravb_set_rx_mode,
1819 .ndo_tx_timeout = ravb_tx_timeout,
1820 .ndo_do_ioctl = ravb_do_ioctl,
1821 .ndo_validate_addr = eth_validate_addr,
1822 .ndo_set_mac_address = eth_mac_addr,
1825 /* MDIO bus init function */
1826 static int ravb_mdio_init(struct ravb_private *priv)
1828 struct platform_device *pdev = priv->pdev;
1829 struct device *dev = &pdev->dev;
1833 priv->mdiobb.ops = &bb_ops;
1835 /* MII controller setting */
1836 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1840 /* Hook up MII support for ethtool */
1841 priv->mii_bus->name = "ravb_mii";
1842 priv->mii_bus->parent = dev;
1843 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1844 pdev->name, pdev->id);
1846 /* Register MDIO bus */
1847 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1854 free_mdio_bitbang(priv->mii_bus);
1858 /* MDIO bus release function */
1859 static int ravb_mdio_release(struct ravb_private *priv)
1861 /* Unregister mdio bus */
1862 mdiobus_unregister(priv->mii_bus);
1864 /* Free bitbang info */
1865 free_mdio_bitbang(priv->mii_bus);
1870 static const struct of_device_id ravb_match_table[] = {
1871 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1872 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1873 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1874 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1875 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1878 MODULE_DEVICE_TABLE(of, ravb_match_table);
1880 static int ravb_set_gti(struct net_device *ndev)
1883 struct device *dev = ndev->dev.parent;
1884 struct device_node *np = dev->of_node;
1889 clk = of_clk_get(np, 0);
1891 dev_err(dev, "could not get clock\n");
1892 return PTR_ERR(clk);
1895 rate = clk_get_rate(clk);
1901 inc = 1000000000ULL << 20;
1904 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1905 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1906 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1910 ravb_write(ndev, inc, GTI);
1915 static void ravb_set_config_mode(struct net_device *ndev)
1917 struct ravb_private *priv = netdev_priv(ndev);
1919 if (priv->chip_id == RCAR_GEN2) {
1920 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1921 /* Set CSEL value */
1922 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1924 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1925 CCC_GAC | CCC_CSEL_HPB);
1929 /* Set tx and rx clock internal delay modes */
1930 static void ravb_set_delay_mode(struct net_device *ndev)
1932 struct ravb_private *priv = netdev_priv(ndev);
1935 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1936 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1939 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1940 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1943 ravb_modify(ndev, APSR, APSR_DM, set);
1946 static int ravb_probe(struct platform_device *pdev)
1948 struct device_node *np = pdev->dev.of_node;
1949 struct ravb_private *priv;
1950 enum ravb_chip_id chip_id;
1951 struct net_device *ndev;
1953 struct resource *res;
1958 "this driver is required to be instantiated from device tree\n");
1962 /* Get base address */
1963 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1965 dev_err(&pdev->dev, "invalid resource\n");
1969 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1970 NUM_TX_QUEUE, NUM_RX_QUEUE);
1974 pm_runtime_enable(&pdev->dev);
1975 pm_runtime_get_sync(&pdev->dev);
1977 /* The Ether-specific entries in the device structure. */
1978 ndev->base_addr = res->start;
1980 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1982 if (chip_id == RCAR_GEN3)
1983 irq = platform_get_irq_byname(pdev, "ch22");
1985 irq = platform_get_irq(pdev, 0);
1992 SET_NETDEV_DEV(ndev, &pdev->dev);
1994 priv = netdev_priv(ndev);
1997 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1998 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1999 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2000 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2001 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2002 if (IS_ERR(priv->addr)) {
2003 error = PTR_ERR(priv->addr);
2007 spin_lock_init(&priv->lock);
2008 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2010 priv->phy_interface = of_get_phy_mode(np);
2012 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2013 priv->avb_link_active_low =
2014 of_property_read_bool(np, "renesas,ether-link-active-low");
2016 if (chip_id == RCAR_GEN3) {
2017 irq = platform_get_irq_byname(pdev, "ch24");
2022 priv->emac_irq = irq;
2023 for (i = 0; i < NUM_RX_QUEUE; i++) {
2024 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2029 priv->rx_irqs[i] = irq;
2031 for (i = 0; i < NUM_TX_QUEUE; i++) {
2032 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2037 priv->tx_irqs[i] = irq;
2041 priv->chip_id = chip_id;
2044 ndev->netdev_ops = &ravb_netdev_ops;
2045 ndev->ethtool_ops = &ravb_ethtool_ops;
2047 /* Set AVB config mode */
2048 ravb_set_config_mode(ndev);
2051 error = ravb_set_gti(ndev);
2055 /* Request GTI loading */
2056 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2058 if (priv->chip_id != RCAR_GEN2)
2059 ravb_set_delay_mode(ndev);
2061 /* Allocate descriptor base address table */
2062 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2063 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2064 &priv->desc_bat_dma, GFP_KERNEL);
2065 if (!priv->desc_bat) {
2067 "Cannot allocate desc base address table (size %d bytes)\n",
2068 priv->desc_bat_size);
2072 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2073 priv->desc_bat[q].die_dt = DT_EOS;
2074 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2076 /* Initialise HW timestamp list */
2077 INIT_LIST_HEAD(&priv->ts_skb_list);
2079 /* Initialise PTP Clock driver */
2080 if (chip_id != RCAR_GEN2)
2081 ravb_ptp_init(ndev, pdev);
2083 /* Debug message level */
2084 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2086 /* Read and set MAC address */
2087 ravb_read_mac_address(ndev, of_get_mac_address(np));
2088 if (!is_valid_ether_addr(ndev->dev_addr)) {
2089 dev_warn(&pdev->dev,
2090 "no valid MAC address supplied, using a random one\n");
2091 eth_hw_addr_random(ndev);
2095 error = ravb_mdio_init(priv);
2097 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2101 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2102 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2104 /* Network device register */
2105 error = register_netdev(ndev);
2109 /* Print device information */
2110 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2111 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2113 platform_set_drvdata(pdev, ndev);
2118 netif_napi_del(&priv->napi[RAVB_NC]);
2119 netif_napi_del(&priv->napi[RAVB_BE]);
2120 ravb_mdio_release(priv);
2122 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2123 priv->desc_bat_dma);
2125 /* Stop PTP Clock driver */
2126 if (chip_id != RCAR_GEN2)
2127 ravb_ptp_stop(ndev);
2132 pm_runtime_put(&pdev->dev);
2133 pm_runtime_disable(&pdev->dev);
2137 static int ravb_remove(struct platform_device *pdev)
2139 struct net_device *ndev = platform_get_drvdata(pdev);
2140 struct ravb_private *priv = netdev_priv(ndev);
2142 /* Stop PTP Clock driver */
2143 if (priv->chip_id != RCAR_GEN2)
2144 ravb_ptp_stop(ndev);
2146 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2147 priv->desc_bat_dma);
2148 /* Set reset mode */
2149 ravb_write(ndev, CCC_OPC_RESET, CCC);
2150 pm_runtime_put_sync(&pdev->dev);
2151 unregister_netdev(ndev);
2152 netif_napi_del(&priv->napi[RAVB_NC]);
2153 netif_napi_del(&priv->napi[RAVB_BE]);
2154 ravb_mdio_release(priv);
2155 pm_runtime_disable(&pdev->dev);
2157 platform_set_drvdata(pdev, NULL);
2162 static int __maybe_unused ravb_suspend(struct device *dev)
2164 struct net_device *ndev = dev_get_drvdata(dev);
2167 if (netif_running(ndev)) {
2168 netif_device_detach(ndev);
2169 ret = ravb_close(ndev);
2175 static int __maybe_unused ravb_resume(struct device *dev)
2177 struct net_device *ndev = dev_get_drvdata(dev);
2178 struct ravb_private *priv = netdev_priv(ndev);
2181 /* All register have been reset to default values.
2182 * Restore all registers which where setup at probe time and
2183 * reopen device if it was running before system suspended.
2186 /* Set AVB config mode */
2187 ravb_set_config_mode(ndev);
2190 ret = ravb_set_gti(ndev);
2194 /* Request GTI loading */
2195 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2197 if (priv->chip_id != RCAR_GEN2)
2198 ravb_set_delay_mode(ndev);
2200 /* Restore descriptor base address table */
2201 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2203 if (netif_running(ndev)) {
2204 ret = ravb_open(ndev);
2207 netif_device_attach(ndev);
2213 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2215 /* Runtime PM callback shared between ->runtime_suspend()
2216 * and ->runtime_resume(). Simply returns success.
2218 * This driver re-initializes all registers after
2219 * pm_runtime_get_sync() anyway so there is no need
2220 * to save and restore registers here.
2225 static const struct dev_pm_ops ravb_dev_pm_ops = {
2226 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2227 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2230 static struct platform_driver ravb_driver = {
2231 .probe = ravb_probe,
2232 .remove = ravb_remove,
2235 .pm = &ravb_dev_pm_ops,
2236 .of_match_table = ravb_match_table,
2240 module_platform_driver(ravb_driver);
2242 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2243 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2244 MODULE_LICENSE("GPL v2");