drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2016 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_ADRH0]     = 0x0100,
 208
 209         [TXNLCR0]       = 0x0080,
 210         [TXALCR0]       = 0x0084,
 211         [RXNLCR0]       = 0x0088,
 212         [RXALCR0]       = 0x008C,
 213 };
 214
 215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 216         SH_ETH_OFFSET_DEFAULTS,
 217
 218         [ECMR]          = 0x0300,
 219         [RFLR]          = 0x0308,
 220         [ECSR]          = 0x0310,
 221         [ECSIPR]        = 0x0318,
 222         [PIR]           = 0x0320,
 223         [PSR]           = 0x0328,
 224         [RDMLR]         = 0x0340,
 225         [IPGR]          = 0x0350,
 226         [APR]           = 0x0354,
 227         [MPR]           = 0x0358,
 228         [RFCF]          = 0x0360,
 229         [TPAUSER]       = 0x0364,
 230         [TPAUSECR]      = 0x0368,
 231         [MAHR]          = 0x03c0,
 232         [MALR]          = 0x03c8,
 233         [TROCR]         = 0x03d0,
 234         [CDCR]          = 0x03d4,
 235         [LCCR]          = 0x03d8,
 236         [CNDCR]         = 0x03dc,
 237         [CEFCR]         = 0x03e4,
 238         [FRECR]         = 0x03e8,
 239         [TSFRCR]        = 0x03ec,
 240         [TLFRCR]        = 0x03f0,
 241         [RFCR]          = 0x03f4,
 242         [MAFCR]         = 0x03f8,
 243
 244         [EDMR]          = 0x0200,
 245         [EDTRR]         = 0x0208,
 246         [EDRRR]         = 0x0210,
 247         [TDLAR]         = 0x0218,
 248         [RDLAR]         = 0x0220,
 249         [EESR]          = 0x0228,
 250         [EESIPR]        = 0x0230,
 251         [TRSCER]        = 0x0238,
 252         [RMFCR]         = 0x0240,
 253         [TFTR]          = 0x0248,
 254         [FDR]           = 0x0250,
 255         [RMCR]          = 0x0258,
 256         [TFUCR]         = 0x0264,
 257         [RFOCR]         = 0x0268,
 258         [RMIIMODE]      = 0x026c,
 259         [FCFTR]         = 0x0270,
 260         [TRIMD]         = 0x027c,
 261 };
 262
 263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 264         SH_ETH_OFFSET_DEFAULTS,
 265
 266         [ECMR]          = 0x0100,
 267         [RFLR]          = 0x0108,
 268         [ECSR]          = 0x0110,
 269         [ECSIPR]        = 0x0118,
 270         [PIR]           = 0x0120,
 271         [PSR]           = 0x0128,
 272         [RDMLR]         = 0x0140,
 273         [IPGR]          = 0x0150,
 274         [APR]           = 0x0154,
 275         [MPR]           = 0x0158,
 276         [TPAUSER]       = 0x0164,
 277         [RFCF]          = 0x0160,
 278         [TPAUSECR]      = 0x0168,
 279         [BCFRR]         = 0x016c,
 280         [MAHR]          = 0x01c0,
 281         [MALR]          = 0x01c8,
 282         [TROCR]         = 0x01d0,
 283         [CDCR]          = 0x01d4,
 284         [LCCR]          = 0x01d8,
 285         [CNDCR]         = 0x01dc,
 286         [CEFCR]         = 0x01e4,
 287         [FRECR]         = 0x01e8,
 288         [TSFRCR]        = 0x01ec,
 289         [TLFRCR]        = 0x01f0,
 290         [RFCR]          = 0x01f4,
 291         [MAFCR]         = 0x01f8,
 292         [RTRATE]        = 0x01fc,
 293
 294         [EDMR]          = 0x0000,
 295         [EDTRR]         = 0x0008,
 296         [EDRRR]         = 0x0010,
 297         [TDLAR]         = 0x0018,
 298         [RDLAR]         = 0x0020,
 299         [EESR]          = 0x0028,
 300         [EESIPR]        = 0x0030,
 301         [TRSCER]        = 0x0038,
 302         [RMFCR]         = 0x0040,
 303         [TFTR]          = 0x0048,
 304         [FDR]           = 0x0050,
 305         [RMCR]          = 0x0058,
 306         [TFUCR]         = 0x0064,
 307         [RFOCR]         = 0x0068,
 308         [FCFTR]         = 0x0070,
 309         [RPADIR]        = 0x0078,
 310         [TRIMD]         = 0x007c,
 311         [RBWAR]         = 0x00c8,
 312         [RDFAR]         = 0x00cc,
 313         [TBRAR]         = 0x00d4,
 314         [TDFAR]         = 0x00d8,
 315 };
 316
 317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 318         SH_ETH_OFFSET_DEFAULTS,
 319
 320         [EDMR]          = 0x0000,
 321         [EDTRR]         = 0x0004,
 322         [EDRRR]         = 0x0008,
 323         [TDLAR]         = 0x000c,
 324         [RDLAR]         = 0x0010,
 325         [EESR]          = 0x0014,
 326         [EESIPR]        = 0x0018,
 327         [TRSCER]        = 0x001c,
 328         [RMFCR]         = 0x0020,
 329         [TFTR]          = 0x0024,
 330         [FDR]           = 0x0028,
 331         [RMCR]          = 0x002c,
 332         [EDOCR]         = 0x0030,
 333         [FCFTR]         = 0x0034,
 334         [RPADIR]        = 0x0038,
 335         [TRIMD]         = 0x003c,
 336         [RBWAR]         = 0x0040,
 337         [RDFAR]         = 0x0044,
 338         [TBRAR]         = 0x004c,
 339         [TDFAR]         = 0x0050,
 340
 341         [ECMR]          = 0x0160,
 342         [ECSR]          = 0x0164,
 343         [ECSIPR]        = 0x0168,
 344         [PIR]           = 0x016c,
 345         [MAHR]          = 0x0170,
 346         [MALR]          = 0x0174,
 347         [RFLR]          = 0x0178,
 348         [PSR]           = 0x017c,
 349         [TROCR]         = 0x0180,
 350         [CDCR]          = 0x0184,
 351         [LCCR]          = 0x0188,
 352         [CNDCR]         = 0x018c,
 353         [CEFCR]         = 0x0194,
 354         [FRECR]         = 0x0198,
 355         [TSFRCR]        = 0x019c,
 356         [TLFRCR]        = 0x01a0,
 357         [RFCR]          = 0x01a4,
 358         [MAFCR]         = 0x01a8,
 359         [IPGR]          = 0x01b4,
 360         [APR]           = 0x01b8,
 361         [MPR]           = 0x01bc,
 362         [TPAUSER]       = 0x01c4,
 363         [BCFR]          = 0x01cc,
 364
 365         [ARSTR]         = 0x0000,
 366         [TSU_CTRST]     = 0x0004,
 367         [TSU_FWEN0]     = 0x0010,
 368         [TSU_FWEN1]     = 0x0014,
 369         [TSU_FCM]       = 0x0018,
 370         [TSU_BSYSL0]    = 0x0020,
 371         [TSU_BSYSL1]    = 0x0024,
 372         [TSU_PRISL0]    = 0x0028,
 373         [TSU_PRISL1]    = 0x002c,
 374         [TSU_FWSL0]     = 0x0030,
 375         [TSU_FWSL1]     = 0x0034,
 376         [TSU_FWSLC]     = 0x0038,
 377         [TSU_QTAGM0]    = 0x0040,
 378         [TSU_QTAGM1]    = 0x0044,
 379         [TSU_ADQT0]     = 0x0048,
 380         [TSU_ADQT1]     = 0x004c,
 381         [TSU_FWSR]      = 0x0050,
 382         [TSU_FWINMK]    = 0x0054,
 383         [TSU_ADSBSY]    = 0x0060,
 384         [TSU_TEN]       = 0x0064,
 385         [TSU_POST1]     = 0x0070,
 386         [TSU_POST2]     = 0x0074,
 387         [TSU_POST3]     = 0x0078,
 388         [TSU_POST4]     = 0x007c,
 389
 390         [TXNLCR0]       = 0x0080,
 391         [TXALCR0]       = 0x0084,
 392         [RXNLCR0]       = 0x0088,
 393         [RXALCR0]       = 0x008c,
 394         [FWNLCR0]       = 0x0090,
 395         [FWALCR0]       = 0x0094,
 396         [TXNLCR1]       = 0x00a0,
 397         [TXALCR1]       = 0x00a0,
 398         [RXNLCR1]       = 0x00a8,
 399         [RXALCR1]       = 0x00ac,
 400         [FWNLCR1]       = 0x00b0,
 401         [FWALCR1]       = 0x00b4,
 402
 403         [TSU_ADRH0]     = 0x0100,
 404 };
 405
 406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 408
 409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 410 {
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412         u16 offset = mdp->reg_offset[enum_index];
 413
 414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 415                 return;
 416
 417         iowrite32(data, mdp->addr + offset);
 418 }
 419
 420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 421 {
 422         struct sh_eth_private *mdp = netdev_priv(ndev);
 423         u16 offset = mdp->reg_offset[enum_index];
 424
 425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 426                 return ~0U;
 427
 428         return ioread32(mdp->addr + offset);
 429 }
 430
 431 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 432                           u32 set)
 433 {
 434         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 435                      enum_index);
 436 }
 437
 438 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 439 {
 440         return mdp->reg_offset == sh_eth_offset_gigabit;
 441 }
 442
 443 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 444 {
 445         return mdp->reg_offset == sh_eth_offset_fast_rz;
 446 }
 447
 448 static void sh_eth_select_mii(struct net_device *ndev)
 449 {
 450         u32 value = 0x0;
 451         struct sh_eth_private *mdp = netdev_priv(ndev);
 452
 453         switch (mdp->phy_interface) {
 454         case PHY_INTERFACE_MODE_GMII:
 455                 value = 0x2;
 456                 break;
 457         case PHY_INTERFACE_MODE_MII:
 458                 value = 0x1;
 459                 break;
 460         case PHY_INTERFACE_MODE_RMII:
 461                 value = 0x0;
 462                 break;
 463         default:
 464                 netdev_warn(ndev,
 465                             "PHY interface mode was not setup. Set to MII.\n");
 466                 value = 0x1;
 467                 break;
 468         }
 469
 470         sh_eth_write(ndev, value, RMII_MII);
 471 }
 472
 473 static void sh_eth_set_duplex(struct net_device *ndev)
 474 {
 475         struct sh_eth_private *mdp = netdev_priv(ndev);
 476
 477         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 478 }
 479
 480 static void sh_eth_chip_reset(struct net_device *ndev)
 481 {
 482         struct sh_eth_private *mdp = netdev_priv(ndev);
 483
 484         /* reset device */
 485         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 486         mdelay(1);
 487 }
 488
 489 static void sh_eth_set_rate_gether(struct net_device *ndev)
 490 {
 491         struct sh_eth_private *mdp = netdev_priv(ndev);
 492
 493         switch (mdp->speed) {
 494         case 10: /* 10BASE */
 495                 sh_eth_write(ndev, GECMR_10, GECMR);
 496                 break;
 497         case 100:/* 100BASE */
 498                 sh_eth_write(ndev, GECMR_100, GECMR);
 499                 break;
 500         case 1000: /* 1000BASE */
 501                 sh_eth_write(ndev, GECMR_1000, GECMR);
 502                 break;
 503         default:
 504                 break;
 505         }
 506 }
 507
 508 #ifdef CONFIG_OF
 509 /* R7S72100 */
 510 static struct sh_eth_cpu_data r7s72100_data = {
 511         .chip_reset     = sh_eth_chip_reset,
 512         .set_duplex     = sh_eth_set_duplex,
 513
 514         .register_type  = SH_ETH_REG_FAST_RZ,
 515
 516         .ecsr_value     = ECSR_ICD,
 517         .ecsipr_value   = ECSIPR_ICDIP,
 518         .eesipr_value   = 0xff7f009f,
 519
 520         .tx_check       = EESR_TC1 | EESR_FTC,
 521         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 522                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 523                           EESR_TDE | EESR_ECI,
 524         .fdr_value      = 0x0000070f,
 525
 526         .no_psr         = 1,
 527         .apr            = 1,
 528         .mpr            = 1,
 529         .tpauser        = 1,
 530         .hw_swap        = 1,
 531         .rpadir         = 1,
 532         .rpadir_value   = 2 << 16,
 533         .no_trimd       = 1,
 534         .no_ade         = 1,
 535         .hw_crc         = 1,
 536         .tsu            = 1,
 537         .shift_rd0      = 1,
 538 };
 539
 540 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 541 {
 542         struct sh_eth_private *mdp = netdev_priv(ndev);
 543
 544         /* reset device */
 545         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 546         mdelay(1);
 547
 548         sh_eth_select_mii(ndev);
 549 }
 550
 551 /* R8A7740 */
 552 static struct sh_eth_cpu_data r8a7740_data = {
 553         .chip_reset     = sh_eth_chip_reset_r8a7740,
 554         .set_duplex     = sh_eth_set_duplex,
 555         .set_rate       = sh_eth_set_rate_gether,
 556
 557         .register_type  = SH_ETH_REG_GIGABIT,
 558
 559         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 560         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 561         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 562
 563         .tx_check       = EESR_TC1 | EESR_FTC,
 564         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 565                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 566                           EESR_TDE | EESR_ECI,
 567         .fdr_value      = 0x0000070f,
 568
 569         .apr            = 1,
 570         .mpr            = 1,
 571         .tpauser        = 1,
 572         .bculr          = 1,
 573         .hw_swap        = 1,
 574         .rpadir         = 1,
 575         .rpadir_value   = 2 << 16,
 576         .no_trimd       = 1,
 577         .no_ade         = 1,
 578         .tsu            = 1,
 579         .select_mii     = 1,
 580         .shift_rd0      = 1,
 581 };
 582
 583 /* There is CPU dependent code */
 584 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 585 {
 586         struct sh_eth_private *mdp = netdev_priv(ndev);
 587
 588         switch (mdp->speed) {
 589         case 10: /* 10BASE */
 590                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 591                 break;
 592         case 100:/* 100BASE */
 593                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 594                 break;
 595         default:
 596                 break;
 597         }
 598 }
 599
 600 /* R8A7778/9 */
 601 static struct sh_eth_cpu_data r8a777x_data = {
 602         .set_duplex     = sh_eth_set_duplex,
 603         .set_rate       = sh_eth_set_rate_r8a777x,
 604
 605         .register_type  = SH_ETH_REG_FAST_RCAR,
 606
 607         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 608         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 609         .eesipr_value   = 0x01ff009f,
 610
 611         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 612         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 613                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 614                           EESR_ECI,
 615         .fdr_value      = 0x00000f0f,
 616
 617         .apr            = 1,
 618         .mpr            = 1,
 619         .tpauser        = 1,
 620         .hw_swap        = 1,
 621 };
 622
 623 /* R8A7790/1 */
 624 static struct sh_eth_cpu_data r8a779x_data = {
 625         .set_duplex     = sh_eth_set_duplex,
 626         .set_rate       = sh_eth_set_rate_r8a777x,
 627
 628         .register_type  = SH_ETH_REG_FAST_RCAR,
 629
 630         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 631         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 632         .eesipr_value   = 0x01ff009f,
 633
 634         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 635         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 636                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 637                           EESR_ECI,
 638         .fdr_value      = 0x00000f0f,
 639
 640         .trscer_err_mask = DESC_I_RINT8,
 641
 642         .apr            = 1,
 643         .mpr            = 1,
 644         .tpauser        = 1,
 645         .hw_swap        = 1,
 646         .rmiimode       = 1,
 647 };
 648 #endif /* CONFIG_OF */
 649
 650 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 651 {
 652         struct sh_eth_private *mdp = netdev_priv(ndev);
 653
 654         switch (mdp->speed) {
 655         case 10: /* 10BASE */
 656                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 657                 break;
 658         case 100:/* 100BASE */
 659                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 660                 break;
 661         default:
 662                 break;
 663         }
 664 }
 665
 666 /* SH7724 */
 667 static struct sh_eth_cpu_data sh7724_data = {
 668         .set_duplex     = sh_eth_set_duplex,
 669         .set_rate       = sh_eth_set_rate_sh7724,
 670
 671         .register_type  = SH_ETH_REG_FAST_SH4,
 672
 673         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 674         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 675         .eesipr_value   = 0x01ff009f,
 676
 677         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 678         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 679                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 680                           EESR_ECI,
 681
 682         .apr            = 1,
 683         .mpr            = 1,
 684         .tpauser        = 1,
 685         .hw_swap        = 1,
 686         .rpadir         = 1,
 687         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 688 };
 689
 690 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 691 {
 692         struct sh_eth_private *mdp = netdev_priv(ndev);
 693
 694         switch (mdp->speed) {
 695         case 10: /* 10BASE */
 696                 sh_eth_write(ndev, 0, RTRATE);
 697                 break;
 698         case 100:/* 100BASE */
 699                 sh_eth_write(ndev, 1, RTRATE);
 700                 break;
 701         default:
 702                 break;
 703         }
 704 }
 705
 706 /* SH7757 */
 707 static struct sh_eth_cpu_data sh7757_data = {
 708         .set_duplex     = sh_eth_set_duplex,
 709         .set_rate       = sh_eth_set_rate_sh7757,
 710
 711         .register_type  = SH_ETH_REG_FAST_SH4,
 712
 713         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 714
 715         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 716         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 717                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 718                           EESR_ECI,
 719
 720         .irq_flags      = IRQF_SHARED,
 721         .apr            = 1,
 722         .mpr            = 1,
 723         .tpauser        = 1,
 724         .hw_swap        = 1,
 725         .no_ade         = 1,
 726         .rpadir         = 1,
 727         .rpadir_value   = 2 << 16,
 728         .rtrate         = 1,
 729 };
 730
 731 #define SH_GIGA_ETH_BASE        0xfee00000UL
 732 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 733 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 734 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 735 {
 736         int i;
 737         u32 mahr[2], malr[2];
 738
 739         /* save MAHR and MALR */
 740         for (i = 0; i < 2; i++) {
 741                 malr[i] = ioread32((void *)GIGA_MALR(i));
 742                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 743         }
 744
 745         /* reset device */
 746         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 747         mdelay(1);
 748
 749         /* restore MAHR and MALR */
 750         for (i = 0; i < 2; i++) {
 751                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 752                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 753         }
 754 }
 755
 756 static void sh_eth_set_rate_giga(struct net_device *ndev)
 757 {
 758         struct sh_eth_private *mdp = netdev_priv(ndev);
 759
 760         switch (mdp->speed) {
 761         case 10: /* 10BASE */
 762                 sh_eth_write(ndev, 0x00000000, GECMR);
 763                 break;
 764         case 100:/* 100BASE */
 765                 sh_eth_write(ndev, 0x00000010, GECMR);
 766                 break;
 767         case 1000: /* 1000BASE */
 768                 sh_eth_write(ndev, 0x00000020, GECMR);
 769                 break;
 770         default:
 771                 break;
 772         }
 773 }
 774
 775 /* SH7757(GETHERC) */
 776 static struct sh_eth_cpu_data sh7757_data_giga = {
 777         .chip_reset     = sh_eth_chip_reset_giga,
 778         .set_duplex     = sh_eth_set_duplex,
 779         .set_rate       = sh_eth_set_rate_giga,
 780
 781         .register_type  = SH_ETH_REG_GIGABIT,
 782
 783         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 784         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 785         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 786
 787         .tx_check       = EESR_TC1 | EESR_FTC,
 788         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 789                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 790                           EESR_TDE | EESR_ECI,
 791         .fdr_value      = 0x0000072f,
 792
 793         .irq_flags      = IRQF_SHARED,
 794         .apr            = 1,
 795         .mpr            = 1,
 796         .tpauser        = 1,
 797         .bculr          = 1,
 798         .hw_swap        = 1,
 799         .rpadir         = 1,
 800         .rpadir_value   = 2 << 16,
 801         .no_trimd       = 1,
 802         .no_ade         = 1,
 803         .tsu            = 1,
 804 };
 805
 806 /* SH7734 */
 807 static struct sh_eth_cpu_data sh7734_data = {
 808         .chip_reset     = sh_eth_chip_reset,
 809         .set_duplex     = sh_eth_set_duplex,
 810         .set_rate       = sh_eth_set_rate_gether,
 811
 812         .register_type  = SH_ETH_REG_GIGABIT,
 813
 814         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 815         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 816         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 817
 818         .tx_check       = EESR_TC1 | EESR_FTC,
 819         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 820                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 821                           EESR_TDE | EESR_ECI,
 822
 823         .apr            = 1,
 824         .mpr            = 1,
 825         .tpauser        = 1,
 826         .bculr          = 1,
 827         .hw_swap        = 1,
 828         .no_trimd       = 1,
 829         .no_ade         = 1,
 830         .tsu            = 1,
 831         .hw_crc         = 1,
 832         .select_mii     = 1,
 833 };
 834
 835 /* SH7763 */
 836 static struct sh_eth_cpu_data sh7763_data = {
 837         .chip_reset     = sh_eth_chip_reset,
 838         .set_duplex     = sh_eth_set_duplex,
 839         .set_rate       = sh_eth_set_rate_gether,
 840
 841         .register_type  = SH_ETH_REG_GIGABIT,
 842
 843         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 844         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 845         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 846
 847         .tx_check       = EESR_TC1 | EESR_FTC,
 848         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 849                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 850                           EESR_ECI,
 851
 852         .apr            = 1,
 853         .mpr            = 1,
 854         .tpauser        = 1,
 855         .bculr          = 1,
 856         .hw_swap        = 1,
 857         .no_trimd       = 1,
 858         .no_ade         = 1,
 859         .tsu            = 1,
 860         .irq_flags      = IRQF_SHARED,
 861 };
 862
 863 static struct sh_eth_cpu_data sh7619_data = {
 864         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 865
 866         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 867
 868         .apr            = 1,
 869         .mpr            = 1,
 870         .tpauser        = 1,
 871         .hw_swap        = 1,
 872 };
 873
 874 static struct sh_eth_cpu_data sh771x_data = {
 875         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 876
 877         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 878         .tsu            = 1,
 879 };
 880
 881 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 882 {
 883         if (!cd->ecsr_value)
 884                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 885
 886         if (!cd->ecsipr_value)
 887                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 888
 889         if (!cd->fcftr_value)
 890                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 891                                   DEFAULT_FIFO_F_D_RFD;
 892
 893         if (!cd->fdr_value)
 894                 cd->fdr_value = DEFAULT_FDR_INIT;
 895
 896         if (!cd->tx_check)
 897                 cd->tx_check = DEFAULT_TX_CHECK;
 898
 899         if (!cd->eesr_err_check)
 900                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 901
 902         if (!cd->trscer_err_mask)
 903                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 904 }
 905
 906 static int sh_eth_check_reset(struct net_device *ndev)
 907 {
 908         int ret = 0;
 909         int cnt = 100;
 910
 911         while (cnt > 0) {
 912                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 913                         break;
 914                 mdelay(1);
 915                 cnt--;
 916         }
 917         if (cnt <= 0) {
 918                 netdev_err(ndev, "Device reset failed\n");
 919                 ret = -ETIMEDOUT;
 920         }
 921         return ret;
 922 }
 923
 924 static int sh_eth_reset(struct net_device *ndev)
 925 {
 926         struct sh_eth_private *mdp = netdev_priv(ndev);
 927         int ret = 0;
 928
 929         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 930                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 931                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 932
 933                 ret = sh_eth_check_reset(ndev);
 934                 if (ret)
 935                         return ret;
 936
 937                 /* Table Init */
 938                 sh_eth_write(ndev, 0x0, TDLAR);
 939                 sh_eth_write(ndev, 0x0, TDFAR);
 940                 sh_eth_write(ndev, 0x0, TDFXR);
 941                 sh_eth_write(ndev, 0x0, TDFFR);
 942                 sh_eth_write(ndev, 0x0, RDLAR);
 943                 sh_eth_write(ndev, 0x0, RDFAR);
 944                 sh_eth_write(ndev, 0x0, RDFXR);
 945                 sh_eth_write(ndev, 0x0, RDFFR);
 946
 947                 /* Reset HW CRC register */
 948                 if (mdp->cd->hw_crc)
 949                         sh_eth_write(ndev, 0x0, CSMR);
 950
 951                 /* Select MII mode */
 952                 if (mdp->cd->select_mii)
 953                         sh_eth_select_mii(ndev);
 954         } else {
 955                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 956                 mdelay(3);
 957                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 958         }
 959
 960         return ret;
 961 }
 962
 963 static void sh_eth_set_receive_align(struct sk_buff *skb)
 964 {
 965         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 966
 967         if (reserve)
 968                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 969 }
 970
 971 /* Program the hardware MAC address from dev->dev_addr. */
 972 static void update_mac_address(struct net_device *ndev)
 973 {
 974         sh_eth_write(ndev,
 975                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 976                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 977         sh_eth_write(ndev,
 978                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 979 }
 980
 981 /* Get MAC address from SuperH MAC address register
 982  *
 983  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 984  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 985  * When you want use this device, you must set MAC address in bootloader.
 986  *
 987  */
 988 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 989 {
 990         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 991                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 992         } else {
 993                 u32 mahr = sh_eth_read(ndev, MAHR);
 994                 u32 malr = sh_eth_read(ndev, MALR);
 995
 996                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
 997                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
 998                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
 999                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1000                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1001                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1002         }
1003 }
1004
1005 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1006 {
1007         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1008                 return EDTRR_TRNS_GETHER;
1009         else
1010                 return EDTRR_TRNS_ETHER;
1011 }
1012
1013 struct bb_info {
1014         void (*set_gate)(void *addr);
1015         struct mdiobb_ctrl ctrl;
1016         void *addr;
1017 };
1018
1019 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1020 {
1021         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1022         u32 pir;
1023
1024         if (bitbang->set_gate)
1025                 bitbang->set_gate(bitbang->addr);
1026
1027         pir = ioread32(bitbang->addr);
1028         if (set)
1029                 pir |=  mask;
1030         else
1031                 pir &= ~mask;
1032         iowrite32(pir, bitbang->addr);
1033 }
1034
1035 /* Data I/O pin control */
1036 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1037 {
1038         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1039 }
1040
1041 /* Set bit data*/
1042 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1043 {
1044         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1045 }
1046
1047 /* Get bit data*/
1048 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1049 {
1050         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1051
1052         if (bitbang->set_gate)
1053                 bitbang->set_gate(bitbang->addr);
1054
1055         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1056 }
1057
1058 /* MDC pin control */
1059 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1060 {
1061         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1062 }
1063
1064 /* mdio bus control struct */
1065 static struct mdiobb_ops bb_ops = {
1066         .owner = THIS_MODULE,
1067         .set_mdc = sh_mdc_ctrl,
1068         .set_mdio_dir = sh_mmd_ctrl,
1069         .set_mdio_data = sh_set_mdio,
1070         .get_mdio_data = sh_get_mdio,
1071 };
1072
1073 /* free skb and descriptor buffer */
1074 static void sh_eth_ring_free(struct net_device *ndev)
1075 {
1076         struct sh_eth_private *mdp = netdev_priv(ndev);
1077         int ringsize, i;
1078
1079         /* Free Rx skb ringbuffer */
1080         if (mdp->rx_skbuff) {
1081                 for (i = 0; i < mdp->num_rx_ring; i++)
1082                         dev_kfree_skb(mdp->rx_skbuff[i]);
1083         }
1084         kfree(mdp->rx_skbuff);
1085         mdp->rx_skbuff = NULL;
1086
1087         /* Free Tx skb ringbuffer */
1088         if (mdp->tx_skbuff) {
1089                 for (i = 0; i < mdp->num_tx_ring; i++)
1090                         dev_kfree_skb(mdp->tx_skbuff[i]);
1091         }
1092         kfree(mdp->tx_skbuff);
1093         mdp->tx_skbuff = NULL;
1094
1095         if (mdp->rx_ring) {
1096                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1097                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1098                                   mdp->rx_desc_dma);
1099                 mdp->rx_ring = NULL;
1100         }
1101
1102         if (mdp->tx_ring) {
1103                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1104                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1105                                   mdp->tx_desc_dma);
1106                 mdp->tx_ring = NULL;
1107         }
1108 }
1109
1110 /* format skb and descriptor buffer */
1111 static void sh_eth_ring_format(struct net_device *ndev)
1112 {
1113         struct sh_eth_private *mdp = netdev_priv(ndev);
1114         int i;
1115         struct sk_buff *skb;
1116         struct sh_eth_rxdesc *rxdesc = NULL;
1117         struct sh_eth_txdesc *txdesc = NULL;
1118         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1119         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1120         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1121         dma_addr_t dma_addr;
1122         u32 buf_len;
1123
1124         mdp->cur_rx = 0;
1125         mdp->cur_tx = 0;
1126         mdp->dirty_rx = 0;
1127         mdp->dirty_tx = 0;
1128
1129         memset(mdp->rx_ring, 0, rx_ringsize);
1130
1131         /* build Rx ring buffer */
1132         for (i = 0; i < mdp->num_rx_ring; i++) {
1133                 /* skb */
1134                 mdp->rx_skbuff[i] = NULL;
1135                 skb = netdev_alloc_skb(ndev, skbuff_size);
1136                 if (skb == NULL)
1137                         break;
1138                 sh_eth_set_receive_align(skb);
1139
1140                 /* RX descriptor */
1141                 rxdesc = &mdp->rx_ring[i];
1142                 /* The size of the buffer is a multiple of 32 bytes. */
1143                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1144                 rxdesc->len = cpu_to_le32(buf_len << 16);
1145                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1146                                           DMA_FROM_DEVICE);
1147                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1148                         kfree_skb(skb);
1149                         break;
1150                 }
1151                 mdp->rx_skbuff[i] = skb;
1152                 rxdesc->addr = cpu_to_le32(dma_addr);
1153                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1154
1155                 /* Rx descriptor address set */
1156                 if (i == 0) {
1157                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1158                         if (sh_eth_is_gether(mdp) ||
1159                             sh_eth_is_rz_fast_ether(mdp))
1160                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1161                 }
1162         }
1163
1164         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1165
1166         /* Mark the last entry as wrapping the ring. */
1167         rxdesc->status |= cpu_to_le32(RD_RDLE);
1168
1169         memset(mdp->tx_ring, 0, tx_ringsize);
1170
1171         /* build Tx ring buffer */
1172         for (i = 0; i < mdp->num_tx_ring; i++) {
1173                 mdp->tx_skbuff[i] = NULL;
1174                 txdesc = &mdp->tx_ring[i];
1175                 txdesc->status = cpu_to_le32(TD_TFP);
1176                 txdesc->len = cpu_to_le32(0);
1177                 if (i == 0) {
1178                         /* Tx descriptor address set */
1179                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1180                         if (sh_eth_is_gether(mdp) ||
1181                             sh_eth_is_rz_fast_ether(mdp))
1182                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1183                 }
1184         }
1185
1186         txdesc->status |= cpu_to_le32(TD_TDLE);
1187 }
1188
1189 /* Get skb and descriptor buffer */
1190 static int sh_eth_ring_init(struct net_device *ndev)
1191 {
1192         struct sh_eth_private *mdp = netdev_priv(ndev);
1193         int rx_ringsize, tx_ringsize;
1194
1195         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1196          * card needs room to do 8 byte alignment, +2 so we can reserve
1197          * the first 2 bytes, and +16 gets room for the status word from the
1198          * card.
1199          */
1200         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1201                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1202         if (mdp->cd->rpadir)
1203                 mdp->rx_buf_sz += NET_IP_ALIGN;
1204
1205         /* Allocate RX and TX skb rings */
1206         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1207                                  GFP_KERNEL);
1208         if (!mdp->rx_skbuff)
1209                 return -ENOMEM;
1210
1211         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1212                                  GFP_KERNEL);
1213         if (!mdp->tx_skbuff)
1214                 goto ring_free;
1215
1216         /* Allocate all Rx descriptors. */
1217         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1218         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1219                                           GFP_KERNEL);
1220         if (!mdp->rx_ring)
1221                 goto ring_free;
1222
1223         mdp->dirty_rx = 0;
1224
1225         /* Allocate all Tx descriptors. */
1226         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1227         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1228                                           GFP_KERNEL);
1229         if (!mdp->tx_ring)
1230                 goto ring_free;
1231         return 0;
1232
1233 ring_free:
1234         /* Free Rx and Tx skb ring buffer and DMA buffer */
1235         sh_eth_ring_free(ndev);
1236
1237         return -ENOMEM;
1238 }
1239
1240 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1241 {
1242         int ret = 0;
1243         struct sh_eth_private *mdp = netdev_priv(ndev);
1244
1245         /* Soft Reset */
1246         ret = sh_eth_reset(ndev);
1247         if (ret)
1248                 return ret;
1249
1250         if (mdp->cd->rmiimode)
1251                 sh_eth_write(ndev, 0x1, RMIIMODE);
1252
1253         /* Descriptor format */
1254         sh_eth_ring_format(ndev);
1255         if (mdp->cd->rpadir)
1256                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1257
1258         /* all sh_eth int mask */
1259         sh_eth_write(ndev, 0, EESIPR);
1260
1261 #if defined(__LITTLE_ENDIAN)
1262         if (mdp->cd->hw_swap)
1263                 sh_eth_write(ndev, EDMR_EL, EDMR);
1264         else
1265 #endif
1266                 sh_eth_write(ndev, 0, EDMR);
1267
1268         /* FIFO size set */
1269         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1270         sh_eth_write(ndev, 0, TFTR);
1271
1272         /* Frame recv control (enable multiple-packets per rx irq) */
1273         sh_eth_write(ndev, RMCR_RNC, RMCR);
1274
1275         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1276
1277         if (mdp->cd->bculr)
1278                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1279
1280         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1281
1282         if (!mdp->cd->no_trimd)
1283                 sh_eth_write(ndev, 0, TRIMD);
1284
1285         /* Recv frame limit set register */
1286         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1287                      RFLR);
1288
1289         sh_eth_modify(ndev, EESR, 0, 0);
1290         if (start) {
1291                 mdp->irq_enabled = true;
1292                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1293         }
1294
1295         /* PAUSE Prohibition */
1296         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1297                      ECMR_TE | ECMR_RE, ECMR);
1298
1299         if (mdp->cd->set_rate)
1300                 mdp->cd->set_rate(ndev);
1301
1302         /* E-MAC Status Register clear */
1303         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1304
1305         /* E-MAC Interrupt Enable register */
1306         if (start)
1307                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1308
1309         /* Set MAC address */
1310         update_mac_address(ndev);
1311
1312         /* mask reset */
1313         if (mdp->cd->apr)
1314                 sh_eth_write(ndev, APR_AP, APR);
1315         if (mdp->cd->mpr)
1316                 sh_eth_write(ndev, MPR_MP, MPR);
1317         if (mdp->cd->tpauser)
1318                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1319
1320         if (start) {
1321                 /* Setting the Rx mode will start the Rx process. */
1322                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1323
1324                 netif_start_queue(ndev);
1325         }
1326
1327         return ret;
1328 }
1329
1330 static void sh_eth_dev_exit(struct net_device *ndev)
1331 {
1332         struct sh_eth_private *mdp = netdev_priv(ndev);
1333         int i;
1334
1335         /* Deactivate all TX descriptors, so DMA should stop at next
1336          * packet boundary if it's currently running
1337          */
1338         for (i = 0; i < mdp->num_tx_ring; i++)
1339                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1340
1341         /* Disable TX FIFO egress to MAC */
1342         sh_eth_rcv_snd_disable(ndev);
1343
1344         /* Stop RX DMA at next packet boundary */
1345         sh_eth_write(ndev, 0, EDRRR);
1346
1347         /* Aside from TX DMA, we can't tell when the hardware is
1348          * really stopped, so we need to reset to make sure.
1349          * Before doing that, wait for long enough to *probably*
1350          * finish transmitting the last packet and poll stats.
1351          */
1352         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1353         sh_eth_get_stats(ndev);
1354         sh_eth_reset(ndev);
1355
1356         /* Set MAC address again */
1357         update_mac_address(ndev);
1358 }
1359
1360 /* free Tx skb function */
1361 static int sh_eth_txfree(struct net_device *ndev)
1362 {
1363         struct sh_eth_private *mdp = netdev_priv(ndev);
1364         struct sh_eth_txdesc *txdesc;
1365         int free_num = 0;
1366         int entry = 0;
1367
1368         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1369                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1370                 txdesc = &mdp->tx_ring[entry];
1371                 if (txdesc->status & cpu_to_le32(TD_TACT))
1372                         break;
1373                 /* TACT bit must be checked before all the following reads */
1374                 dma_rmb();
1375                 netif_info(mdp, tx_done, ndev,
1376                            "tx entry %d status 0x%08x\n",
1377                            entry, le32_to_cpu(txdesc->status));
1378                 /* Free the original skb. */
1379                 if (mdp->tx_skbuff[entry]) {
1380                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1381                                          le32_to_cpu(txdesc->len) >> 16,
1382                                          DMA_TO_DEVICE);
1383                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1384                         mdp->tx_skbuff[entry] = NULL;
1385                         free_num++;
1386                 }
1387                 txdesc->status = cpu_to_le32(TD_TFP);
1388                 if (entry >= mdp->num_tx_ring - 1)
1389                         txdesc->status |= cpu_to_le32(TD_TDLE);
1390
1391                 ndev->stats.tx_packets++;
1392                 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1393         }
1394         return free_num;
1395 }
1396
1397 /* Packet receive function */
1398 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1399 {
1400         struct sh_eth_private *mdp = netdev_priv(ndev);
1401         struct sh_eth_rxdesc *rxdesc;
1402
1403         int entry = mdp->cur_rx % mdp->num_rx_ring;
1404         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1405         int limit;
1406         struct sk_buff *skb;
1407         u16 pkt_len = 0;
1408         u32 desc_status;
1409         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1410         dma_addr_t dma_addr;
1411         u32 buf_len;
1412
1413         boguscnt = min(boguscnt, *quota);
1414         limit = boguscnt;
1415         rxdesc = &mdp->rx_ring[entry];
1416         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1417                 /* RACT bit must be checked before all the following reads */
1418                 dma_rmb();
1419                 desc_status = le32_to_cpu(rxdesc->status);
1420                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1421
1422                 if (--boguscnt < 0)
1423                         break;
1424
1425                 netif_info(mdp, rx_status, ndev,
1426                            "rx entry %d status 0x%08x len %d\n",
1427                            entry, desc_status, pkt_len);
1428
1429                 if (!(desc_status & RDFEND))
1430                         ndev->stats.rx_length_errors++;
1431
1432                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1433                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1434                  * bit 0. However, in case of the R8A7740 and R7S72100
1435                  * the RFS bits are from bit 25 to bit 16. So, the
1436                  * driver needs right shifting by 16.
1437                  */
1438                 if (mdp->cd->shift_rd0)
1439                         desc_status >>= 16;
1440
1441                 skb = mdp->rx_skbuff[entry];
1442                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1443                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1444                         ndev->stats.rx_errors++;
1445                         if (desc_status & RD_RFS1)
1446                                 ndev->stats.rx_crc_errors++;
1447                         if (desc_status & RD_RFS2)
1448                                 ndev->stats.rx_frame_errors++;
1449                         if (desc_status & RD_RFS3)
1450                                 ndev->stats.rx_length_errors++;
1451                         if (desc_status & RD_RFS4)
1452                                 ndev->stats.rx_length_errors++;
1453                         if (desc_status & RD_RFS6)
1454                                 ndev->stats.rx_missed_errors++;
1455                         if (desc_status & RD_RFS10)
1456                                 ndev->stats.rx_over_errors++;
1457                 } else  if (skb) {
1458                         dma_addr = le32_to_cpu(rxdesc->addr);
1459                         if (!mdp->cd->hw_swap)
1460                                 sh_eth_soft_swap(
1461                                         phys_to_virt(ALIGN(dma_addr, 4)),
1462                                         pkt_len + 2);
1463                         mdp->rx_skbuff[entry] = NULL;
1464                         if (mdp->cd->rpadir)
1465                                 skb_reserve(skb, NET_IP_ALIGN);
1466                         dma_unmap_single(&ndev->dev, dma_addr,
1467                                          ALIGN(mdp->rx_buf_sz, 32),
1468                                          DMA_FROM_DEVICE);
1469                         skb_put(skb, pkt_len);
1470                         skb->protocol = eth_type_trans(skb, ndev);
1471                         netif_receive_skb(skb);
1472                         ndev->stats.rx_packets++;
1473                         ndev->stats.rx_bytes += pkt_len;
1474                         if (desc_status & RD_RFS8)
1475                                 ndev->stats.multicast++;
1476                 }
1477                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1478                 rxdesc = &mdp->rx_ring[entry];
1479         }
1480
1481         /* Refill the Rx ring buffers. */
1482         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1483                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1484                 rxdesc = &mdp->rx_ring[entry];
1485                 /* The size of the buffer is 32 byte boundary. */
1486                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1487                 rxdesc->len = cpu_to_le32(buf_len << 16);
1488
1489                 if (mdp->rx_skbuff[entry] == NULL) {
1490                         skb = netdev_alloc_skb(ndev, skbuff_size);
1491                         if (skb == NULL)
1492                                 break;  /* Better luck next round. */
1493                         sh_eth_set_receive_align(skb);
1494                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1495                                                   buf_len, DMA_FROM_DEVICE);
1496                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1497                                 kfree_skb(skb);
1498                                 break;
1499                         }
1500                         mdp->rx_skbuff[entry] = skb;
1501
1502                         skb_checksum_none_assert(skb);
1503                         rxdesc->addr = cpu_to_le32(dma_addr);
1504                 }
1505                 dma_wmb(); /* RACT bit must be set after all the above writes */
1506                 if (entry >= mdp->num_rx_ring - 1)
1507                         rxdesc->status |=
1508                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1509                 else
1510                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1511         }
1512
1513         /* Restart Rx engine if stopped. */
1514         /* If we don't need to check status, don't. -KDU */
1515         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1516                 /* fix the values for the next receiving if RDE is set */
1517                 if (intr_status & EESR_RDE &&
1518                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1519                         u32 count = (sh_eth_read(ndev, RDFAR) -
1520                                      sh_eth_read(ndev, RDLAR)) >> 4;
1521
1522                         mdp->cur_rx = count;
1523                         mdp->dirty_rx = count;
1524                 }
1525                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1526         }
1527
1528         *quota -= limit - boguscnt - 1;
1529
1530         return *quota <= 0;
1531 }
1532
1533 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1534 {
1535         /* disable tx and rx */
1536         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1537 }
1538
1539 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1540 {
1541         /* enable tx and rx */
1542         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1543 }
1544
1545 /* error control function */
1546 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1547 {
1548         struct sh_eth_private *mdp = netdev_priv(ndev);
1549         u32 felic_stat;
1550         u32 link_stat;
1551         u32 mask;
1552
1553         if (intr_status & EESR_ECI) {
1554                 felic_stat = sh_eth_read(ndev, ECSR);
1555                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1556                 if (felic_stat & ECSR_ICD)
1557                         ndev->stats.tx_carrier_errors++;
1558                 if (felic_stat & ECSR_LCHNG) {
1559                         /* Link Changed */
1560                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1561                                 goto ignore_link;
1562                         } else {
1563                                 link_stat = (sh_eth_read(ndev, PSR));
1564                                 if (mdp->ether_link_active_low)
1565                                         link_stat = ~link_stat;
1566                         }
1567                         if (!(link_stat & PHY_ST_LINK)) {
1568                                 sh_eth_rcv_snd_disable(ndev);
1569                         } else {
1570                                 /* Link Up */
1571                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1572                                 /* clear int */
1573                                 sh_eth_modify(ndev, ECSR, 0, 0);
1574                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1575                                               DMAC_M_ECI);
1576                                 /* enable tx and rx */
1577                                 sh_eth_rcv_snd_enable(ndev);
1578                         }
1579                 }
1580         }
1581
1582 ignore_link:
1583         if (intr_status & EESR_TWB) {
1584                 /* Unused write back interrupt */
1585                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1586                         ndev->stats.tx_aborted_errors++;
1587                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1588                 }
1589         }
1590
1591         if (intr_status & EESR_RABT) {
1592                 /* Receive Abort int */
1593                 if (intr_status & EESR_RFRMER) {
1594                         /* Receive Frame Overflow int */
1595                         ndev->stats.rx_frame_errors++;
1596                 }
1597         }
1598
1599         if (intr_status & EESR_TDE) {
1600                 /* Transmit Descriptor Empty int */
1601                 ndev->stats.tx_fifo_errors++;
1602                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1603         }
1604
1605         if (intr_status & EESR_TFE) {
1606                 /* FIFO under flow */
1607                 ndev->stats.tx_fifo_errors++;
1608                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1609         }
1610
1611         if (intr_status & EESR_RDE) {
1612                 /* Receive Descriptor Empty int */
1613                 ndev->stats.rx_over_errors++;
1614         }
1615
1616         if (intr_status & EESR_RFE) {
1617                 /* Receive FIFO Overflow int */
1618                 ndev->stats.rx_fifo_errors++;
1619         }
1620
1621         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1622                 /* Address Error */
1623                 ndev->stats.tx_fifo_errors++;
1624                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1625         }
1626
1627         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1628         if (mdp->cd->no_ade)
1629                 mask &= ~EESR_ADE;
1630         if (intr_status & mask) {
1631                 /* Tx error */
1632                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1633
1634                 /* dmesg */
1635                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1636                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1637                            (u32)ndev->state, edtrr);
1638                 /* dirty buffer free */
1639                 sh_eth_txfree(ndev);
1640
1641                 /* SH7712 BUG */
1642                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1643                         /* tx dma start */
1644                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1645                 }
1646                 /* wakeup */
1647                 netif_wake_queue(ndev);
1648         }
1649 }
1650
1651 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1652 {
1653         struct net_device *ndev = netdev;
1654         struct sh_eth_private *mdp = netdev_priv(ndev);
1655         struct sh_eth_cpu_data *cd = mdp->cd;
1656         irqreturn_t ret = IRQ_NONE;
1657         u32 intr_status, intr_enable;
1658
1659         spin_lock(&mdp->lock);
1660
1661         /* Get interrupt status */
1662         intr_status = sh_eth_read(ndev, EESR);
1663         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1664          * enabled since it's the one that  comes thru regardless of the mask,
1665          * and we need to fully handle it in sh_eth_error() in order to quench
1666          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1667          */
1668         intr_enable = sh_eth_read(ndev, EESIPR);
1669         intr_status &= intr_enable | DMAC_M_ECI;
1670         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1671                 ret = IRQ_HANDLED;
1672         else
1673                 goto out;
1674
1675         if (!likely(mdp->irq_enabled)) {
1676                 sh_eth_write(ndev, 0, EESIPR);
1677                 goto out;
1678         }
1679
1680         if (intr_status & EESR_RX_CHECK) {
1681                 if (napi_schedule_prep(&mdp->napi)) {
1682                         /* Mask Rx interrupts */
1683                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1684                                      EESIPR);
1685                         __napi_schedule(&mdp->napi);
1686                 } else {
1687                         netdev_warn(ndev,
1688                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1689                                     intr_status, intr_enable);
1690                 }
1691         }
1692
1693         /* Tx Check */
1694         if (intr_status & cd->tx_check) {
1695                 /* Clear Tx interrupts */
1696                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1697
1698                 sh_eth_txfree(ndev);
1699                 netif_wake_queue(ndev);
1700         }
1701
1702         if (intr_status & cd->eesr_err_check) {
1703                 /* Clear error interrupts */
1704                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1705
1706                 sh_eth_error(ndev, intr_status);
1707         }
1708
1709 out:
1710         spin_unlock(&mdp->lock);
1711
1712         return ret;
1713 }
1714
1715 static int sh_eth_poll(struct napi_struct *napi, int budget)
1716 {
1717         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1718                                                   napi);
1719         struct net_device *ndev = napi->dev;
1720         int quota = budget;
1721         u32 intr_status;
1722
1723         for (;;) {
1724                 intr_status = sh_eth_read(ndev, EESR);
1725                 if (!(intr_status & EESR_RX_CHECK))
1726                         break;
1727                 /* Clear Rx interrupts */
1728                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1729
1730                 if (sh_eth_rx(ndev, intr_status, &quota))
1731                         goto out;
1732         }
1733
1734         napi_complete(napi);
1735
1736         /* Reenable Rx interrupts */
1737         if (mdp->irq_enabled)
1738                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1739 out:
1740         return budget - quota;
1741 }
1742
1743 /* PHY state control function */
1744 static void sh_eth_adjust_link(struct net_device *ndev)
1745 {
1746         struct sh_eth_private *mdp = netdev_priv(ndev);
1747         struct phy_device *phydev = mdp->phydev;
1748         int new_state = 0;
1749
1750         if (phydev->link) {
1751                 if (phydev->duplex != mdp->duplex) {
1752                         new_state = 1;
1753                         mdp->duplex = phydev->duplex;
1754                         if (mdp->cd->set_duplex)
1755                                 mdp->cd->set_duplex(ndev);
1756                 }
1757
1758                 if (phydev->speed != mdp->speed) {
1759                         new_state = 1;
1760                         mdp->speed = phydev->speed;
1761                         if (mdp->cd->set_rate)
1762                                 mdp->cd->set_rate(ndev);
1763                 }
1764                 if (!mdp->link) {
1765                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1766                         new_state = 1;
1767                         mdp->link = phydev->link;
1768                         if (mdp->cd->no_psr || mdp->no_ether_link)
1769                                 sh_eth_rcv_snd_enable(ndev);
1770                 }
1771         } else if (mdp->link) {
1772                 new_state = 1;
1773                 mdp->link = 0;
1774                 mdp->speed = 0;
1775                 mdp->duplex = -1;
1776                 if (mdp->cd->no_psr || mdp->no_ether_link)
1777                         sh_eth_rcv_snd_disable(ndev);
1778         }
1779
1780         if (new_state && netif_msg_link(mdp))
1781                 phy_print_status(phydev);
1782 }
1783
1784 /* PHY init function */
1785 static int sh_eth_phy_init(struct net_device *ndev)
1786 {
1787         struct device_node *np = ndev->dev.parent->of_node;
1788         struct sh_eth_private *mdp = netdev_priv(ndev);
1789         struct phy_device *phydev = NULL;
1790
1791         mdp->link = 0;
1792         mdp->speed = 0;
1793         mdp->duplex = -1;
1794
1795         /* Try connect to PHY */
1796         if (np) {
1797                 struct device_node *pn;
1798
1799                 pn = of_parse_phandle(np, "phy-handle", 0);
1800                 phydev = of_phy_connect(ndev, pn,
1801                                         sh_eth_adjust_link, 0,
1802                                         mdp->phy_interface);
1803
1804                 if (!phydev)
1805                         phydev = ERR_PTR(-ENOENT);
1806         } else {
1807                 char phy_id[MII_BUS_ID_SIZE + 3];
1808
1809                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1810                          mdp->mii_bus->id, mdp->phy_id);
1811
1812                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1813                                      mdp->phy_interface);
1814         }
1815
1816         if (IS_ERR(phydev)) {
1817                 netdev_err(ndev, "failed to connect PHY\n");
1818                 return PTR_ERR(phydev);
1819         }
1820
1821         phy_attached_info(phydev);
1822
1823         mdp->phydev = phydev;
1824
1825         return 0;
1826 }
1827
1828 /* PHY control start function */
1829 static int sh_eth_phy_start(struct net_device *ndev)
1830 {
1831         struct sh_eth_private *mdp = netdev_priv(ndev);
1832         int ret;
1833
1834         ret = sh_eth_phy_init(ndev);
1835         if (ret)
1836                 return ret;
1837
1838         phy_start(mdp->phydev);
1839
1840         return 0;
1841 }
1842
1843 static int sh_eth_get_settings(struct net_device *ndev,
1844                                struct ethtool_cmd *ecmd)
1845 {
1846         struct sh_eth_private *mdp = netdev_priv(ndev);
1847         unsigned long flags;
1848         int ret;
1849
1850         if (!mdp->phydev)
1851                 return -ENODEV;
1852
1853         spin_lock_irqsave(&mdp->lock, flags);
1854         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1855         spin_unlock_irqrestore(&mdp->lock, flags);
1856
1857         return ret;
1858 }
1859
1860 static int sh_eth_set_settings(struct net_device *ndev,
1861                                struct ethtool_cmd *ecmd)
1862 {
1863         struct sh_eth_private *mdp = netdev_priv(ndev);
1864         unsigned long flags;
1865         int ret;
1866
1867         if (!mdp->phydev)
1868                 return -ENODEV;
1869
1870         spin_lock_irqsave(&mdp->lock, flags);
1871
1872         /* disable tx and rx */
1873         sh_eth_rcv_snd_disable(ndev);
1874
1875         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1876         if (ret)
1877                 goto error_exit;
1878
1879         if (ecmd->duplex == DUPLEX_FULL)
1880                 mdp->duplex = 1;
1881         else
1882                 mdp->duplex = 0;
1883
1884         if (mdp->cd->set_duplex)
1885                 mdp->cd->set_duplex(ndev);
1886
1887 error_exit:
1888         mdelay(1);
1889
1890         /* enable tx and rx */
1891         sh_eth_rcv_snd_enable(ndev);
1892
1893         spin_unlock_irqrestore(&mdp->lock, flags);
1894
1895         return ret;
1896 }
1897
1898 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1899  * version must be bumped as well.  Just adding registers up to that
1900  * limit is fine, as long as the existing register indices don't
1901  * change.
1902  */
1903 #define SH_ETH_REG_DUMP_VERSION         1
1904 #define SH_ETH_REG_DUMP_MAX_REGS        256
1905
1906 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1907 {
1908         struct sh_eth_private *mdp = netdev_priv(ndev);
1909         struct sh_eth_cpu_data *cd = mdp->cd;
1910         u32 *valid_map;
1911         size_t len;
1912
1913         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1914
1915         /* Dump starts with a bitmap that tells ethtool which
1916          * registers are defined for this chip.
1917          */
1918         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1919         if (buf) {
1920                 valid_map = buf;
1921                 buf += len;
1922         } else {
1923                 valid_map = NULL;
1924         }
1925
1926         /* Add a register to the dump, if it has a defined offset.
1927          * This automatically skips most undefined registers, but for
1928          * some it is also necessary to check a capability flag in
1929          * struct sh_eth_cpu_data.
1930          */
1931 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1932 #define add_reg_from(reg, read_expr) do {                               \
1933                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1934                         if (buf) {                                      \
1935                                 mark_reg_valid(reg);                    \
1936                                 *buf++ = read_expr;                     \
1937                         }                                               \
1938                         ++len;                                          \
1939                 }                                                       \
1940         } while (0)
1941 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1942 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1943
1944         add_reg(EDSR);
1945         add_reg(EDMR);
1946         add_reg(EDTRR);
1947         add_reg(EDRRR);
1948         add_reg(EESR);
1949         add_reg(EESIPR);
1950         add_reg(TDLAR);
1951         add_reg(TDFAR);
1952         add_reg(TDFXR);
1953         add_reg(TDFFR);
1954         add_reg(RDLAR);
1955         add_reg(RDFAR);
1956         add_reg(RDFXR);
1957         add_reg(RDFFR);
1958         add_reg(TRSCER);
1959         add_reg(RMFCR);
1960         add_reg(TFTR);
1961         add_reg(FDR);
1962         add_reg(RMCR);
1963         add_reg(TFUCR);
1964         add_reg(RFOCR);
1965         if (cd->rmiimode)
1966                 add_reg(RMIIMODE);
1967         add_reg(FCFTR);
1968         if (cd->rpadir)
1969                 add_reg(RPADIR);
1970         if (!cd->no_trimd)
1971                 add_reg(TRIMD);
1972         add_reg(ECMR);
1973         add_reg(ECSR);
1974         add_reg(ECSIPR);
1975         add_reg(PIR);
1976         if (!cd->no_psr)
1977                 add_reg(PSR);
1978         add_reg(RDMLR);
1979         add_reg(RFLR);
1980         add_reg(IPGR);
1981         if (cd->apr)
1982                 add_reg(APR);
1983         if (cd->mpr)
1984                 add_reg(MPR);
1985         add_reg(RFCR);
1986         add_reg(RFCF);
1987         if (cd->tpauser)
1988                 add_reg(TPAUSER);
1989         add_reg(TPAUSECR);
1990         add_reg(GECMR);
1991         if (cd->bculr)
1992                 add_reg(BCULR);
1993         add_reg(MAHR);
1994         add_reg(MALR);
1995         add_reg(TROCR);
1996         add_reg(CDCR);
1997         add_reg(LCCR);
1998         add_reg(CNDCR);
1999         add_reg(CEFCR);
2000         add_reg(FRECR);
2001         add_reg(TSFRCR);
2002         add_reg(TLFRCR);
2003         add_reg(CERCR);
2004         add_reg(CEECR);
2005         add_reg(MAFCR);
2006         if (cd->rtrate)
2007                 add_reg(RTRATE);
2008         if (cd->hw_crc)
2009                 add_reg(CSMR);
2010         if (cd->select_mii)
2011                 add_reg(RMII_MII);
2012         add_reg(ARSTR);
2013         if (cd->tsu) {
2014                 add_tsu_reg(TSU_CTRST);
2015                 add_tsu_reg(TSU_FWEN0);
2016                 add_tsu_reg(TSU_FWEN1);
2017                 add_tsu_reg(TSU_FCM);
2018                 add_tsu_reg(TSU_BSYSL0);
2019                 add_tsu_reg(TSU_BSYSL1);
2020                 add_tsu_reg(TSU_PRISL0);
2021                 add_tsu_reg(TSU_PRISL1);
2022                 add_tsu_reg(TSU_FWSL0);
2023                 add_tsu_reg(TSU_FWSL1);
2024                 add_tsu_reg(TSU_FWSLC);
2025                 add_tsu_reg(TSU_QTAG0);
2026                 add_tsu_reg(TSU_QTAG1);
2027                 add_tsu_reg(TSU_QTAGM0);
2028                 add_tsu_reg(TSU_QTAGM1);
2029                 add_tsu_reg(TSU_FWSR);
2030                 add_tsu_reg(TSU_FWINMK);
2031                 add_tsu_reg(TSU_ADQT0);
2032                 add_tsu_reg(TSU_ADQT1);
2033                 add_tsu_reg(TSU_VTAG0);
2034                 add_tsu_reg(TSU_VTAG1);
2035                 add_tsu_reg(TSU_ADSBSY);
2036                 add_tsu_reg(TSU_TEN);
2037                 add_tsu_reg(TSU_POST1);
2038                 add_tsu_reg(TSU_POST2);
2039                 add_tsu_reg(TSU_POST3);
2040                 add_tsu_reg(TSU_POST4);
2041                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2042                         /* This is the start of a table, not just a single
2043                          * register.
2044                          */
2045                         if (buf) {
2046                                 unsigned int i;
2047
2048                                 mark_reg_valid(TSU_ADRH0);
2049                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2050                                         *buf++ = ioread32(
2051                                                 mdp->tsu_addr +
2052                                                 mdp->reg_offset[TSU_ADRH0] +
2053                                                 i * 4);
2054                         }
2055                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2056                 }
2057         }
2058
2059 #undef mark_reg_valid
2060 #undef add_reg_from
2061 #undef add_reg
2062 #undef add_tsu_reg
2063
2064         return len * 4;
2065 }
2066
2067 static int sh_eth_get_regs_len(struct net_device *ndev)
2068 {
2069         return __sh_eth_get_regs(ndev, NULL);
2070 }
2071
2072 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2073                             void *buf)
2074 {
2075         struct sh_eth_private *mdp = netdev_priv(ndev);
2076
2077         regs->version = SH_ETH_REG_DUMP_VERSION;
2078
2079         pm_runtime_get_sync(&mdp->pdev->dev);
2080         __sh_eth_get_regs(ndev, buf);
2081         pm_runtime_put_sync(&mdp->pdev->dev);
2082 }
2083
2084 static int sh_eth_nway_reset(struct net_device *ndev)
2085 {
2086         struct sh_eth_private *mdp = netdev_priv(ndev);
2087         unsigned long flags;
2088         int ret;
2089
2090         if (!mdp->phydev)
2091                 return -ENODEV;
2092
2093         spin_lock_irqsave(&mdp->lock, flags);
2094         ret = phy_start_aneg(mdp->phydev);
2095         spin_unlock_irqrestore(&mdp->lock, flags);
2096
2097         return ret;
2098 }
2099
2100 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2101 {
2102         struct sh_eth_private *mdp = netdev_priv(ndev);
2103         return mdp->msg_enable;
2104 }
2105
2106 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2107 {
2108         struct sh_eth_private *mdp = netdev_priv(ndev);
2109         mdp->msg_enable = value;
2110 }
2111
2112 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2113         "rx_current", "tx_current",
2114         "rx_dirty", "tx_dirty",
2115 };
2116 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2117
2118 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2119 {
2120         switch (sset) {
2121         case ETH_SS_STATS:
2122                 return SH_ETH_STATS_LEN;
2123         default:
2124                 return -EOPNOTSUPP;
2125         }
2126 }
2127
2128 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2129                                      struct ethtool_stats *stats, u64 *data)
2130 {
2131         struct sh_eth_private *mdp = netdev_priv(ndev);
2132         int i = 0;
2133
2134         /* device-specific stats */
2135         data[i++] = mdp->cur_rx;
2136         data[i++] = mdp->cur_tx;
2137         data[i++] = mdp->dirty_rx;
2138         data[i++] = mdp->dirty_tx;
2139 }
2140
2141 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2142 {
2143         switch (stringset) {
2144         case ETH_SS_STATS:
2145                 memcpy(data, *sh_eth_gstrings_stats,
2146                        sizeof(sh_eth_gstrings_stats));
2147                 break;
2148         }
2149 }
2150
2151 static void sh_eth_get_ringparam(struct net_device *ndev,
2152                                  struct ethtool_ringparam *ring)
2153 {
2154         struct sh_eth_private *mdp = netdev_priv(ndev);
2155
2156         ring->rx_max_pending = RX_RING_MAX;
2157         ring->tx_max_pending = TX_RING_MAX;
2158         ring->rx_pending = mdp->num_rx_ring;
2159         ring->tx_pending = mdp->num_tx_ring;
2160 }
2161
2162 static int sh_eth_set_ringparam(struct net_device *ndev,
2163                                 struct ethtool_ringparam *ring)
2164 {
2165         struct sh_eth_private *mdp = netdev_priv(ndev);
2166         int ret;
2167
2168         if (ring->tx_pending > TX_RING_MAX ||
2169             ring->rx_pending > RX_RING_MAX ||
2170             ring->tx_pending < TX_RING_MIN ||
2171             ring->rx_pending < RX_RING_MIN)
2172                 return -EINVAL;
2173         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2174                 return -EINVAL;
2175
2176         if (netif_running(ndev)) {
2177                 netif_device_detach(ndev);
2178                 netif_tx_disable(ndev);
2179
2180                 /* Serialise with the interrupt handler and NAPI, then
2181                  * disable interrupts.  We have to clear the
2182                  * irq_enabled flag first to ensure that interrupts
2183                  * won't be re-enabled.
2184                  */
2185                 mdp->irq_enabled = false;
2186                 synchronize_irq(ndev->irq);
2187                 napi_synchronize(&mdp->napi);
2188                 sh_eth_write(ndev, 0x0000, EESIPR);
2189
2190                 sh_eth_dev_exit(ndev);
2191
2192                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2193                 sh_eth_ring_free(ndev);
2194         }
2195
2196         /* Set new parameters */
2197         mdp->num_rx_ring = ring->rx_pending;
2198         mdp->num_tx_ring = ring->tx_pending;
2199
2200         if (netif_running(ndev)) {
2201                 ret = sh_eth_ring_init(ndev);
2202                 if (ret < 0) {
2203                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2204                                    __func__);
2205                         return ret;
2206                 }
2207                 ret = sh_eth_dev_init(ndev, false);
2208                 if (ret < 0) {
2209                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2210                                    __func__);
2211                         return ret;
2212                 }
2213
2214                 mdp->irq_enabled = true;
2215                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2216                 /* Setting the Rx mode will start the Rx process. */
2217                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2218                 netif_device_attach(ndev);
2219         }
2220
2221         return 0;
2222 }
2223
2224 static const struct ethtool_ops sh_eth_ethtool_ops = {
2225         .get_settings   = sh_eth_get_settings,
2226         .set_settings   = sh_eth_set_settings,
2227         .get_regs_len   = sh_eth_get_regs_len,
2228         .get_regs       = sh_eth_get_regs,
2229         .nway_reset     = sh_eth_nway_reset,
2230         .get_msglevel   = sh_eth_get_msglevel,
2231         .set_msglevel   = sh_eth_set_msglevel,
2232         .get_link       = ethtool_op_get_link,
2233         .get_strings    = sh_eth_get_strings,
2234         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2235         .get_sset_count     = sh_eth_get_sset_count,
2236         .get_ringparam  = sh_eth_get_ringparam,
2237         .set_ringparam  = sh_eth_set_ringparam,
2238 };
2239
2240 /* network device open function */
2241 static int sh_eth_open(struct net_device *ndev)
2242 {
2243         int ret = 0;
2244         struct sh_eth_private *mdp = netdev_priv(ndev);
2245
2246         pm_runtime_get_sync(&mdp->pdev->dev);
2247
2248         napi_enable(&mdp->napi);
2249
2250         ret = request_irq(ndev->irq, sh_eth_interrupt,
2251                           mdp->cd->irq_flags, ndev->name, ndev);
2252         if (ret) {
2253                 netdev_err(ndev, "Can not assign IRQ number\n");
2254                 goto out_napi_off;
2255         }
2256
2257         /* Descriptor set */
2258         ret = sh_eth_ring_init(ndev);
2259         if (ret)
2260                 goto out_free_irq;
2261
2262         /* device init */
2263         ret = sh_eth_dev_init(ndev, true);
2264         if (ret)
2265                 goto out_free_irq;
2266
2267         /* PHY control start*/
2268         ret = sh_eth_phy_start(ndev);
2269         if (ret)
2270                 goto out_free_irq;
2271
2272         mdp->is_opened = 1;
2273
2274         return ret;
2275
2276 out_free_irq:
2277         free_irq(ndev->irq, ndev);
2278 out_napi_off:
2279         napi_disable(&mdp->napi);
2280         pm_runtime_put_sync(&mdp->pdev->dev);
2281         return ret;
2282 }
2283
2284 /* Timeout function */
2285 static void sh_eth_tx_timeout(struct net_device *ndev)
2286 {
2287         struct sh_eth_private *mdp = netdev_priv(ndev);
2288         struct sh_eth_rxdesc *rxdesc;
2289         int i;
2290
2291         netif_stop_queue(ndev);
2292
2293         netif_err(mdp, timer, ndev,
2294                   "transmit timed out, status %8.8x, resetting...\n",
2295                   sh_eth_read(ndev, EESR));
2296
2297         /* tx_errors count up */
2298         ndev->stats.tx_errors++;
2299
2300         /* Free all the skbuffs in the Rx queue. */
2301         for (i = 0; i < mdp->num_rx_ring; i++) {
2302                 rxdesc = &mdp->rx_ring[i];
2303                 rxdesc->status = cpu_to_le32(0);
2304                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2305                 dev_kfree_skb(mdp->rx_skbuff[i]);
2306                 mdp->rx_skbuff[i] = NULL;
2307         }
2308         for (i = 0; i < mdp->num_tx_ring; i++) {
2309                 dev_kfree_skb(mdp->tx_skbuff[i]);
2310                 mdp->tx_skbuff[i] = NULL;
2311         }
2312
2313         /* device init */
2314         sh_eth_dev_init(ndev, true);
2315 }
2316
2317 /* Packet transmit function */
2318 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2319 {
2320         struct sh_eth_private *mdp = netdev_priv(ndev);
2321         struct sh_eth_txdesc *txdesc;
2322         dma_addr_t dma_addr;
2323         u32 entry;
2324         unsigned long flags;
2325
2326         spin_lock_irqsave(&mdp->lock, flags);
2327         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2328                 if (!sh_eth_txfree(ndev)) {
2329                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2330                         netif_stop_queue(ndev);
2331                         spin_unlock_irqrestore(&mdp->lock, flags);
2332                         return NETDEV_TX_BUSY;
2333                 }
2334         }
2335         spin_unlock_irqrestore(&mdp->lock, flags);
2336
2337         if (skb_put_padto(skb, ETH_ZLEN))
2338                 return NETDEV_TX_OK;
2339
2340         entry = mdp->cur_tx % mdp->num_tx_ring;
2341         mdp->tx_skbuff[entry] = skb;
2342         txdesc = &mdp->tx_ring[entry];
2343         /* soft swap. */
2344         if (!mdp->cd->hw_swap)
2345                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2346         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2347                                   DMA_TO_DEVICE);
2348         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2349                 kfree_skb(skb);
2350                 return NETDEV_TX_OK;
2351         }
2352         txdesc->addr = cpu_to_le32(dma_addr);
2353         txdesc->len  = cpu_to_le32(skb->len << 16);
2354
2355         dma_wmb(); /* TACT bit must be set after all the above writes */
2356         if (entry >= mdp->num_tx_ring - 1)
2357                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2358         else
2359                 txdesc->status |= cpu_to_le32(TD_TACT);
2360
2361         mdp->cur_tx++;
2362
2363         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2364                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2365
2366         return NETDEV_TX_OK;
2367 }
2368
2369 /* The statistics registers have write-clear behaviour, which means we
2370  * will lose any increment between the read and write.  We mitigate
2371  * this by only clearing when we read a non-zero value, so we will
2372  * never falsely report a total of zero.
2373  */
2374 static void
2375 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2376 {
2377         u32 delta = sh_eth_read(ndev, reg);
2378
2379         if (delta) {
2380                 *stat += delta;
2381                 sh_eth_write(ndev, 0, reg);
2382         }
2383 }
2384
2385 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2386 {
2387         struct sh_eth_private *mdp = netdev_priv(ndev);
2388
2389         if (sh_eth_is_rz_fast_ether(mdp))
2390                 return &ndev->stats;
2391
2392         if (!mdp->is_opened)
2393                 return &ndev->stats;
2394
2395         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2396         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2397         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2398
2399         if (sh_eth_is_gether(mdp)) {
2400                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2401                                    CERCR);
2402                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2403                                    CEECR);
2404         } else {
2405                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2406                                    CNDCR);
2407         }
2408
2409         return &ndev->stats;
2410 }
2411
2412 /* device close function */
2413 static int sh_eth_close(struct net_device *ndev)
2414 {
2415         struct sh_eth_private *mdp = netdev_priv(ndev);
2416
2417         netif_stop_queue(ndev);
2418
2419         /* Serialise with the interrupt handler and NAPI, then disable
2420          * interrupts.  We have to clear the irq_enabled flag first to
2421          * ensure that interrupts won't be re-enabled.
2422          */
2423         mdp->irq_enabled = false;
2424         synchronize_irq(ndev->irq);
2425         napi_disable(&mdp->napi);
2426         sh_eth_write(ndev, 0x0000, EESIPR);
2427
2428         sh_eth_dev_exit(ndev);
2429
2430         /* PHY Disconnect */
2431         if (mdp->phydev) {
2432                 phy_stop(mdp->phydev);
2433                 phy_disconnect(mdp->phydev);
2434                 mdp->phydev = NULL;
2435         }
2436
2437         free_irq(ndev->irq, ndev);
2438
2439         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2440         sh_eth_ring_free(ndev);
2441
2442         pm_runtime_put_sync(&mdp->pdev->dev);
2443
2444         mdp->is_opened = 0;
2445
2446         return 0;
2447 }
2448
2449 /* ioctl to device function */
2450 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2451 {
2452         struct sh_eth_private *mdp = netdev_priv(ndev);
2453         struct phy_device *phydev = mdp->phydev;
2454
2455         if (!netif_running(ndev))
2456                 return -EINVAL;
2457
2458         if (!phydev)
2459                 return -ENODEV;
2460
2461         return phy_mii_ioctl(phydev, rq, cmd);
2462 }
2463
2464 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2465 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2466                                             int entry)
2467 {
2468         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2469 }
2470
2471 static u32 sh_eth_tsu_get_post_mask(int entry)
2472 {
2473         return 0x0f << (28 - ((entry % 8) * 4));
2474 }
2475
2476 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2477 {
2478         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2479 }
2480
2481 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2482                                              int entry)
2483 {
2484         struct sh_eth_private *mdp = netdev_priv(ndev);
2485         u32 tmp;
2486         void *reg_offset;
2487
2488         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2489         tmp = ioread32(reg_offset);
2490         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2491 }
2492
2493 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2494                                               int entry)
2495 {
2496         struct sh_eth_private *mdp = netdev_priv(ndev);
2497         u32 post_mask, ref_mask, tmp;
2498         void *reg_offset;
2499
2500         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2501         post_mask = sh_eth_tsu_get_post_mask(entry);
2502         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2503
2504         tmp = ioread32(reg_offset);
2505         iowrite32(tmp & ~post_mask, reg_offset);
2506
2507         /* If other port enables, the function returns "true" */
2508         return tmp & ref_mask;
2509 }
2510
2511 static int sh_eth_tsu_busy(struct net_device *ndev)
2512 {
2513         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2514         struct sh_eth_private *mdp = netdev_priv(ndev);
2515
2516         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2517                 udelay(10);
2518                 timeout--;
2519                 if (timeout <= 0) {
2520                         netdev_err(ndev, "%s: timeout\n", __func__);
2521                         return -ETIMEDOUT;
2522                 }
2523         }
2524
2525         return 0;
2526 }
2527
2528 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2529                                   const u8 *addr)
2530 {
2531         u32 val;
2532
2533         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2534         iowrite32(val, reg);
2535         if (sh_eth_tsu_busy(ndev) < 0)
2536                 return -EBUSY;
2537
2538         val = addr[4] << 8 | addr[5];
2539         iowrite32(val, reg + 4);
2540         if (sh_eth_tsu_busy(ndev) < 0)
2541                 return -EBUSY;
2542
2543         return 0;
2544 }
2545
2546 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2547 {
2548         u32 val;
2549
2550         val = ioread32(reg);
2551         addr[0] = (val >> 24) & 0xff;
2552         addr[1] = (val >> 16) & 0xff;
2553         addr[2] = (val >> 8) & 0xff;
2554         addr[3] = val & 0xff;
2555         val = ioread32(reg + 4);
2556         addr[4] = (val >> 8) & 0xff;
2557         addr[5] = val & 0xff;
2558 }
2559
2560
2561 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2562 {
2563         struct sh_eth_private *mdp = netdev_priv(ndev);
2564         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2565         int i;
2566         u8 c_addr[ETH_ALEN];
2567
2568         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2569                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2570                 if (ether_addr_equal(addr, c_addr))
2571                         return i;
2572         }
2573
2574         return -ENOENT;
2575 }
2576
2577 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2578 {
2579         u8 blank[ETH_ALEN];
2580         int entry;
2581
2582         memset(blank, 0, sizeof(blank));
2583         entry = sh_eth_tsu_find_entry(ndev, blank);
2584         return (entry < 0) ? -ENOMEM : entry;
2585 }
2586
2587 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2588                                               int entry)
2589 {
2590         struct sh_eth_private *mdp = netdev_priv(ndev);
2591         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2592         int ret;
2593         u8 blank[ETH_ALEN];
2594
2595         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2596                          ~(1 << (31 - entry)), TSU_TEN);
2597
2598         memset(blank, 0, sizeof(blank));
2599         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2600         if (ret < 0)
2601                 return ret;
2602         return 0;
2603 }
2604
2605 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2606 {
2607         struct sh_eth_private *mdp = netdev_priv(ndev);
2608         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2609         int i, ret;
2610
2611         if (!mdp->cd->tsu)
2612                 return 0;
2613
2614         i = sh_eth_tsu_find_entry(ndev, addr);
2615         if (i < 0) {
2616                 /* No entry found, create one */
2617                 i = sh_eth_tsu_find_empty(ndev);
2618                 if (i < 0)
2619                         return -ENOMEM;
2620                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2621                 if (ret < 0)
2622                         return ret;
2623
2624                 /* Enable the entry */
2625                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2626                                  (1 << (31 - i)), TSU_TEN);
2627         }
2628
2629         /* Entry found or created, enable POST */
2630         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2631
2632         return 0;
2633 }
2634
2635 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2636 {
2637         struct sh_eth_private *mdp = netdev_priv(ndev);
2638         int i, ret;
2639
2640         if (!mdp->cd->tsu)
2641                 return 0;
2642
2643         i = sh_eth_tsu_find_entry(ndev, addr);
2644         if (i) {
2645                 /* Entry found */
2646                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2647                         goto done;
2648
2649                 /* Disable the entry if both ports was disabled */
2650                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2651                 if (ret < 0)
2652                         return ret;
2653         }
2654 done:
2655         return 0;
2656 }
2657
2658 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2659 {
2660         struct sh_eth_private *mdp = netdev_priv(ndev);
2661         int i, ret;
2662
2663         if (!mdp->cd->tsu)
2664                 return 0;
2665
2666         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2667                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2668                         continue;
2669
2670                 /* Disable the entry if both ports was disabled */
2671                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2672                 if (ret < 0)
2673                         return ret;
2674         }
2675
2676         return 0;
2677 }
2678
2679 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2680 {
2681         struct sh_eth_private *mdp = netdev_priv(ndev);
2682         u8 addr[ETH_ALEN];
2683         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2684         int i;
2685
2686         if (!mdp->cd->tsu)
2687                 return;
2688
2689         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2690                 sh_eth_tsu_read_entry(reg_offset, addr);
2691                 if (is_multicast_ether_addr(addr))
2692                         sh_eth_tsu_del_entry(ndev, addr);
2693         }
2694 }
2695
2696 /* Update promiscuous flag and multicast filter */
2697 static void sh_eth_set_rx_mode(struct net_device *ndev)
2698 {
2699         struct sh_eth_private *mdp = netdev_priv(ndev);
2700         u32 ecmr_bits;
2701         int mcast_all = 0;
2702         unsigned long flags;
2703
2704         spin_lock_irqsave(&mdp->lock, flags);
2705         /* Initial condition is MCT = 1, PRM = 0.
2706          * Depending on ndev->flags, set PRM or clear MCT
2707          */
2708         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2709         if (mdp->cd->tsu)
2710                 ecmr_bits |= ECMR_MCT;
2711
2712         if (!(ndev->flags & IFF_MULTICAST)) {
2713                 sh_eth_tsu_purge_mcast(ndev);
2714                 mcast_all = 1;
2715         }
2716         if (ndev->flags & IFF_ALLMULTI) {
2717                 sh_eth_tsu_purge_mcast(ndev);
2718                 ecmr_bits &= ~ECMR_MCT;
2719                 mcast_all = 1;
2720         }
2721
2722         if (ndev->flags & IFF_PROMISC) {
2723                 sh_eth_tsu_purge_all(ndev);
2724                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2725         } else if (mdp->cd->tsu) {
2726                 struct netdev_hw_addr *ha;
2727                 netdev_for_each_mc_addr(ha, ndev) {
2728                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2729                                 continue;
2730
2731                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2732                                 if (!mcast_all) {
2733                                         sh_eth_tsu_purge_mcast(ndev);
2734                                         ecmr_bits &= ~ECMR_MCT;
2735                                         mcast_all = 1;
2736                                 }
2737                         }
2738                 }
2739         }
2740
2741         /* update the ethernet mode */
2742         sh_eth_write(ndev, ecmr_bits, ECMR);
2743
2744         spin_unlock_irqrestore(&mdp->lock, flags);
2745 }
2746
2747 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2748 {
2749         if (!mdp->port)
2750                 return TSU_VTAG0;
2751         else
2752                 return TSU_VTAG1;
2753 }
2754
2755 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2756                                   __be16 proto, u16 vid)
2757 {
2758         struct sh_eth_private *mdp = netdev_priv(ndev);
2759         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2760
2761         if (unlikely(!mdp->cd->tsu))
2762                 return -EPERM;
2763
2764         /* No filtering if vid = 0 */
2765         if (!vid)
2766                 return 0;
2767
2768         mdp->vlan_num_ids++;
2769
2770         /* The controller has one VLAN tag HW filter. So, if the filter is
2771          * already enabled, the driver disables it and the filte
2772          */
2773         if (mdp->vlan_num_ids > 1) {
2774                 /* disable VLAN filter */
2775                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2776                 return 0;
2777         }
2778
2779         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2780                          vtag_reg_index);
2781
2782         return 0;
2783 }
2784
2785 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2786                                    __be16 proto, u16 vid)
2787 {
2788         struct sh_eth_private *mdp = netdev_priv(ndev);
2789         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2790
2791         if (unlikely(!mdp->cd->tsu))
2792                 return -EPERM;
2793
2794         /* No filtering if vid = 0 */
2795         if (!vid)
2796                 return 0;
2797
2798         mdp->vlan_num_ids--;
2799         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2800
2801         return 0;
2802 }
2803
2804 /* SuperH's TSU register init function */
2805 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2806 {
2807         if (sh_eth_is_rz_fast_ether(mdp)) {
2808                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2809                 return;
2810         }
2811
2812         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2813         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2814         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2815         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2816         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2817         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2818         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2819         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2820         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2821         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2822         if (sh_eth_is_gether(mdp)) {
2823                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2824                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2825         } else {
2826                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2827                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2828         }
2829         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2830         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2831         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2832         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2833         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2834         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2835         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2836 }
2837
2838 /* MDIO bus release function */
2839 static int sh_mdio_release(struct sh_eth_private *mdp)
2840 {
2841         /* unregister mdio bus */
2842         mdiobus_unregister(mdp->mii_bus);
2843
2844         /* free bitbang info */
2845         free_mdio_bitbang(mdp->mii_bus);
2846
2847         return 0;
2848 }
2849
2850 /* MDIO bus init function */
2851 static int sh_mdio_init(struct sh_eth_private *mdp,
2852                         struct sh_eth_plat_data *pd)
2853 {
2854         int ret;
2855         struct bb_info *bitbang;
2856         struct platform_device *pdev = mdp->pdev;
2857         struct device *dev = &mdp->pdev->dev;
2858
2859         /* create bit control struct for PHY */
2860         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2861         if (!bitbang)
2862                 return -ENOMEM;
2863
2864         /* bitbang init */
2865         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2866         bitbang->set_gate = pd->set_mdio_gate;
2867         bitbang->ctrl.ops = &bb_ops;
2868
2869         /* MII controller setting */
2870         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2871         if (!mdp->mii_bus)
2872                 return -ENOMEM;
2873
2874         /* Hook up MII support for ethtool */
2875         mdp->mii_bus->name = "sh_mii";
2876         mdp->mii_bus->parent = dev;
2877         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2878                  pdev->name, pdev->id);
2879
2880         /* register MDIO bus */
2881         if (dev->of_node) {
2882                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2883         } else {
2884                 if (pd->phy_irq > 0)
2885                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2886
2887                 ret = mdiobus_register(mdp->mii_bus);
2888         }
2889
2890         if (ret)
2891                 goto out_free_bus;
2892
2893         return 0;
2894
2895 out_free_bus:
2896         free_mdio_bitbang(mdp->mii_bus);
2897         return ret;
2898 }
2899
2900 static const u16 *sh_eth_get_register_offset(int register_type)
2901 {
2902         const u16 *reg_offset = NULL;
2903
2904         switch (register_type) {
2905         case SH_ETH_REG_GIGABIT:
2906                 reg_offset = sh_eth_offset_gigabit;
2907                 break;
2908         case SH_ETH_REG_FAST_RZ:
2909                 reg_offset = sh_eth_offset_fast_rz;
2910                 break;
2911         case SH_ETH_REG_FAST_RCAR:
2912                 reg_offset = sh_eth_offset_fast_rcar;
2913                 break;
2914         case SH_ETH_REG_FAST_SH4:
2915                 reg_offset = sh_eth_offset_fast_sh4;
2916                 break;
2917         case SH_ETH_REG_FAST_SH3_SH2:
2918                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2919                 break;
2920         default:
2921                 break;
2922         }
2923
2924         return reg_offset;
2925 }
2926
2927 static const struct net_device_ops sh_eth_netdev_ops = {
2928         .ndo_open               = sh_eth_open,
2929         .ndo_stop               = sh_eth_close,
2930         .ndo_start_xmit         = sh_eth_start_xmit,
2931         .ndo_get_stats          = sh_eth_get_stats,
2932         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2933         .ndo_tx_timeout         = sh_eth_tx_timeout,
2934         .ndo_do_ioctl           = sh_eth_do_ioctl,
2935         .ndo_validate_addr      = eth_validate_addr,
2936         .ndo_set_mac_address    = eth_mac_addr,
2937         .ndo_change_mtu         = eth_change_mtu,
2938 };
2939
2940 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2941         .ndo_open               = sh_eth_open,
2942         .ndo_stop               = sh_eth_close,
2943         .ndo_start_xmit         = sh_eth_start_xmit,
2944         .ndo_get_stats          = sh_eth_get_stats,
2945         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2946         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2947         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2948         .ndo_tx_timeout         = sh_eth_tx_timeout,
2949         .ndo_do_ioctl           = sh_eth_do_ioctl,
2950         .ndo_validate_addr      = eth_validate_addr,
2951         .ndo_set_mac_address    = eth_mac_addr,
2952         .ndo_change_mtu         = eth_change_mtu,
2953 };
2954
2955 #ifdef CONFIG_OF
2956 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2957 {
2958         struct device_node *np = dev->of_node;
2959         struct sh_eth_plat_data *pdata;
2960         const char *mac_addr;
2961
2962         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2963         if (!pdata)
2964                 return NULL;
2965
2966         pdata->phy_interface = of_get_phy_mode(np);
2967
2968         mac_addr = of_get_mac_address(np);
2969         if (mac_addr)
2970                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2971
2972         pdata->no_ether_link =
2973                 of_property_read_bool(np, "renesas,no-ether-link");
2974         pdata->ether_link_active_low =
2975                 of_property_read_bool(np, "renesas,ether-link-active-low");
2976
2977         return pdata;
2978 }
2979
2980 static const struct of_device_id sh_eth_match_table[] = {
2981         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2982         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2983         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2984         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2985         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2986         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2987         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2988         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2989         { }
2990 };
2991 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2992 #else
2993 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2994 {
2995         return NULL;
2996 }
2997 #endif
2998
2999 static int sh_eth_drv_probe(struct platform_device *pdev)
3000 {
3001         int ret, devno = 0;
3002         struct resource *res;
3003         struct net_device *ndev = NULL;
3004         struct sh_eth_private *mdp = NULL;
3005         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3006         const struct platform_device_id *id = platform_get_device_id(pdev);
3007
3008         /* get base addr */
3009         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3010
3011         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3012         if (!ndev)
3013                 return -ENOMEM;
3014
3015         pm_runtime_enable(&pdev->dev);
3016         pm_runtime_get_sync(&pdev->dev);
3017
3018         devno = pdev->id;
3019         if (devno < 0)
3020                 devno = 0;
3021
3022         ndev->dma = -1;
3023         ret = platform_get_irq(pdev, 0);
3024         if (ret < 0)
3025                 goto out_release;
3026         ndev->irq = ret;
3027
3028         SET_NETDEV_DEV(ndev, &pdev->dev);
3029
3030         mdp = netdev_priv(ndev);
3031         mdp->num_tx_ring = TX_RING_SIZE;
3032         mdp->num_rx_ring = RX_RING_SIZE;
3033         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3034         if (IS_ERR(mdp->addr)) {
3035                 ret = PTR_ERR(mdp->addr);
3036                 goto out_release;
3037         }
3038
3039         ndev->base_addr = res->start;
3040
3041         spin_lock_init(&mdp->lock);
3042         mdp->pdev = pdev;
3043
3044         if (pdev->dev.of_node)
3045                 pd = sh_eth_parse_dt(&pdev->dev);
3046         if (!pd) {
3047                 dev_err(&pdev->dev, "no platform data\n");
3048                 ret = -EINVAL;
3049                 goto out_release;
3050         }
3051
3052         /* get PHY ID */
3053         mdp->phy_id = pd->phy;
3054         mdp->phy_interface = pd->phy_interface;
3055         mdp->no_ether_link = pd->no_ether_link;
3056         mdp->ether_link_active_low = pd->ether_link_active_low;
3057
3058         /* set cpu data */
3059         if (id) {
3060                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3061         } else  {
3062                 const struct of_device_id *match;
3063
3064                 match = of_match_device(of_match_ptr(sh_eth_match_table),
3065                                         &pdev->dev);
3066                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3067         }
3068         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3069         if (!mdp->reg_offset) {
3070                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3071                         mdp->cd->register_type);
3072                 ret = -EINVAL;
3073                 goto out_release;
3074         }
3075         sh_eth_set_default_cpu_data(mdp->cd);
3076
3077         /* set function */
3078         if (mdp->cd->tsu)
3079                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3080         else
3081                 ndev->netdev_ops = &sh_eth_netdev_ops;
3082         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3083         ndev->watchdog_timeo = TX_TIMEOUT;
3084
3085         /* debug message level */
3086         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3087
3088         /* read and set MAC address */
3089         read_mac_address(ndev, pd->mac_addr);
3090         if (!is_valid_ether_addr(ndev->dev_addr)) {
3091                 dev_warn(&pdev->dev,
3092                          "no valid MAC address supplied, using a random one.\n");
3093                 eth_hw_addr_random(ndev);
3094         }
3095
3096         /* ioremap the TSU registers */
3097         if (mdp->cd->tsu) {
3098                 struct resource *rtsu;
3099                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3100                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3101                 if (IS_ERR(mdp->tsu_addr)) {
3102                         ret = PTR_ERR(mdp->tsu_addr);
3103                         goto out_release;
3104                 }
3105                 mdp->port = devno % 2;
3106                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3107         }
3108
3109         /* initialize first or needed device */
3110         if (!devno || pd->needs_init) {
3111                 if (mdp->cd->chip_reset)
3112                         mdp->cd->chip_reset(ndev);
3113
3114                 if (mdp->cd->tsu) {
3115                         /* TSU init (Init only)*/
3116                         sh_eth_tsu_init(mdp);
3117                 }
3118         }
3119
3120         if (mdp->cd->rmiimode)
3121                 sh_eth_write(ndev, 0x1, RMIIMODE);
3122
3123         /* MDIO bus init */
3124         ret = sh_mdio_init(mdp, pd);
3125         if (ret) {
3126                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3127                 goto out_release;
3128         }
3129
3130         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3131
3132         /* network device register */
3133         ret = register_netdev(ndev);
3134         if (ret)
3135                 goto out_napi_del;
3136
3137         /* print device information */
3138         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3139                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3140
3141         pm_runtime_put(&pdev->dev);
3142         platform_set_drvdata(pdev, ndev);
3143
3144         return ret;
3145
3146 out_napi_del:
3147         netif_napi_del(&mdp->napi);
3148         sh_mdio_release(mdp);
3149
3150 out_release:
3151         /* net_dev free */
3152         if (ndev)
3153                 free_netdev(ndev);
3154
3155         pm_runtime_put(&pdev->dev);
3156         pm_runtime_disable(&pdev->dev);
3157         return ret;
3158 }
3159
3160 static int sh_eth_drv_remove(struct platform_device *pdev)
3161 {
3162         struct net_device *ndev = platform_get_drvdata(pdev);
3163         struct sh_eth_private *mdp = netdev_priv(ndev);
3164
3165         unregister_netdev(ndev);
3166         netif_napi_del(&mdp->napi);
3167         sh_mdio_release(mdp);
3168         pm_runtime_disable(&pdev->dev);
3169         free_netdev(ndev);
3170
3171         return 0;
3172 }
3173
3174 #ifdef CONFIG_PM
3175 #ifdef CONFIG_PM_SLEEP
3176 static int sh_eth_suspend(struct device *dev)
3177 {
3178         struct net_device *ndev = dev_get_drvdata(dev);
3179         int ret = 0;
3180
3181         if (netif_running(ndev)) {
3182                 netif_device_detach(ndev);
3183                 ret = sh_eth_close(ndev);
3184         }
3185
3186         return ret;
3187 }
3188
3189 static int sh_eth_resume(struct device *dev)
3190 {
3191         struct net_device *ndev = dev_get_drvdata(dev);
3192         int ret = 0;
3193
3194         if (netif_running(ndev)) {
3195                 ret = sh_eth_open(ndev);
3196                 if (ret < 0)
3197                         return ret;
3198                 netif_device_attach(ndev);
3199         }
3200
3201         return ret;
3202 }
3203 #endif
3204
3205 static int sh_eth_runtime_nop(struct device *dev)
3206 {
3207         /* Runtime PM callback shared between ->runtime_suspend()
3208          * and ->runtime_resume(). Simply returns success.
3209          *
3210          * This driver re-initializes all registers after
3211          * pm_runtime_get_sync() anyway so there is no need
3212          * to save and restore registers here.
3213          */
3214         return 0;
3215 }
3216
3217 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3218         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3219         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3220 };
3221 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3222 #else
3223 #define SH_ETH_PM_OPS NULL
3224 #endif
3225
3226 static struct platform_device_id sh_eth_id_table[] = {
3227         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3228         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3229         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3230         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3231         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3232         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3233         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3234         { }
3235 };
3236 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3237
3238 static struct platform_driver sh_eth_driver = {
3239         .probe = sh_eth_drv_probe,
3240         .remove = sh_eth_drv_remove,
3241         .id_table = sh_eth_id_table,
3242         .driver = {
3243                    .name = CARDNAME,
3244                    .pm = SH_ETH_PM_OPS,
3245                    .of_match_table = of_match_ptr(sh_eth_match_table),
3246         },
3247 };
3248
3249 module_platform_driver(sh_eth_driver);
3250
3251 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3252 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3253 MODULE_LICENSE("GPL v2");