drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_DEFAULTS                  \
  56         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  57
  58 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  59         SH_ETH_OFFSET_DEFAULTS,
  60
  61         [EDSR]          = 0x0000,
  62         [EDMR]          = 0x0400,
  63         [EDTRR]         = 0x0408,
  64         [EDRRR]         = 0x0410,
  65         [EESR]          = 0x0428,
  66         [EESIPR]        = 0x0430,
  67         [TDLAR]         = 0x0010,
  68         [TDFAR]         = 0x0014,
  69         [TDFXR]         = 0x0018,
  70         [TDFFR]         = 0x001c,
  71         [RDLAR]         = 0x0030,
  72         [RDFAR]         = 0x0034,
  73         [RDFXR]         = 0x0038,
  74         [RDFFR]         = 0x003c,
  75         [TRSCER]        = 0x0438,
  76         [RMFCR]         = 0x0440,
  77         [TFTR]          = 0x0448,
  78         [FDR]           = 0x0450,
  79         [RMCR]          = 0x0458,
  80         [RPADIR]        = 0x0460,
  81         [FCFTR]         = 0x0468,
  82         [CSMR]          = 0x04E4,
  83
  84         [ECMR]          = 0x0500,
  85         [ECSR]          = 0x0510,
  86         [ECSIPR]        = 0x0518,
  87         [PIR]           = 0x0520,
  88         [PSR]           = 0x0528,
  89         [PIPR]          = 0x052c,
  90         [RFLR]          = 0x0508,
  91         [APR]           = 0x0554,
  92         [MPR]           = 0x0558,
  93         [PFTCR]         = 0x055c,
  94         [PFRCR]         = 0x0560,
  95         [TPAUSER]       = 0x0564,
  96         [GECMR]         = 0x05b0,
  97         [BCULR]         = 0x05b4,
  98         [MAHR]          = 0x05c0,
  99         [MALR]          = 0x05c8,
 100         [TROCR]         = 0x0700,
 101         [CDCR]          = 0x0708,
 102         [LCCR]          = 0x0710,
 103         [CEFCR]         = 0x0740,
 104         [FRECR]         = 0x0748,
 105         [TSFRCR]        = 0x0750,
 106         [TLFRCR]        = 0x0758,
 107         [RFCR]          = 0x0760,
 108         [CERCR]         = 0x0768,
 109         [CEECR]         = 0x0770,
 110         [MAFCR]         = 0x0778,
 111         [RMII_MII]      = 0x0790,
 112
 113         [ARSTR]         = 0x0000,
 114         [TSU_CTRST]     = 0x0004,
 115         [TSU_FWEN0]     = 0x0010,
 116         [TSU_FWEN1]     = 0x0014,
 117         [TSU_FCM]       = 0x0018,
 118         [TSU_BSYSL0]    = 0x0020,
 119         [TSU_BSYSL1]    = 0x0024,
 120         [TSU_PRISL0]    = 0x0028,
 121         [TSU_PRISL1]    = 0x002c,
 122         [TSU_FWSL0]     = 0x0030,
 123         [TSU_FWSL1]     = 0x0034,
 124         [TSU_FWSLC]     = 0x0038,
 125         [TSU_QTAG0]     = 0x0040,
 126         [TSU_QTAG1]     = 0x0044,
 127         [TSU_FWSR]      = 0x0050,
 128         [TSU_FWINMK]    = 0x0054,
 129         [TSU_ADQT0]     = 0x0048,
 130         [TSU_ADQT1]     = 0x004c,
 131         [TSU_VTAG0]     = 0x0058,
 132         [TSU_VTAG1]     = 0x005c,
 133         [TSU_ADSBSY]    = 0x0060,
 134         [TSU_TEN]       = 0x0064,
 135         [TSU_POST1]     = 0x0070,
 136         [TSU_POST2]     = 0x0074,
 137         [TSU_POST3]     = 0x0078,
 138         [TSU_POST4]     = 0x007c,
 139         [TSU_ADRH0]     = 0x0100,
 140
 141         [TXNLCR0]       = 0x0080,
 142         [TXALCR0]       = 0x0084,
 143         [RXNLCR0]       = 0x0088,
 144         [RXALCR0]       = 0x008c,
 145         [FWNLCR0]       = 0x0090,
 146         [FWALCR0]       = 0x0094,
 147         [TXNLCR1]       = 0x00a0,
 148         [TXALCR1]       = 0x00a0,
 149         [RXNLCR1]       = 0x00a8,
 150         [RXALCR1]       = 0x00ac,
 151         [FWNLCR1]       = 0x00b0,
 152         [FWALCR1]       = 0x00b4,
 153 };
 154
 155 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 156         SH_ETH_OFFSET_DEFAULTS,
 157
 158         [EDSR]          = 0x0000,
 159         [EDMR]          = 0x0400,
 160         [EDTRR]         = 0x0408,
 161         [EDRRR]         = 0x0410,
 162         [EESR]          = 0x0428,
 163         [EESIPR]        = 0x0430,
 164         [TDLAR]         = 0x0010,
 165         [TDFAR]         = 0x0014,
 166         [TDFXR]         = 0x0018,
 167         [TDFFR]         = 0x001c,
 168         [RDLAR]         = 0x0030,
 169         [RDFAR]         = 0x0034,
 170         [RDFXR]         = 0x0038,
 171         [RDFFR]         = 0x003c,
 172         [TRSCER]        = 0x0438,
 173         [RMFCR]         = 0x0440,
 174         [TFTR]          = 0x0448,
 175         [FDR]           = 0x0450,
 176         [RMCR]          = 0x0458,
 177         [RPADIR]        = 0x0460,
 178         [FCFTR]         = 0x0468,
 179         [CSMR]          = 0x04E4,
 180
 181         [ECMR]          = 0x0500,
 182         [RFLR]          = 0x0508,
 183         [ECSR]          = 0x0510,
 184         [ECSIPR]        = 0x0518,
 185         [PIR]           = 0x0520,
 186         [APR]           = 0x0554,
 187         [MPR]           = 0x0558,
 188         [PFTCR]         = 0x055c,
 189         [PFRCR]         = 0x0560,
 190         [TPAUSER]       = 0x0564,
 191         [MAHR]          = 0x05c0,
 192         [MALR]          = 0x05c8,
 193         [CEFCR]         = 0x0740,
 194         [FRECR]         = 0x0748,
 195         [TSFRCR]        = 0x0750,
 196         [TLFRCR]        = 0x0758,
 197         [RFCR]          = 0x0760,
 198         [MAFCR]         = 0x0778,
 199
 200         [ARSTR]         = 0x0000,
 201         [TSU_CTRST]     = 0x0004,
 202         [TSU_VTAG0]     = 0x0058,
 203         [TSU_ADSBSY]    = 0x0060,
 204         [TSU_TEN]       = 0x0064,
 205         [TSU_ADRH0]     = 0x0100,
 206
 207         [TXNLCR0]       = 0x0080,
 208         [TXALCR0]       = 0x0084,
 209         [RXNLCR0]       = 0x0088,
 210         [RXALCR0]       = 0x008C,
 211 };
 212
 213 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 214         SH_ETH_OFFSET_DEFAULTS,
 215
 216         [ECMR]          = 0x0300,
 217         [RFLR]          = 0x0308,
 218         [ECSR]          = 0x0310,
 219         [ECSIPR]        = 0x0318,
 220         [PIR]           = 0x0320,
 221         [PSR]           = 0x0328,
 222         [RDMLR]         = 0x0340,
 223         [IPGR]          = 0x0350,
 224         [APR]           = 0x0354,
 225         [MPR]           = 0x0358,
 226         [RFCF]          = 0x0360,
 227         [TPAUSER]       = 0x0364,
 228         [TPAUSECR]      = 0x0368,
 229         [MAHR]          = 0x03c0,
 230         [MALR]          = 0x03c8,
 231         [TROCR]         = 0x03d0,
 232         [CDCR]          = 0x03d4,
 233         [LCCR]          = 0x03d8,
 234         [CNDCR]         = 0x03dc,
 235         [CEFCR]         = 0x03e4,
 236         [FRECR]         = 0x03e8,
 237         [TSFRCR]        = 0x03ec,
 238         [TLFRCR]        = 0x03f0,
 239         [RFCR]          = 0x03f4,
 240         [MAFCR]         = 0x03f8,
 241
 242         [EDMR]          = 0x0200,
 243         [EDTRR]         = 0x0208,
 244         [EDRRR]         = 0x0210,
 245         [TDLAR]         = 0x0218,
 246         [RDLAR]         = 0x0220,
 247         [EESR]          = 0x0228,
 248         [EESIPR]        = 0x0230,
 249         [TRSCER]        = 0x0238,
 250         [RMFCR]         = 0x0240,
 251         [TFTR]          = 0x0248,
 252         [FDR]           = 0x0250,
 253         [RMCR]          = 0x0258,
 254         [TFUCR]         = 0x0264,
 255         [RFOCR]         = 0x0268,
 256         [RMIIMODE]      = 0x026c,
 257         [FCFTR]         = 0x0270,
 258         [TRIMD]         = 0x027c,
 259 };
 260
 261 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 262         SH_ETH_OFFSET_DEFAULTS,
 263
 264         [ECMR]          = 0x0100,
 265         [RFLR]          = 0x0108,
 266         [ECSR]          = 0x0110,
 267         [ECSIPR]        = 0x0118,
 268         [PIR]           = 0x0120,
 269         [PSR]           = 0x0128,
 270         [RDMLR]         = 0x0140,
 271         [IPGR]          = 0x0150,
 272         [APR]           = 0x0154,
 273         [MPR]           = 0x0158,
 274         [TPAUSER]       = 0x0164,
 275         [RFCF]          = 0x0160,
 276         [TPAUSECR]      = 0x0168,
 277         [BCFRR]         = 0x016c,
 278         [MAHR]          = 0x01c0,
 279         [MALR]          = 0x01c8,
 280         [TROCR]         = 0x01d0,
 281         [CDCR]          = 0x01d4,
 282         [LCCR]          = 0x01d8,
 283         [CNDCR]         = 0x01dc,
 284         [CEFCR]         = 0x01e4,
 285         [FRECR]         = 0x01e8,
 286         [TSFRCR]        = 0x01ec,
 287         [TLFRCR]        = 0x01f0,
 288         [RFCR]          = 0x01f4,
 289         [MAFCR]         = 0x01f8,
 290         [RTRATE]        = 0x01fc,
 291
 292         [EDMR]          = 0x0000,
 293         [EDTRR]         = 0x0008,
 294         [EDRRR]         = 0x0010,
 295         [TDLAR]         = 0x0018,
 296         [RDLAR]         = 0x0020,
 297         [EESR]          = 0x0028,
 298         [EESIPR]        = 0x0030,
 299         [TRSCER]        = 0x0038,
 300         [RMFCR]         = 0x0040,
 301         [TFTR]          = 0x0048,
 302         [FDR]           = 0x0050,
 303         [RMCR]          = 0x0058,
 304         [TFUCR]         = 0x0064,
 305         [RFOCR]         = 0x0068,
 306         [FCFTR]         = 0x0070,
 307         [RPADIR]        = 0x0078,
 308         [TRIMD]         = 0x007c,
 309         [RBWAR]         = 0x00c8,
 310         [RDFAR]         = 0x00cc,
 311         [TBRAR]         = 0x00d4,
 312         [TDFAR]         = 0x00d8,
 313 };
 314
 315 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 316         SH_ETH_OFFSET_DEFAULTS,
 317
 318         [EDMR]          = 0x0000,
 319         [EDTRR]         = 0x0004,
 320         [EDRRR]         = 0x0008,
 321         [TDLAR]         = 0x000c,
 322         [RDLAR]         = 0x0010,
 323         [EESR]          = 0x0014,
 324         [EESIPR]        = 0x0018,
 325         [TRSCER]        = 0x001c,
 326         [RMFCR]         = 0x0020,
 327         [TFTR]          = 0x0024,
 328         [FDR]           = 0x0028,
 329         [RMCR]          = 0x002c,
 330         [EDOCR]         = 0x0030,
 331         [FCFTR]         = 0x0034,
 332         [RPADIR]        = 0x0038,
 333         [TRIMD]         = 0x003c,
 334         [RBWAR]         = 0x0040,
 335         [RDFAR]         = 0x0044,
 336         [TBRAR]         = 0x004c,
 337         [TDFAR]         = 0x0050,
 338
 339         [ECMR]          = 0x0160,
 340         [ECSR]          = 0x0164,
 341         [ECSIPR]        = 0x0168,
 342         [PIR]           = 0x016c,
 343         [MAHR]          = 0x0170,
 344         [MALR]          = 0x0174,
 345         [RFLR]          = 0x0178,
 346         [PSR]           = 0x017c,
 347         [TROCR]         = 0x0180,
 348         [CDCR]          = 0x0184,
 349         [LCCR]          = 0x0188,
 350         [CNDCR]         = 0x018c,
 351         [CEFCR]         = 0x0194,
 352         [FRECR]         = 0x0198,
 353         [TSFRCR]        = 0x019c,
 354         [TLFRCR]        = 0x01a0,
 355         [RFCR]          = 0x01a4,
 356         [MAFCR]         = 0x01a8,
 357         [IPGR]          = 0x01b4,
 358         [APR]           = 0x01b8,
 359         [MPR]           = 0x01bc,
 360         [TPAUSER]       = 0x01c4,
 361         [BCFR]          = 0x01cc,
 362
 363         [ARSTR]         = 0x0000,
 364         [TSU_CTRST]     = 0x0004,
 365         [TSU_FWEN0]     = 0x0010,
 366         [TSU_FWEN1]     = 0x0014,
 367         [TSU_FCM]       = 0x0018,
 368         [TSU_BSYSL0]    = 0x0020,
 369         [TSU_BSYSL1]    = 0x0024,
 370         [TSU_PRISL0]    = 0x0028,
 371         [TSU_PRISL1]    = 0x002c,
 372         [TSU_FWSL0]     = 0x0030,
 373         [TSU_FWSL1]     = 0x0034,
 374         [TSU_FWSLC]     = 0x0038,
 375         [TSU_QTAGM0]    = 0x0040,
 376         [TSU_QTAGM1]    = 0x0044,
 377         [TSU_ADQT0]     = 0x0048,
 378         [TSU_ADQT1]     = 0x004c,
 379         [TSU_FWSR]      = 0x0050,
 380         [TSU_FWINMK]    = 0x0054,
 381         [TSU_ADSBSY]    = 0x0060,
 382         [TSU_TEN]       = 0x0064,
 383         [TSU_POST1]     = 0x0070,
 384         [TSU_POST2]     = 0x0074,
 385         [TSU_POST3]     = 0x0078,
 386         [TSU_POST4]     = 0x007c,
 387
 388         [TXNLCR0]       = 0x0080,
 389         [TXALCR0]       = 0x0084,
 390         [RXNLCR0]       = 0x0088,
 391         [RXALCR0]       = 0x008c,
 392         [FWNLCR0]       = 0x0090,
 393         [FWALCR0]       = 0x0094,
 394         [TXNLCR1]       = 0x00a0,
 395         [TXALCR1]       = 0x00a0,
 396         [RXNLCR1]       = 0x00a8,
 397         [RXALCR1]       = 0x00ac,
 398         [FWNLCR1]       = 0x00b0,
 399         [FWALCR1]       = 0x00b4,
 400
 401         [TSU_ADRH0]     = 0x0100,
 402 };
 403
 404 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 405 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 406
 407 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 408 {
 409         return mdp->reg_offset == sh_eth_offset_gigabit;
 410 }
 411
 412 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 413 {
 414         return mdp->reg_offset == sh_eth_offset_fast_rz;
 415 }
 416
 417 static void sh_eth_select_mii(struct net_device *ndev)
 418 {
 419         u32 value = 0x0;
 420         struct sh_eth_private *mdp = netdev_priv(ndev);
 421
 422         switch (mdp->phy_interface) {
 423         case PHY_INTERFACE_MODE_GMII:
 424                 value = 0x2;
 425                 break;
 426         case PHY_INTERFACE_MODE_MII:
 427                 value = 0x1;
 428                 break;
 429         case PHY_INTERFACE_MODE_RMII:
 430                 value = 0x0;
 431                 break;
 432         default:
 433                 netdev_warn(ndev,
 434                             "PHY interface mode was not setup. Set to MII.\n");
 435                 value = 0x1;
 436                 break;
 437         }
 438
 439         sh_eth_write(ndev, value, RMII_MII);
 440 }
 441
 442 static void sh_eth_set_duplex(struct net_device *ndev)
 443 {
 444         struct sh_eth_private *mdp = netdev_priv(ndev);
 445
 446         if (mdp->duplex) /* Full */
 447                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 448         else            /* Half */
 449                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 450 }
 451
 452 static void sh_eth_chip_reset(struct net_device *ndev)
 453 {
 454         struct sh_eth_private *mdp = netdev_priv(ndev);
 455
 456         /* reset device */
 457         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 458         mdelay(1);
 459 }
 460
 461 static void sh_eth_set_rate_gether(struct net_device *ndev)
 462 {
 463         struct sh_eth_private *mdp = netdev_priv(ndev);
 464
 465         switch (mdp->speed) {
 466         case 10: /* 10BASE */
 467                 sh_eth_write(ndev, GECMR_10, GECMR);
 468                 break;
 469         case 100:/* 100BASE */
 470                 sh_eth_write(ndev, GECMR_100, GECMR);
 471                 break;
 472         case 1000: /* 1000BASE */
 473                 sh_eth_write(ndev, GECMR_1000, GECMR);
 474                 break;
 475         default:
 476                 break;
 477         }
 478 }
 479
 480 #ifdef CONFIG_OF
 481 /* R7S72100 */
 482 static struct sh_eth_cpu_data r7s72100_data = {
 483         .chip_reset     = sh_eth_chip_reset,
 484         .set_duplex     = sh_eth_set_duplex,
 485
 486         .register_type  = SH_ETH_REG_FAST_RZ,
 487
 488         .ecsr_value     = ECSR_ICD,
 489         .ecsipr_value   = ECSIPR_ICDIP,
 490         .eesipr_value   = 0xff7f009f,
 491
 492         .tx_check       = EESR_TC1 | EESR_FTC,
 493         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 494                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 495                           EESR_TDE | EESR_ECI,
 496         .fdr_value      = 0x0000070f,
 497
 498         .no_psr         = 1,
 499         .apr            = 1,
 500         .mpr            = 1,
 501         .tpauser        = 1,
 502         .hw_swap        = 1,
 503         .rpadir         = 1,
 504         .rpadir_value   = 2 << 16,
 505         .no_trimd       = 1,
 506         .no_ade         = 1,
 507         .hw_crc         = 1,
 508         .tsu            = 1,
 509         .shift_rd0      = 1,
 510 };
 511
 512 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 513 {
 514         struct sh_eth_private *mdp = netdev_priv(ndev);
 515
 516         /* reset device */
 517         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 518         mdelay(1);
 519
 520         sh_eth_select_mii(ndev);
 521 }
 522
 523 /* R8A7740 */
 524 static struct sh_eth_cpu_data r8a7740_data = {
 525         .chip_reset     = sh_eth_chip_reset_r8a7740,
 526         .set_duplex     = sh_eth_set_duplex,
 527         .set_rate       = sh_eth_set_rate_gether,
 528
 529         .register_type  = SH_ETH_REG_GIGABIT,
 530
 531         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 532         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 533         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 534
 535         .tx_check       = EESR_TC1 | EESR_FTC,
 536         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 537                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 538                           EESR_TDE | EESR_ECI,
 539         .fdr_value      = 0x0000070f,
 540
 541         .apr            = 1,
 542         .mpr            = 1,
 543         .tpauser        = 1,
 544         .bculr          = 1,
 545         .hw_swap        = 1,
 546         .rpadir         = 1,
 547         .rpadir_value   = 2 << 16,
 548         .no_trimd       = 1,
 549         .no_ade         = 1,
 550         .tsu            = 1,
 551         .select_mii     = 1,
 552         .shift_rd0      = 1,
 553 };
 554
 555 /* There is CPU dependent code */
 556 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 557 {
 558         struct sh_eth_private *mdp = netdev_priv(ndev);
 559
 560         switch (mdp->speed) {
 561         case 10: /* 10BASE */
 562                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 563                 break;
 564         case 100:/* 100BASE */
 565                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 566                 break;
 567         default:
 568                 break;
 569         }
 570 }
 571
 572 /* R8A7778/9 */
 573 static struct sh_eth_cpu_data r8a777x_data = {
 574         .set_duplex     = sh_eth_set_duplex,
 575         .set_rate       = sh_eth_set_rate_r8a777x,
 576
 577         .register_type  = SH_ETH_REG_FAST_RCAR,
 578
 579         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 580         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 581         .eesipr_value   = 0x01ff009f,
 582
 583         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 584         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 585                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 586                           EESR_ECI,
 587         .fdr_value      = 0x00000f0f,
 588
 589         .apr            = 1,
 590         .mpr            = 1,
 591         .tpauser        = 1,
 592         .hw_swap        = 1,
 593 };
 594
 595 /* R8A7790/1 */
 596 static struct sh_eth_cpu_data r8a779x_data = {
 597         .set_duplex     = sh_eth_set_duplex,
 598         .set_rate       = sh_eth_set_rate_r8a777x,
 599
 600         .register_type  = SH_ETH_REG_FAST_RCAR,
 601
 602         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 603         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 604         .eesipr_value   = 0x01ff009f,
 605
 606         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 607         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 608                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 609                           EESR_ECI,
 610         .fdr_value      = 0x00000f0f,
 611
 612         .trscer_err_mask = DESC_I_RINT8,
 613
 614         .apr            = 1,
 615         .mpr            = 1,
 616         .tpauser        = 1,
 617         .hw_swap        = 1,
 618         .rmiimode       = 1,
 619 };
 620 #endif /* CONFIG_OF */
 621
 622 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 623 {
 624         struct sh_eth_private *mdp = netdev_priv(ndev);
 625
 626         switch (mdp->speed) {
 627         case 10: /* 10BASE */
 628                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 629                 break;
 630         case 100:/* 100BASE */
 631                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 632                 break;
 633         default:
 634                 break;
 635         }
 636 }
 637
 638 /* SH7724 */
 639 static struct sh_eth_cpu_data sh7724_data = {
 640         .set_duplex     = sh_eth_set_duplex,
 641         .set_rate       = sh_eth_set_rate_sh7724,
 642
 643         .register_type  = SH_ETH_REG_FAST_SH4,
 644
 645         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 646         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 647         .eesipr_value   = 0x01ff009f,
 648
 649         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 650         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 651                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 652                           EESR_ECI,
 653
 654         .apr            = 1,
 655         .mpr            = 1,
 656         .tpauser        = 1,
 657         .hw_swap        = 1,
 658         .rpadir         = 1,
 659         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 660 };
 661
 662 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 663 {
 664         struct sh_eth_private *mdp = netdev_priv(ndev);
 665
 666         switch (mdp->speed) {
 667         case 10: /* 10BASE */
 668                 sh_eth_write(ndev, 0, RTRATE);
 669                 break;
 670         case 100:/* 100BASE */
 671                 sh_eth_write(ndev, 1, RTRATE);
 672                 break;
 673         default:
 674                 break;
 675         }
 676 }
 677
 678 /* SH7757 */
 679 static struct sh_eth_cpu_data sh7757_data = {
 680         .set_duplex     = sh_eth_set_duplex,
 681         .set_rate       = sh_eth_set_rate_sh7757,
 682
 683         .register_type  = SH_ETH_REG_FAST_SH4,
 684
 685         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 686
 687         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 688         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 689                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 690                           EESR_ECI,
 691
 692         .irq_flags      = IRQF_SHARED,
 693         .apr            = 1,
 694         .mpr            = 1,
 695         .tpauser        = 1,
 696         .hw_swap        = 1,
 697         .no_ade         = 1,
 698         .rpadir         = 1,
 699         .rpadir_value   = 2 << 16,
 700         .rtrate         = 1,
 701 };
 702
 703 #define SH_GIGA_ETH_BASE        0xfee00000UL
 704 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 705 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 706 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 707 {
 708         int i;
 709         u32 mahr[2], malr[2];
 710
 711         /* save MAHR and MALR */
 712         for (i = 0; i < 2; i++) {
 713                 malr[i] = ioread32((void *)GIGA_MALR(i));
 714                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 715         }
 716
 717         /* reset device */
 718         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 719         mdelay(1);
 720
 721         /* restore MAHR and MALR */
 722         for (i = 0; i < 2; i++) {
 723                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 724                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 725         }
 726 }
 727
 728 static void sh_eth_set_rate_giga(struct net_device *ndev)
 729 {
 730         struct sh_eth_private *mdp = netdev_priv(ndev);
 731
 732         switch (mdp->speed) {
 733         case 10: /* 10BASE */
 734                 sh_eth_write(ndev, 0x00000000, GECMR);
 735                 break;
 736         case 100:/* 100BASE */
 737                 sh_eth_write(ndev, 0x00000010, GECMR);
 738                 break;
 739         case 1000: /* 1000BASE */
 740                 sh_eth_write(ndev, 0x00000020, GECMR);
 741                 break;
 742         default:
 743                 break;
 744         }
 745 }
 746
 747 /* SH7757(GETHERC) */
 748 static struct sh_eth_cpu_data sh7757_data_giga = {
 749         .chip_reset     = sh_eth_chip_reset_giga,
 750         .set_duplex     = sh_eth_set_duplex,
 751         .set_rate       = sh_eth_set_rate_giga,
 752
 753         .register_type  = SH_ETH_REG_GIGABIT,
 754
 755         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 756         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 757         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 758
 759         .tx_check       = EESR_TC1 | EESR_FTC,
 760         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 761                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 762                           EESR_TDE | EESR_ECI,
 763         .fdr_value      = 0x0000072f,
 764
 765         .irq_flags      = IRQF_SHARED,
 766         .apr            = 1,
 767         .mpr            = 1,
 768         .tpauser        = 1,
 769         .bculr          = 1,
 770         .hw_swap        = 1,
 771         .rpadir         = 1,
 772         .rpadir_value   = 2 << 16,
 773         .no_trimd       = 1,
 774         .no_ade         = 1,
 775         .tsu            = 1,
 776 };
 777
 778 /* SH7734 */
 779 static struct sh_eth_cpu_data sh7734_data = {
 780         .chip_reset     = sh_eth_chip_reset,
 781         .set_duplex     = sh_eth_set_duplex,
 782         .set_rate       = sh_eth_set_rate_gether,
 783
 784         .register_type  = SH_ETH_REG_GIGABIT,
 785
 786         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 787         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 788         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 789
 790         .tx_check       = EESR_TC1 | EESR_FTC,
 791         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 792                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 793                           EESR_TDE | EESR_ECI,
 794
 795         .apr            = 1,
 796         .mpr            = 1,
 797         .tpauser        = 1,
 798         .bculr          = 1,
 799         .hw_swap        = 1,
 800         .no_trimd       = 1,
 801         .no_ade         = 1,
 802         .tsu            = 1,
 803         .hw_crc         = 1,
 804         .select_mii     = 1,
 805 };
 806
 807 /* SH7763 */
 808 static struct sh_eth_cpu_data sh7763_data = {
 809         .chip_reset     = sh_eth_chip_reset,
 810         .set_duplex     = sh_eth_set_duplex,
 811         .set_rate       = sh_eth_set_rate_gether,
 812
 813         .register_type  = SH_ETH_REG_GIGABIT,
 814
 815         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 816         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 817         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 818
 819         .tx_check       = EESR_TC1 | EESR_FTC,
 820         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 821                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 822                           EESR_ECI,
 823
 824         .apr            = 1,
 825         .mpr            = 1,
 826         .tpauser        = 1,
 827         .bculr          = 1,
 828         .hw_swap        = 1,
 829         .no_trimd       = 1,
 830         .no_ade         = 1,
 831         .tsu            = 1,
 832         .irq_flags      = IRQF_SHARED,
 833 };
 834
 835 static struct sh_eth_cpu_data sh7619_data = {
 836         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 837
 838         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 839
 840         .apr            = 1,
 841         .mpr            = 1,
 842         .tpauser        = 1,
 843         .hw_swap        = 1,
 844 };
 845
 846 static struct sh_eth_cpu_data sh771x_data = {
 847         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 848
 849         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 850         .tsu            = 1,
 851 };
 852
 853 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 854 {
 855         if (!cd->ecsr_value)
 856                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 857
 858         if (!cd->ecsipr_value)
 859                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 860
 861         if (!cd->fcftr_value)
 862                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 863                                   DEFAULT_FIFO_F_D_RFD;
 864
 865         if (!cd->fdr_value)
 866                 cd->fdr_value = DEFAULT_FDR_INIT;
 867
 868         if (!cd->tx_check)
 869                 cd->tx_check = DEFAULT_TX_CHECK;
 870
 871         if (!cd->eesr_err_check)
 872                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 873
 874         if (!cd->trscer_err_mask)
 875                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 876 }
 877
 878 static int sh_eth_check_reset(struct net_device *ndev)
 879 {
 880         int ret = 0;
 881         int cnt = 100;
 882
 883         while (cnt > 0) {
 884                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 885                         break;
 886                 mdelay(1);
 887                 cnt--;
 888         }
 889         if (cnt <= 0) {
 890                 netdev_err(ndev, "Device reset failed\n");
 891                 ret = -ETIMEDOUT;
 892         }
 893         return ret;
 894 }
 895
 896 static int sh_eth_reset(struct net_device *ndev)
 897 {
 898         struct sh_eth_private *mdp = netdev_priv(ndev);
 899         int ret = 0;
 900
 901         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 902                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 903                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 904                              EDMR);
 905
 906                 ret = sh_eth_check_reset(ndev);
 907                 if (ret)
 908                         return ret;
 909
 910                 /* Table Init */
 911                 sh_eth_write(ndev, 0x0, TDLAR);
 912                 sh_eth_write(ndev, 0x0, TDFAR);
 913                 sh_eth_write(ndev, 0x0, TDFXR);
 914                 sh_eth_write(ndev, 0x0, TDFFR);
 915                 sh_eth_write(ndev, 0x0, RDLAR);
 916                 sh_eth_write(ndev, 0x0, RDFAR);
 917                 sh_eth_write(ndev, 0x0, RDFXR);
 918                 sh_eth_write(ndev, 0x0, RDFFR);
 919
 920                 /* Reset HW CRC register */
 921                 if (mdp->cd->hw_crc)
 922                         sh_eth_write(ndev, 0x0, CSMR);
 923
 924                 /* Select MII mode */
 925                 if (mdp->cd->select_mii)
 926                         sh_eth_select_mii(ndev);
 927         } else {
 928                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 929                              EDMR);
 930                 mdelay(3);
 931                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 932                              EDMR);
 933         }
 934
 935         return ret;
 936 }
 937
 938 static void sh_eth_set_receive_align(struct sk_buff *skb)
 939 {
 940         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 941
 942         if (reserve)
 943                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 944 }
 945
 946
 947 /* CPU <-> EDMAC endian convert */
 948 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 949 {
 950         switch (mdp->edmac_endian) {
 951         case EDMAC_LITTLE_ENDIAN:
 952                 return cpu_to_le32(x);
 953         case EDMAC_BIG_ENDIAN:
 954                 return cpu_to_be32(x);
 955         }
 956         return x;
 957 }
 958
 959 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 960 {
 961         switch (mdp->edmac_endian) {
 962         case EDMAC_LITTLE_ENDIAN:
 963                 return le32_to_cpu(x);
 964         case EDMAC_BIG_ENDIAN:
 965                 return be32_to_cpu(x);
 966         }
 967         return x;
 968 }
 969
 970 /* Program the hardware MAC address from dev->dev_addr. */
 971 static void update_mac_address(struct net_device *ndev)
 972 {
 973         sh_eth_write(ndev,
 974                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 975                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 976         sh_eth_write(ndev,
 977                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 978 }
 979
 980 /* Get MAC address from SuperH MAC address register
 981  *
 982  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 983  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 984  * When you want use this device, you must set MAC address in bootloader.
 985  *
 986  */
 987 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 988 {
 989         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 990                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 991         } else {
 992                 u32 mahr = sh_eth_read(ndev, MAHR);
 993                 u32 malr = sh_eth_read(ndev, MALR);
 994
 995                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
 996                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
 997                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
 998                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
 999                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1000                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1001         }
1002 }
1003
1004 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1005 {
1006         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1007                 return EDTRR_TRNS_GETHER;
1008         else
1009                 return EDTRR_TRNS_ETHER;
1010 }
1011
1012 struct bb_info {
1013         void (*set_gate)(void *addr);
1014         struct mdiobb_ctrl ctrl;
1015         void *addr;
1016         u32 mmd_msk;/* MMD */
1017         u32 mdo_msk;
1018         u32 mdi_msk;
1019         u32 mdc_msk;
1020 };
1021
1022 /* PHY bit set */
1023 static void bb_set(void *addr, u32 msk)
1024 {
1025         iowrite32(ioread32(addr) | msk, addr);
1026 }
1027
1028 /* PHY bit clear */
1029 static void bb_clr(void *addr, u32 msk)
1030 {
1031         iowrite32((ioread32(addr) & ~msk), addr);
1032 }
1033
1034 /* PHY bit read */
1035 static int bb_read(void *addr, u32 msk)
1036 {
1037         return (ioread32(addr) & msk) != 0;
1038 }
1039
1040 /* Data I/O pin control */
1041 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1042 {
1043         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1044
1045         if (bitbang->set_gate)
1046                 bitbang->set_gate(bitbang->addr);
1047
1048         if (bit)
1049                 bb_set(bitbang->addr, bitbang->mmd_msk);
1050         else
1051                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1052 }
1053
1054 /* Set bit data*/
1055 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1056 {
1057         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1058
1059         if (bitbang->set_gate)
1060                 bitbang->set_gate(bitbang->addr);
1061
1062         if (bit)
1063                 bb_set(bitbang->addr, bitbang->mdo_msk);
1064         else
1065                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1066 }
1067
1068 /* Get bit data*/
1069 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1070 {
1071         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1072
1073         if (bitbang->set_gate)
1074                 bitbang->set_gate(bitbang->addr);
1075
1076         return bb_read(bitbang->addr, bitbang->mdi_msk);
1077 }
1078
1079 /* MDC pin control */
1080 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1081 {
1082         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1083
1084         if (bitbang->set_gate)
1085                 bitbang->set_gate(bitbang->addr);
1086
1087         if (bit)
1088                 bb_set(bitbang->addr, bitbang->mdc_msk);
1089         else
1090                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1091 }
1092
1093 /* mdio bus control struct */
1094 static struct mdiobb_ops bb_ops = {
1095         .owner = THIS_MODULE,
1096         .set_mdc = sh_mdc_ctrl,
1097         .set_mdio_dir = sh_mmd_ctrl,
1098         .set_mdio_data = sh_set_mdio,
1099         .get_mdio_data = sh_get_mdio,
1100 };
1101
1102 /* free skb and descriptor buffer */
1103 static void sh_eth_ring_free(struct net_device *ndev)
1104 {
1105         struct sh_eth_private *mdp = netdev_priv(ndev);
1106         int ringsize, i;
1107
1108         /* Free Rx skb ringbuffer */
1109         if (mdp->rx_skbuff) {
1110                 for (i = 0; i < mdp->num_rx_ring; i++)
1111                         dev_kfree_skb(mdp->rx_skbuff[i]);
1112         }
1113         kfree(mdp->rx_skbuff);
1114         mdp->rx_skbuff = NULL;
1115
1116         /* Free Tx skb ringbuffer */
1117         if (mdp->tx_skbuff) {
1118                 for (i = 0; i < mdp->num_tx_ring; i++)
1119                         dev_kfree_skb(mdp->tx_skbuff[i]);
1120         }
1121         kfree(mdp->tx_skbuff);
1122         mdp->tx_skbuff = NULL;
1123
1124         if (mdp->rx_ring) {
1125                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1126                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1127                                   mdp->rx_desc_dma);
1128                 mdp->rx_ring = NULL;
1129         }
1130
1131         if (mdp->tx_ring) {
1132                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1133                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1134                                   mdp->tx_desc_dma);
1135                 mdp->tx_ring = NULL;
1136         }
1137 }
1138
1139 /* format skb and descriptor buffer */
1140 static void sh_eth_ring_format(struct net_device *ndev)
1141 {
1142         struct sh_eth_private *mdp = netdev_priv(ndev);
1143         int i;
1144         struct sk_buff *skb;
1145         struct sh_eth_rxdesc *rxdesc = NULL;
1146         struct sh_eth_txdesc *txdesc = NULL;
1147         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1148         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1149         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1150         dma_addr_t dma_addr;
1151
1152         mdp->cur_rx = 0;
1153         mdp->cur_tx = 0;
1154         mdp->dirty_rx = 0;
1155         mdp->dirty_tx = 0;
1156
1157         memset(mdp->rx_ring, 0, rx_ringsize);
1158
1159         /* build Rx ring buffer */
1160         for (i = 0; i < mdp->num_rx_ring; i++) {
1161                 /* skb */
1162                 mdp->rx_skbuff[i] = NULL;
1163                 skb = netdev_alloc_skb(ndev, skbuff_size);
1164                 if (skb == NULL)
1165                         break;
1166                 sh_eth_set_receive_align(skb);
1167
1168                 /* RX descriptor */
1169                 rxdesc = &mdp->rx_ring[i];
1170                 /* The size of the buffer is a multiple of 32 bytes. */
1171                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1172                 dma_addr = dma_map_single(&ndev->dev, skb->data,
1173                                           rxdesc->buffer_length,
1174                                           DMA_FROM_DEVICE);
1175                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1176                         kfree_skb(skb);
1177                         break;
1178                 }
1179                 mdp->rx_skbuff[i] = skb;
1180                 rxdesc->addr = dma_addr;
1181                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1182
1183                 /* Rx descriptor address set */
1184                 if (i == 0) {
1185                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1186                         if (sh_eth_is_gether(mdp) ||
1187                             sh_eth_is_rz_fast_ether(mdp))
1188                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1189                 }
1190         }
1191
1192         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1193
1194         /* Mark the last entry as wrapping the ring. */
1195         rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1196
1197         memset(mdp->tx_ring, 0, tx_ringsize);
1198
1199         /* build Tx ring buffer */
1200         for (i = 0; i < mdp->num_tx_ring; i++) {
1201                 mdp->tx_skbuff[i] = NULL;
1202                 txdesc = &mdp->tx_ring[i];
1203                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1204                 txdesc->buffer_length = 0;
1205                 if (i == 0) {
1206                         /* Tx descriptor address set */
1207                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1208                         if (sh_eth_is_gether(mdp) ||
1209                             sh_eth_is_rz_fast_ether(mdp))
1210                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1211                 }
1212         }
1213
1214         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1215 }
1216
1217 /* Get skb and descriptor buffer */
1218 static int sh_eth_ring_init(struct net_device *ndev)
1219 {
1220         struct sh_eth_private *mdp = netdev_priv(ndev);
1221         int rx_ringsize, tx_ringsize;
1222
1223         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1224          * card needs room to do 8 byte alignment, +2 so we can reserve
1225          * the first 2 bytes, and +16 gets room for the status word from the
1226          * card.
1227          */
1228         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1229                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1230         if (mdp->cd->rpadir)
1231                 mdp->rx_buf_sz += NET_IP_ALIGN;
1232
1233         /* Allocate RX and TX skb rings */
1234         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1235                                  GFP_KERNEL);
1236         if (!mdp->rx_skbuff)
1237                 return -ENOMEM;
1238
1239         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1240                                  GFP_KERNEL);
1241         if (!mdp->tx_skbuff)
1242                 goto ring_free;
1243
1244         /* Allocate all Rx descriptors. */
1245         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1246         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1247                                           GFP_KERNEL);
1248         if (!mdp->rx_ring)
1249                 goto ring_free;
1250
1251         mdp->dirty_rx = 0;
1252
1253         /* Allocate all Tx descriptors. */
1254         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1255         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1256                                           GFP_KERNEL);
1257         if (!mdp->tx_ring)
1258                 goto ring_free;
1259         return 0;
1260
1261 ring_free:
1262         /* Free Rx and Tx skb ring buffer and DMA buffer */
1263         sh_eth_ring_free(ndev);
1264
1265         return -ENOMEM;
1266 }
1267
1268 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1269 {
1270         int ret = 0;
1271         struct sh_eth_private *mdp = netdev_priv(ndev);
1272         u32 val;
1273
1274         /* Soft Reset */
1275         ret = sh_eth_reset(ndev);
1276         if (ret)
1277                 return ret;
1278
1279         if (mdp->cd->rmiimode)
1280                 sh_eth_write(ndev, 0x1, RMIIMODE);
1281
1282         /* Descriptor format */
1283         sh_eth_ring_format(ndev);
1284         if (mdp->cd->rpadir)
1285                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1286
1287         /* all sh_eth int mask */
1288         sh_eth_write(ndev, 0, EESIPR);
1289
1290 #if defined(__LITTLE_ENDIAN)
1291         if (mdp->cd->hw_swap)
1292                 sh_eth_write(ndev, EDMR_EL, EDMR);
1293         else
1294 #endif
1295                 sh_eth_write(ndev, 0, EDMR);
1296
1297         /* FIFO size set */
1298         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1299         sh_eth_write(ndev, 0, TFTR);
1300
1301         /* Frame recv control (enable multiple-packets per rx irq) */
1302         sh_eth_write(ndev, RMCR_RNC, RMCR);
1303
1304         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1305
1306         if (mdp->cd->bculr)
1307                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1308
1309         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1310
1311         if (!mdp->cd->no_trimd)
1312                 sh_eth_write(ndev, 0, TRIMD);
1313
1314         /* Recv frame limit set register */
1315         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1316                      RFLR);
1317
1318         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1319         if (start) {
1320                 mdp->irq_enabled = true;
1321                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1322         }
1323
1324         /* PAUSE Prohibition */
1325         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1326                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1327
1328         sh_eth_write(ndev, val, ECMR);
1329
1330         if (mdp->cd->set_rate)
1331                 mdp->cd->set_rate(ndev);
1332
1333         /* E-MAC Status Register clear */
1334         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1335
1336         /* E-MAC Interrupt Enable register */
1337         if (start)
1338                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1339
1340         /* Set MAC address */
1341         update_mac_address(ndev);
1342
1343         /* mask reset */
1344         if (mdp->cd->apr)
1345                 sh_eth_write(ndev, APR_AP, APR);
1346         if (mdp->cd->mpr)
1347                 sh_eth_write(ndev, MPR_MP, MPR);
1348         if (mdp->cd->tpauser)
1349                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1350
1351         if (start) {
1352                 /* Setting the Rx mode will start the Rx process. */
1353                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1354
1355                 netif_start_queue(ndev);
1356         }
1357
1358         return ret;
1359 }
1360
1361 static void sh_eth_dev_exit(struct net_device *ndev)
1362 {
1363         struct sh_eth_private *mdp = netdev_priv(ndev);
1364         int i;
1365
1366         /* Deactivate all TX descriptors, so DMA should stop at next
1367          * packet boundary if it's currently running
1368          */
1369         for (i = 0; i < mdp->num_tx_ring; i++)
1370                 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1371
1372         /* Disable TX FIFO egress to MAC */
1373         sh_eth_rcv_snd_disable(ndev);
1374
1375         /* Stop RX DMA at next packet boundary */
1376         sh_eth_write(ndev, 0, EDRRR);
1377
1378         /* Aside from TX DMA, we can't tell when the hardware is
1379          * really stopped, so we need to reset to make sure.
1380          * Before doing that, wait for long enough to *probably*
1381          * finish transmitting the last packet and poll stats.
1382          */
1383         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1384         sh_eth_get_stats(ndev);
1385         sh_eth_reset(ndev);
1386
1387         /* Set MAC address again */
1388         update_mac_address(ndev);
1389 }
1390
1391 /* free Tx skb function */
1392 static int sh_eth_txfree(struct net_device *ndev)
1393 {
1394         struct sh_eth_private *mdp = netdev_priv(ndev);
1395         struct sh_eth_txdesc *txdesc;
1396         int free_num = 0;
1397         int entry = 0;
1398
1399         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1400                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1401                 txdesc = &mdp->tx_ring[entry];
1402                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1403                         break;
1404                 /* TACT bit must be checked before all the following reads */
1405                 dma_rmb();
1406                 netif_info(mdp, tx_done, ndev,
1407                            "tx entry %d status 0x%08x\n",
1408                            entry, edmac_to_cpu(mdp, txdesc->status));
1409                 /* Free the original skb. */
1410                 if (mdp->tx_skbuff[entry]) {
1411                         dma_unmap_single(&ndev->dev, txdesc->addr,
1412                                          txdesc->buffer_length, DMA_TO_DEVICE);
1413                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1414                         mdp->tx_skbuff[entry] = NULL;
1415                         free_num++;
1416                 }
1417                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1418                 if (entry >= mdp->num_tx_ring - 1)
1419                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1420
1421                 ndev->stats.tx_packets++;
1422                 ndev->stats.tx_bytes += txdesc->buffer_length;
1423         }
1424         return free_num;
1425 }
1426
1427 /* Packet receive function */
1428 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1429 {
1430         struct sh_eth_private *mdp = netdev_priv(ndev);
1431         struct sh_eth_rxdesc *rxdesc;
1432
1433         int entry = mdp->cur_rx % mdp->num_rx_ring;
1434         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1435         int limit;
1436         struct sk_buff *skb;
1437         u16 pkt_len = 0;
1438         u32 desc_status;
1439         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1440         dma_addr_t dma_addr;
1441
1442         boguscnt = min(boguscnt, *quota);
1443         limit = boguscnt;
1444         rxdesc = &mdp->rx_ring[entry];
1445         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1446                 /* RACT bit must be checked before all the following reads */
1447                 dma_rmb();
1448                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1449                 pkt_len = rxdesc->frame_length;
1450
1451                 if (--boguscnt < 0)
1452                         break;
1453
1454                 netif_info(mdp, rx_status, ndev,
1455                            "rx entry %d status 0x%08x len %d\n",
1456                            entry, desc_status, pkt_len);
1457
1458                 if (!(desc_status & RDFEND))
1459                         ndev->stats.rx_length_errors++;
1460
1461                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1462                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1463                  * bit 0. However, in case of the R8A7740 and R7S72100
1464                  * the RFS bits are from bit 25 to bit 16. So, the
1465                  * driver needs right shifting by 16.
1466                  */
1467                 if (mdp->cd->shift_rd0)
1468                         desc_status >>= 16;
1469
1470                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1471                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1472                         ndev->stats.rx_errors++;
1473                         if (desc_status & RD_RFS1)
1474                                 ndev->stats.rx_crc_errors++;
1475                         if (desc_status & RD_RFS2)
1476                                 ndev->stats.rx_frame_errors++;
1477                         if (desc_status & RD_RFS3)
1478                                 ndev->stats.rx_length_errors++;
1479                         if (desc_status & RD_RFS4)
1480                                 ndev->stats.rx_length_errors++;
1481                         if (desc_status & RD_RFS6)
1482                                 ndev->stats.rx_missed_errors++;
1483                         if (desc_status & RD_RFS10)
1484                                 ndev->stats.rx_over_errors++;
1485                 } else {
1486                         if (!mdp->cd->hw_swap)
1487                                 sh_eth_soft_swap(
1488                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1489                                         pkt_len + 2);
1490                         skb = mdp->rx_skbuff[entry];
1491                         mdp->rx_skbuff[entry] = NULL;
1492                         if (mdp->cd->rpadir)
1493                                 skb_reserve(skb, NET_IP_ALIGN);
1494                         dma_unmap_single(&ndev->dev, rxdesc->addr,
1495                                          ALIGN(mdp->rx_buf_sz, 32),
1496                                          DMA_FROM_DEVICE);
1497                         skb_put(skb, pkt_len);
1498                         skb->protocol = eth_type_trans(skb, ndev);
1499                         netif_receive_skb(skb);
1500                         ndev->stats.rx_packets++;
1501                         ndev->stats.rx_bytes += pkt_len;
1502                         if (desc_status & RD_RFS8)
1503                                 ndev->stats.multicast++;
1504                 }
1505                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1506                 rxdesc = &mdp->rx_ring[entry];
1507         }
1508
1509         /* Refill the Rx ring buffers. */
1510         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1511                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1512                 rxdesc = &mdp->rx_ring[entry];
1513                 /* The size of the buffer is 32 byte boundary. */
1514                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1515
1516                 if (mdp->rx_skbuff[entry] == NULL) {
1517                         skb = netdev_alloc_skb(ndev, skbuff_size);
1518                         if (skb == NULL)
1519                                 break;  /* Better luck next round. */
1520                         sh_eth_set_receive_align(skb);
1521                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1522                                                   rxdesc->buffer_length,
1523                                                   DMA_FROM_DEVICE);
1524                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1525                                 kfree_skb(skb);
1526                                 break;
1527                         }
1528                         mdp->rx_skbuff[entry] = skb;
1529
1530                         skb_checksum_none_assert(skb);
1531                         rxdesc->addr = dma_addr;
1532                 }
1533                 dma_wmb(); /* RACT bit must be set after all the above writes */
1534                 if (entry >= mdp->num_rx_ring - 1)
1535                         rxdesc->status |=
1536                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1537                 else
1538                         rxdesc->status |=
1539                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1540         }
1541
1542         /* Restart Rx engine if stopped. */
1543         /* If we don't need to check status, don't. -KDU */
1544         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1545                 /* fix the values for the next receiving if RDE is set */
1546                 if (intr_status & EESR_RDE &&
1547                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1548                         u32 count = (sh_eth_read(ndev, RDFAR) -
1549                                      sh_eth_read(ndev, RDLAR)) >> 4;
1550
1551                         mdp->cur_rx = count;
1552                         mdp->dirty_rx = count;
1553                 }
1554                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1555         }
1556
1557         *quota -= limit - boguscnt - 1;
1558
1559         return *quota <= 0;
1560 }
1561
1562 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1563 {
1564         /* disable tx and rx */
1565         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1566                 ~(ECMR_RE | ECMR_TE), ECMR);
1567 }
1568
1569 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1570 {
1571         /* enable tx and rx */
1572         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1573                 (ECMR_RE | ECMR_TE), ECMR);
1574 }
1575
1576 /* error control function */
1577 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1578 {
1579         struct sh_eth_private *mdp = netdev_priv(ndev);
1580         u32 felic_stat;
1581         u32 link_stat;
1582         u32 mask;
1583
1584         if (intr_status & EESR_ECI) {
1585                 felic_stat = sh_eth_read(ndev, ECSR);
1586                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1587                 if (felic_stat & ECSR_ICD)
1588                         ndev->stats.tx_carrier_errors++;
1589                 if (felic_stat & ECSR_LCHNG) {
1590                         /* Link Changed */
1591                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1592                                 goto ignore_link;
1593                         } else {
1594                                 link_stat = (sh_eth_read(ndev, PSR));
1595                                 if (mdp->ether_link_active_low)
1596                                         link_stat = ~link_stat;
1597                         }
1598                         if (!(link_stat & PHY_ST_LINK)) {
1599                                 sh_eth_rcv_snd_disable(ndev);
1600                         } else {
1601                                 /* Link Up */
1602                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1603                                                    ~DMAC_M_ECI, EESIPR);
1604                                 /* clear int */
1605                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1606                                              ECSR);
1607                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1608                                                    DMAC_M_ECI, EESIPR);
1609                                 /* enable tx and rx */
1610                                 sh_eth_rcv_snd_enable(ndev);
1611                         }
1612                 }
1613         }
1614
1615 ignore_link:
1616         if (intr_status & EESR_TWB) {
1617                 /* Unused write back interrupt */
1618                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1619                         ndev->stats.tx_aborted_errors++;
1620                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1621                 }
1622         }
1623
1624         if (intr_status & EESR_RABT) {
1625                 /* Receive Abort int */
1626                 if (intr_status & EESR_RFRMER) {
1627                         /* Receive Frame Overflow int */
1628                         ndev->stats.rx_frame_errors++;
1629                 }
1630         }
1631
1632         if (intr_status & EESR_TDE) {
1633                 /* Transmit Descriptor Empty int */
1634                 ndev->stats.tx_fifo_errors++;
1635                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1636         }
1637
1638         if (intr_status & EESR_TFE) {
1639                 /* FIFO under flow */
1640                 ndev->stats.tx_fifo_errors++;
1641                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1642         }
1643
1644         if (intr_status & EESR_RDE) {
1645                 /* Receive Descriptor Empty int */
1646                 ndev->stats.rx_over_errors++;
1647         }
1648
1649         if (intr_status & EESR_RFE) {
1650                 /* Receive FIFO Overflow int */
1651                 ndev->stats.rx_fifo_errors++;
1652         }
1653
1654         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1655                 /* Address Error */
1656                 ndev->stats.tx_fifo_errors++;
1657                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1658         }
1659
1660         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1661         if (mdp->cd->no_ade)
1662                 mask &= ~EESR_ADE;
1663         if (intr_status & mask) {
1664                 /* Tx error */
1665                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1666
1667                 /* dmesg */
1668                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1669                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1670                            (u32)ndev->state, edtrr);
1671                 /* dirty buffer free */
1672                 sh_eth_txfree(ndev);
1673
1674                 /* SH7712 BUG */
1675                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1676                         /* tx dma start */
1677                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1678                 }
1679                 /* wakeup */
1680                 netif_wake_queue(ndev);
1681         }
1682 }
1683
1684 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1685 {
1686         struct net_device *ndev = netdev;
1687         struct sh_eth_private *mdp = netdev_priv(ndev);
1688         struct sh_eth_cpu_data *cd = mdp->cd;
1689         irqreturn_t ret = IRQ_NONE;
1690         u32 intr_status, intr_enable;
1691
1692         spin_lock(&mdp->lock);
1693
1694         /* Get interrupt status */
1695         intr_status = sh_eth_read(ndev, EESR);
1696         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1697          * enabled since it's the one that  comes thru regardless of the mask,
1698          * and we need to fully handle it in sh_eth_error() in order to quench
1699          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1700          */
1701         intr_enable = sh_eth_read(ndev, EESIPR);
1702         intr_status &= intr_enable | DMAC_M_ECI;
1703         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1704                 ret = IRQ_HANDLED;
1705         else
1706                 goto out;
1707
1708         if (!likely(mdp->irq_enabled)) {
1709                 sh_eth_write(ndev, 0, EESIPR);
1710                 goto out;
1711         }
1712
1713         if (intr_status & EESR_RX_CHECK) {
1714                 if (napi_schedule_prep(&mdp->napi)) {
1715                         /* Mask Rx interrupts */
1716                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1717                                      EESIPR);
1718                         __napi_schedule(&mdp->napi);
1719                 } else {
1720                         netdev_warn(ndev,
1721                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1722                                     intr_status, intr_enable);
1723                 }
1724         }
1725
1726         /* Tx Check */
1727         if (intr_status & cd->tx_check) {
1728                 /* Clear Tx interrupts */
1729                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1730
1731                 sh_eth_txfree(ndev);
1732                 netif_wake_queue(ndev);
1733         }
1734
1735         if (intr_status & cd->eesr_err_check) {
1736                 /* Clear error interrupts */
1737                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1738
1739                 sh_eth_error(ndev, intr_status);
1740         }
1741
1742 out:
1743         spin_unlock(&mdp->lock);
1744
1745         return ret;
1746 }
1747
1748 static int sh_eth_poll(struct napi_struct *napi, int budget)
1749 {
1750         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1751                                                   napi);
1752         struct net_device *ndev = napi->dev;
1753         int quota = budget;
1754         u32 intr_status;
1755
1756         for (;;) {
1757                 intr_status = sh_eth_read(ndev, EESR);
1758                 if (!(intr_status & EESR_RX_CHECK))
1759                         break;
1760                 /* Clear Rx interrupts */
1761                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1762
1763                 if (sh_eth_rx(ndev, intr_status, &quota))
1764                         goto out;
1765         }
1766
1767         napi_complete(napi);
1768
1769         /* Reenable Rx interrupts */
1770         if (mdp->irq_enabled)
1771                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1772 out:
1773         return budget - quota;
1774 }
1775
1776 /* PHY state control function */
1777 static void sh_eth_adjust_link(struct net_device *ndev)
1778 {
1779         struct sh_eth_private *mdp = netdev_priv(ndev);
1780         struct phy_device *phydev = mdp->phydev;
1781         int new_state = 0;
1782
1783         if (phydev->link) {
1784                 if (phydev->duplex != mdp->duplex) {
1785                         new_state = 1;
1786                         mdp->duplex = phydev->duplex;
1787                         if (mdp->cd->set_duplex)
1788                                 mdp->cd->set_duplex(ndev);
1789                 }
1790
1791                 if (phydev->speed != mdp->speed) {
1792                         new_state = 1;
1793                         mdp->speed = phydev->speed;
1794                         if (mdp->cd->set_rate)
1795                                 mdp->cd->set_rate(ndev);
1796                 }
1797                 if (!mdp->link) {
1798                         sh_eth_write(ndev,
1799                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1800                                      ECMR);
1801                         new_state = 1;
1802                         mdp->link = phydev->link;
1803                         if (mdp->cd->no_psr || mdp->no_ether_link)
1804                                 sh_eth_rcv_snd_enable(ndev);
1805                 }
1806         } else if (mdp->link) {
1807                 new_state = 1;
1808                 mdp->link = 0;
1809                 mdp->speed = 0;
1810                 mdp->duplex = -1;
1811                 if (mdp->cd->no_psr || mdp->no_ether_link)
1812                         sh_eth_rcv_snd_disable(ndev);
1813         }
1814
1815         if (new_state && netif_msg_link(mdp))
1816                 phy_print_status(phydev);
1817 }
1818
1819 /* PHY init function */
1820 static int sh_eth_phy_init(struct net_device *ndev)
1821 {
1822         struct device_node *np = ndev->dev.parent->of_node;
1823         struct sh_eth_private *mdp = netdev_priv(ndev);
1824         struct phy_device *phydev = NULL;
1825
1826         mdp->link = 0;
1827         mdp->speed = 0;
1828         mdp->duplex = -1;
1829
1830         /* Try connect to PHY */
1831         if (np) {
1832                 struct device_node *pn;
1833
1834                 pn = of_parse_phandle(np, "phy-handle", 0);
1835                 phydev = of_phy_connect(ndev, pn,
1836                                         sh_eth_adjust_link, 0,
1837                                         mdp->phy_interface);
1838
1839                 if (!phydev)
1840                         phydev = ERR_PTR(-ENOENT);
1841         } else {
1842                 char phy_id[MII_BUS_ID_SIZE + 3];
1843
1844                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1845                          mdp->mii_bus->id, mdp->phy_id);
1846
1847                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1848                                      mdp->phy_interface);
1849         }
1850
1851         if (IS_ERR(phydev)) {
1852                 netdev_err(ndev, "failed to connect PHY\n");
1853                 return PTR_ERR(phydev);
1854         }
1855
1856         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1857                     phydev->addr, phydev->irq, phydev->drv->name);
1858
1859         mdp->phydev = phydev;
1860
1861         return 0;
1862 }
1863
1864 /* PHY control start function */
1865 static int sh_eth_phy_start(struct net_device *ndev)
1866 {
1867         struct sh_eth_private *mdp = netdev_priv(ndev);
1868         int ret;
1869
1870         ret = sh_eth_phy_init(ndev);
1871         if (ret)
1872                 return ret;
1873
1874         phy_start(mdp->phydev);
1875
1876         return 0;
1877 }
1878
1879 static int sh_eth_get_settings(struct net_device *ndev,
1880                                struct ethtool_cmd *ecmd)
1881 {
1882         struct sh_eth_private *mdp = netdev_priv(ndev);
1883         unsigned long flags;
1884         int ret;
1885
1886         if (!mdp->phydev)
1887                 return -ENODEV;
1888
1889         spin_lock_irqsave(&mdp->lock, flags);
1890         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1891         spin_unlock_irqrestore(&mdp->lock, flags);
1892
1893         return ret;
1894 }
1895
1896 static int sh_eth_set_settings(struct net_device *ndev,
1897                                struct ethtool_cmd *ecmd)
1898 {
1899         struct sh_eth_private *mdp = netdev_priv(ndev);
1900         unsigned long flags;
1901         int ret;
1902
1903         if (!mdp->phydev)
1904                 return -ENODEV;
1905
1906         spin_lock_irqsave(&mdp->lock, flags);
1907
1908         /* disable tx and rx */
1909         sh_eth_rcv_snd_disable(ndev);
1910
1911         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1912         if (ret)
1913                 goto error_exit;
1914
1915         if (ecmd->duplex == DUPLEX_FULL)
1916                 mdp->duplex = 1;
1917         else
1918                 mdp->duplex = 0;
1919
1920         if (mdp->cd->set_duplex)
1921                 mdp->cd->set_duplex(ndev);
1922
1923 error_exit:
1924         mdelay(1);
1925
1926         /* enable tx and rx */
1927         sh_eth_rcv_snd_enable(ndev);
1928
1929         spin_unlock_irqrestore(&mdp->lock, flags);
1930
1931         return ret;
1932 }
1933
1934 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1935  * version must be bumped as well.  Just adding registers up to that
1936  * limit is fine, as long as the existing register indices don't
1937  * change.
1938  */
1939 #define SH_ETH_REG_DUMP_VERSION         1
1940 #define SH_ETH_REG_DUMP_MAX_REGS        256
1941
1942 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1943 {
1944         struct sh_eth_private *mdp = netdev_priv(ndev);
1945         struct sh_eth_cpu_data *cd = mdp->cd;
1946         u32 *valid_map;
1947         size_t len;
1948
1949         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1950
1951         /* Dump starts with a bitmap that tells ethtool which
1952          * registers are defined for this chip.
1953          */
1954         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1955         if (buf) {
1956                 valid_map = buf;
1957                 buf += len;
1958         } else {
1959                 valid_map = NULL;
1960         }
1961
1962         /* Add a register to the dump, if it has a defined offset.
1963          * This automatically skips most undefined registers, but for
1964          * some it is also necessary to check a capability flag in
1965          * struct sh_eth_cpu_data.
1966          */
1967 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1968 #define add_reg_from(reg, read_expr) do {                               \
1969                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1970                         if (buf) {                                      \
1971                                 mark_reg_valid(reg);                    \
1972                                 *buf++ = read_expr;                     \
1973                         }                                               \
1974                         ++len;                                          \
1975                 }                                                       \
1976         } while (0)
1977 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1978 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1979
1980         add_reg(EDSR);
1981         add_reg(EDMR);
1982         add_reg(EDTRR);
1983         add_reg(EDRRR);
1984         add_reg(EESR);
1985         add_reg(EESIPR);
1986         add_reg(TDLAR);
1987         add_reg(TDFAR);
1988         add_reg(TDFXR);
1989         add_reg(TDFFR);
1990         add_reg(RDLAR);
1991         add_reg(RDFAR);
1992         add_reg(RDFXR);
1993         add_reg(RDFFR);
1994         add_reg(TRSCER);
1995         add_reg(RMFCR);
1996         add_reg(TFTR);
1997         add_reg(FDR);
1998         add_reg(RMCR);
1999         add_reg(TFUCR);
2000         add_reg(RFOCR);
2001         if (cd->rmiimode)
2002                 add_reg(RMIIMODE);
2003         add_reg(FCFTR);
2004         if (cd->rpadir)
2005                 add_reg(RPADIR);
2006         if (!cd->no_trimd)
2007                 add_reg(TRIMD);
2008         add_reg(ECMR);
2009         add_reg(ECSR);
2010         add_reg(ECSIPR);
2011         add_reg(PIR);
2012         if (!cd->no_psr)
2013                 add_reg(PSR);
2014         add_reg(RDMLR);
2015         add_reg(RFLR);
2016         add_reg(IPGR);
2017         if (cd->apr)
2018                 add_reg(APR);
2019         if (cd->mpr)
2020                 add_reg(MPR);
2021         add_reg(RFCR);
2022         add_reg(RFCF);
2023         if (cd->tpauser)
2024                 add_reg(TPAUSER);
2025         add_reg(TPAUSECR);
2026         add_reg(GECMR);
2027         if (cd->bculr)
2028                 add_reg(BCULR);
2029         add_reg(MAHR);
2030         add_reg(MALR);
2031         add_reg(TROCR);
2032         add_reg(CDCR);
2033         add_reg(LCCR);
2034         add_reg(CNDCR);
2035         add_reg(CEFCR);
2036         add_reg(FRECR);
2037         add_reg(TSFRCR);
2038         add_reg(TLFRCR);
2039         add_reg(CERCR);
2040         add_reg(CEECR);
2041         add_reg(MAFCR);
2042         if (cd->rtrate)
2043                 add_reg(RTRATE);
2044         if (cd->hw_crc)
2045                 add_reg(CSMR);
2046         if (cd->select_mii)
2047                 add_reg(RMII_MII);
2048         add_reg(ARSTR);
2049         if (cd->tsu) {
2050                 add_tsu_reg(TSU_CTRST);
2051                 add_tsu_reg(TSU_FWEN0);
2052                 add_tsu_reg(TSU_FWEN1);
2053                 add_tsu_reg(TSU_FCM);
2054                 add_tsu_reg(TSU_BSYSL0);
2055                 add_tsu_reg(TSU_BSYSL1);
2056                 add_tsu_reg(TSU_PRISL0);
2057                 add_tsu_reg(TSU_PRISL1);
2058                 add_tsu_reg(TSU_FWSL0);
2059                 add_tsu_reg(TSU_FWSL1);
2060                 add_tsu_reg(TSU_FWSLC);
2061                 add_tsu_reg(TSU_QTAG0);
2062                 add_tsu_reg(TSU_QTAG1);
2063                 add_tsu_reg(TSU_QTAGM0);
2064                 add_tsu_reg(TSU_QTAGM1);
2065                 add_tsu_reg(TSU_FWSR);
2066                 add_tsu_reg(TSU_FWINMK);
2067                 add_tsu_reg(TSU_ADQT0);
2068                 add_tsu_reg(TSU_ADQT1);
2069                 add_tsu_reg(TSU_VTAG0);
2070                 add_tsu_reg(TSU_VTAG1);
2071                 add_tsu_reg(TSU_ADSBSY);
2072                 add_tsu_reg(TSU_TEN);
2073                 add_tsu_reg(TSU_POST1);
2074                 add_tsu_reg(TSU_POST2);
2075                 add_tsu_reg(TSU_POST3);
2076                 add_tsu_reg(TSU_POST4);
2077                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2078                         /* This is the start of a table, not just a single
2079                          * register.
2080                          */
2081                         if (buf) {
2082                                 unsigned int i;
2083
2084                                 mark_reg_valid(TSU_ADRH0);
2085                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2086                                         *buf++ = ioread32(
2087                                                 mdp->tsu_addr +
2088                                                 mdp->reg_offset[TSU_ADRH0] +
2089                                                 i * 4);
2090                         }
2091                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2092                 }
2093         }
2094
2095 #undef mark_reg_valid
2096 #undef add_reg_from
2097 #undef add_reg
2098 #undef add_tsu_reg
2099
2100         return len * 4;
2101 }
2102
2103 static int sh_eth_get_regs_len(struct net_device *ndev)
2104 {
2105         return __sh_eth_get_regs(ndev, NULL);
2106 }
2107
2108 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2109                             void *buf)
2110 {
2111         struct sh_eth_private *mdp = netdev_priv(ndev);
2112
2113         regs->version = SH_ETH_REG_DUMP_VERSION;
2114
2115         pm_runtime_get_sync(&mdp->pdev->dev);
2116         __sh_eth_get_regs(ndev, buf);
2117         pm_runtime_put_sync(&mdp->pdev->dev);
2118 }
2119
2120 static int sh_eth_nway_reset(struct net_device *ndev)
2121 {
2122         struct sh_eth_private *mdp = netdev_priv(ndev);
2123         unsigned long flags;
2124         int ret;
2125
2126         if (!mdp->phydev)
2127                 return -ENODEV;
2128
2129         spin_lock_irqsave(&mdp->lock, flags);
2130         ret = phy_start_aneg(mdp->phydev);
2131         spin_unlock_irqrestore(&mdp->lock, flags);
2132
2133         return ret;
2134 }
2135
2136 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2137 {
2138         struct sh_eth_private *mdp = netdev_priv(ndev);
2139         return mdp->msg_enable;
2140 }
2141
2142 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2143 {
2144         struct sh_eth_private *mdp = netdev_priv(ndev);
2145         mdp->msg_enable = value;
2146 }
2147
2148 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2149         "rx_current", "tx_current",
2150         "rx_dirty", "tx_dirty",
2151 };
2152 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2153
2154 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2155 {
2156         switch (sset) {
2157         case ETH_SS_STATS:
2158                 return SH_ETH_STATS_LEN;
2159         default:
2160                 return -EOPNOTSUPP;
2161         }
2162 }
2163
2164 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2165                                      struct ethtool_stats *stats, u64 *data)
2166 {
2167         struct sh_eth_private *mdp = netdev_priv(ndev);
2168         int i = 0;
2169
2170         /* device-specific stats */
2171         data[i++] = mdp->cur_rx;
2172         data[i++] = mdp->cur_tx;
2173         data[i++] = mdp->dirty_rx;
2174         data[i++] = mdp->dirty_tx;
2175 }
2176
2177 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2178 {
2179         switch (stringset) {
2180         case ETH_SS_STATS:
2181                 memcpy(data, *sh_eth_gstrings_stats,
2182                        sizeof(sh_eth_gstrings_stats));
2183                 break;
2184         }
2185 }
2186
2187 static void sh_eth_get_ringparam(struct net_device *ndev,
2188                                  struct ethtool_ringparam *ring)
2189 {
2190         struct sh_eth_private *mdp = netdev_priv(ndev);
2191
2192         ring->rx_max_pending = RX_RING_MAX;
2193         ring->tx_max_pending = TX_RING_MAX;
2194         ring->rx_pending = mdp->num_rx_ring;
2195         ring->tx_pending = mdp->num_tx_ring;
2196 }
2197
2198 static int sh_eth_set_ringparam(struct net_device *ndev,
2199                                 struct ethtool_ringparam *ring)
2200 {
2201         struct sh_eth_private *mdp = netdev_priv(ndev);
2202         int ret;
2203
2204         if (ring->tx_pending > TX_RING_MAX ||
2205             ring->rx_pending > RX_RING_MAX ||
2206             ring->tx_pending < TX_RING_MIN ||
2207             ring->rx_pending < RX_RING_MIN)
2208                 return -EINVAL;
2209         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2210                 return -EINVAL;
2211
2212         if (netif_running(ndev)) {
2213                 netif_device_detach(ndev);
2214                 netif_tx_disable(ndev);
2215
2216                 /* Serialise with the interrupt handler and NAPI, then
2217                  * disable interrupts.  We have to clear the
2218                  * irq_enabled flag first to ensure that interrupts
2219                  * won't be re-enabled.
2220                  */
2221                 mdp->irq_enabled = false;
2222                 synchronize_irq(ndev->irq);
2223                 napi_synchronize(&mdp->napi);
2224                 sh_eth_write(ndev, 0x0000, EESIPR);
2225
2226                 sh_eth_dev_exit(ndev);
2227
2228                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2229                 sh_eth_ring_free(ndev);
2230         }
2231
2232         /* Set new parameters */
2233         mdp->num_rx_ring = ring->rx_pending;
2234         mdp->num_tx_ring = ring->tx_pending;
2235
2236         if (netif_running(ndev)) {
2237                 ret = sh_eth_ring_init(ndev);
2238                 if (ret < 0) {
2239                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2240                                    __func__);
2241                         return ret;
2242                 }
2243                 ret = sh_eth_dev_init(ndev, false);
2244                 if (ret < 0) {
2245                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2246                                    __func__);
2247                         return ret;
2248                 }
2249
2250                 mdp->irq_enabled = true;
2251                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2252                 /* Setting the Rx mode will start the Rx process. */
2253                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2254                 netif_device_attach(ndev);
2255         }
2256
2257         return 0;
2258 }
2259
2260 static const struct ethtool_ops sh_eth_ethtool_ops = {
2261         .get_settings   = sh_eth_get_settings,
2262         .set_settings   = sh_eth_set_settings,
2263         .get_regs_len   = sh_eth_get_regs_len,
2264         .get_regs       = sh_eth_get_regs,
2265         .nway_reset     = sh_eth_nway_reset,
2266         .get_msglevel   = sh_eth_get_msglevel,
2267         .set_msglevel   = sh_eth_set_msglevel,
2268         .get_link       = ethtool_op_get_link,
2269         .get_strings    = sh_eth_get_strings,
2270         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2271         .get_sset_count     = sh_eth_get_sset_count,
2272         .get_ringparam  = sh_eth_get_ringparam,
2273         .set_ringparam  = sh_eth_set_ringparam,
2274 };
2275
2276 /* network device open function */
2277 static int sh_eth_open(struct net_device *ndev)
2278 {
2279         int ret = 0;
2280         struct sh_eth_private *mdp = netdev_priv(ndev);
2281
2282         pm_runtime_get_sync(&mdp->pdev->dev);
2283
2284         napi_enable(&mdp->napi);
2285
2286         ret = request_irq(ndev->irq, sh_eth_interrupt,
2287                           mdp->cd->irq_flags, ndev->name, ndev);
2288         if (ret) {
2289                 netdev_err(ndev, "Can not assign IRQ number\n");
2290                 goto out_napi_off;
2291         }
2292
2293         /* Descriptor set */
2294         ret = sh_eth_ring_init(ndev);
2295         if (ret)
2296                 goto out_free_irq;
2297
2298         /* device init */
2299         ret = sh_eth_dev_init(ndev, true);
2300         if (ret)
2301                 goto out_free_irq;
2302
2303         /* PHY control start*/
2304         ret = sh_eth_phy_start(ndev);
2305         if (ret)
2306                 goto out_free_irq;
2307
2308         mdp->is_opened = 1;
2309
2310         return ret;
2311
2312 out_free_irq:
2313         free_irq(ndev->irq, ndev);
2314 out_napi_off:
2315         napi_disable(&mdp->napi);
2316         pm_runtime_put_sync(&mdp->pdev->dev);
2317         return ret;
2318 }
2319
2320 /* Timeout function */
2321 static void sh_eth_tx_timeout(struct net_device *ndev)
2322 {
2323         struct sh_eth_private *mdp = netdev_priv(ndev);
2324         struct sh_eth_rxdesc *rxdesc;
2325         int i;
2326
2327         netif_stop_queue(ndev);
2328
2329         netif_err(mdp, timer, ndev,
2330                   "transmit timed out, status %8.8x, resetting...\n",
2331                   sh_eth_read(ndev, EESR));
2332
2333         /* tx_errors count up */
2334         ndev->stats.tx_errors++;
2335
2336         /* Free all the skbuffs in the Rx queue. */
2337         for (i = 0; i < mdp->num_rx_ring; i++) {
2338                 rxdesc = &mdp->rx_ring[i];
2339                 rxdesc->status = 0;
2340                 rxdesc->addr = 0xBADF00D0;
2341                 dev_kfree_skb(mdp->rx_skbuff[i]);
2342                 mdp->rx_skbuff[i] = NULL;
2343         }
2344         for (i = 0; i < mdp->num_tx_ring; i++) {
2345                 dev_kfree_skb(mdp->tx_skbuff[i]);
2346                 mdp->tx_skbuff[i] = NULL;
2347         }
2348
2349         /* device init */
2350         sh_eth_dev_init(ndev, true);
2351 }
2352
2353 /* Packet transmit function */
2354 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2355 {
2356         struct sh_eth_private *mdp = netdev_priv(ndev);
2357         struct sh_eth_txdesc *txdesc;
2358         u32 entry;
2359         unsigned long flags;
2360
2361         spin_lock_irqsave(&mdp->lock, flags);
2362         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2363                 if (!sh_eth_txfree(ndev)) {
2364                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2365                         netif_stop_queue(ndev);
2366                         spin_unlock_irqrestore(&mdp->lock, flags);
2367                         return NETDEV_TX_BUSY;
2368                 }
2369         }
2370         spin_unlock_irqrestore(&mdp->lock, flags);
2371
2372         if (skb_put_padto(skb, ETH_ZLEN))
2373                 return NETDEV_TX_OK;
2374
2375         entry = mdp->cur_tx % mdp->num_tx_ring;
2376         mdp->tx_skbuff[entry] = skb;
2377         txdesc = &mdp->tx_ring[entry];
2378         /* soft swap. */
2379         if (!mdp->cd->hw_swap)
2380                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2381                                  skb->len + 2);
2382         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2383                                       DMA_TO_DEVICE);
2384         if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2385                 kfree_skb(skb);
2386                 return NETDEV_TX_OK;
2387         }
2388         txdesc->buffer_length = skb->len;
2389
2390         dma_wmb(); /* TACT bit must be set after all the above writes */
2391         if (entry >= mdp->num_tx_ring - 1)
2392                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2393         else
2394                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2395
2396         mdp->cur_tx++;
2397
2398         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2399                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2400
2401         return NETDEV_TX_OK;
2402 }
2403
2404 /* The statistics registers have write-clear behaviour, which means we
2405  * will lose any increment between the read and write.  We mitigate
2406  * this by only clearing when we read a non-zero value, so we will
2407  * never falsely report a total of zero.
2408  */
2409 static void
2410 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2411 {
2412         u32 delta = sh_eth_read(ndev, reg);
2413
2414         if (delta) {
2415                 *stat += delta;
2416                 sh_eth_write(ndev, 0, reg);
2417         }
2418 }
2419
2420 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2421 {
2422         struct sh_eth_private *mdp = netdev_priv(ndev);
2423
2424         if (sh_eth_is_rz_fast_ether(mdp))
2425                 return &ndev->stats;
2426
2427         if (!mdp->is_opened)
2428                 return &ndev->stats;
2429
2430         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2431         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2432         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2433
2434         if (sh_eth_is_gether(mdp)) {
2435                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2436                                    CERCR);
2437                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2438                                    CEECR);
2439         } else {
2440                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2441                                    CNDCR);
2442         }
2443
2444         return &ndev->stats;
2445 }
2446
2447 /* device close function */
2448 static int sh_eth_close(struct net_device *ndev)
2449 {
2450         struct sh_eth_private *mdp = netdev_priv(ndev);
2451
2452         netif_stop_queue(ndev);
2453
2454         /* Serialise with the interrupt handler and NAPI, then disable
2455          * interrupts.  We have to clear the irq_enabled flag first to
2456          * ensure that interrupts won't be re-enabled.
2457          */
2458         mdp->irq_enabled = false;
2459         synchronize_irq(ndev->irq);
2460         napi_disable(&mdp->napi);
2461         sh_eth_write(ndev, 0x0000, EESIPR);
2462
2463         sh_eth_dev_exit(ndev);
2464
2465         /* PHY Disconnect */
2466         if (mdp->phydev) {
2467                 phy_stop(mdp->phydev);
2468                 phy_disconnect(mdp->phydev);
2469                 mdp->phydev = NULL;
2470         }
2471
2472         free_irq(ndev->irq, ndev);
2473
2474         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2475         sh_eth_ring_free(ndev);
2476
2477         pm_runtime_put_sync(&mdp->pdev->dev);
2478
2479         mdp->is_opened = 0;
2480
2481         return 0;
2482 }
2483
2484 /* ioctl to device function */
2485 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2486 {
2487         struct sh_eth_private *mdp = netdev_priv(ndev);
2488         struct phy_device *phydev = mdp->phydev;
2489
2490         if (!netif_running(ndev))
2491                 return -EINVAL;
2492
2493         if (!phydev)
2494                 return -ENODEV;
2495
2496         return phy_mii_ioctl(phydev, rq, cmd);
2497 }
2498
2499 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2500 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2501                                             int entry)
2502 {
2503         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2504 }
2505
2506 static u32 sh_eth_tsu_get_post_mask(int entry)
2507 {
2508         return 0x0f << (28 - ((entry % 8) * 4));
2509 }
2510
2511 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2512 {
2513         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2514 }
2515
2516 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2517                                              int entry)
2518 {
2519         struct sh_eth_private *mdp = netdev_priv(ndev);
2520         u32 tmp;
2521         void *reg_offset;
2522
2523         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2524         tmp = ioread32(reg_offset);
2525         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2526 }
2527
2528 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2529                                               int entry)
2530 {
2531         struct sh_eth_private *mdp = netdev_priv(ndev);
2532         u32 post_mask, ref_mask, tmp;
2533         void *reg_offset;
2534
2535         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2536         post_mask = sh_eth_tsu_get_post_mask(entry);
2537         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2538
2539         tmp = ioread32(reg_offset);
2540         iowrite32(tmp & ~post_mask, reg_offset);
2541
2542         /* If other port enables, the function returns "true" */
2543         return tmp & ref_mask;
2544 }
2545
2546 static int sh_eth_tsu_busy(struct net_device *ndev)
2547 {
2548         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2549         struct sh_eth_private *mdp = netdev_priv(ndev);
2550
2551         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2552                 udelay(10);
2553                 timeout--;
2554                 if (timeout <= 0) {
2555                         netdev_err(ndev, "%s: timeout\n", __func__);
2556                         return -ETIMEDOUT;
2557                 }
2558         }
2559
2560         return 0;
2561 }
2562
2563 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2564                                   const u8 *addr)
2565 {
2566         u32 val;
2567
2568         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2569         iowrite32(val, reg);
2570         if (sh_eth_tsu_busy(ndev) < 0)
2571                 return -EBUSY;
2572
2573         val = addr[4] << 8 | addr[5];
2574         iowrite32(val, reg + 4);
2575         if (sh_eth_tsu_busy(ndev) < 0)
2576                 return -EBUSY;
2577
2578         return 0;
2579 }
2580
2581 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2582 {
2583         u32 val;
2584
2585         val = ioread32(reg);
2586         addr[0] = (val >> 24) & 0xff;
2587         addr[1] = (val >> 16) & 0xff;
2588         addr[2] = (val >> 8) & 0xff;
2589         addr[3] = val & 0xff;
2590         val = ioread32(reg + 4);
2591         addr[4] = (val >> 8) & 0xff;
2592         addr[5] = val & 0xff;
2593 }
2594
2595
2596 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2597 {
2598         struct sh_eth_private *mdp = netdev_priv(ndev);
2599         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2600         int i;
2601         u8 c_addr[ETH_ALEN];
2602
2603         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2604                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2605                 if (ether_addr_equal(addr, c_addr))
2606                         return i;
2607         }
2608
2609         return -ENOENT;
2610 }
2611
2612 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2613 {
2614         u8 blank[ETH_ALEN];
2615         int entry;
2616
2617         memset(blank, 0, sizeof(blank));
2618         entry = sh_eth_tsu_find_entry(ndev, blank);
2619         return (entry < 0) ? -ENOMEM : entry;
2620 }
2621
2622 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2623                                               int entry)
2624 {
2625         struct sh_eth_private *mdp = netdev_priv(ndev);
2626         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2627         int ret;
2628         u8 blank[ETH_ALEN];
2629
2630         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2631                          ~(1 << (31 - entry)), TSU_TEN);
2632
2633         memset(blank, 0, sizeof(blank));
2634         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2635         if (ret < 0)
2636                 return ret;
2637         return 0;
2638 }
2639
2640 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2641 {
2642         struct sh_eth_private *mdp = netdev_priv(ndev);
2643         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2644         int i, ret;
2645
2646         if (!mdp->cd->tsu)
2647                 return 0;
2648
2649         i = sh_eth_tsu_find_entry(ndev, addr);
2650         if (i < 0) {
2651                 /* No entry found, create one */
2652                 i = sh_eth_tsu_find_empty(ndev);
2653                 if (i < 0)
2654                         return -ENOMEM;
2655                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2656                 if (ret < 0)
2657                         return ret;
2658
2659                 /* Enable the entry */
2660                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2661                                  (1 << (31 - i)), TSU_TEN);
2662         }
2663
2664         /* Entry found or created, enable POST */
2665         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2666
2667         return 0;
2668 }
2669
2670 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2671 {
2672         struct sh_eth_private *mdp = netdev_priv(ndev);
2673         int i, ret;
2674
2675         if (!mdp->cd->tsu)
2676                 return 0;
2677
2678         i = sh_eth_tsu_find_entry(ndev, addr);
2679         if (i) {
2680                 /* Entry found */
2681                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2682                         goto done;
2683
2684                 /* Disable the entry if both ports was disabled */
2685                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2686                 if (ret < 0)
2687                         return ret;
2688         }
2689 done:
2690         return 0;
2691 }
2692
2693 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2694 {
2695         struct sh_eth_private *mdp = netdev_priv(ndev);
2696         int i, ret;
2697
2698         if (!mdp->cd->tsu)
2699                 return 0;
2700
2701         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2702                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2703                         continue;
2704
2705                 /* Disable the entry if both ports was disabled */
2706                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2707                 if (ret < 0)
2708                         return ret;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2715 {
2716         struct sh_eth_private *mdp = netdev_priv(ndev);
2717         u8 addr[ETH_ALEN];
2718         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2719         int i;
2720
2721         if (!mdp->cd->tsu)
2722                 return;
2723
2724         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2725                 sh_eth_tsu_read_entry(reg_offset, addr);
2726                 if (is_multicast_ether_addr(addr))
2727                         sh_eth_tsu_del_entry(ndev, addr);
2728         }
2729 }
2730
2731 /* Update promiscuous flag and multicast filter */
2732 static void sh_eth_set_rx_mode(struct net_device *ndev)
2733 {
2734         struct sh_eth_private *mdp = netdev_priv(ndev);
2735         u32 ecmr_bits;
2736         int mcast_all = 0;
2737         unsigned long flags;
2738
2739         spin_lock_irqsave(&mdp->lock, flags);
2740         /* Initial condition is MCT = 1, PRM = 0.
2741          * Depending on ndev->flags, set PRM or clear MCT
2742          */
2743         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2744         if (mdp->cd->tsu)
2745                 ecmr_bits |= ECMR_MCT;
2746
2747         if (!(ndev->flags & IFF_MULTICAST)) {
2748                 sh_eth_tsu_purge_mcast(ndev);
2749                 mcast_all = 1;
2750         }
2751         if (ndev->flags & IFF_ALLMULTI) {
2752                 sh_eth_tsu_purge_mcast(ndev);
2753                 ecmr_bits &= ~ECMR_MCT;
2754                 mcast_all = 1;
2755         }
2756
2757         if (ndev->flags & IFF_PROMISC) {
2758                 sh_eth_tsu_purge_all(ndev);
2759                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2760         } else if (mdp->cd->tsu) {
2761                 struct netdev_hw_addr *ha;
2762                 netdev_for_each_mc_addr(ha, ndev) {
2763                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2764                                 continue;
2765
2766                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2767                                 if (!mcast_all) {
2768                                         sh_eth_tsu_purge_mcast(ndev);
2769                                         ecmr_bits &= ~ECMR_MCT;
2770                                         mcast_all = 1;
2771                                 }
2772                         }
2773                 }
2774         }
2775
2776         /* update the ethernet mode */
2777         sh_eth_write(ndev, ecmr_bits, ECMR);
2778
2779         spin_unlock_irqrestore(&mdp->lock, flags);
2780 }
2781
2782 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2783 {
2784         if (!mdp->port)
2785                 return TSU_VTAG0;
2786         else
2787                 return TSU_VTAG1;
2788 }
2789
2790 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2791                                   __be16 proto, u16 vid)
2792 {
2793         struct sh_eth_private *mdp = netdev_priv(ndev);
2794         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2795
2796         if (unlikely(!mdp->cd->tsu))
2797                 return -EPERM;
2798
2799         /* No filtering if vid = 0 */
2800         if (!vid)
2801                 return 0;
2802
2803         mdp->vlan_num_ids++;
2804
2805         /* The controller has one VLAN tag HW filter. So, if the filter is
2806          * already enabled, the driver disables it and the filte
2807          */
2808         if (mdp->vlan_num_ids > 1) {
2809                 /* disable VLAN filter */
2810                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2811                 return 0;
2812         }
2813
2814         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2815                          vtag_reg_index);
2816
2817         return 0;
2818 }
2819
2820 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2821                                    __be16 proto, u16 vid)
2822 {
2823         struct sh_eth_private *mdp = netdev_priv(ndev);
2824         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2825
2826         if (unlikely(!mdp->cd->tsu))
2827                 return -EPERM;
2828
2829         /* No filtering if vid = 0 */
2830         if (!vid)
2831                 return 0;
2832
2833         mdp->vlan_num_ids--;
2834         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2835
2836         return 0;
2837 }
2838
2839 /* SuperH's TSU register init function */
2840 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2841 {
2842         if (sh_eth_is_rz_fast_ether(mdp)) {
2843                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2844                 return;
2845         }
2846
2847         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2848         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2849         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2850         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2851         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2852         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2853         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2854         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2855         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2856         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2857         if (sh_eth_is_gether(mdp)) {
2858                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2859                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2860         } else {
2861                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2862                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2863         }
2864         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2865         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2866         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2867         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2868         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2869         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2870         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2871 }
2872
2873 /* MDIO bus release function */
2874 static int sh_mdio_release(struct sh_eth_private *mdp)
2875 {
2876         /* unregister mdio bus */
2877         mdiobus_unregister(mdp->mii_bus);
2878
2879         /* free bitbang info */
2880         free_mdio_bitbang(mdp->mii_bus);
2881
2882         return 0;
2883 }
2884
2885 /* MDIO bus init function */
2886 static int sh_mdio_init(struct sh_eth_private *mdp,
2887                         struct sh_eth_plat_data *pd)
2888 {
2889         int ret, i;
2890         struct bb_info *bitbang;
2891         struct platform_device *pdev = mdp->pdev;
2892         struct device *dev = &mdp->pdev->dev;
2893
2894         /* create bit control struct for PHY */
2895         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2896         if (!bitbang)
2897                 return -ENOMEM;
2898
2899         /* bitbang init */
2900         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2901         bitbang->set_gate = pd->set_mdio_gate;
2902         bitbang->mdi_msk = PIR_MDI;
2903         bitbang->mdo_msk = PIR_MDO;
2904         bitbang->mmd_msk = PIR_MMD;
2905         bitbang->mdc_msk = PIR_MDC;
2906         bitbang->ctrl.ops = &bb_ops;
2907
2908         /* MII controller setting */
2909         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2910         if (!mdp->mii_bus)
2911                 return -ENOMEM;
2912
2913         /* Hook up MII support for ethtool */
2914         mdp->mii_bus->name = "sh_mii";
2915         mdp->mii_bus->parent = dev;
2916         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2917                  pdev->name, pdev->id);
2918
2919         /* PHY IRQ */
2920         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2921                                                GFP_KERNEL);
2922         if (!mdp->mii_bus->irq) {
2923                 ret = -ENOMEM;
2924                 goto out_free_bus;
2925         }
2926
2927         /* register MDIO bus */
2928         if (dev->of_node) {
2929                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2930         } else {
2931                 for (i = 0; i < PHY_MAX_ADDR; i++)
2932                         mdp->mii_bus->irq[i] = PHY_POLL;
2933                 if (pd->phy_irq > 0)
2934                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2935
2936                 ret = mdiobus_register(mdp->mii_bus);
2937         }
2938
2939         if (ret)
2940                 goto out_free_bus;
2941
2942         return 0;
2943
2944 out_free_bus:
2945         free_mdio_bitbang(mdp->mii_bus);
2946         return ret;
2947 }
2948
2949 static const u16 *sh_eth_get_register_offset(int register_type)
2950 {
2951         const u16 *reg_offset = NULL;
2952
2953         switch (register_type) {
2954         case SH_ETH_REG_GIGABIT:
2955                 reg_offset = sh_eth_offset_gigabit;
2956                 break;
2957         case SH_ETH_REG_FAST_RZ:
2958                 reg_offset = sh_eth_offset_fast_rz;
2959                 break;
2960         case SH_ETH_REG_FAST_RCAR:
2961                 reg_offset = sh_eth_offset_fast_rcar;
2962                 break;
2963         case SH_ETH_REG_FAST_SH4:
2964                 reg_offset = sh_eth_offset_fast_sh4;
2965                 break;
2966         case SH_ETH_REG_FAST_SH3_SH2:
2967                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2968                 break;
2969         default:
2970                 break;
2971         }
2972
2973         return reg_offset;
2974 }
2975
2976 static const struct net_device_ops sh_eth_netdev_ops = {
2977         .ndo_open               = sh_eth_open,
2978         .ndo_stop               = sh_eth_close,
2979         .ndo_start_xmit         = sh_eth_start_xmit,
2980         .ndo_get_stats          = sh_eth_get_stats,
2981         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2982         .ndo_tx_timeout         = sh_eth_tx_timeout,
2983         .ndo_do_ioctl           = sh_eth_do_ioctl,
2984         .ndo_validate_addr      = eth_validate_addr,
2985         .ndo_set_mac_address    = eth_mac_addr,
2986         .ndo_change_mtu         = eth_change_mtu,
2987 };
2988
2989 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2990         .ndo_open               = sh_eth_open,
2991         .ndo_stop               = sh_eth_close,
2992         .ndo_start_xmit         = sh_eth_start_xmit,
2993         .ndo_get_stats          = sh_eth_get_stats,
2994         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2995         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2996         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2997         .ndo_tx_timeout         = sh_eth_tx_timeout,
2998         .ndo_do_ioctl           = sh_eth_do_ioctl,
2999         .ndo_validate_addr      = eth_validate_addr,
3000         .ndo_set_mac_address    = eth_mac_addr,
3001         .ndo_change_mtu         = eth_change_mtu,
3002 };
3003
3004 #ifdef CONFIG_OF
3005 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3006 {
3007         struct device_node *np = dev->of_node;
3008         struct sh_eth_plat_data *pdata;
3009         const char *mac_addr;
3010
3011         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3012         if (!pdata)
3013                 return NULL;
3014
3015         pdata->phy_interface = of_get_phy_mode(np);
3016
3017         mac_addr = of_get_mac_address(np);
3018         if (mac_addr)
3019                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3020
3021         pdata->no_ether_link =
3022                 of_property_read_bool(np, "renesas,no-ether-link");
3023         pdata->ether_link_active_low =
3024                 of_property_read_bool(np, "renesas,ether-link-active-low");
3025
3026         return pdata;
3027 }
3028
3029 static const struct of_device_id sh_eth_match_table[] = {
3030         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3031         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3032         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3033         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3034         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3035         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3036         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3037         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3038         { }
3039 };
3040 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3041 #else
3042 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3043 {
3044         return NULL;
3045 }
3046 #endif
3047
3048 static int sh_eth_drv_probe(struct platform_device *pdev)
3049 {
3050         int ret, devno = 0;
3051         struct resource *res;
3052         struct net_device *ndev = NULL;
3053         struct sh_eth_private *mdp = NULL;
3054         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3055         const struct platform_device_id *id = platform_get_device_id(pdev);
3056
3057         /* get base addr */
3058         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3059
3060         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3061         if (!ndev)
3062                 return -ENOMEM;
3063
3064         pm_runtime_enable(&pdev->dev);
3065         pm_runtime_get_sync(&pdev->dev);
3066
3067         devno = pdev->id;
3068         if (devno < 0)
3069                 devno = 0;
3070
3071         ndev->dma = -1;
3072         ret = platform_get_irq(pdev, 0);
3073         if (ret < 0)
3074                 goto out_release;
3075         ndev->irq = ret;
3076
3077         SET_NETDEV_DEV(ndev, &pdev->dev);
3078
3079         mdp = netdev_priv(ndev);
3080         mdp->num_tx_ring = TX_RING_SIZE;
3081         mdp->num_rx_ring = RX_RING_SIZE;
3082         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3083         if (IS_ERR(mdp->addr)) {
3084                 ret = PTR_ERR(mdp->addr);
3085                 goto out_release;
3086         }
3087
3088         ndev->base_addr = res->start;
3089
3090         spin_lock_init(&mdp->lock);
3091         mdp->pdev = pdev;
3092
3093         if (pdev->dev.of_node)
3094                 pd = sh_eth_parse_dt(&pdev->dev);
3095         if (!pd) {
3096                 dev_err(&pdev->dev, "no platform data\n");
3097                 ret = -EINVAL;
3098                 goto out_release;
3099         }
3100
3101         /* get PHY ID */
3102         mdp->phy_id = pd->phy;
3103         mdp->phy_interface = pd->phy_interface;
3104         /* EDMAC endian */
3105         mdp->edmac_endian = pd->edmac_endian;
3106         mdp->no_ether_link = pd->no_ether_link;
3107         mdp->ether_link_active_low = pd->ether_link_active_low;
3108
3109         /* set cpu data */
3110         if (id) {
3111                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3112         } else  {
3113                 const struct of_device_id *match;
3114
3115                 match = of_match_device(of_match_ptr(sh_eth_match_table),
3116                                         &pdev->dev);
3117                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3118         }
3119         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3120         if (!mdp->reg_offset) {
3121                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3122                         mdp->cd->register_type);
3123                 ret = -EINVAL;
3124                 goto out_release;
3125         }
3126         sh_eth_set_default_cpu_data(mdp->cd);
3127
3128         /* set function */
3129         if (mdp->cd->tsu)
3130                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3131         else
3132                 ndev->netdev_ops = &sh_eth_netdev_ops;
3133         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3134         ndev->watchdog_timeo = TX_TIMEOUT;
3135
3136         /* debug message level */
3137         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3138
3139         /* read and set MAC address */
3140         read_mac_address(ndev, pd->mac_addr);
3141         if (!is_valid_ether_addr(ndev->dev_addr)) {
3142                 dev_warn(&pdev->dev,
3143                          "no valid MAC address supplied, using a random one.\n");
3144                 eth_hw_addr_random(ndev);
3145         }
3146
3147         /* ioremap the TSU registers */
3148         if (mdp->cd->tsu) {
3149                 struct resource *rtsu;
3150                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3151                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3152                 if (IS_ERR(mdp->tsu_addr)) {
3153                         ret = PTR_ERR(mdp->tsu_addr);
3154                         goto out_release;
3155                 }
3156                 mdp->port = devno % 2;
3157                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3158         }
3159
3160         /* initialize first or needed device */
3161         if (!devno || pd->needs_init) {
3162                 if (mdp->cd->chip_reset)
3163                         mdp->cd->chip_reset(ndev);
3164
3165                 if (mdp->cd->tsu) {
3166                         /* TSU init (Init only)*/
3167                         sh_eth_tsu_init(mdp);
3168                 }
3169         }
3170
3171         if (mdp->cd->rmiimode)
3172                 sh_eth_write(ndev, 0x1, RMIIMODE);
3173
3174         /* MDIO bus init */
3175         ret = sh_mdio_init(mdp, pd);
3176         if (ret) {
3177                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3178                 goto out_release;
3179         }
3180
3181         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3182
3183         /* network device register */
3184         ret = register_netdev(ndev);
3185         if (ret)
3186                 goto out_napi_del;
3187
3188         /* print device information */
3189         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3190                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3191
3192         pm_runtime_put(&pdev->dev);
3193         platform_set_drvdata(pdev, ndev);
3194
3195         return ret;
3196
3197 out_napi_del:
3198         netif_napi_del(&mdp->napi);
3199         sh_mdio_release(mdp);
3200
3201 out_release:
3202         /* net_dev free */
3203         if (ndev)
3204                 free_netdev(ndev);
3205
3206         pm_runtime_put(&pdev->dev);
3207         pm_runtime_disable(&pdev->dev);
3208         return ret;
3209 }
3210
3211 static int sh_eth_drv_remove(struct platform_device *pdev)
3212 {
3213         struct net_device *ndev = platform_get_drvdata(pdev);
3214         struct sh_eth_private *mdp = netdev_priv(ndev);
3215
3216         unregister_netdev(ndev);
3217         netif_napi_del(&mdp->napi);
3218         sh_mdio_release(mdp);
3219         pm_runtime_disable(&pdev->dev);
3220         free_netdev(ndev);
3221
3222         return 0;
3223 }
3224
3225 #ifdef CONFIG_PM
3226 #ifdef CONFIG_PM_SLEEP
3227 static int sh_eth_suspend(struct device *dev)
3228 {
3229         struct net_device *ndev = dev_get_drvdata(dev);
3230         int ret = 0;
3231
3232         if (netif_running(ndev)) {
3233                 netif_device_detach(ndev);
3234                 ret = sh_eth_close(ndev);
3235         }
3236
3237         return ret;
3238 }
3239
3240 static int sh_eth_resume(struct device *dev)
3241 {
3242         struct net_device *ndev = dev_get_drvdata(dev);
3243         int ret = 0;
3244
3245         if (netif_running(ndev)) {
3246                 ret = sh_eth_open(ndev);
3247                 if (ret < 0)
3248                         return ret;
3249                 netif_device_attach(ndev);
3250         }
3251
3252         return ret;
3253 }
3254 #endif
3255
3256 static int sh_eth_runtime_nop(struct device *dev)
3257 {
3258         /* Runtime PM callback shared between ->runtime_suspend()
3259          * and ->runtime_resume(). Simply returns success.
3260          *
3261          * This driver re-initializes all registers after
3262          * pm_runtime_get_sync() anyway so there is no need
3263          * to save and restore registers here.
3264          */
3265         return 0;
3266 }
3267
3268 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3269         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3270         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3271 };
3272 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3273 #else
3274 #define SH_ETH_PM_OPS NULL
3275 #endif
3276
3277 static struct platform_device_id sh_eth_id_table[] = {
3278         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3279         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3280         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3281         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3282         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3283         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3284         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3285         { }
3286 };
3287 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3288
3289 static struct platform_driver sh_eth_driver = {
3290         .probe = sh_eth_drv_probe,
3291         .remove = sh_eth_drv_remove,
3292         .id_table = sh_eth_id_table,
3293         .driver = {
3294                    .name = CARDNAME,
3295                    .pm = SH_ETH_PM_OPS,
3296                    .of_match_table = of_match_ptr(sh_eth_match_table),
3297         },
3298 };
3299
3300 module_platform_driver(sh_eth_driver);
3301
3302 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3303 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3304 MODULE_LICENSE("GPL v2");