2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/mdio-bitbang.h>
34 #include <linux/netdevice.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
47 #define SH_ETH_DEF_MSG_ENABLE \
53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
274 [TSU_CTRST] = 0x0004,
275 [TSU_FWEN0] = 0x0010,
276 [TSU_FWEN1] = 0x0014,
278 [TSU_BSYSL0] = 0x0020,
279 [TSU_BSYSL1] = 0x0024,
280 [TSU_PRISL0] = 0x0028,
281 [TSU_PRISL1] = 0x002c,
282 [TSU_FWSL0] = 0x0030,
283 [TSU_FWSL1] = 0x0034,
284 [TSU_FWSLC] = 0x0038,
285 [TSU_QTAGM0] = 0x0040,
286 [TSU_QTAGM1] = 0x0044,
287 [TSU_ADQT0] = 0x0048,
288 [TSU_ADQT1] = 0x004c,
290 [TSU_FWINMK] = 0x0054,
291 [TSU_ADSBSY] = 0x0060,
293 [TSU_POST1] = 0x0070,
294 [TSU_POST2] = 0x0074,
295 [TSU_POST3] = 0x0078,
296 [TSU_POST4] = 0x007c,
311 [TSU_ADRH0] = 0x0100,
312 [TSU_ADRL0] = 0x0104,
313 [TSU_ADRL31] = 0x01fc,
316 static int sh_eth_is_gether(struct sh_eth_private *mdp)
318 if (mdp->reg_offset == sh_eth_offset_gigabit)
324 static void sh_eth_select_mii(struct net_device *ndev)
327 struct sh_eth_private *mdp = netdev_priv(ndev);
329 switch (mdp->phy_interface) {
330 case PHY_INTERFACE_MODE_GMII:
333 case PHY_INTERFACE_MODE_MII:
336 case PHY_INTERFACE_MODE_RMII:
340 pr_warn("PHY interface mode was not setup. Set to MII.\n");
345 sh_eth_write(ndev, value, RMII_MII);
348 static void sh_eth_set_duplex(struct net_device *ndev)
350 struct sh_eth_private *mdp = netdev_priv(ndev);
352 if (mdp->duplex) /* Full */
353 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
355 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
358 /* There is CPU dependent code */
359 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
361 struct sh_eth_private *mdp = netdev_priv(ndev);
363 switch (mdp->speed) {
364 case 10: /* 10BASE */
365 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
367 case 100:/* 100BASE */
368 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
376 static struct sh_eth_cpu_data r8a777x_data = {
377 .set_duplex = sh_eth_set_duplex,
378 .set_rate = sh_eth_set_rate_r8a777x,
380 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
381 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
382 .eesipr_value = 0x01ff009f,
384 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
385 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
386 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
395 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
397 struct sh_eth_private *mdp = netdev_priv(ndev);
399 switch (mdp->speed) {
400 case 10: /* 10BASE */
401 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
403 case 100:/* 100BASE */
404 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
412 static struct sh_eth_cpu_data sh7724_data = {
413 .set_duplex = sh_eth_set_duplex,
414 .set_rate = sh_eth_set_rate_sh7724,
416 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
417 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
418 .eesipr_value = 0x01ff009f,
420 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
421 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
422 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
430 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
433 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
435 struct sh_eth_private *mdp = netdev_priv(ndev);
437 switch (mdp->speed) {
438 case 10: /* 10BASE */
439 sh_eth_write(ndev, 0, RTRATE);
441 case 100:/* 100BASE */
442 sh_eth_write(ndev, 1, RTRATE);
450 static struct sh_eth_cpu_data sh7757_data = {
451 .set_duplex = sh_eth_set_duplex,
452 .set_rate = sh_eth_set_rate_sh7757,
454 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
455 .rmcr_value = 0x00000001,
457 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
458 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
459 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
462 .irq_flags = IRQF_SHARED,
469 .rpadir_value = 2 << 16,
472 #define SH_GIGA_ETH_BASE 0xfee00000UL
473 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
474 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
475 static void sh_eth_chip_reset_giga(struct net_device *ndev)
478 unsigned long mahr[2], malr[2];
480 /* save MAHR and MALR */
481 for (i = 0; i < 2; i++) {
482 malr[i] = ioread32((void *)GIGA_MALR(i));
483 mahr[i] = ioread32((void *)GIGA_MAHR(i));
487 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
490 /* restore MAHR and MALR */
491 for (i = 0; i < 2; i++) {
492 iowrite32(malr[i], (void *)GIGA_MALR(i));
493 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
497 static void sh_eth_set_rate_giga(struct net_device *ndev)
499 struct sh_eth_private *mdp = netdev_priv(ndev);
501 switch (mdp->speed) {
502 case 10: /* 10BASE */
503 sh_eth_write(ndev, 0x00000000, GECMR);
505 case 100:/* 100BASE */
506 sh_eth_write(ndev, 0x00000010, GECMR);
508 case 1000: /* 1000BASE */
509 sh_eth_write(ndev, 0x00000020, GECMR);
516 /* SH7757(GETHERC) */
517 static struct sh_eth_cpu_data sh7757_data_giga = {
518 .chip_reset = sh_eth_chip_reset_giga,
519 .set_duplex = sh_eth_set_duplex,
520 .set_rate = sh_eth_set_rate_giga,
522 .ecsr_value = ECSR_ICD | ECSR_MPD,
523 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
524 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
526 .tx_check = EESR_TC1 | EESR_FTC,
527 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
528 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
530 .fdr_value = 0x0000072f,
531 .rmcr_value = 0x00000001,
533 .irq_flags = IRQF_SHARED,
540 .rpadir_value = 2 << 16,
546 static void sh_eth_chip_reset(struct net_device *ndev)
548 struct sh_eth_private *mdp = netdev_priv(ndev);
551 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
555 static void sh_eth_set_rate_gether(struct net_device *ndev)
557 struct sh_eth_private *mdp = netdev_priv(ndev);
559 switch (mdp->speed) {
560 case 10: /* 10BASE */
561 sh_eth_write(ndev, GECMR_10, GECMR);
563 case 100:/* 100BASE */
564 sh_eth_write(ndev, GECMR_100, GECMR);
566 case 1000: /* 1000BASE */
567 sh_eth_write(ndev, GECMR_1000, GECMR);
575 static struct sh_eth_cpu_data sh7734_data = {
576 .chip_reset = sh_eth_chip_reset,
577 .set_duplex = sh_eth_set_duplex,
578 .set_rate = sh_eth_set_rate_gether,
580 .ecsr_value = ECSR_ICD | ECSR_MPD,
581 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
582 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
584 .tx_check = EESR_TC1 | EESR_FTC,
585 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
586 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
602 static struct sh_eth_cpu_data sh7763_data = {
603 .chip_reset = sh_eth_chip_reset,
604 .set_duplex = sh_eth_set_duplex,
605 .set_rate = sh_eth_set_rate_gether,
607 .ecsr_value = ECSR_ICD | ECSR_MPD,
608 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
609 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
611 .tx_check = EESR_TC1 | EESR_FTC,
612 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
613 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
624 .irq_flags = IRQF_SHARED,
627 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
629 struct sh_eth_private *mdp = netdev_priv(ndev);
632 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
635 sh_eth_select_mii(ndev);
639 static struct sh_eth_cpu_data r8a7740_data = {
640 .chip_reset = sh_eth_chip_reset_r8a7740,
641 .set_duplex = sh_eth_set_duplex,
642 .set_rate = sh_eth_set_rate_gether,
644 .ecsr_value = ECSR_ICD | ECSR_MPD,
645 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
646 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
648 .tx_check = EESR_TC1 | EESR_FTC,
649 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
650 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
665 static struct sh_eth_cpu_data sh7619_data = {
666 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
674 static struct sh_eth_cpu_data sh771x_data = {
675 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
679 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
682 cd->ecsr_value = DEFAULT_ECSR_INIT;
684 if (!cd->ecsipr_value)
685 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
687 if (!cd->fcftr_value)
688 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
689 DEFAULT_FIFO_F_D_RFD;
692 cd->fdr_value = DEFAULT_FDR_INIT;
695 cd->rmcr_value = DEFAULT_RMCR_VALUE;
698 cd->tx_check = DEFAULT_TX_CHECK;
700 if (!cd->eesr_err_check)
701 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
704 static int sh_eth_check_reset(struct net_device *ndev)
710 if (!(sh_eth_read(ndev, EDMR) & 0x3))
716 pr_err("Device reset failed\n");
722 static int sh_eth_reset(struct net_device *ndev)
724 struct sh_eth_private *mdp = netdev_priv(ndev);
727 if (sh_eth_is_gether(mdp)) {
728 sh_eth_write(ndev, EDSR_ENALL, EDSR);
729 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
732 ret = sh_eth_check_reset(ndev);
737 sh_eth_write(ndev, 0x0, TDLAR);
738 sh_eth_write(ndev, 0x0, TDFAR);
739 sh_eth_write(ndev, 0x0, TDFXR);
740 sh_eth_write(ndev, 0x0, TDFFR);
741 sh_eth_write(ndev, 0x0, RDLAR);
742 sh_eth_write(ndev, 0x0, RDFAR);
743 sh_eth_write(ndev, 0x0, RDFXR);
744 sh_eth_write(ndev, 0x0, RDFFR);
746 /* Reset HW CRC register */
748 sh_eth_write(ndev, 0x0, CSMR);
750 /* Select MII mode */
751 if (mdp->cd->select_mii)
752 sh_eth_select_mii(ndev);
754 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
757 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
765 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
766 static void sh_eth_set_receive_align(struct sk_buff *skb)
770 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
772 skb_reserve(skb, reserve);
775 static void sh_eth_set_receive_align(struct sk_buff *skb)
777 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
782 /* CPU <-> EDMAC endian convert */
783 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
785 switch (mdp->edmac_endian) {
786 case EDMAC_LITTLE_ENDIAN:
787 return cpu_to_le32(x);
788 case EDMAC_BIG_ENDIAN:
789 return cpu_to_be32(x);
794 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
796 switch (mdp->edmac_endian) {
797 case EDMAC_LITTLE_ENDIAN:
798 return le32_to_cpu(x);
799 case EDMAC_BIG_ENDIAN:
800 return be32_to_cpu(x);
806 * Program the hardware MAC address from dev->dev_addr.
808 static void update_mac_address(struct net_device *ndev)
811 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
812 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
814 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
818 * Get MAC address from SuperH MAC address register
820 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
821 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
822 * When you want use this device, you must set MAC address in bootloader.
825 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
827 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
828 memcpy(ndev->dev_addr, mac, 6);
830 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
831 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
832 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
833 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
834 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
835 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
839 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
841 if (sh_eth_is_gether(mdp))
842 return EDTRR_TRNS_GETHER;
844 return EDTRR_TRNS_ETHER;
848 void (*set_gate)(void *addr);
849 struct mdiobb_ctrl ctrl;
851 u32 mmd_msk;/* MMD */
858 static void bb_set(void *addr, u32 msk)
860 iowrite32(ioread32(addr) | msk, addr);
864 static void bb_clr(void *addr, u32 msk)
866 iowrite32((ioread32(addr) & ~msk), addr);
870 static int bb_read(void *addr, u32 msk)
872 return (ioread32(addr) & msk) != 0;
875 /* Data I/O pin control */
876 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
878 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
880 if (bitbang->set_gate)
881 bitbang->set_gate(bitbang->addr);
884 bb_set(bitbang->addr, bitbang->mmd_msk);
886 bb_clr(bitbang->addr, bitbang->mmd_msk);
890 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
892 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
894 if (bitbang->set_gate)
895 bitbang->set_gate(bitbang->addr);
898 bb_set(bitbang->addr, bitbang->mdo_msk);
900 bb_clr(bitbang->addr, bitbang->mdo_msk);
904 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
906 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
908 if (bitbang->set_gate)
909 bitbang->set_gate(bitbang->addr);
911 return bb_read(bitbang->addr, bitbang->mdi_msk);
914 /* MDC pin control */
915 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
917 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
919 if (bitbang->set_gate)
920 bitbang->set_gate(bitbang->addr);
923 bb_set(bitbang->addr, bitbang->mdc_msk);
925 bb_clr(bitbang->addr, bitbang->mdc_msk);
928 /* mdio bus control struct */
929 static struct mdiobb_ops bb_ops = {
930 .owner = THIS_MODULE,
931 .set_mdc = sh_mdc_ctrl,
932 .set_mdio_dir = sh_mmd_ctrl,
933 .set_mdio_data = sh_set_mdio,
934 .get_mdio_data = sh_get_mdio,
937 /* free skb and descriptor buffer */
938 static void sh_eth_ring_free(struct net_device *ndev)
940 struct sh_eth_private *mdp = netdev_priv(ndev);
943 /* Free Rx skb ringbuffer */
944 if (mdp->rx_skbuff) {
945 for (i = 0; i < mdp->num_rx_ring; i++) {
946 if (mdp->rx_skbuff[i])
947 dev_kfree_skb(mdp->rx_skbuff[i]);
950 kfree(mdp->rx_skbuff);
951 mdp->rx_skbuff = NULL;
953 /* Free Tx skb ringbuffer */
954 if (mdp->tx_skbuff) {
955 for (i = 0; i < mdp->num_tx_ring; i++) {
956 if (mdp->tx_skbuff[i])
957 dev_kfree_skb(mdp->tx_skbuff[i]);
960 kfree(mdp->tx_skbuff);
961 mdp->tx_skbuff = NULL;
964 /* format skb and descriptor buffer */
965 static void sh_eth_ring_format(struct net_device *ndev)
967 struct sh_eth_private *mdp = netdev_priv(ndev);
970 struct sh_eth_rxdesc *rxdesc = NULL;
971 struct sh_eth_txdesc *txdesc = NULL;
972 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
973 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
975 mdp->cur_rx = mdp->cur_tx = 0;
976 mdp->dirty_rx = mdp->dirty_tx = 0;
978 memset(mdp->rx_ring, 0, rx_ringsize);
980 /* build Rx ring buffer */
981 for (i = 0; i < mdp->num_rx_ring; i++) {
983 mdp->rx_skbuff[i] = NULL;
984 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
985 mdp->rx_skbuff[i] = skb;
988 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
990 sh_eth_set_receive_align(skb);
993 rxdesc = &mdp->rx_ring[i];
994 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
995 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
997 /* The size of the buffer is 16 byte boundary. */
998 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
999 /* Rx descriptor address set */
1001 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1002 if (sh_eth_is_gether(mdp))
1003 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1007 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1009 /* Mark the last entry as wrapping the ring. */
1010 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1012 memset(mdp->tx_ring, 0, tx_ringsize);
1014 /* build Tx ring buffer */
1015 for (i = 0; i < mdp->num_tx_ring; i++) {
1016 mdp->tx_skbuff[i] = NULL;
1017 txdesc = &mdp->tx_ring[i];
1018 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1019 txdesc->buffer_length = 0;
1021 /* Tx descriptor address set */
1022 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1023 if (sh_eth_is_gether(mdp))
1024 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1028 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1031 /* Get skb and descriptor buffer */
1032 static int sh_eth_ring_init(struct net_device *ndev)
1034 struct sh_eth_private *mdp = netdev_priv(ndev);
1035 int rx_ringsize, tx_ringsize, ret = 0;
1038 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1039 * card needs room to do 8 byte alignment, +2 so we can reserve
1040 * the first 2 bytes, and +16 gets room for the status word from the
1043 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1044 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1045 if (mdp->cd->rpadir)
1046 mdp->rx_buf_sz += NET_IP_ALIGN;
1048 /* Allocate RX and TX skb rings */
1049 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1050 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1051 if (!mdp->rx_skbuff) {
1056 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1057 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1058 if (!mdp->tx_skbuff) {
1063 /* Allocate all Rx descriptors. */
1064 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1065 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1067 if (!mdp->rx_ring) {
1069 goto desc_ring_free;
1074 /* Allocate all Tx descriptors. */
1075 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1076 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1078 if (!mdp->tx_ring) {
1080 goto desc_ring_free;
1085 /* free DMA buffer */
1086 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1089 /* Free Rx and Tx skb ring buffer */
1090 sh_eth_ring_free(ndev);
1091 mdp->tx_ring = NULL;
1092 mdp->rx_ring = NULL;
1097 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1102 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1103 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1105 mdp->rx_ring = NULL;
1109 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1110 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1112 mdp->tx_ring = NULL;
1116 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1119 struct sh_eth_private *mdp = netdev_priv(ndev);
1123 ret = sh_eth_reset(ndev);
1127 /* Descriptor format */
1128 sh_eth_ring_format(ndev);
1129 if (mdp->cd->rpadir)
1130 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1132 /* all sh_eth int mask */
1133 sh_eth_write(ndev, 0, EESIPR);
1135 #if defined(__LITTLE_ENDIAN)
1136 if (mdp->cd->hw_swap)
1137 sh_eth_write(ndev, EDMR_EL, EDMR);
1140 sh_eth_write(ndev, 0, EDMR);
1143 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1144 sh_eth_write(ndev, 0, TFTR);
1146 /* Frame recv control */
1147 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1149 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1152 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1154 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1156 if (!mdp->cd->no_trimd)
1157 sh_eth_write(ndev, 0, TRIMD);
1159 /* Recv frame limit set register */
1160 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1163 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1165 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1167 /* PAUSE Prohibition */
1168 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1169 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1171 sh_eth_write(ndev, val, ECMR);
1173 if (mdp->cd->set_rate)
1174 mdp->cd->set_rate(ndev);
1176 /* E-MAC Status Register clear */
1177 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1179 /* E-MAC Interrupt Enable register */
1181 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1183 /* Set MAC address */
1184 update_mac_address(ndev);
1188 sh_eth_write(ndev, APR_AP, APR);
1190 sh_eth_write(ndev, MPR_MP, MPR);
1191 if (mdp->cd->tpauser)
1192 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1195 /* Setting the Rx mode will start the Rx process. */
1196 sh_eth_write(ndev, EDRRR_R, EDRRR);
1198 netif_start_queue(ndev);
1205 /* free Tx skb function */
1206 static int sh_eth_txfree(struct net_device *ndev)
1208 struct sh_eth_private *mdp = netdev_priv(ndev);
1209 struct sh_eth_txdesc *txdesc;
1213 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1214 entry = mdp->dirty_tx % mdp->num_tx_ring;
1215 txdesc = &mdp->tx_ring[entry];
1216 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1218 /* Free the original skb. */
1219 if (mdp->tx_skbuff[entry]) {
1220 dma_unmap_single(&ndev->dev, txdesc->addr,
1221 txdesc->buffer_length, DMA_TO_DEVICE);
1222 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1223 mdp->tx_skbuff[entry] = NULL;
1226 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1227 if (entry >= mdp->num_tx_ring - 1)
1228 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1230 ndev->stats.tx_packets++;
1231 ndev->stats.tx_bytes += txdesc->buffer_length;
1236 /* Packet receive function */
1237 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1239 struct sh_eth_private *mdp = netdev_priv(ndev);
1240 struct sh_eth_rxdesc *rxdesc;
1242 int entry = mdp->cur_rx % mdp->num_rx_ring;
1243 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1244 struct sk_buff *skb;
1249 rxdesc = &mdp->rx_ring[entry];
1250 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1251 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1252 pkt_len = rxdesc->frame_length;
1263 if (!(desc_status & RDFEND))
1264 ndev->stats.rx_length_errors++;
1267 * In case of almost all GETHER/ETHERs, the Receive Frame State
1268 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1269 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1270 * bits are from bit 25 to bit 16. So, the driver needs right
1273 if (mdp->cd->shift_rd0)
1276 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1277 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1278 ndev->stats.rx_errors++;
1279 if (desc_status & RD_RFS1)
1280 ndev->stats.rx_crc_errors++;
1281 if (desc_status & RD_RFS2)
1282 ndev->stats.rx_frame_errors++;
1283 if (desc_status & RD_RFS3)
1284 ndev->stats.rx_length_errors++;
1285 if (desc_status & RD_RFS4)
1286 ndev->stats.rx_length_errors++;
1287 if (desc_status & RD_RFS6)
1288 ndev->stats.rx_missed_errors++;
1289 if (desc_status & RD_RFS10)
1290 ndev->stats.rx_over_errors++;
1292 if (!mdp->cd->hw_swap)
1294 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1296 skb = mdp->rx_skbuff[entry];
1297 mdp->rx_skbuff[entry] = NULL;
1298 if (mdp->cd->rpadir)
1299 skb_reserve(skb, NET_IP_ALIGN);
1300 skb_put(skb, pkt_len);
1301 skb->protocol = eth_type_trans(skb, ndev);
1302 netif_receive_skb(skb);
1303 ndev->stats.rx_packets++;
1304 ndev->stats.rx_bytes += pkt_len;
1306 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1307 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1308 rxdesc = &mdp->rx_ring[entry];
1311 /* Refill the Rx ring buffers. */
1312 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1313 entry = mdp->dirty_rx % mdp->num_rx_ring;
1314 rxdesc = &mdp->rx_ring[entry];
1315 /* The size of the buffer is 16 byte boundary. */
1316 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1318 if (mdp->rx_skbuff[entry] == NULL) {
1319 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1320 mdp->rx_skbuff[entry] = skb;
1322 break; /* Better luck next round. */
1323 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1325 sh_eth_set_receive_align(skb);
1327 skb_checksum_none_assert(skb);
1328 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1330 if (entry >= mdp->num_rx_ring - 1)
1332 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1335 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1338 /* Restart Rx engine if stopped. */
1339 /* If we don't need to check status, don't. -KDU */
1340 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1341 /* fix the values for the next receiving if RDE is set */
1342 if (intr_status & EESR_RDE)
1343 mdp->cur_rx = mdp->dirty_rx =
1344 (sh_eth_read(ndev, RDFAR) -
1345 sh_eth_read(ndev, RDLAR)) >> 4;
1346 sh_eth_write(ndev, EDRRR_R, EDRRR);
1352 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1354 /* disable tx and rx */
1355 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1356 ~(ECMR_RE | ECMR_TE), ECMR);
1359 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1361 /* enable tx and rx */
1362 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1363 (ECMR_RE | ECMR_TE), ECMR);
1366 /* error control function */
1367 static void sh_eth_error(struct net_device *ndev, int intr_status)
1369 struct sh_eth_private *mdp = netdev_priv(ndev);
1374 if (intr_status & EESR_ECI) {
1375 felic_stat = sh_eth_read(ndev, ECSR);
1376 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1377 if (felic_stat & ECSR_ICD)
1378 ndev->stats.tx_carrier_errors++;
1379 if (felic_stat & ECSR_LCHNG) {
1381 if (mdp->cd->no_psr || mdp->no_ether_link) {
1384 link_stat = (sh_eth_read(ndev, PSR));
1385 if (mdp->ether_link_active_low)
1386 link_stat = ~link_stat;
1388 if (!(link_stat & PHY_ST_LINK))
1389 sh_eth_rcv_snd_disable(ndev);
1392 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1393 ~DMAC_M_ECI, EESIPR);
1395 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1397 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1398 DMAC_M_ECI, EESIPR);
1399 /* enable tx and rx */
1400 sh_eth_rcv_snd_enable(ndev);
1406 if (intr_status & EESR_TWB) {
1407 /* Unused write back interrupt */
1408 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1409 ndev->stats.tx_aborted_errors++;
1410 if (netif_msg_tx_err(mdp))
1411 dev_err(&ndev->dev, "Transmit Abort\n");
1415 if (intr_status & EESR_RABT) {
1416 /* Receive Abort int */
1417 if (intr_status & EESR_RFRMER) {
1418 /* Receive Frame Overflow int */
1419 ndev->stats.rx_frame_errors++;
1420 if (netif_msg_rx_err(mdp))
1421 dev_err(&ndev->dev, "Receive Abort\n");
1425 if (intr_status & EESR_TDE) {
1426 /* Transmit Descriptor Empty int */
1427 ndev->stats.tx_fifo_errors++;
1428 if (netif_msg_tx_err(mdp))
1429 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1432 if (intr_status & EESR_TFE) {
1433 /* FIFO under flow */
1434 ndev->stats.tx_fifo_errors++;
1435 if (netif_msg_tx_err(mdp))
1436 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1439 if (intr_status & EESR_RDE) {
1440 /* Receive Descriptor Empty int */
1441 ndev->stats.rx_over_errors++;
1443 if (netif_msg_rx_err(mdp))
1444 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1447 if (intr_status & EESR_RFE) {
1448 /* Receive FIFO Overflow int */
1449 ndev->stats.rx_fifo_errors++;
1450 if (netif_msg_rx_err(mdp))
1451 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1454 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1456 ndev->stats.tx_fifo_errors++;
1457 if (netif_msg_tx_err(mdp))
1458 dev_err(&ndev->dev, "Address Error\n");
1461 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1462 if (mdp->cd->no_ade)
1464 if (intr_status & mask) {
1466 u32 edtrr = sh_eth_read(ndev, EDTRR);
1468 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1469 intr_status, mdp->cur_tx);
1470 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1471 mdp->dirty_tx, (u32) ndev->state, edtrr);
1472 /* dirty buffer free */
1473 sh_eth_txfree(ndev);
1476 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1478 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1481 netif_wake_queue(ndev);
1485 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1487 struct net_device *ndev = netdev;
1488 struct sh_eth_private *mdp = netdev_priv(ndev);
1489 struct sh_eth_cpu_data *cd = mdp->cd;
1490 irqreturn_t ret = IRQ_NONE;
1491 unsigned long intr_status, intr_enable;
1493 spin_lock(&mdp->lock);
1495 /* Get interrupt status */
1496 intr_status = sh_eth_read(ndev, EESR);
1497 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1498 * enabled since it's the one that comes thru regardless of the mask,
1499 * and we need to fully handle it in sh_eth_error() in order to quench
1500 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1502 intr_enable = sh_eth_read(ndev, EESIPR);
1503 intr_status &= intr_enable | DMAC_M_ECI;
1504 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1509 if (intr_status & EESR_RX_CHECK) {
1510 if (napi_schedule_prep(&mdp->napi)) {
1511 /* Mask Rx interrupts */
1512 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1514 __napi_schedule(&mdp->napi);
1516 dev_warn(&ndev->dev,
1517 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1518 intr_status, intr_enable);
1523 if (intr_status & cd->tx_check) {
1524 /* Clear Tx interrupts */
1525 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1527 sh_eth_txfree(ndev);
1528 netif_wake_queue(ndev);
1531 if (intr_status & cd->eesr_err_check) {
1532 /* Clear error interrupts */
1533 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1535 sh_eth_error(ndev, intr_status);
1539 spin_unlock(&mdp->lock);
1544 static int sh_eth_poll(struct napi_struct *napi, int budget)
1546 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1548 struct net_device *ndev = napi->dev;
1550 unsigned long intr_status;
1553 intr_status = sh_eth_read(ndev, EESR);
1554 if (!(intr_status & EESR_RX_CHECK))
1556 /* Clear Rx interrupts */
1557 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1559 if (sh_eth_rx(ndev, intr_status, "a))
1563 napi_complete(napi);
1565 /* Reenable Rx interrupts */
1566 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1568 return budget - quota;
1571 /* PHY state control function */
1572 static void sh_eth_adjust_link(struct net_device *ndev)
1574 struct sh_eth_private *mdp = netdev_priv(ndev);
1575 struct phy_device *phydev = mdp->phydev;
1579 if (phydev->duplex != mdp->duplex) {
1581 mdp->duplex = phydev->duplex;
1582 if (mdp->cd->set_duplex)
1583 mdp->cd->set_duplex(ndev);
1586 if (phydev->speed != mdp->speed) {
1588 mdp->speed = phydev->speed;
1589 if (mdp->cd->set_rate)
1590 mdp->cd->set_rate(ndev);
1594 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1596 mdp->link = phydev->link;
1597 if (mdp->cd->no_psr || mdp->no_ether_link)
1598 sh_eth_rcv_snd_enable(ndev);
1600 } else if (mdp->link) {
1605 if (mdp->cd->no_psr || mdp->no_ether_link)
1606 sh_eth_rcv_snd_disable(ndev);
1609 if (new_state && netif_msg_link(mdp))
1610 phy_print_status(phydev);
1613 /* PHY init function */
1614 static int sh_eth_phy_init(struct net_device *ndev)
1616 struct sh_eth_private *mdp = netdev_priv(ndev);
1617 char phy_id[MII_BUS_ID_SIZE + 3];
1618 struct phy_device *phydev = NULL;
1620 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1621 mdp->mii_bus->id , mdp->phy_id);
1627 /* Try connect to PHY */
1628 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1629 mdp->phy_interface);
1630 if (IS_ERR(phydev)) {
1631 dev_err(&ndev->dev, "phy_connect failed\n");
1632 return PTR_ERR(phydev);
1635 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1636 phydev->addr, phydev->drv->name);
1638 mdp->phydev = phydev;
1643 /* PHY control start function */
1644 static int sh_eth_phy_start(struct net_device *ndev)
1646 struct sh_eth_private *mdp = netdev_priv(ndev);
1649 ret = sh_eth_phy_init(ndev);
1653 /* reset phy - this also wakes it from PDOWN */
1654 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1655 phy_start(mdp->phydev);
1660 static int sh_eth_get_settings(struct net_device *ndev,
1661 struct ethtool_cmd *ecmd)
1663 struct sh_eth_private *mdp = netdev_priv(ndev);
1664 unsigned long flags;
1667 spin_lock_irqsave(&mdp->lock, flags);
1668 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1669 spin_unlock_irqrestore(&mdp->lock, flags);
1674 static int sh_eth_set_settings(struct net_device *ndev,
1675 struct ethtool_cmd *ecmd)
1677 struct sh_eth_private *mdp = netdev_priv(ndev);
1678 unsigned long flags;
1681 spin_lock_irqsave(&mdp->lock, flags);
1683 /* disable tx and rx */
1684 sh_eth_rcv_snd_disable(ndev);
1686 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1690 if (ecmd->duplex == DUPLEX_FULL)
1695 if (mdp->cd->set_duplex)
1696 mdp->cd->set_duplex(ndev);
1701 /* enable tx and rx */
1702 sh_eth_rcv_snd_enable(ndev);
1704 spin_unlock_irqrestore(&mdp->lock, flags);
1709 static int sh_eth_nway_reset(struct net_device *ndev)
1711 struct sh_eth_private *mdp = netdev_priv(ndev);
1712 unsigned long flags;
1715 spin_lock_irqsave(&mdp->lock, flags);
1716 ret = phy_start_aneg(mdp->phydev);
1717 spin_unlock_irqrestore(&mdp->lock, flags);
1722 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1724 struct sh_eth_private *mdp = netdev_priv(ndev);
1725 return mdp->msg_enable;
1728 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1730 struct sh_eth_private *mdp = netdev_priv(ndev);
1731 mdp->msg_enable = value;
1734 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1735 "rx_current", "tx_current",
1736 "rx_dirty", "tx_dirty",
1738 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1740 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1744 return SH_ETH_STATS_LEN;
1750 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1751 struct ethtool_stats *stats, u64 *data)
1753 struct sh_eth_private *mdp = netdev_priv(ndev);
1756 /* device-specific stats */
1757 data[i++] = mdp->cur_rx;
1758 data[i++] = mdp->cur_tx;
1759 data[i++] = mdp->dirty_rx;
1760 data[i++] = mdp->dirty_tx;
1763 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1765 switch (stringset) {
1767 memcpy(data, *sh_eth_gstrings_stats,
1768 sizeof(sh_eth_gstrings_stats));
1773 static void sh_eth_get_ringparam(struct net_device *ndev,
1774 struct ethtool_ringparam *ring)
1776 struct sh_eth_private *mdp = netdev_priv(ndev);
1778 ring->rx_max_pending = RX_RING_MAX;
1779 ring->tx_max_pending = TX_RING_MAX;
1780 ring->rx_pending = mdp->num_rx_ring;
1781 ring->tx_pending = mdp->num_tx_ring;
1784 static int sh_eth_set_ringparam(struct net_device *ndev,
1785 struct ethtool_ringparam *ring)
1787 struct sh_eth_private *mdp = netdev_priv(ndev);
1790 if (ring->tx_pending > TX_RING_MAX ||
1791 ring->rx_pending > RX_RING_MAX ||
1792 ring->tx_pending < TX_RING_MIN ||
1793 ring->rx_pending < RX_RING_MIN)
1795 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1798 if (netif_running(ndev)) {
1799 netif_tx_disable(ndev);
1800 /* Disable interrupts by clearing the interrupt mask. */
1801 sh_eth_write(ndev, 0x0000, EESIPR);
1802 /* Stop the chip's Tx and Rx processes. */
1803 sh_eth_write(ndev, 0, EDTRR);
1804 sh_eth_write(ndev, 0, EDRRR);
1805 synchronize_irq(ndev->irq);
1808 /* Free all the skbuffs in the Rx queue. */
1809 sh_eth_ring_free(ndev);
1810 /* Free DMA buffer */
1811 sh_eth_free_dma_buffer(mdp);
1813 /* Set new parameters */
1814 mdp->num_rx_ring = ring->rx_pending;
1815 mdp->num_tx_ring = ring->tx_pending;
1817 ret = sh_eth_ring_init(ndev);
1819 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1822 ret = sh_eth_dev_init(ndev, false);
1824 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1828 if (netif_running(ndev)) {
1829 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1830 /* Setting the Rx mode will start the Rx process. */
1831 sh_eth_write(ndev, EDRRR_R, EDRRR);
1832 netif_wake_queue(ndev);
1838 static const struct ethtool_ops sh_eth_ethtool_ops = {
1839 .get_settings = sh_eth_get_settings,
1840 .set_settings = sh_eth_set_settings,
1841 .nway_reset = sh_eth_nway_reset,
1842 .get_msglevel = sh_eth_get_msglevel,
1843 .set_msglevel = sh_eth_set_msglevel,
1844 .get_link = ethtool_op_get_link,
1845 .get_strings = sh_eth_get_strings,
1846 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1847 .get_sset_count = sh_eth_get_sset_count,
1848 .get_ringparam = sh_eth_get_ringparam,
1849 .set_ringparam = sh_eth_set_ringparam,
1852 /* network device open function */
1853 static int sh_eth_open(struct net_device *ndev)
1856 struct sh_eth_private *mdp = netdev_priv(ndev);
1858 pm_runtime_get_sync(&mdp->pdev->dev);
1860 napi_enable(&mdp->napi);
1862 ret = request_irq(ndev->irq, sh_eth_interrupt,
1863 mdp->cd->irq_flags, ndev->name, ndev);
1865 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1869 /* Descriptor set */
1870 ret = sh_eth_ring_init(ndev);
1875 ret = sh_eth_dev_init(ndev, true);
1879 /* PHY control start*/
1880 ret = sh_eth_phy_start(ndev);
1887 free_irq(ndev->irq, ndev);
1889 napi_disable(&mdp->napi);
1890 pm_runtime_put_sync(&mdp->pdev->dev);
1894 /* Timeout function */
1895 static void sh_eth_tx_timeout(struct net_device *ndev)
1897 struct sh_eth_private *mdp = netdev_priv(ndev);
1898 struct sh_eth_rxdesc *rxdesc;
1901 netif_stop_queue(ndev);
1903 if (netif_msg_timer(mdp))
1904 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1905 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1907 /* tx_errors count up */
1908 ndev->stats.tx_errors++;
1910 /* Free all the skbuffs in the Rx queue. */
1911 for (i = 0; i < mdp->num_rx_ring; i++) {
1912 rxdesc = &mdp->rx_ring[i];
1914 rxdesc->addr = 0xBADF00D0;
1915 if (mdp->rx_skbuff[i])
1916 dev_kfree_skb(mdp->rx_skbuff[i]);
1917 mdp->rx_skbuff[i] = NULL;
1919 for (i = 0; i < mdp->num_tx_ring; i++) {
1920 if (mdp->tx_skbuff[i])
1921 dev_kfree_skb(mdp->tx_skbuff[i]);
1922 mdp->tx_skbuff[i] = NULL;
1926 sh_eth_dev_init(ndev, true);
1929 /* Packet transmit function */
1930 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1932 struct sh_eth_private *mdp = netdev_priv(ndev);
1933 struct sh_eth_txdesc *txdesc;
1935 unsigned long flags;
1937 spin_lock_irqsave(&mdp->lock, flags);
1938 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1939 if (!sh_eth_txfree(ndev)) {
1940 if (netif_msg_tx_queued(mdp))
1941 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1942 netif_stop_queue(ndev);
1943 spin_unlock_irqrestore(&mdp->lock, flags);
1944 return NETDEV_TX_BUSY;
1947 spin_unlock_irqrestore(&mdp->lock, flags);
1949 entry = mdp->cur_tx % mdp->num_tx_ring;
1950 mdp->tx_skbuff[entry] = skb;
1951 txdesc = &mdp->tx_ring[entry];
1953 if (!mdp->cd->hw_swap)
1954 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1956 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1958 if (skb->len < ETHERSMALL)
1959 txdesc->buffer_length = ETHERSMALL;
1961 txdesc->buffer_length = skb->len;
1963 if (entry >= mdp->num_tx_ring - 1)
1964 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1966 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1970 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1971 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1973 return NETDEV_TX_OK;
1976 /* device close function */
1977 static int sh_eth_close(struct net_device *ndev)
1979 struct sh_eth_private *mdp = netdev_priv(ndev);
1981 netif_stop_queue(ndev);
1983 /* Disable interrupts by clearing the interrupt mask. */
1984 sh_eth_write(ndev, 0x0000, EESIPR);
1986 /* Stop the chip's Tx and Rx processes. */
1987 sh_eth_write(ndev, 0, EDTRR);
1988 sh_eth_write(ndev, 0, EDRRR);
1990 /* PHY Disconnect */
1992 phy_stop(mdp->phydev);
1993 phy_disconnect(mdp->phydev);
1996 free_irq(ndev->irq, ndev);
1998 napi_disable(&mdp->napi);
2000 /* Free all the skbuffs in the Rx queue. */
2001 sh_eth_ring_free(ndev);
2003 /* free DMA buffer */
2004 sh_eth_free_dma_buffer(mdp);
2006 pm_runtime_put_sync(&mdp->pdev->dev);
2011 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2013 struct sh_eth_private *mdp = netdev_priv(ndev);
2015 pm_runtime_get_sync(&mdp->pdev->dev);
2017 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2018 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2019 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2020 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2021 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2022 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2023 if (sh_eth_is_gether(mdp)) {
2024 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2025 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2026 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2027 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2029 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2030 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2032 pm_runtime_put_sync(&mdp->pdev->dev);
2034 return &ndev->stats;
2037 /* ioctl to device function */
2038 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2041 struct sh_eth_private *mdp = netdev_priv(ndev);
2042 struct phy_device *phydev = mdp->phydev;
2044 if (!netif_running(ndev))
2050 return phy_mii_ioctl(phydev, rq, cmd);
2053 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2054 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2057 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2060 static u32 sh_eth_tsu_get_post_mask(int entry)
2062 return 0x0f << (28 - ((entry % 8) * 4));
2065 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2067 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2070 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2073 struct sh_eth_private *mdp = netdev_priv(ndev);
2077 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2078 tmp = ioread32(reg_offset);
2079 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2082 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2085 struct sh_eth_private *mdp = netdev_priv(ndev);
2086 u32 post_mask, ref_mask, tmp;
2089 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2090 post_mask = sh_eth_tsu_get_post_mask(entry);
2091 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2093 tmp = ioread32(reg_offset);
2094 iowrite32(tmp & ~post_mask, reg_offset);
2096 /* If other port enables, the function returns "true" */
2097 return tmp & ref_mask;
2100 static int sh_eth_tsu_busy(struct net_device *ndev)
2102 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2103 struct sh_eth_private *mdp = netdev_priv(ndev);
2105 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2109 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2117 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2122 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2123 iowrite32(val, reg);
2124 if (sh_eth_tsu_busy(ndev) < 0)
2127 val = addr[4] << 8 | addr[5];
2128 iowrite32(val, reg + 4);
2129 if (sh_eth_tsu_busy(ndev) < 0)
2135 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2139 val = ioread32(reg);
2140 addr[0] = (val >> 24) & 0xff;
2141 addr[1] = (val >> 16) & 0xff;
2142 addr[2] = (val >> 8) & 0xff;
2143 addr[3] = val & 0xff;
2144 val = ioread32(reg + 4);
2145 addr[4] = (val >> 8) & 0xff;
2146 addr[5] = val & 0xff;
2150 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2152 struct sh_eth_private *mdp = netdev_priv(ndev);
2153 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2155 u8 c_addr[ETH_ALEN];
2157 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2158 sh_eth_tsu_read_entry(reg_offset, c_addr);
2159 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2166 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2171 memset(blank, 0, sizeof(blank));
2172 entry = sh_eth_tsu_find_entry(ndev, blank);
2173 return (entry < 0) ? -ENOMEM : entry;
2176 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2179 struct sh_eth_private *mdp = netdev_priv(ndev);
2180 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2184 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2185 ~(1 << (31 - entry)), TSU_TEN);
2187 memset(blank, 0, sizeof(blank));
2188 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2194 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2196 struct sh_eth_private *mdp = netdev_priv(ndev);
2197 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2203 i = sh_eth_tsu_find_entry(ndev, addr);
2205 /* No entry found, create one */
2206 i = sh_eth_tsu_find_empty(ndev);
2209 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2213 /* Enable the entry */
2214 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2215 (1 << (31 - i)), TSU_TEN);
2218 /* Entry found or created, enable POST */
2219 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2224 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2226 struct sh_eth_private *mdp = netdev_priv(ndev);
2232 i = sh_eth_tsu_find_entry(ndev, addr);
2235 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2238 /* Disable the entry if both ports was disabled */
2239 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2247 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2249 struct sh_eth_private *mdp = netdev_priv(ndev);
2252 if (unlikely(!mdp->cd->tsu))
2255 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2256 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2259 /* Disable the entry if both ports was disabled */
2260 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2268 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2270 struct sh_eth_private *mdp = netdev_priv(ndev);
2272 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2275 if (unlikely(!mdp->cd->tsu))
2278 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2279 sh_eth_tsu_read_entry(reg_offset, addr);
2280 if (is_multicast_ether_addr(addr))
2281 sh_eth_tsu_del_entry(ndev, addr);
2285 /* Multicast reception directions set */
2286 static void sh_eth_set_multicast_list(struct net_device *ndev)
2288 struct sh_eth_private *mdp = netdev_priv(ndev);
2291 unsigned long flags;
2293 spin_lock_irqsave(&mdp->lock, flags);
2295 * Initial condition is MCT = 1, PRM = 0.
2296 * Depending on ndev->flags, set PRM or clear MCT
2298 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2300 if (!(ndev->flags & IFF_MULTICAST)) {
2301 sh_eth_tsu_purge_mcast(ndev);
2304 if (ndev->flags & IFF_ALLMULTI) {
2305 sh_eth_tsu_purge_mcast(ndev);
2306 ecmr_bits &= ~ECMR_MCT;
2310 if (ndev->flags & IFF_PROMISC) {
2311 sh_eth_tsu_purge_all(ndev);
2312 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2313 } else if (mdp->cd->tsu) {
2314 struct netdev_hw_addr *ha;
2315 netdev_for_each_mc_addr(ha, ndev) {
2316 if (mcast_all && is_multicast_ether_addr(ha->addr))
2319 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2321 sh_eth_tsu_purge_mcast(ndev);
2322 ecmr_bits &= ~ECMR_MCT;
2328 /* Normal, unicast/broadcast-only mode. */
2329 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2332 /* update the ethernet mode */
2333 sh_eth_write(ndev, ecmr_bits, ECMR);
2335 spin_unlock_irqrestore(&mdp->lock, flags);
2338 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2346 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2347 __be16 proto, u16 vid)
2349 struct sh_eth_private *mdp = netdev_priv(ndev);
2350 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2352 if (unlikely(!mdp->cd->tsu))
2355 /* No filtering if vid = 0 */
2359 mdp->vlan_num_ids++;
2362 * The controller has one VLAN tag HW filter. So, if the filter is
2363 * already enabled, the driver disables it and the filte
2365 if (mdp->vlan_num_ids > 1) {
2366 /* disable VLAN filter */
2367 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2371 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2377 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2378 __be16 proto, u16 vid)
2380 struct sh_eth_private *mdp = netdev_priv(ndev);
2381 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2383 if (unlikely(!mdp->cd->tsu))
2386 /* No filtering if vid = 0 */
2390 mdp->vlan_num_ids--;
2391 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2396 /* SuperH's TSU register init function */
2397 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2399 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2400 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2401 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2402 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2403 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2404 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2405 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2406 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2407 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2408 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2409 if (sh_eth_is_gether(mdp)) {
2410 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2411 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2413 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2414 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2416 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2417 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2418 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2419 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2420 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2421 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2422 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2425 /* MDIO bus release function */
2426 static int sh_mdio_release(struct net_device *ndev)
2428 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2430 /* unregister mdio bus */
2431 mdiobus_unregister(bus);
2433 /* remove mdio bus info from net_device */
2434 dev_set_drvdata(&ndev->dev, NULL);
2436 /* free bitbang info */
2437 free_mdio_bitbang(bus);
2442 /* MDIO bus init function */
2443 static int sh_mdio_init(struct net_device *ndev, int id,
2444 struct sh_eth_plat_data *pd)
2447 struct bb_info *bitbang;
2448 struct sh_eth_private *mdp = netdev_priv(ndev);
2450 /* create bit control struct for PHY */
2451 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2459 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2460 bitbang->set_gate = pd->set_mdio_gate;
2461 bitbang->mdi_msk = PIR_MDI;
2462 bitbang->mdo_msk = PIR_MDO;
2463 bitbang->mmd_msk = PIR_MMD;
2464 bitbang->mdc_msk = PIR_MDC;
2465 bitbang->ctrl.ops = &bb_ops;
2467 /* MII controller setting */
2468 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2469 if (!mdp->mii_bus) {
2474 /* Hook up MII support for ethtool */
2475 mdp->mii_bus->name = "sh_mii";
2476 mdp->mii_bus->parent = &ndev->dev;
2477 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2478 mdp->pdev->name, id);
2481 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2482 sizeof(int) * PHY_MAX_ADDR,
2484 if (!mdp->mii_bus->irq) {
2489 for (i = 0; i < PHY_MAX_ADDR; i++)
2490 mdp->mii_bus->irq[i] = PHY_POLL;
2492 /* register mdio bus */
2493 ret = mdiobus_register(mdp->mii_bus);
2497 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2502 free_mdio_bitbang(mdp->mii_bus);
2508 static const u16 *sh_eth_get_register_offset(int register_type)
2510 const u16 *reg_offset = NULL;
2512 switch (register_type) {
2513 case SH_ETH_REG_GIGABIT:
2514 reg_offset = sh_eth_offset_gigabit;
2516 case SH_ETH_REG_FAST_RCAR:
2517 reg_offset = sh_eth_offset_fast_rcar;
2519 case SH_ETH_REG_FAST_SH4:
2520 reg_offset = sh_eth_offset_fast_sh4;
2522 case SH_ETH_REG_FAST_SH3_SH2:
2523 reg_offset = sh_eth_offset_fast_sh3_sh2;
2526 pr_err("Unknown register type (%d)\n", register_type);
2533 static const struct net_device_ops sh_eth_netdev_ops = {
2534 .ndo_open = sh_eth_open,
2535 .ndo_stop = sh_eth_close,
2536 .ndo_start_xmit = sh_eth_start_xmit,
2537 .ndo_get_stats = sh_eth_get_stats,
2538 .ndo_tx_timeout = sh_eth_tx_timeout,
2539 .ndo_do_ioctl = sh_eth_do_ioctl,
2540 .ndo_validate_addr = eth_validate_addr,
2541 .ndo_set_mac_address = eth_mac_addr,
2542 .ndo_change_mtu = eth_change_mtu,
2545 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2546 .ndo_open = sh_eth_open,
2547 .ndo_stop = sh_eth_close,
2548 .ndo_start_xmit = sh_eth_start_xmit,
2549 .ndo_get_stats = sh_eth_get_stats,
2550 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2551 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2552 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2553 .ndo_tx_timeout = sh_eth_tx_timeout,
2554 .ndo_do_ioctl = sh_eth_do_ioctl,
2555 .ndo_validate_addr = eth_validate_addr,
2556 .ndo_set_mac_address = eth_mac_addr,
2557 .ndo_change_mtu = eth_change_mtu,
2560 static int sh_eth_drv_probe(struct platform_device *pdev)
2563 struct resource *res;
2564 struct net_device *ndev = NULL;
2565 struct sh_eth_private *mdp = NULL;
2566 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2567 const struct platform_device_id *id = platform_get_device_id(pdev);
2570 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2571 if (unlikely(res == NULL)) {
2572 dev_err(&pdev->dev, "invalid resource\n");
2577 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2583 /* The sh Ether-specific entries in the device structure. */
2584 ndev->base_addr = res->start;
2590 ret = platform_get_irq(pdev, 0);
2597 SET_NETDEV_DEV(ndev, &pdev->dev);
2599 /* Fill in the fields of the device structure with ethernet values. */
2602 mdp = netdev_priv(ndev);
2603 mdp->num_tx_ring = TX_RING_SIZE;
2604 mdp->num_rx_ring = RX_RING_SIZE;
2605 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2606 if (IS_ERR(mdp->addr)) {
2607 ret = PTR_ERR(mdp->addr);
2611 spin_lock_init(&mdp->lock);
2613 pm_runtime_enable(&pdev->dev);
2614 pm_runtime_resume(&pdev->dev);
2617 mdp->phy_id = pd->phy;
2618 mdp->phy_interface = pd->phy_interface;
2620 mdp->edmac_endian = pd->edmac_endian;
2621 mdp->no_ether_link = pd->no_ether_link;
2622 mdp->ether_link_active_low = pd->ether_link_active_low;
2623 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2626 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2627 sh_eth_set_default_cpu_data(mdp->cd);
2631 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2633 ndev->netdev_ops = &sh_eth_netdev_ops;
2634 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2635 ndev->watchdog_timeo = TX_TIMEOUT;
2637 /* debug message level */
2638 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2640 /* read and set MAC address */
2641 read_mac_address(ndev, pd->mac_addr);
2642 if (!is_valid_ether_addr(ndev->dev_addr)) {
2643 dev_warn(&pdev->dev,
2644 "no valid MAC address supplied, using a random one.\n");
2645 eth_hw_addr_random(ndev);
2648 /* ioremap the TSU registers */
2650 struct resource *rtsu;
2651 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2652 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2653 if (IS_ERR(mdp->tsu_addr)) {
2654 ret = PTR_ERR(mdp->tsu_addr);
2657 mdp->port = devno % 2;
2658 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2661 /* initialize first or needed device */
2662 if (!devno || pd->needs_init) {
2663 if (mdp->cd->chip_reset)
2664 mdp->cd->chip_reset(ndev);
2667 /* TSU init (Init only)*/
2668 sh_eth_tsu_init(mdp);
2672 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2674 /* network device register */
2675 ret = register_netdev(ndev);
2680 ret = sh_mdio_init(ndev, pdev->id, pd);
2682 goto out_unregister;
2684 /* print device information */
2685 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2686 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2688 platform_set_drvdata(pdev, ndev);
2693 unregister_netdev(ndev);
2696 netif_napi_del(&mdp->napi);
2707 static int sh_eth_drv_remove(struct platform_device *pdev)
2709 struct net_device *ndev = platform_get_drvdata(pdev);
2710 struct sh_eth_private *mdp = netdev_priv(ndev);
2712 sh_mdio_release(ndev);
2713 unregister_netdev(ndev);
2714 netif_napi_del(&mdp->napi);
2715 pm_runtime_disable(&pdev->dev);
2722 static int sh_eth_runtime_nop(struct device *dev)
2725 * Runtime PM callback shared between ->runtime_suspend()
2726 * and ->runtime_resume(). Simply returns success.
2728 * This driver re-initializes all registers after
2729 * pm_runtime_get_sync() anyway so there is no need
2730 * to save and restore registers here.
2735 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2736 .runtime_suspend = sh_eth_runtime_nop,
2737 .runtime_resume = sh_eth_runtime_nop,
2739 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2741 #define SH_ETH_PM_OPS NULL
2744 static struct platform_device_id sh_eth_id_table[] = {
2745 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2746 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2747 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2748 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2749 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2750 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2751 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2752 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2753 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2756 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2758 static struct platform_driver sh_eth_driver = {
2759 .probe = sh_eth_drv_probe,
2760 .remove = sh_eth_drv_remove,
2761 .id_table = sh_eth_id_table,
2764 .pm = SH_ETH_PM_OPS,
2768 module_platform_driver(sh_eth_driver);
2770 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2771 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2772 MODULE_LICENSE("GPL v2");